Source line driving method of display panel and driving circuit using same

Abstract

The invention discloses a driving circuit for driving a source line of a display panel. The display panel comprises a first area and a second area. The driving circuit comprises a gamma voltage generator and a source driver. The gamma voltage generator updates the gamma voltage set according to at least a first refresh rate of the first region and a second refresh rate of the second region. The source driver is coupled to the gamma voltage generator, generates a pixel voltage according to the pixel data and the gamma voltage set, and drives the source line according to the pixel voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to display technology, and in particular, to a source line driving method for providing uniform brightness and a driving circuit using the method. BACKGROUND

[0002] Flat panel displays are widely used in various devices such as televisions, computer monitors, smartphones, and tablets. Flat panel displays use technologies such as liquid crystal displays (LCDs), light-emitting diodes (LEDs), and organic light-emitting diodes (OLEDs). Each technology has unique advantages in terms of brightness, color accuracy, energy efficiency, and viewing angle.

[0003] Multi-area frame rate technology for flat panel displays allows different areas of the screen to be refreshed at different refresh rates, optimizing performance and visual quality. This approach is particularly suitable for applications such as gaming and video playback, where certain areas of the screen may require higher refresh rates to smoothly display rapidly moving content, while other areas can operate at lower refresh rates to conserve energy and reduce heat generation. By dynamically adjusting the frame rates of different areas, flat panel displays can provide a more efficient and visually appealing experience, minimizing issues such as motion blur and screen tearing. This technology maintains energy efficiency while providing clearer images and smoother transitions in high-demand areas, enhancing overall user experience.

[0004] However, the implementation of multi-area frame rate technology can result in significant brightness differences between high-frequency and low-frequency areas, leading to visual inconsistencies and a decline in overall visual quality. SUMMARY

[0005] Embodiments of the present application provide a method for driving a source line of a display panel. The display panel includes a first area and a second area. The method includes updating a set of gamma voltages according to at least a first refresh rate of the first area and a second refresh rate of the second area, generating pixel voltages according to pixel data and the set of gamma voltages, and driving the source line according to the pixel voltages.

[0006] The embodiment of the present application further provides a driving circuit for driving a source line of a display panel. The display panel comprises a first region and a second region. The driving circuit comprises a gamma voltage generator and a source driver. The gamma voltage generator updates a gamma voltage set according to at least a first refresh rate of the first region and a second refresh rate of the second region. The source driver is coupled to the gamma voltage generator, pixel data and the gamma voltage set generate a pixel voltage, and the source line is driven according to the pixel voltage. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 FIG. 1 is a block diagram of a display device according to an embodiment of the present application.

[0008] Figure 2A FIG. 2 is a circuit diagram of a pixel in FIG. 1. Figure 2B Figure 1

[0009] Figure 3 FIG. 3 is a multi-region frame rate scheme diagram of the display device in FIG. 1. Figure 1

[0010] Figure 4 FIG. 4 is a block diagram of a data driver in FIG. 1. Figure 1

[0011] Figure 5 FIG. 5 is a circuit diagram of the data driver in FIG. 1. Figure 1

[0012] Figure 6 FIG. 6 is a pixel data and pixel voltage conversion diagram.

[0013] Figure 7 FIG. 7 is a timing diagram of the multi-region frame rate scheme according to an embodiment of the present application.

[0014] Figure 8 FIG. 8 is a flow chart of a driving method of a source line of a display panel in FIG. 1. Figure 1

[0015] In the figures, the following signs are used:

[0016] 1: display device

[0017] 10: display panel

[0018] 100: pixel array

[0019] 102a and 102b: gate array driver

[0020] 12: driving circuit

[0021] 120: power generator

[0022] 121: clock generator

[0023] 122: data driver​​​​​​

[0024] 123: timing generator

[0025] 124: data path circuitry

[0026] 125: oscillator

[0027] 126: instruction decoder

[0028] 127: interface circuitry

[0029] 30: high refresh rate area

[0030] 32: low refresh rate area

[0031] 20: source driver

[0032] 200: digital-to-analog converter

[0033] 202: output buffer

[0034] 22: gamma voltage generator

[0035] 220: resistor string

[0036] 60p, 62p, 60n, and 62n: gamma curve

[0037] 800; method

[0038] S802 to S806: step

[0039] Cd1, Cd2: capacitor

[0040] D: light emitting diode

[0041] Din: data signal

[0042] Dpx: pixel data

[0043] ELVDD: power supply terminal

[0044] GCK, GCK1 to GCK4: clock signal

[0045] GL(0) to G(M), GL: gate line

[0046] GVDDP, GVDDN: supply voltage

[0047] PX: pixel

[0048] SG: gate voltage

[0049] SL(0) to SL(N), SL: source line

[0050] STV: start vertical signal

[0051] t1 to t14, t: time

[0052] Td: drive transistor

[0053] Tsw1, Tsw2: switch transistor

[0054] RST: reset signal

[0055] V: voltage

[0056] VCOM: reference voltage

[0057] VD(0) to VD(N), VD: data voltage

[0058] VG(S:-S),: gamma voltage set

[0059] VG(255:0): gamma voltage

[0060] VGH and VGL: supply voltage

[0061] Vpx: pixel voltage

[0062] Vsync: vertical synchronization signal

[0063] Hsync: horizontal synchronization signal DETAILED DESCRIPTION

[0064] Figure 1 is a block diagram of a display device 1 of an embodiment of the present application. The display device 1 can include a display panel 10 and a driving circuit 12 coupled to the display panel 10. The display panel 10 can be a liquid crystal display (LCD) panel or an organic light-emitting diode (OLED) panel. The driving circuit 12 can be implemented as a stand-alone integrated circuit.

[0065] The display panel 10 can include a pixel array 100 and gate on array (GOA) drivers 102a and 102b. The GOA drivers 102a and 102b are coupled to the display panel 100. The pixel array 100 can include a plurality of pixels PX, source lines SL(0) to SL(N), and gate lines GL(0) to GL(M), where N and M are positive integers. The plurality of pixels PX can be arranged in (N+l) columns and (M+l) rows, and each pixel PX can be a red (R) pixel, a green (G) pixel, or a blue (B) pixel. The (N+l) columns of pixels PX can be coupled to the driving circuit 12 through the source lines SL(0) to SL(N) to receive data voltages VD(0) to VD(N) (referred to as VD(0:N)) for displaying an image. The (M+l) rows of pixels PX can be coupled to the GOA drivers 102a and 102b through the gate lines GL(0) to GL(M). Each pixel PX can be coupled to a corresponding gate line and a corresponding source line. The pixel PX can be activated by a gate signal on the corresponding gate line and can load pixel data on the corresponding source line, which is represented by the data voltage.

[0066] Figure 2A and 2B are circuit diagrams of a pixel PX in a liquid crystal panel and an organic light emitting diode panel, respectively. In Figure 2A , the pixel PX in the liquid crystal panel includes a switching transistor Tsw1 and a capacitor Cd1. The switching transistor Tsw1 includes a control terminal coupled to a gate line GL to receive a gate voltage SG, a first terminal coupled to a source line SL to receive a data voltage VD, and a second terminal. The capacitor Cd1 includes a first terminal coupled to the second terminal of the switching transistor Tsw1 and a second terminal coupled to a ground terminal to receive a ground voltage. When the switching transistor Tsw1 is turned on, the capacitor Cd1 can be charged by the data voltage VD. Conversely, when the switching transistor Tsw1 is turned off, the capacitor Cd1 can maintain the data voltage VD. However, in practical applications, it takes a certain amount of time to charge the capacitor Cd1 to the desired data voltage VD level due to the resistor-capacitor (RC) load effect. In addition, the voltage maintained by the capacitor Cd1 tends to gradually decrease due to a leakage current when the switching transistor Tsw1 is turned off. The brightness level of the pixel PX is determined by the voltage stored in the capacitor Cd1.

[0067] In Figure 2BIn the OLED panel, a pixel PX includes a switch transistor Tsw2, a drive transistor Td, a capacitor Cd2, and a light-emitting diode (LED) D. The switch transistor Tsw2 includes a control terminal coupled to the gate line GL to receive the gate voltage SG, a first terminal coupled to the source line SL to receive the data voltage VD, and a second terminal. The capacitor Cd2 includes a first terminal coupled to the second terminal of the switch transistor Tsw2, and a second terminal. The drive transistor Td includes a control terminal coupled to the second terminal of the switch transistor Tsw2, a first terminal coupled to the power supply terminal ELVDD, and a second terminal. The LED D includes an anode terminal coupled to the second terminal of the drive transistor Td, and a cathode terminal coupled to the ground terminal to receive the ground voltage. When the switch transistor Tsw2 is turned on, the capacitor Cd2 can be charged by the data voltage VD. Conversely, when the switch transistor Tsw2 is turned off, the capacitor Cd2 can maintain the data voltage VD. However, due to the effect of RC load, it takes a certain time to charge the capacitor Cd2 to the required data voltage VD. In addition, when the switch transistor Tsw2 is turned off, the voltage stored in the capacitor Cd2 can be reduced due to current leakage. The drive transistor Td generates a drive current according to the voltage stored in the capacitor Cd2, and uses the drive current to power the LED D, causing the LED D to emit light. The brightness of the LED D is proportional to the drive current, and the drive current depends on the voltage in the capacitor Cd2.

[0068] The display device 1 can employ a multi-area frame rate (MAFR) scheme to divide the pixel array 100 into multiple areas to be updated at different refresh rates. The refresh rate can be dynamically allocated according to the image content. The MAFR scheme can reduce power consumption by reducing the refresh rate of low refresh rate areas while maintaining high image quality of high refresh rate areas. Figure 3is a schematic diagram of a MAFR scheme used by the display device 1. The pixel array 100 is divided into a high refresh rate region 30 and a low refresh rate region 32. The high refresh rate region 30 can be updated at a high refresh rate and the low refresh rate region 32 can be updated at a low refresh rate, where the high refresh rate exceeds the low refresh rate. For example, the high refresh rate region 30 can display dynamic content, such as a video play or a game image, at a frequency of 120 Hz, while the low refresh rate region 32 can display static content, such as a background element, at a frequency of 40 Hz. The MAFR scheme achieves an efficient update rate between the two regions. The high refresh rate region 30 is updated three times for every update of the low refresh rate region 32. However, the different refresh rates can cause the luminance of the high refresh rate region 30 and the low refresh rate region 32 to be different. In the high refresh rate region 30, due to RC load effect, the voltage in the capacitance of each pixel PX gradually approaches the required voltage during the three consecutive frame updates, causing the luminance level to rise. In the low refresh rate region 32, due to the leakage current effect, the voltage in the capacitance of each pixel PX gradually decreases during the three consecutive frame updates, causing the luminance level to drop. The difference in luminance level between the high refresh rate region 30 and the low refresh rate region 32 can cause the entire pixel array 100 to have a significant difference in luminance level. The high refresh rate region 30 can appear brighter than the low refresh rate region 32. These luminance differences can affect the overall visual consistency and image quality of the displayed image, thereby posing a technical challenge to providing uniform luminance distribution for the pixel array 100.

[0069] In Figure 1 , the driving circuit 12 can include a power generator 120, a clock generator (CG) 121, a data driver 122, a timing generator (TG) 123, a datapath circuit 124, an oscillator (OSC) 125, an instruction decoder 126, and an interface circuit 127. The interface circuit 127 can be coupled to the instruction decoder 126. The instruction decoder 126 and the oscillator 125 can be coupled to the timing generator 123. The timing generator 123 can be coupled to the power generator 120, the clock generator 121, and the datapath circuit 124. The datapath circuit 124 can be coupled to the data driver 122. The power generator 120, the clock generator 121, and the data driver 122 can be coupled to the display panel 10.

[0070] The interface circuit 127 can receive image data and control data from a host device and transfer the image data and control data to the instruction decoder 126. The interface circuit 127 can be a mobile industry processor interface (MIPI), a serial peripheral interface (SPI), a display serial interface (DSI), an embedded display port (EDP) interface, a low-voltage differential signaling (LVDS) interface, or other display interface. The host device can be a display card, a smartphone, or an embedded system. The image data can include visual content to be displayed on the display panel 100. The control data can be instructions for managing the display, such as brightness adjustment or picture update. The instruction decoder 126 can interpret the control data to generate specific instructions for the display panel, such as updating a pixel, adjusting contrast, or changing a display mode. The instruction decoder 126 can send the instructions and the image data to the timing generator 123.

[0071] The oscillator 125 can generate a system clock signal and transmit the system clock signal to the timing generator 123. The timing generator 123 can generate a vertical synchronization (Vsync) signal, a horizontal synchronization (Hsync) signal, and other image control signals according to the system clock signal, the image data, and the commands, and forward the Vsync signal, the Hsync signal, and the other image control signals to the power generator 120, the clock generator 121, the data path circuit 124, and the display panel 10. The power generator 120 can generate supply voltages VGH and VGL and provide the supply voltages VGH and VGL to the display panel 10 for display operation. For example, the supply voltages VGH and VGL can be set to specific voltage levels, such as VGH = 8 V and VGL = -8 V. The clock generator 121 can generate and provide a start vertical (STV) signal, a clock signal GCK, and a reset signal RST to the display panel 10. The STV signal indicates the start of pixel data in each frame, facilitating display synchronization for each frame. The clock signal GCK can be used to selectively sample pixel data, thereby reducing power consumption. The reset signal RST can be used to reset the GOA drivers 102a and 102b.

[0072] The data path circuit 124 can process the image data to generate pixel data, which is then input to the data driver 122 to generate data voltages VD(0) to VD(N). Figure 4 is a block diagram of a single-channel data driver 122. The data driver 122 can convert pixel data Dpx into data voltages VD.

[0073] The data driver 122 can include a source driver 20 and a gamma voltage generator 22 coupled to each other. The source driver 20 can include a digital-to-analog converter (DAC) 200 and an output buffer 202 to precisely control the brightness of each pixel PX.

[0074] The pixel data Dpx can represent a gray level from 0 to 255, providing 256 possible gray levels. The data voltage VD can vary between a reference voltage VCOM and a positive supply voltage GVDDP or a negative supply voltage GVDDN. In an example, the reference voltage VCOM can be set to 0 V, the positive supply voltage GVDDP can be set to 5 V, and the negative supply voltage GVDDN can be set to -5 V. The negative supply voltage GVDDN and the positive supply voltage GVDDP can be adaptably set.

[0075] The gamma voltage generator 22 can generate a set of gamma voltages VG(-S:S), where S is a positive integer. For example, if S = 255, the gamma voltage generator 22 can generate 511 gamma voltages. The span of the set of gamma voltages VG(-S:S) is from the negative supply voltage GVDDN to the positive supply voltage GVDDP, and the reference voltage VCOM can be located at the midpoint of the negative supply voltage GVDDN to the positive supply voltage GVDDP.

[0076] The DAC 200 can receive the pixel data Dpx from the data path circuit 124 and the set of gamma voltages VG(-S:S) from the gamma voltage generator 22. The DAC 200 can select an appropriate gamma voltage from the set of gamma voltages VG(-S:S) according to the pixel data Dpx, effectively converting the digital pixel data to an analog pixel voltage Vpx.

[0077] The output buffer 202 is coupled to the DAC 200. The output buffer 202 can maintain signal integrity and / or amplify the power of the pixel voltage Vpx to generate the data voltage VD, which is driven to the display panel 10 through a source line SL(n), where n is an integer between 0 and N.

[0078] For the sake of clarity, Figure 4The data driver 122 is presented for a single channel, but those skilled in the art will appreciate that the data driver 122 can also be adapted for a multi-channel situation according to similar principles.

[0079] Figure 5 is a circuit diagram of the data driver 122. The gamma voltage generator 22 can include a resistor string 220, a set of positive gamma voltage buffers 222, and a second set of negative gamma voltage buffers 224. The resistor string 220 can be coupled between a high reference end and a low reference end. The high reference end can provide a positive supply voltage GVDDP, and the low reference end can provide a negative supply voltage GVDDN. The resistor string 220 can generate a set of gradient raw voltages from the positive supply voltage GVDDP to the negative supply voltage GVDDN.

[0080] In some embodiments, the set of positive gamma voltage buffers 222 can tap into appropriate locations on the upper half of the resistor string 220 to generate a set of positive reference gamma voltages, from which the gamma voltage generator 22 can select a set of gamma voltages VG(S:0) according to a gamma table that conforms to a desired gamma curve. The number of the set of positive reference gamma voltages can exceed the number of gamma voltages VG(S:0). For example, the set of positive gamma voltage buffers 222 can be evenly tapped along the upper half of the resistor string 220 to generate 1001 positive reference gamma voltages from the positive supply voltage GVDDP of 5V to the reference voltage VCOM of 0V, with a resolution of 5mV (=5 / 1000). In some embodiments, the gamma voltage generator 22 can generate other numbers of positive reference gamma voltages to achieve a desired resolution. For example, the set of positive gamma voltage buffers 222 can generate 1024 or 2048 positive reference gamma voltages to meet a desired design requirement. The resistor string 220 can provide a fine-grained voltage level needed for accurate gamma correction by decreasing the voltage by 5mV for each step down. The gamma table can be stored in a local memory to pair a gray level with a positive reference gamma voltage that conforms to a desired gamma curve, such as the gamma curve 62p in Figure 6

[0081] Figure 6 ​is a pixel data and pixel voltage conversion diagram, where the horizontal axis represents pixel data Dpx in gray scale level, and the vertical axis represents pixel voltage Vpx in voltage. The conversion of pixel data Dpx to pixel voltage Vpx can be performed according to one of the gamma curves 60p, 62p, 60n, and 62n. The data driver 122 can select one of the non-linear gamma curves 60p, 62p, 60n, and 62n according to the pixel array 100 to compensate for the non-linear luminance response, ensuring accurate gray scale reproduction and color fidelity over the entire luminance range. The gamma voltage generator 22 can select a set of gamma voltages VG(255:0) from the 1001 positive reference gamma voltages according to a gamma table, generating a set of gamma voltages VG(255:0) that conforms to the gamma curve 62p. The generation of the gamma voltages VG(255:0) can be achieved in a variety of ways, of which the above method is only one possible implementation. Specifically, both digital and analog gamma techniques can be used to generate the gamma voltages VG(255:0). The digital method relies on a look-up table to map the desired gamma curve in digital form, while the analog method employs a dedicated circuit to generate the gamma curve. To improve the accuracy of the two methods, dithering techniques can be used to provide more detailed control of the voltage conversion, resulting in a smoother gradient.

[0082] Similarly, the negative gamma voltage buffer 224 can tap into the lower half of the resistor string 220 at appropriate locations to generate a set of negative reference gamma voltages, and then the gamma voltage generator 22 can select a set of gamma voltages VG(0:-S) from the set of negative reference gamma voltages according to a gamma table that conforms to another desired gamma curve. For example, the negative gamma voltage buffer 224 can be uniformly tapped along the lower half of the resistor string 220 to generate 1001 negative reference gamma voltages (referred to as a set of reference gamma voltages) from a reference voltage VCOM of 0 V to a negative supply voltage GVDDN of -5 V, with a resolution of 5 mV (= 5 / 1000). The voltage decreases by 5 mV for each step down the resistor string 220, thereby providing the fine-grained voltage levels required for accurate gamma correction. The gamma table can be stored in local memory to pair gray scale levels with negative reference gamma voltages that conform to other desired gamma curves, such as the gamma curve 62n in FIG. 6B. The gamma voltage generator 22 can select a set of gamma voltages VG(0:-255) from the 1001 negative reference gamma voltages according to the gamma table, providing a set of gamma voltages VG(0:-255) that conforms to the gamma curve 62n. Figure 6

[0083] ​The gamma voltage generator 22 can generate the gamma voltage set VG(255:-255), the multi-channel source driver 20 can obtain the gamma voltage set VG(255:-255), the DACs can convert the (N+1) pixel data into (N+1) pixel voltages, and the output buffer 202 can drive the data voltages VD(0:N) to the pixel array 100 through the source lines SL(0) to SL(N).

[0084] Therefore, modifying the positive supply voltage GVDDP / negative supply voltage GVDDN and / or employing different gamma curves can achieve the effect of adjusting the gamma voltage set VG(255:-255). For example, if the positive supply voltage GVDDP is reduced from 5V to 4.9V, the resolution of the positive reference gamma voltage will be reduced from 5mV to 4.9mV. If the negative supply voltage GVDDN is increased from -5V to -4.9V, the resolution of the negative reference gamma voltage will be reduced from 5mV to 4.9mV. In addition, the gamma voltage generator 22 can also select the gamma voltages VG(255:0) according to different gamma curves, such as the gamma curves 60p in FIG. 6B. Figure 6 The flexibility of adjusting the positive supply voltage GVDDP / negative supply voltage GVDDN and selecting different gamma curves enables the display device 1 to achieve uniform brightness distribution of the pixel array 100 in the MAFR scheme.

[0085] Figure 7 is a timing diagram of the MAFR scheme in an embodiment of the present application. The pixel array 100 can be updated by alternating frames F1 and F2. The frame F1 is a full refresh frame (hereinafter referred to as a full brush frame), in which all pixels PX, including those in the high refresh rate area and the low refresh rate area, are updated, while the frame F2 is a partial refresh frame (hereinafter referred to as a partial brush frame), in which only the pixels PX in the high refresh rate area are updated, and the pixels PX in the low refresh rate area are not updated. By adjusting the positive supply voltage GVDDP / negative supply voltage GVDDN and / or employing different gamma tables Gamma for the full brush frame and the partial brush frame, the brightness of the high refresh rate area can be adjusted to be closer to that of the low refresh rate area in the partial refresh frame F2, thereby ensuring consistent brightness performance between the high refresh rate area and the low refresh rate area.

[0086] At time t1, a pulse of the Vsync signal indicates the beginning of the frame F1. The positive supply voltage GVDDP is set to the positive supply voltage GVDDP-A, the negative supply voltage GVDDN is set to the negative supply voltage GVDDN-A, and the gamma table Gamma is set to the gamma table Gamma-A. In an example, the positive supply voltage GVDDP-A is 5V, the negative supply voltage GVDDN is -5V, and the gamma table Gamma-A corresponds to the curves 60p and 60n.

[0087] At time t2, a pulse P1 of the reset signal Reset clears the data voltage in each pixel PX. At time t3, a pulse of the STV signal indicates the beginning of pixel data in frame F1. The clock signals GCK1 to GCK4 are derived from the CGK clock signal, each clock signal GCK1 to GCK4 being shifted by 90 degrees in sequence. At time t4, the data voltage on the source line is sampled by the rising edge of a pulse of the clock signal GCK1 to produce data 1 in the data signal Din at time t5. Between times t4 and t6, the data voltage on the source line is sequentially sampled by the clock signals GCK1 to GCK4 to produce data 1 to data 20 in the data signal Din. Data 1 to data 20 can be driven to the pixels PX on the 1st to 20th gate lines, respectively, to refresh all the pixels PX on the source line. In this embodiment, data 1 to data 8 can be driven to the pixels PX in the high refresh rate area, and data 9 to data 20 can be driven to the pixels PX in the low refresh rate area.

[0088] At time t7, a pulse of the Vsync signal indicates the beginning of frame F2. The positive supply voltage GVDDP is set to positive supply voltage GVDDP-B, the negative supply voltage GVDDN is set to negative supply voltage GVDDN-B, and the gamma table Gamma is set to gamma table Gamma-B. In one example, the positive supply voltage GVDDP-B is 4.9 V, the negative supply voltage GVDDN is -4.9 V, and the gamma table Gamma-B corresponds to curves 62p and 62n.

[0089] At time t8, a pulse P21 of the reset signal Reset clears the data voltage in each pixel PX. At time t9, a pulse of the STV signal indicates the beginning of pixel data in frame F2. At time t10, a rising edge of a pulse in the clock signal GCK1 samples the data voltage on the source line to produce data 1 in the data signal Din at time t11. Between time t10 and time t12, the data voltage on the source line is sequentially sampled by the clock signals GCK1 to GCK4 to produce data 1 to data 8 in the data signal Din, thereby updating data to the pixels PX in the high refresh rate region. At time t12, a pulse P22 of the reset signal Reset resets the GOA drivers 102a and 102b, and the clock signals GCK1 to GCK4 are disabled to inhibit clock pulses, thereby preventing further data sampling of the low refresh rate region. In some embodiments, the pulse P22 can be removed to leave the data signal Din at a ground voltage (e.g., 0 V) for the low refresh rate region between time t12 and time t13 without sampling the data voltage on the source line. Thus, the high refresh rate region and the low refresh rate region can be defined by the clock signals GCK1 to GCK4. The clock signals GCK1 to GCK4 are enabled in the high refresh rate region and disabled in the low refresh rate region. In some embodiments, the clock generator 121, the data path circuit 124, and the data driver 122 can be suspended from operation between time t12 and time t13, thereby reducing energy consumption and ensuring that the display device 1 does not consume excess power when no data is being processed.

[0090] Figure 8 A flowchart of a method 800 of driving source lines of a display panel 100 having multiple regions operating at different refresh rates. The method 800 includes steps S802 to S806 of dynamically updating a set of gamma voltages for a frame according to different refresh rates, thereby providing uniform luminance across the pixel array 100. Any reasonable variation or adjustment of the steps is within the scope of the present disclosure. Steps S802 to S806 are detailed as follows: step S802: the gamma voltage generator 22 updates the set of gamma voltages according to at least a first refresh rate of a first region and a second refresh rate of a second region;

[0091] Step S804: the source driver 20 generates pixel voltages Vpx according to the pixel data Dpx and the set of gamma voltages;

[0092] Step S806: the source driver 20 drives the source lines according to the pixel voltages Vpx.

[0093] In step S802, the first region and the second region are located on the display panel 100, where the first region can be a high refresh rate region and the second region can be a low refresh rate region. The driving circuit 12 can determine the ratio of the full flush frame and the partial flush frame according to the first refresh rate fl of the first region and the second refresh rate f2 of the second region. In some embodiments, the ratio of the full flush frame and the partial flush frame can be f2:(fl-f2). For example, if the first refresh rate fl is 120 Hz and the second refresh rate f2 is 60 Hz, the pixel array 100 can update by alternating the full flush frame and the partial flush frame, so as to achieve a ratio of 1:1 (60:(120-60)). Then, the gamma voltage generator 22 can generate a set of gamma voltages VG1 (S:-S) for the full flush frame and another set of gamma voltages VG2 (S:-S) for the partial flush frame. In another example, if the first refresh rate fl is 120 Hz and the second refresh rate f2 is 40 Hz, the pixel array 100 can update by 1 full flush frame and 2 partial flush frames, so as to form a ratio of 1:2 (40:(120-40)). At this time, the gamma voltage generator 22 can generate a set of gamma voltages VG1 (S:-S) for the full flush frame and another set of gamma voltages VG2 (S:-S) for the partial flush frame. In other embodiments, the gamma voltage generator 22 can generate a set of gamma voltages VG1 (S:-S), VG2 (S:-S), and VG3 (S:-S) for the full flush frame, the first partial flush frame, and the second partial flush frame, respectively. For the full flush frame, the gamma voltage generator 22 can generate the set of gamma voltages VG1 (S:-S) according to the preset positive supply voltage GVDDP, the preset negative supply voltage GVDDN, and the preset gamma table Gamma. For the partial flush frame, the gamma voltage generator 22 can generate the set of gamma voltages VG2 (S:-S) / VG3 (S:-S) according to the modified positive supply voltage GVDDP, the modified negative supply voltage GVDDN, and / or another gamma table Gamma.

[0094] In step S804, the DAC 200 selects one of the newly adjusted sets of gamma voltages according to the pixel data Dpx to generate the pixel voltage Vpx. In step S806, the output buffer 202 retains or amplifies the power of the pixel voltage Vpx to produce the data voltage VD and applies the data voltage VD to the pixel array 100 through the source line.

[0095] For the liquid crystal display panel 10, the gamma voltage generator 22 can determine a frame update type according to the first refresh rate and the second refresh rate, and update the gamma voltage set VG(S:-S) according to a polarity parameter and the frame update type. The frame update type can be a fully refreshed frame or a partially refreshed frame. The polarity parameter indicates a polarity of a data voltage VD applied to a pixel PX in a frame. The liquid crystal display panel 10 can use a polarity inversion technique, in which the data voltage VD applied to each pixel PX is alternated between positive and negative to prevent damage and reduce visual artifacts. In addition, the gamma voltage set VG(S:-S) can be updated according to the frame. Table 1 illustrates an embodiment configuration of the display device 1. The gamma voltage set VG(S:-S) is updated once per frame. In a fully refreshed frame, the polarity parameter can be inverted, and both the first region and the second region are refreshed. In Table 1, the symbols "+" and "-" represent positive polarity and negative polarity, respectively.

[0096] Table 1

[0097] F1 (FR) F2 (PR) F3 (FR) F4 (PR) GVDDP GVDDP-A GVDDP-B GVDDP-A GVDDP-B GVDDN GVDDN-A GVDDN-B GVDDN-A GVDDN-B Gamma Table Gamma-A Gamma-B Gamma-A Gamma-B GL(0) + + - - GL(1) + + - - GL(2) + + - - GL(3) + + - - GL(4) + + - - GL(5) + + - - GL(6) + + - - GL(7) + + - - GL(8) + + - - GL(9) + + - - GL(10) + + - - GL(11) + + - - GL(12) + + - - GL(13) + + - - GL(14) + + - - GL(15) + + - - GL(16) + + - - GL(17) + + - - GL(18) + + - - GL(19) + + - -

[0098] The pixel array 100 includes gate lines GL(0) to GL(19), in which the gate lines GL(0) to GL(7) are located in the high refresh rate region, and the gate lines GL(8) to GL(19) are located in the low refresh rate region. The pixel array 100 sequentially receives a fully refreshed (FR) frame Fl, a partially refreshed (PR) frame F2, a fully refreshed frame F3, and a partially refreshed frame F4. Polarity inversion occurs during the fully refreshed frame F3.

[0099] In the fully refreshed frame Fl, the data voltage VD applied to the pixel PX has a positive polarity, and the gamma voltage generator 22 generates a gamma voltage set VG11(S:-S) using a supply voltage GVDDP-A and / or a gamma table Gamma-A. The supply voltage GVDDP-A can be 5V, and the gamma table Gamma-A can correspond to the curve 60p. Next, the source driver 20 generates 20 pixel voltages Vpx using the gamma voltage set VG11(S:-S), and sequentially drives the source lines according to the 20 pixel voltages Vpx to update the data voltage VD of the pixels PX on the gate lines GL(0) to GL(19).

[0100] In the partial brush frame F2, the data voltage VD applied to the pixel PX has a positive polarity, and the gamma voltage generator 22 generates the gamma voltage set VG12(S:-S) using the supply voltage GVDDP-B and / or the gamma table Gamma-B. The supply voltage GVDDP-A can be 4.9 V, and the gamma table Gamma-A can correspond to the curve 62p. Then, the source driver 20 generates 8 pixel voltages Vpx using the gamma voltage set VG12(S:-S), and sequentially drives the source lines according to the 8 pixel voltages Vpx to update the data voltage VD of the pixel PX on the gate lines GL(0) to GL(7). In the partial brush frame F2, the gate lines GL(8) to GL(19) remain deactivated, and the update of the pixel PX on the gate lines GL(8) to GL(19) is stopped.

[0101] In the full brush frame F3, the data voltage VD applied to the pixel PX has a negative polarity, and the gamma voltage generator 22 generates the gamma voltage set VG13(S:-S) using the supply voltage GVDDN-A and / or the gamma table Gamma-C. The supply voltage GVDDP-B can be -5 V, and the gamma table Gamma-A can correspond to the curve 60n. Then, the source driver 20 generates 20 pixel voltages Vpx using the gamma voltage set VG13(S:-S), and sequentially drives the source lines according to the 20 pixel voltages Vpx to update the data voltage VD of the pixel PX on the gate lines GL(0) to GL(19).

[0102] In the partial brush frame F4, the data voltage VD applied to the pixel PX has a negative polarity, and the gamma voltage generator 22 generates the gamma voltage set VG14(S:-S) using the supply voltage GVDDN-B and / or the gamma table Gamma-D. The supply voltage GVDDP-B can be -4.9 V, and the gamma table Gamma-A can correspond to the curve 62n. Then, the source driver 20 generates 8 pixel voltages Vpx using the gamma voltage set VG14(S:-S), and sequentially drives the source lines according to the 8 pixel voltages Vpx to update the data voltage VD of the pixel PX on the gate lines GL(0) to GL(7). In the partial brush frame F4, the gate lines GL(8) to GL(19) remain deactivated, and the update of the pixel PX on the gate lines GL(8) to GL(19) is stopped.

[0103] In some embodiments, the gamma voltage generator 22 can update the gamma voltage set VG(S:-S) by modifying the positive supply voltage GVDDP / negative supply voltage GVDDN. Specifically, the gamma voltage generator 22 can determine the positive supply voltage GVDDP / negative supply voltage GVDDN according to the polarity parameter and the frame update type, and update the gamma voltage set according to the positive supply voltage GVDDP / negative supply voltage GVDDN. In frame Fl, the polarity parameter indicates positive polarity and the frame update type is a full brush frame. Thus, the gamma voltage generator 22 can generate the gamma voltage set according to the positive supply voltage GVDDP-A. In frame F2, the polarity parameter indicates positive polarity and the frame update type is a partial brush frame. Thus, the gamma voltage generator 22 can generate the gamma voltage set according to the positive supply voltage GVDDP-B, which is different from the positive supply voltage GVDDP-A. In frame F3, the polarity parameter indicates negative polarity and the frame update type is a full brush frame. Thus, the gamma voltage generator 22 can generate the gamma voltage set according to the negative supply voltage GVDDN-A. In frame F4, the polarity parameter indicates negative polarity and the frame update type is a partial brush frame. Thus, the gamma voltage generator 22 can generate the gamma voltage set according to the negative supply voltage GVDDN-B, which is different from the negative supply voltage GVDDN-A. The selection of the supply voltages GVDDP-A, GVDDP-B, GVDDN-A, and GVDDN-B can depend on the electrical characteristics of the pixel array 100, such as RC load and leakage current. The positive supply voltage GVDDP-B selected for large RC time constant and / or high leakage current can be lower than the voltage selected for small RC time constant and / or low leakage current to compensate for slow charging response and / or fast current drop of each pixel PX. Likewise, the negative supply voltage GVDDN-B selected for large RC time constant and / or high leakage current can be higher than the voltage selected for small RC time constant and / or low leakage current. Relevant numerical examples can be shown in Table 2.

[0104] Table 2 illustrates another embodiment configuration of the display device 1. Table 2 updates the gamma voltage set VG(S:-S) frame by frame with modified supply voltages. The gray level of refreshed data can be "255" and the gray level of unrefreshed data can be "0". Polarity inversion occurs in full brush frames. Each cell in the table includes the polarity parameter, the voltage in the pixel PX capacitance, and the brightness of the pixel PX, where the symbols "+" and "-" represent positive polarity and negative polarity, respectively.

[0105] Table 2

[0106]

[0107]

[0108] The pixel array 100 includes gate lines GL(0) to GL(5), in which the gate lines GL(0) to GL(2) are located in the high refresh rate area, and the gate lines GL(3) to GL(5) are located in the low refresh rate area. The pixel array 100 sequentially receives the full-flush frame Fl, the partial-flush frame F2, the full-flush frame F3, and the partial-flush frame F4. The polarity inversion occurs during the full-flush frame F3.

[0109] In the full-flush frame Fl, the data voltage VD applied to the pixel PX has a positive polarity, and the gamma voltage generator 22 generates a set of gamma voltages VG21 (S:-S) using a positive supply voltage GVDDP of +5 V and a default gamma table. Then, the source driver 20 generates 6 pixel voltages Vpx using the set of gamma voltages VG21 (S:-S), and sequentially drives the source lines according to the 6 pixel voltages Vpx to update the data voltage VD of the pixels PX on the gate lines GL(0) to GL(5). The refresh data of the gray scale "255" corresponds to the data voltage VD of +5 V. When the voltage on the source line is +5 V, the capacitance of the pixels PX on the gate lines GL(0) to GL(5) is charged to +4.9 V due to the RC load effect, thus generating a uniform brightness of 300 nits.

[0110] In the partial-flush frame F2, the data voltage VD applied to the pixel PX has a positive polarity, and the gamma voltage generator 22 generates a set of gamma voltages VG22 (S:-S) using a positive supply voltage GVDDP of +4.9 V and the default gamma table. Then, the source driver 20 generates 3 pixel voltages Vpx using the set of gamma voltages VG22 (S:-S), and sequentially drives the source lines according to the 3 pixel voltages Vpx to update the data voltage VD of the pixels PX on the gate lines GL(0) to GL(2). The refresh data of the gray scale "255" corresponds to the data voltage VD of +4.9 V. When the +4.9 V voltage is applied to the source line, the capacitance of the pixels PX on the gate lines GL(0) to GL(2) maintains the +4.9 V voltage, thus maintaining the brightness at 300 nits. In the partial-flush frame F2, the gate lines GL(3) to GL(5) remain in the inactive state, and the update of the pixels PX on the gate lines GL(3) to GL(5) is stopped, so the capacitance of the pixels PX on the gate lines GL(3) to GL(5) continues to maintain the +4.9 V voltage, thus maintaining the brightness at 300 nits. Therefore, the pixels PX on the gate lines GL(0) to GL(5) maintain the uniform brightness of 300 nits.

[0111] In the full brush frame F3, the data voltage VD applied to the pixel PX has a negative polarity, and the gamma voltage generator 22 generates a set of gamma voltages VG23 (S:-S) using the negative supply voltage GVDDN (-5V) and the preset gamma table. Then, the source driver 20 generates 6 pixel voltages Vpx using the set of gamma voltages VG23 (S:-S), and sequentially drives the source lines according to the 6 pixel voltages Vpx to update the data voltage VD of the pixels PX on the gate lines GL(0) to GL(5). The data voltage VD corresponding to the refresh data of the gray scale "255" is -5V. When the voltage on the source line is -5V, the capacitance of the pixels PX on the gate lines GL(0) to GL(5) is charged to -4.9V due to the RC load effect, and thus a uniform brightness of 300 nits is generated.

[0112] In the partial brush frame F4, the data voltage VD applied to the pixel PX has a negative polarity, and the gamma voltage generator 22 generates a set of gamma voltages VG24 (S:-S) using the negative supply voltage GVDDN (-5V) and the preset gamma table. Then, the source driver 20 generates 3 pixel voltages Vpx using the set of gamma voltages VG24 (S:-S), and sequentially drives the source lines according to the 3 pixel voltages Vpx to update the data voltage VD of the pixels PX on the gate lines GL(0) to GL(2). In the partial brush frame F4, the gate lines GL(3) to GL(5) remain in the inactive state, and the update of the pixels PX on the gate lines GL(3) to GL(5) is stopped. The data voltage VD corresponding to the refresh data of the gray scale "255" is -4.9V. When the -4.9V voltage is applied to the source line, the capacitance of the pixels PX on the gate lines GL(0) to GL(2) remains at -4.9V, and thus the brightness is maintained at 300 nits. Therefore, the capacitance of the pixels PX on the gate lines GL(3) to GL(5) continues to remain at -4.9V, and the brightness is maintained at 300 nits. Thus, the pixels PX on the gate lines GL(0) to GL(5) maintain a uniform brightness of 300 nits.

[0113] Therefore, the embodiment in Table 2 can provide a consistent brightness of 300 nits in the frames F1 to F4.

[0114] In some embodiments, the gamma voltage generator 22 can update the gamma voltage set VG(S:-S) by selecting an appropriate gamma table. The gamma voltage generator can determine the gamma table according to the polarity parameter and the frame update type, and update the gamma voltage set according to the gamma table. Referring to Table 1, in frame Fl, the polarity parameter indicates positive polarity and the frame update type is a full brush frame. Thus, the gamma voltage generator 22 can generate the gamma voltage set according to gamma table Gamma-A. In frame F2, the polarity parameter indicates positive polarity and the frame update type is a partial brush frame. Thus, the gamma voltage generator 22 can generate the gamma voltage set according to gamma table Gamma-B, which is different from gamma table Gamma-A. In frame F3, the polarity parameter indicates negative polarity and the frame update type is a full brush frame. Thus, the gamma voltage generator 22 can generate the gamma voltage set according to gamma table Gamma-C. In frame F4, the polarity parameter indicates negative polarity and the frame update type is a partial brush frame. Thus, the gamma voltage generator 22 can generate the gamma voltage set according to gamma table Gamma-D, which is different from gamma table Gamma-C. The selection of the supply voltage and the gamma tables Gamma-A, Gamma-B, Gamma-C, and Gamma-D depends on the electrical characteristics of the pixel array 100, such as the RC load and the leakage current. In some embodiments, different gamma tables can be used for positive and negative polarities, as well as for full brush frames and partial brush frames. Numerical examples can be shown in Table 3. In one example, each gamma voltage in gamma table Gamma-C can be equal to the corresponding gamma voltage in gamma table Gamma-A minus 100 mV. In addition, each gamma voltage in gamma table Gamma-B can be equal to the corresponding gamma voltage in gamma table Gamma-A minus 50 mV, and each gamma voltage in gamma table Gamma-D can be equal to the corresponding gamma voltage in gamma table Gamma-C minus 50 mV.

[0115] Table 3 illustrates another embodiment configuration of the display device 1. Table 3 uses selected gamma tables to update the gamma voltage set VG(S:-S) frame by frame. The gray level of the refreshed data is "255" and the gray level of the unrefreshed data is "0". The polarity inversion occurs in the full brush frames. Each cell in the table includes the polarity parameter, the voltage in the pixel PX capacitance, and the brightness of the pixel PX, where the "signs" "+" and "-" represent positive polarity and negative polarity, respectively.

[0116] Table 3

[0117]

[0118]

[0119] Table 3 is similar to Table 2, but instead of modifying the supply voltage, a different gamma table is selected to update the gamma voltages VG(S:-S). The explanation is similar to that of Table 2 and is not repeated here for brevity. Thus, the embodiment of Table 3 can provide consistent 300 nits brightness in frames Fl to F4.

[0120] In some embodiments, the gamma voltage set VG(S:-S) can be updated according to the gate lines. Table 4 illustrates the configuration of display device 1 of another embodiment of the present application. Table 4 updates the gamma voltage set VG(S:-S) using the adjusting supply voltage approach, updating the gamma voltage set VG(S:-S) every 3 gate lines. The gray level of the refreshed data is "255" and the gray level of the un-refreshed data is "0". Each cell in the table includes the polarity parameter, the capacitor voltage of pixel PX, and the brightness of pixel PX, where the symbols "+" and "-" represent positive and negative polarities, respectively.

[0121] Table 4

[0122]

[0123]

[0124] The pixel array 100 includes gate lines GL(0) to GL(5), where gate lines GL(0) to GL(2) are in the high refresh rate region and gate lines GL(3) to GL(5) are in the low refresh rate region. The pixel array 100 receives full brush frame Fl, local brush frame F2, full brush frame F3, and local brush frame F4 in sequence. The polarity inversion occurs during the full brush frame F3.

[0125] During the gate lines GL(0) to GL(2) of the full brush frame Fl, the data voltage VD applied to the pixels PX has a positive polarity, and the gamma voltage generator 22 generates a set of gamma voltages VG41 (S:-S) using a positive supply voltage GVDDP of +5 V and a preset gamma table. Then, the source driver 20 generates three pixel voltages Vpx using the set of gamma voltages VG41 (S:-S) and sequentially drives the source lines according to the three pixel voltages Vpx to update the data voltage VD of the pixels PX on the gate lines GL(0) to GL(2). The refresh data of the gray scale "255" corresponds to a data voltage VD of +5 V. When the +5 V voltage is applied to the source lines, the capacitances of the pixels PX on the gate lines GL(0) to GL(2) are charged to a voltage of +4.9 V due to the RC load effect, and thus a luminance of 300 nits is generated. During the gate lines GL(3) to GL(5) of the full brush frame Fl, the data voltage VD applied to the pixels PX has a positive polarity, and the gamma voltage generator 22 generates a set of gamma voltages VG42 (S:-S) using a positive supply voltage GVDDP of +5.1 V and a preset gamma table. Then, the source driver 20 generates three pixel voltages Vpx using the set of gamma voltages VG42 (S:-S) and sequentially drives the source lines according to the three pixel voltages Vpx to update the data voltage VD of the pixels PX on the gate lines GL(3) to GL(5). The refresh data of the gray scale "255" corresponds to a data voltage VD of +5.1 V. When the +5.1 V voltage is applied to the source lines, the capacitances of the pixels PX on the gate lines GL(3) to GL(5) are charged to a voltage of +4.99 V due to the RC load effect, and thus a luminance of 310 nits is generated. Subsequently, the pixels PX on the gate lines GL(0) to GL(5) generate substantially uniform luminances between 300 and 310 nits.

[0126] During the gate line GL(0) to GL(2) of the local brush frame F2, the data voltage VD applied to the pixel PX has a positive polarity, and the gamma voltage generator 22 generates a gamma voltage set VG43(S:-S) using a positive supply voltage GVDDP of +5V and a preset gamma table. Then, the source driver 20 generates three pixel voltages Vpx using the gamma voltage set VG43(S:-S), and sequentially drives the source lines according to the three pixel voltages Vpx to update the data voltage VD of the pixel PX on the gate line GL(0) to GL(2). The refresh data of the gray scale "255" corresponds to the data voltage VD of +5V. When the voltage on the source line is +5V, the capacitance of the pixel PX on the gate line GL(0) to GL(2) is further charged to +4.99V, so that the brightness reaches 310 nits. In the local brush frame F2, the gate lines GL(3) to GL(5) remain in the inactive state, and the update of the pixel PX on the gate lines GL(3) to GL(5) is stopped. Subsequently, due to current leakage, the capacitance voltage of the pixel PX on the gate lines GL(3) to GL(5) drops to +4.9V, resulting in a brightness of 300 nits. Subsequently, the pixel PX on the gate lines GL(0) to GL(5) generates a substantially uniform brightness between 300 and 310 nits.

[0127] During the gate lines GL(0) to GL(2) of the full brush frame F3, the data voltage VD applied to the pixel PX has a negative polarity, and the gamma voltage generator 22 generates a set of gamma voltages VG44(S:-S) using the negative supply voltage GVDDN(-5V) and the preset gamma table. Then, the source driver 20 generates three pixel voltages Vpx using the set of gamma voltages VG44(S:-S) and sequentially drives the source lines according to the three pixel voltages Vpx to update the data voltage VD of the pixel PX on the gate lines GL(0) to GL(2). The data voltage VD corresponding to the refresh data of the gray scale "255" is -5V. When the voltage on the source line is -5V, the capacitance of the pixel PX on the gate lines GL(0) to GL(2) is charged to -4.9V due to the RC load effect, thereby generating a brightness of 300 nits. During the gate lines GL(3) to GL(5) of the full brush frame F3, the data voltage VD applied to the pixel PX has a negative polarity, and the gamma voltage generator 22 generates a set of gamma voltages VG45(S:-S) using the negative supply voltage GVDDN(-5.1V) and the preset gamma table. Then, the source driver 20 generates three pixel voltages Vpx using the set of gamma voltages VG45(S:-S) and sequentially drives the source lines according to the three pixel voltages Vpx to update the data voltage VD of the pixel PX on the gate lines GL(3) to GL(5). The data voltage VD corresponding to the refresh data of the gray scale "255" is -5.1V. When the voltage of -5.1V is applied to the source line, the capacitance of the pixel PX on the gate lines GL(3) to GL(5) is charged to a voltage of -4.99V due to the RC load effect, thereby generating a brightness of 300 nits. Subsequently, the pixel PX on the gate lines GL(0) to GL(5) generates substantially uniform brightness between 300 and 310 nits.

[0128] During the gate line GL(0) to GL(2) period of the local brush frame F4, the data voltage VD applied to the pixel PX has a negative polarity, and the gamma voltage generator 22 generates the gamma voltage set VG46(S:-S) using the negative supply voltage GVDDP of -5.1 V and the preset gamma table. Then, the source driver 20 generates three pixel voltages Vpx using the gamma voltage set VG46(S:-S) and sequentially drives the source lines according to the three pixel voltages Vpx to update the data voltage VD of the pixel PX on the gate line GL(0) to GL(2). The data voltage VD corresponding to the refresh data of the gray scale "255" is -5.1 V. When -5.1 V is added to the source line, the capacitance of the pixel PX on the gate line GL(0) to GL(2) is further charged to -4.99 V, so that the brightness reaches 310 nits. In the local brush frame F4, the gate line GL(3) to GL(5) remains in the inactive state, and the update of the pixel PX on the gate line GL(3) to GL(5) is stopped. Subsequently, due to current leakage, the capacitance voltage of the pixel PX on the gate line GL(3) to GL(5) drops to -4.9 V, resulting in a brightness of 300 nits. Subsequently, the pixel PX on the gate line GL(0) to GL(5) generates a substantially uniform brightness between 300 and 310 nits.

[0129] Therefore, the embodiment in Table 4 provides a uniform brightness between 300 and 310 nits between the F1 to F4 frames.

[0130] In some embodiments, the gamma voltage set can be updated before the gate line of the second region is activated, as shown in Table 5. In other embodiments, the gamma voltage set can be updated after the gate line of the second region is activated. Table 5 illustrates another embodiment configuration of the display device 1. Table 5 uses supply voltage modification to update the gate line-based gamma voltage set VG(S:-S). The gray scale of the refresh data is "255", and the gray scale of the non-refresh data is "0". Each cell in the table includes a polarity parameter, a capacitance voltage of the pixel PX, and a brightness of the pixel PX, where the symbols "+" and "-" represent positive polarity and negative polarity, respectively.

[0131] Table 5

[0132]

[0133] Table 5 is similar to Table 4, but the supply voltage is switched at gate line GL(2) instead of at gate line GL(3), which gives sufficient time for the voltage to transition from +5V to +5.1V, or from -5V to -5.1V, in preparation for updating the next line's gamma voltage VG(S:-S), smoothing the transition between the two sets of gamma voltage sets VG(S:-S). The description of Table 5 can be similar to that of Table 4, and is not repeated here for brevity. Thus, the embodiment shown in Table 5 can provide uniform luminance between 300 and 310 nits in frames F1 to F4.

[0134] In some embodiments, the polarity parameter can be inverted in a partial brush frame, in which a first region of the partial brush frame is refreshed and a second region is not refreshed. Table 6 illustrates the configuration of display device 1 in another embodiment of the present application. The gamma voltage sets VG(S:-S) are updated every frame. The symbols "+" and "-" represent positive and negative polarity, respectively.

[0135] Table 6

[0136]

[0137]

[0138] Pixel array 100 includes gate lines GL(0) to GL(19), in which gate lines GL(0) to GL(7) are in the high refresh rate region and gate lines GL(8) to GL(19) are in the low refresh rate region. Pixel array 100 receives full brush frame Fl, partial brush frame F2, full brush frame F3, and partial brush frame F4 in sequence. Polarity inversion occurs during partial brush frames F2 and F4.

[0139] In full brush frame Fl, data voltages VD applied to pixels PX have positive polarity, and gamma voltage generator 22 generates gamma voltage set VG71(S:-S) using supply voltage GVDDP-A and / or gamma table Gamma-A. Source driver 20 then generates 20 pixel voltages Vpx using gamma voltage set VG71(S:-S), and sequentially drives source lines according to the 20 pixel voltages Vpx to update data voltages VD of pixels PX on gate lines GL(0) to GL(19).

[0140] In the partial brush frame F2, the data voltage VD applied to the pixel PX has a negative polarity, and the gamma voltage generator 22 generates the gamma voltage set VG72 (S:-S) using the supply voltage GVDDN-B and / or the gamma table Gamma-B. Then, the source driver 20 generates 8 pixel voltages Vpx using the gamma voltage set VG72 (S:-S), and sequentially drives the source lines according to the 8 pixel voltages Vpx to update the data voltage VD of the pixels PX on the gate lines GL(0) to GL(7). In the partial brush frame F2, the gate lines GL(8) to GL(19) remain in the inactive state, and the update of the pixels PX on the gate lines GL(8) to GL(19) is stopped.

[0141] In the full brush frame F3, the data voltage VD applied to the pixel PX has a negative polarity, and the gamma voltage generator 22 generates the gamma voltage set VG73 (S:-S) using the supply voltage GVDDN-A and / or the gamma table Gamma-C. Then, the source driver 20 generates 20 pixel voltages Vpx using the gamma voltage set VG73 (S:-S), and sequentially drives the source lines according to the 20 pixel voltages Vpx to update the data voltage VD of the pixels PX on the gate lines GL(0) to GL(19).

[0142] In the partial brush frame F4, the data voltage VD applied to the pixel PX has a positive polarity, and the gamma voltage generator 22 generates the gamma voltage set VG74 (S:-S) using the supply voltage GVDDP-B and / or the gamma table Gamma-D. Then, the source driver 20 generates 8 pixel voltages Vpx using the gamma voltage set VG14 (S:-S), and sequentially drives the source lines according to the 8 pixel voltages Vpx to update the data voltage VD of the pixels PX on the gate lines GL(0) to GL(7). In the partial brush frame F4, the gate lines GL(8) to GL(19) remain in the inactive state, and the update of the pixels PX on the gate lines GL(8) to GL(19) is stopped.

[0143] Table 7 illustrates another embodiment configuration of the display device 1. The pixel array 100 can be updated by 1 full brush frame and 2 partial brush frames. The gamma voltage set VG (S:-S) is updated every frame. The symbols "+" and "-" represent the positive polarity and the negative polarity, respectively.

[0144] Table 7

[0145]

[0146]

[0147] The pixel array 100 includes gate lines GL(0) to GL(19), in which the gate lines GL(0) to GL(7) are located in the high refresh rate region, and the gate lines GL(8) to GL(19) are located in the low refresh rate region. The pixel array 100 sequentially receives the full brush frame Fl, the local brush frame F2, the local brush frame F3, the full brush frame F4, the local brush frame F5, and the local brush frame F6. The polarity inversion occurs during the full brush frame F4.

[0148] In the full brush frame Fl, the data voltage VD applied to the pixel PX has a positive polarity, and the gamma voltage generator 22 generates a gamma voltage set VG81 (S:-S) using a supply voltage GVDDP-A and / or a gamma table Gamma-A. The supply voltage GVDDP-A can be 5 V, and the gamma table Gamma-A can correspond to the curves 60p and 60n. Then, the source driver 20 generates 20 pixel voltages Vpx using the gamma voltage set VG81 (S:-S), and sequentially drives the source lines according to the 20 pixel voltages Vpx to update the data voltage VD of the pixels PX on the gate lines GL(0) to GL(19).

[0149] In the local brush frame F2, the data voltage VD applied to the pixel PX has a positive polarity, and the gamma voltage generator 22 generates a gamma voltage set VG82 (S:-S) using a supply voltage GVDDP-B and / or a gamma table Gamma-B. The supply voltage GVDDP-B can be 4.9 V, and the gamma table Gamma-B can correspond to the curves 62p and 62n. Then, the source driver 20 generates 8 pixel voltages Vpx using the gamma voltage set VG82 (S:-S), and sequentially drives the source lines according to the 8 pixel voltages Vpx to update the data voltage VD of the pixels PX on the gate lines GL(0) to GL(7). In the local brush frame F2, the gate lines GL(8) to GL(19) remain in the inactive state, and the updating of the pixels PX on the gate lines GL(8) to GL(19) is stopped.

[0150] In the local brush frame F3, the data voltage VD applied to the pixel PX has a positive polarity, and the gamma voltage generator 22 generates a gamma voltage set VG83 (S:-S) using a supply voltage GVDDP-C and / or a gamma table Gamma-C. The supply voltage GVDDP-C can be 4.8 V, and the gamma table Gamma-C can correspond to another set of gamma curves. Then, the source driver 20 generates 8 pixel voltages Vpx using the gamma voltage set VG83 (S:-S), and sequentially drives the source lines according to the 8 pixel voltages Vpx to update the data voltage VD of the pixels PX on the gate lines GL(0) to GL(7). In the local brush frame F3, the gate lines GL(8) to GL(19) remain in the inactive state, and the updating of the pixels PX on the gate lines GL(8) to GL(19) is stopped.

[0151] In the full brush frame F4, the data voltage VD applied to the pixel PX has a negative polarity, and the gamma voltage generator 22 generates a set of gamma voltages VG84(S:-S) using the supply voltage GVDDN-A and / or the gamma table Gamma-A. The supply voltage GVDDN-A can be -5V, and the gamma table Gamma-A can correspond to the curves 60p and 60n. Then, the source driver 20 generates 20 pixel voltages Vpx using the set of gamma voltages VG84(S:-S), and sequentially drives the source lines according to the 20 pixel voltages Vpx to update the data voltages VD of the pixels PX on the gate lines GL(0) to GL(19).

[0152] In the partial brush frame F5, the data voltage VD applied to the pixel PX has a negative polarity, and the gamma voltage generator 22 generates a set of gamma voltages VG85(S:-S) using the supply voltage GVDDN-B and / or the gamma table Gamma-B. The supply voltage GVDDN-B can be -4.9V, and the gamma table Gamma-B can correspond to the curves 62p and 62n. Then, the source driver 20 generates 8 pixel voltages Vpx using the set of gamma voltages VG85(S:-S), and sequentially drives the source lines according to the 8 pixel voltages Vpx to update the data voltages VD of the pixels PX on the gate lines GL(0) to GL(7). In the partial brush frame F5, the gate lines GL(8) to GL(19) remain in the inactive state, and the pixels PX on the gate lines GL(8) to GL(19) are stopped from being updated.

[0153] In the partial brush frame F6, the data voltage VD applied to the pixel PX has a negative polarity, and the gamma voltage generator 22 generates a set of gamma voltages VG86(S:-S) using the supply voltage GVDDN-C and / or the gamma table Gamma-C. The supply voltage GVDDN-C can be -4.8V, and the gamma table Gamma-C can correspond to a set of gamma curves. Then, the source driver 20 generates 8 pixel voltages Vpx using the set of gamma voltages VG86(S:-S), and sequentially drives the source lines according to the 8 pixel voltages Vpx to update the data voltages VD of the pixels PX on the gate lines GL(0) to GL(7). In the partial brush frame F6, the gate lines GL(8) to GL(19) remain in the inactive state, and the pixels PX on the gate lines GL(8) to GL(19) are stopped from being updated.

[0154] Table 8 illustrates the configuration of the display device 1 of another embodiment of the present application. The pixel array 100 can be updated by 1 full brush frame and 2 partial brush frames. The set of gamma voltages VG(S:-S) is updated in each frame. The symbols "+" and "-" represent the positive polarity and the negative polarity, respectively.

[0155] Table 8

[0156]

[0157]

[0158] The pixel array 100 includes gate lines GL(0) to GL(5), in which the gate lines GL(0) to GL(2) are located in the high refresh rate area, and the gate lines GL(3) to GL(5) are located in the low refresh rate area. The pixel array 100 sequentially receives the full brush frame Fl, the local brush frame F2, the local brush frame F3, the full brush frame F4, the local brush frame F5, and the local brush frame F6. The polarity inversion occurs during the local brush frames F2 and F3, the full brush frame F4, the local brush frames F5 and F6.

[0159] In the full brush frame Fl, the data voltage VD applied to the pixel PX has a positive polarity, and the gamma voltage generator 22 generates a gamma voltage set VG91(S:-S) using a supply voltage GVDDP of +5V and a preset gamma table. Then, the source driver 20 generates 6 pixel voltages Vpx using the gamma voltage set VG91(S:-S), and sequentially drives the source lines according to the 6 pixel voltages Vpx to update the data voltage VD of the pixels PX on the gate lines GL(0) to GL(5). The refresh data of the gray scale "255" corresponds to the data voltage VD of +5V. When the +5V voltage is applied to the source line, the capacitance of the pixel PX on the gate lines GL(0) to GL(5) is charged to the +4.9V voltage due to the RC load effect, and thus a brightness of 300 nits is generated.

[0160] In the local brush frame F2, the data voltage VD applied to the pixel PX has a negative polarity, and the gamma voltage generator 22 generates a gamma voltage set VG92(S:-S) using a supply voltage GVDDN of -4.8V and a preset gamma table. Then, the source driver 20 generates 3 pixel voltages Vpx using the gamma voltage set VG92(S:-S), and sequentially drives the source lines according to the 3 pixel voltages Vpx to update the data voltage VD of the pixels PX on the gate lines GL(0) to GL(2). In the local brush frame F2, the gate lines GL(3) to GL(5) remain in the inactive state, and the update of the pixels PX on the gate lines GL(3) to GL(5) is stopped. The data voltage VD corresponding to the refresh data of the gray scale "255" is -4.8V. When the -4.8V voltage is applied to the source line, the capacitance of the pixel PX on the gate lines GL(0) to GL(2) is charged to -4.8V, and a brightness of 290 nits is generated. In the local brush frame F2, the gate lines GL(3) to GL(5) remain in the inactive state, and the update of the pixels PX on the gate lines GL(3) to GL(5) is stopped. Subsequently, the capacitance voltage of the pixels PX on the gate lines GL(3) to GL(5) decays to +4.8V, and thus a brightness of 290 nits is generated. Therefore, the pixels PX on the gate lines GL(0) to GL(5) can maintain a uniform brightness of 290 nits.

[0161] In the local brush frame F3, the data voltage VD applied to the pixel PX has a positive polarity, and the gamma voltage generator 22 generates a gamma voltage set VG93(S:-S) using a supply voltage GVDDP of +4.7 V and a preset gamma table. Then, the source driver 20 generates three pixel voltages Vpx using the gamma voltage set VG93(S:-S), and sequentially drives the source lines according to the three pixel voltages Vpx to update the data voltage VD of the pixel PX on the gate lines GL(0) to GL(2). In the local brush frame F3, the gate lines GL(3) to GL(5) remain in a disabled state, and the update of the pixel PX on the gate lines GL(3) to GL(5) is stopped. The data voltage VD corresponding to the refresh data of the gray scale "255" is +4.7 V. When the +4.7 V voltage is applied to the source line, the capacitance in the pixel PX on the gate lines GL(0) to GL(2) is charged to the +4.7 V voltage, and a brightness of 280 nits is generated. In the local brush frame F3, the gate lines GL(3) to GL(5) remain in a disabled state, and the update of the pixel PX on the gate lines GL(3) to GL(5) is stopped. Subsequently, the capacitance voltage of the pixel PX on the gate lines GL(3) to GL(5) decays to +4.7 V, and a brightness of 280 nits is generated. Therefore, the pixel PX on the gate lines GL(0) to GL(5) maintains a uniform brightness of 280 nits.

[0162] In the local brush frame F3, the data voltage VD applied to the pixel PX has a positive polarity, and the gamma voltage generator 22 generates a gamma voltage set VG93(S:-S) using a supply voltage GVDDP of +4.7 V and a preset gamma table. Then, the source driver 20 generates three pixel voltages Vpx using the gamma voltage set VG93(S:-S), and sequentially drives the source lines according to the three pixel voltages Vpx to update the data voltage VD of the pixel PX on the gate lines GL(0) to GL(2). In the local brush frame F3, the gate lines GL(3) to GL(5) remain in a disabled state, and the update of the pixel PX on the gate lines GL(3) to GL(5) is stopped. The data voltage VD corresponding to the refresh data of the gray scale "255" is +4.7 V. When the +4.7 V voltage is applied to the source line, the capacitance in the pixel PX on the gate lines GL(0) to GL(2) is charged to the +4.7 V voltage, and a brightness of 280 nits is generated. In the local brush frame F3, the gate lines GL(3) to GL(5) remain in a disabled state, and the update of the pixel PX on the gate lines GL(3) to GL(5) is stopped. Subsequently, the capacitance voltage of the pixel PX on the gate lines GL(3) to GL(5) decays to +4.7 V, and a brightness of 280 nits is generated. Therefore, the pixel PX on the gate lines GL(0) to GL(5) maintains a uniform brightness of 280 nits.

[0163] In the local brush frame F5, the data voltage VD applied to the pixel PX has a positive polarity, and the gamma voltage generator 22 generates the gamma voltage set VG95(S:-S) using the supply voltage GVDDP of +4.8 V and the preset gamma table. Then, the source driver 20 generates three pixel voltages Vpx using the gamma voltage set VG95(S:-S), and sequentially drives the data voltage VD of the pixel PX on the source line to update the gate lines GL(0) to GL(2). In the local brush frame F5, the gate lines GL(3) to GL(5) remain in the inactive state, and the update of the pixel PX on the gate lines GL(3) to GL(5) is stopped. The data voltage VD corresponding to the refresh data of the gray scale "255" is +4.8 V. When the +4.8 V voltage is applied to the source line, the capacitance of the pixel PX on the gate lines GL(0) to GL(2) is charged to the +4.8 V voltage, and a luminance of 290 nits is generated. In the local brush frame F5, the gate lines GL(3) to GL(5) remain in the inactive state, and the update of the pixel PX on the gate lines GL(3) to GL(5) is stopped. Subsequently, the capacitance voltage of the pixel PX on the gate lines GL(3) to GL(5) decays to +4.8 V, and a luminance of 290 nits is generated. Thus, the pixel PX on the gate lines GL(0) to GL(5) maintains a uniform luminance of 290 nits.

[0164] In the local brush frame F6, the data voltage VD applied to the pixel PX has a negative polarity, and the gamma voltage generator 22 generates the gamma voltage set VG96(S:-S) using the supply voltage GVDDN of -4.7 V and the preset gamma table. Then, the source driver 20 generates three pixel voltages Vpx using the gamma voltage set VG96(S:-S), and sequentially drives the data voltage VD of the pixel PX on the source line to update the gate lines GL(0) to GL(2). In the local brush frame F6, the gate lines GL(3) to GL(5) remain in the inactive state, and the update of the pixel PX on the gate lines GL(3) to GL(5) is stopped. The data voltage VD corresponding to the refresh data of the gray scale "255" is -4.7 V. When the -4.7 V voltage is applied to the source line, the capacitance of the pixel PX on the gate lines GL(0) to GL(2) is charged to the -4.7 V voltage, and a luminance of 280 nits is generated. In the local brush frame F6, the gate lines GL(3) to GL(5) remain in the inactive state, and the update of the pixel PX on the gate lines GL(3) to GL(5) is stopped. Subsequently, the capacitance voltage of the pixel PX on the gate lines GL(3) to GL(5) decays to -4.7 V, and a luminance of 280 nits is generated. Thus, the pixel PX on the gate lines GL(0) to GL(5) maintains a uniform luminance of 280 nits.

[0165] Thus, the example in Table 4 provides a consistent luminance in the entire screen of the frames F1 to F6, ranging between 300 nits and 280 nits.

[0166] For OLED display panel 10, gamma voltage generator 22 can determine frame update type according to first refresh rate and second refresh rate, and update gamma voltage set VG(S:-S) according to frame update type. As shown in Table 9, the method of updating gamma voltage set VG(S:-S) can be similar to that of liquid crystal display panel 10, however, without considering polarity parameter. In Table 9, frames F1 and F3 are full brush frames, and gamma voltage set VG(S:-S) can be generated according to supply voltage GVDDP-A and / or gamma table Gamma-A. Frames F2 and F4 are partial brush frames, and gamma voltage set VG(S:-S) can be generated according to supply voltage GVDDP-B and / or gamma table Gamma-B.

[0167] Table 9

[0168] F1 (FR) F2 (PR) F3 (FR) F4 (PR) GVDDP GVDDP-A GVDDP-B GVDDP-A GVDDP-B Gamma Table Gamma-A Gamma-B Gamma-A Gamma-B

[0169] Then, source driver 20 can generate pixel voltage Vpx according to pixel data Dpx and gamma voltage set VG(S:-S), reset first region before driving source line according to pixel voltage Vpx, and drive source line according to pixel voltage Vpx. Frame update type can be full refresh or partial refresh.

[0170] In some embodiments, gamma voltage generator 22 can update gamma voltage set VG(S:-S) by modifying positive supply voltage GVDDP / negative supply voltage GVDDN. Driving circuit 12 can determine frame update type according to first refresh rate and second refresh rate, and gamma voltage generator 22 can determine supply voltage according to frame update type, and update gamma voltage set according to supply voltage. In some embodiments, gamma voltage generator 22 can update gamma voltage set VG(S:-S) by selecting appropriate gamma table. Driving circuit 12 can determine frame update type according to first refresh rate and second refresh rate, and gamma voltage generator 22 can generate gamma table according to frame update type, and update gamma voltage set according to gamma table.

[0171] Although embodiments of the present application demonstrate multi-region frame update scheme operating at two refresh rates, one skilled in the art would understand that, by similar principles, multi-region frame update scheme can be extended to more than two refresh rates.

[0172] According to the method and driving circuit of various embodiments of the present application, by dynamically adjusting gamma table or supply voltage GVDDP / GVDDN according to frame type, region boundary, polarity type and other related parameters, luminance level between high refresh rate region and low refresh rate region is coordinated, and visual inconsistency caused by luminance difference between different regions is reduced.

[0173] The above merely provides the preferred embodiments of the present application, and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the principles and technical scope of the present application shall fall into the scope of the present application.

Claims

1. A method for driving a source line of a display panel, wherein the display panel comprises a first area and a second area, wherein: The method comprises: updating a gamma voltage set according to at least a first refresh rate of the first region and a second refresh rate of the second region; generating a pixel voltage according to the pixel data and the gamma voltage set; and A source line is driven according to the pixel voltage.

2. The method according to claim 1, wherein Updating the gamma voltage set according to at least the first refresh rate of the first region and the second refresh rate of the second region includes: Determining a frame update type according to the first refresh rate and the second refresh rate; and The gamma voltage set is updated according to a polarity parameter and the frame update type.

3. The method according to claim 2, wherein Updating the gamma voltage set according to the polarity parameter and the frame update type includes: determining a supply voltage according to the polarity parameter and the frame update type; and The gamma voltage set is updated according to the supply voltage.

4. The method according to claim 2, wherein Updating the gamma voltage set according to the polarity parameter and the frame update type includes: determining a gamma table according to the polarity parameter and the frame update type; and The gamma voltage set is updated according to the gamma table.

5. The method according to claim 1, wherein The first refresh rate exceeds the second refresh rate.

6. The method according to claim 1, wherein The gamma voltage set is updated based on the frame.

7. The method according to claim 1, wherein The gamma voltage sets are updated according to the gate lines.

8. The method according to claim 7, wherein The gamma voltage set is updated before a gate line of the second region is activated.

9. The method according to claim 1, wherein The first area and the second area are defined by a clock signal.

10. The method according to claim 1, wherein The method further comprises: Before driving the source line according to the pixel voltage, the first region is reset.

11. The method according to claim 10, wherein Updating the gamma voltage set according to at least the first refresh rate of the first region and the second refresh rate of the second region includes: determining a frame update type according to the first refresh rate and the second refresh rate; Determining a supply voltage according to the frame update type; and The gamma voltage set is updated according to the supply voltage.

12. The method according to claim 10, wherein Updating the gamma voltage set according to at least the first refresh rate of the first region and the second refresh rate of the second region includes: determining a frame update type according to the first refresh rate and the second refresh rate; generating a gamma table according to the frame update type; and The gamma voltage set is updated according to the gamma table.

13. A driving circuit for driving a source line of a display panel, wherein the display panel comprises a first area and a second area, wherein: The driving circuit includes: a gamma voltage generator that updates a gamma voltage set according to at least a first refresh rate of the first region and a second refresh rate of the second region; and A source driver is coupled to the gamma voltage generator, generates a pixel voltage according to pixel data and the gamma voltage set, and drives a source line according to the pixel voltage.

14. The driving circuit according to claim 13, wherein: The driving circuit determines a frame update type according to the first refresh rate and the second refresh rate; and The gamma voltage generator updates the gamma voltage set according to a polarity parameter and the frame update type.

15. The driving circuit according to claim 14, wherein: The gamma voltage generator determines a supply voltage according to the polarity parameter and the frame update type, and updates the gamma voltage set according to the supply voltage.

16. The driving circuit according to claim 14, wherein: The gamma voltage generator determines a gamma table according to the polarity parameter and the frame update type, and updates the gamma voltage set according to the gamma table.

17. The driving circuit according to claim 13, wherein: The first refresh rate exceeds the second refresh rate.

18. The driving circuit according to claim 13, wherein: The gamma voltage set is updated based on the frame.

19. The driving circuit according to claim 13, wherein: The gamma voltage sets are updated according to the gate lines.

20. The driving circuit according to claim 19, wherein: The gamma voltage set is updated before a gate line of the second region is activated.

21. The driving circuit according to claim 13, wherein: The first area and the second area are defined by a clock signal.

22. The driving circuit according to claim 13, wherein: Before driving the source line according to the pixel voltage, the driving circuit further resets the first region.

23. The driving circuit according to claim 22, wherein: The driving circuit determines a frame update type according to the first refresh rate and the second refresh rate; and The gamma voltage generator determines a supply voltage according to the frame update type, and updates the gamma voltage set according to the supply voltage.

24. The driving circuit according to claim 22, wherein: The driving circuit determines a frame update type according to the first refresh rate and the second refresh rate; and The gamma voltage generator generates a gamma table according to the frame update type, and updates the gamma voltage set according to the gamma table.

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