Driving circuit, display driving chip and electronic equipment

Abstract

The invention discloses a driving circuit, a display driving chip and electronic equipment, and belongs to the technical field of electronics. The driving circuit comprises a control module and an output module, the control module is connected with the output module, and the output module is connected with the display panel. And the control module is used for generating a control signal under the condition that the absolute value of a first voltage difference value between the input first signal and the second signal output by the output module is greater than a reference threshold value. The output module is used for outputting a driving signal according to the control signal, the absolute value of a second voltage difference value between the first signal and the driving signal is smaller than the absolute value of the first voltage difference value, and the driving signal is used for driving pixels on the display panel to emit light. The control signal is automatically generated through the control module, so that the voltage of the signal output by the output module is rapidly controlled, adaptive enhancement of the slew rate of the driving circuit is realized, pixels on the display panel can be rapidly driven to emit light, and a relatively high refresh rate is provided.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of electronics, and particularly relate to a driving circuit, a display driving chip and an electronic device. BACKGROUND

[0002] With the continuous development of electronic technology, users have higher and higher requirements for the refresh rate of display panels. How to improve the refresh rate of display panels has become a problem worthy of attention. SUMMARY

[0003] The present application provides a driving circuit, a display driving chip and an electronic device to improve the refresh rate of the display panel. The technical solution includes the following contents.

[0004] In one aspect, a driving circuit is provided, which includes a control module and an output module, the control module is connected with the output module, and the output module is connected with a display panel; the control module is configured to generate a control signal in a case where an absolute value of a first voltage difference between an input first signal and a second signal output by the output module is greater than a reference threshold value; the output module is configured to output a driving signal according to the control signal, an absolute value of a second voltage difference between the first signal and the driving signal is less than the absolute value of the first voltage difference, and the driving signal is used to drive a pixel on the display panel to emit light.

[0005] In an example embodiment, the control module includes a first control unit and a second control unit, the first control unit and the second control unit are respectively connected with the output module, and the first voltage difference is a voltage difference obtained by subtracting a voltage of the second signal from a voltage of the first signal. The first control unit is configured to generate a control signal indicating voltage increase according to the first voltage difference. The output module is configured to output the driving signal according to the control signal indicating voltage increase, the driving signal being a third signal, and a voltage of the third signal being greater than a voltage of the second signal. The second control unit is configured to generate a control signal indicating voltage decrease according to the first voltage difference. The output module is configured to output the driving signal according to the control signal indicating voltage decrease, the driving signal being a fourth signal, and a voltage of the fourth signal being less than the voltage of the second signal.

[0006] In an example embodiment, the output module includes an output terminal, the output terminal is used for the output module to output the second signal, the third signal or the fourth signal; in a case where the third signal is output through the output terminal, the voltage of the third signal is used to charge a load capacitance on the display panel to drive the load capacitance corresponding pixel to emit light and increase brightness; in a case where the fourth signal is output through the output terminal, the voltage of the fourth signal is used to discharge the load capacitance on the display panel to drive the load capacitance corresponding pixel to emit light and decrease brightness.

[0007] In the example embodiment, the first control unit comprises a first trigger unit, a first inverter and a first generating unit, the first trigger unit is connected with the first inverter, the first inverter is further connected with the first generating unit, and the first generating unit is further connected with a first current source grounded and an output module respectively. The first trigger unit is configured to generate a first trigger signal according to the first voltage difference; the first inverter is configured to generate a first inverted signal according to the first trigger signal; and the first generating unit is configured to generate a control signal indicating voltage increase according to the first inverted signal.

[0008] In the example embodiment, the gear of the first current source is adjustable, and the gear of the first current source is used to control the generation speed of the control signal indicating voltage increase.

[0009] In the example embodiment, the first trigger signal is generated in the case that a transistor included in the first trigger unit is in a conducting state, and a source of the transistor included in the first trigger unit is connected with a substrate.

[0010] In the example embodiment, the second control unit comprises a second trigger unit, a second inverter and a second generating unit, the second trigger unit is connected with the second inverter, the second inverter is further connected with the second generating unit, and the second generating unit is further connected with a second current source connected with a positive power supply and an output module respectively. The second trigger unit is configured to generate a second trigger signal according to the first voltage difference; the second inverter is configured to generate a second inverted signal according to the second trigger signal; and the second generating unit is configured to generate a control signal indicating voltage decrease according to the second inverted signal.

[0011] In the example embodiment, the gear of the second current source is adjustable, and the gear of the second current source is used to control the generation speed of the control signal indicating voltage decrease.

[0012] In the example embodiment, the second trigger signal is generated in the case that a transistor included in the second trigger unit is in a conducting state, and a source of the transistor included in the second trigger unit is connected with a well potential.

[0013] In another aspect, a display driving chip is provided, which comprises any one of the driving circuits described above.

[0014] In another aspect, an electronic device is provided, which comprises a display panel and the display driving chip described above.

[0015] The technical scheme provided in the application brings at least the following beneficial effects:

[0016] The control module automatically generates a control signal to quickly control the voltage of the signal output by the output module, thereby achieving adaptive enhancement of the slew rate of the driving circuit, quickly driving the pixels on the display panel to emit light, and providing a high refresh rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 1 is a schematic structural diagram of a display driver integrated circuit (DDIC) provided in an embodiment of the present application;

[0019] Figure 2 This is a schematic structural diagram of a push-pull amplifier provided in an embodiment of the present application;

[0020] Figure 3 This is a schematic structural diagram of another push-pull amplifier provided in an embodiment of the present application;

[0021] Figure 4 This is a structural diagram of a driving circuit and a display panel provided in an embodiment of the present application;

[0022] Figure 5 This is a schematic structural diagram of another driving circuit provided in an embodiment of the present application;

[0023] Figure 6 is a structural diagram of another driving circuit provided in an embodiment of the present application;

[0024] Figure 7 1 is a schematic diagram of the shutdown time of a self slew rate boost (Self_SRB) function provided in an embodiment of the present application;

[0025] Figure 8 is a structural diagram of another driving circuit provided in an embodiment of the present application;

[0026] Figure 9 is a schematic diagram of a deep n-well provided in an embodiment of the present application;

[0027] Figure 10 This is a schematic diagram of the gear positions of a first current source and a second current source provided in an embodiment of the present application;

[0028] Figure 11 This is a schematic diagram of voltage changes at different positions in a driving circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0030] With the development of electronic technology and integrated circuit technology, the scale of use of electronic devices such as mobile phones, tablets (pads), personal computers (PCs), smart watches and smart car-mounted devices (also known as mobile terminal products) has ushered in explosive growth. The electronic device is provided with a display panel, and the refresh rate is a performance indicator of the display panel. The refresh rate refers to the number of times the display panel refreshes the image per second. For example, a refresh rate of 120 hertz (Hz) means that the display panel refreshes the image 120 times per second, or the display panel displays the image 120 times per second. The higher the refresh rate, the more times the display panel refreshes the image per second, the better the performance of the display panel, and the smoother the visual experience for the user. Therefore, how to improve the refresh rate of the display panel has become an issue worthy of attention.

[0031] The display panel relies on a display driver integrated circuit (DDIC) to display images. Figure 1 As shown, the DDIC integrates various devices such as a high-speed data interface, an oscillator, a timing control (TCON) module, a gate driver module, and a source driver module.

[0032] The high-speed data interface is used to receive data and a first clock signal sent by a host (eg, a processor in an electronic device). The first clock signal is used for clock synchronization between the host and the high-speed data interface.

[0033] The TCON module is used to receive data sent by the high-speed data interface and a second clock signal (also called a system clock) sent by the oscillator, and generate a control signal based on the received data and the second clock signal. The control signal includes a gate control signal and a source control signal.

[0034] The gate drive module is used to receive the gate control signal sent by the TCON module, and control each pixel row on the display panel to be in the on state or the off state through the gate line according to the received gate control signal.

[0035] The source driver module is used to receive the source control signal sent by the TCON module, and control the display state of each pixel column on the display panel through the data line according to the received source control signal, such as the brightness when the display state is emitting light.

[0036] For any one pixel on the display panel, when the pixel row where the pixel is located is in the on state, the pixel emits light according to the display state of the pixel column where the pixel is located. Thus, through cooperation between the gate drive module and the source drive module, the display state of any one pixel can be controlled, and thus the display panel can be controlled to display an image.

[0037] Exemplarily, a power supply (not shown in the figure) is integrated in the DDIC, and the power supply is used to supply power to various devices integrated in the DDIC. The voltage required by the power supply to supply power to different devices can be the same or different, which is not limited in the embodiments of the present application. Figure 1

[0038] Optionally, the source drive module includes a plurality of channels, and the plurality of channels correspond to each pixel column on the display panel in one-to-one correspondence. Each channel includes a digital-to-analog converter (DAC) and a drive circuit. The source drive signal described above includes a digital signal, the DAC is used to convert the digital signal into a first analog signal (for example, an analog voltage, unit: volt (V)), and input the first analog signal to the drive circuit. The drive circuit is used to receive the first analog signal, output a second analog signal according to the first analog signal, and transmit the second analog signal to the load capacitor corresponding to the pixel on the display panel through the data line, so as to charge or discharge the load capacitor, thereby realizing control of the display state of the pixel. When the second analog signal is used to charge the load capacitor, the brightness of the pixel emitting light can be increased. When the second analog signal is used to discharge the load capacitor, the brightness of the pixel emitting light can be reduced.

[0039] In addition, the faster the speed of charging or discharging the load capacitor by the drive circuit, the faster the speed of controlling the display state of the pixel, so that the refresh rate of the display panel is higher. The slower the speed of charging or discharging the load capacitor by the drive circuit, the slower the speed of controlling the display state of the pixel, so that the refresh rate of the display panel is lower. Therefore, in order to improve the refresh rate of the display panel, it is necessary to improve the speed of charging or discharging the load capacitor by the drive circuit, and the process of charging and discharging the load capacitor by the drive circuit is described below.

[0040] Exemplarily, the drive circuit includes an output module, which is an operational amplifier, for example, a push-pull amplifier, including but not limited to a class A amplifier or a class B amplifier.

[0041] As Figure 2 ​As shown, the push-pull amplifier includes a positive input terminal VIN+, a negative input terminal VIN-, an output terminal VOUT, a voltage supply for positive polarity (VSP, hereinafter referred to as the positive power supply), and an analog voltage supply substrate (AVSS, hereinafter referred to as the analog ground). VIN+ is connected to the DAC and is used to receive the first analog signal, while VOUT is used to output the second analog signal. VOUT is connected to VIN-, a connection also known as a unity-gain connection. VOUT is also connected to the load capacitor via the data line to charge or discharge the load capacitor.

[0042] For example, Figure 2 As shown, the push-pull amplifier also includes: a floating voltage source (at Figure 2 Indicated as F), capacitor (in Figure 2 In the figure, CC1 and CC2 are shown), P-type transistors and N-type transistors. Optionally, the P-type transistors are, for example, P-channel metal-oxide-semiconductor field-effect transistors (P MOSFET, PMOS). Figure 2 The N-type transistor is, for example, an N-channel metal-oxide-semiconductor field-effect transistor (N MOSFET, NMOS). Figure 2 Shown in the figure is NM1.

[0043] See also Figure 3 , Figure 3 yes Figure 2 The equivalent circuit diagram of . Among them, Figure 3 The connection relationship between VOUT and VIN- is not shown to avoid redundancy. Figure 2 The components VIN+, VIN-, current source X, current source Y and floating voltage source F are: Figure 3 The more detailed structures of these devices are shown in FIG. 3 , which are composed of transistors and circuits and will not be described in detail here. Figure 3 The V BIAS2 To V BIAS5 The bias voltage is provided by the bias voltage module in the display driver.

[0044] according to Figure 2 and Figure 3It can be known that the source of the PM1 is connected with the positive power supply VSP, and the drain of the PM1 is connected with the VOUT. The gate of the PM1 is connected with the positive input terminal VIN+ through the transistor structure shown in the figure, and the gate of the PM1 is connected with the floating voltage source F. The gate of the PM1 is also connected with the positive power supply VSP through the current source X. The capacitor CC1 is connected in parallel with the gate and the drain of the PM1. Figure 3 It can be known that the source of the PM1 is connected with the positive power supply VSP, and the drain of the PM1 is connected with the VOUT. The gate of the PM1 is connected with the positive input terminal VIN+ through the transistor structure shown in the figure, and the gate of the PM1 is connected with the floating voltage source F. The gate of the PM1 is also connected with the positive power supply VSP through the current source X. The capacitor CC1 is connected in parallel with the gate and the drain of the PM1.

[0045] During the process of charging the load capacitor, the voltage of the first analog signal input by the positive input terminal VIN+ increases, so that the PM1 is turned on. The current flows from the positive power supply VSP to the VOUT through the source and the drain of the PM1, and the voltage of the second analog signal output by the VOUT increases, so as to charge the load capacitor. Since the gate and the drain of the PM1 are connected in parallel with the capacitor CC1, a loop is formed with the PM1, and thus the voltage of the second analog signal output by the VOUT will slowly increase under the influence of the capacitor CC1, which results in a slow charging speed of the load capacitor. As known from the foregoing description, this will result in a low refresh rate of the display panel.

[0046] According to Figure 2 and Figure 3 It can be known that the source of the PM1 is connected with the positive power supply VSP, and the drain of the PM1 is connected with the VOUT. The gate of the PM1 is connected with the positive input terminal VIN+ through the transistor structure shown in the figure, and the gate of the PM1 is connected with the floating voltage source F. The gate of the PM1 is also connected with the positive power supply VSP through the current source X. The capacitor CC1 is connected in parallel with the gate and the drain of the PM1. Figure 3 It can be known that the source of the PM1 is connected with the positive power supply VSP, and the drain of the PM1 is connected with the VOUT. The gate of the PM1 is connected with the positive input terminal VIN+ through the transistor structure shown in the figure, and the gate of the PM1 is connected with the floating voltage source F. The gate of the PM1 is also connected with the positive power supply VSP through the current source X. The capacitor CC1 is connected in parallel with the gate and the drain of the PM1.

[0047] During the process of charging the load capacitor, the voltage of the first analog signal input by the positive input terminal VIN+ increases, so that the PM1 is turned on. The current flows from the positive power supply VSP to the VOUT through the source and the drain of the PM1, and the voltage of the second analog signal output by the VOUT increases, so as to charge the load capacitor. Since the gate and the drain of the PM1 are connected in parallel with the capacitor CC1, a loop is formed with the PM1, and thus the voltage of the second analog signal output by the VOUT will slowly increase under the influence of the capacitor CC1, which results in a slow charging speed of the load capacitor. As known from the foregoing description, this will result in a low refresh rate of the display panel.

[0048] In addition, the floating voltage source F is also connected with the positive power supply VSP through the current source X, and the floating voltage source F is also connected with the analog ground AVSS through the current source Y. Thus, during the process of charging or discharging the load capacitor, the floating voltage source F is used to avoid the PM1 and the NM1 being turned on at the same time. Or in other words, the floating voltage source F is used to make the overlap length between the on period of the PM1 and the on period of the NM1 be within a tolerable length range.

[0049] In summary, Figure 2and Figure 3 The structure shown includes: a rail-to-rail folded cascode input stage (referring to the positive input end VIN+ being connected to the gate of PM1 and the gate of NM1 respectively), a common gate of a series floating voltage source structure (referring to the floating voltage source F being connected to the gate of PM1 and the gate of NM1 respectively), and a power output stage (referring to the drain of PM1 and the drain of NM1 being connected to the output end VOUT respectively).

[0050] In the related art, the bias current in the driving circuit is less than or equal to 1 microampere (uA) to reduce the power consumption of the driving circuit. In this regard, the TCON module controls the bias current in the driving circuit by increasing the size of the bias current to increase the refresh rate of the display panel. Specifically, when the source control signal sent to the source driving module is switched (for example, has a large fluctuation), the TCON module synchronously controls the bias current in the driving circuit included in the source driving module to increase, so as to increase the speed of charging or discharging the load capacitance and increase the refresh rate of the display panel. When the source control signal sent to the source driving module is stable (for example, has a small fluctuation), the TCON module synchronously controls the bias current in the driving circuit included in the source driving module to decrease, so as to reduce the power consumption of the driving circuit.

[0051] However, the solution in the related art requires fine synchronization control in the time dimension by the TCON module, which not only depends on the TCON module but also has high design complexity. Moreover, since the bias current in the driving circuit is increased, additional power consumption is generated. The longer the bias current is increased, the greater the additional power consumption is generated.

[0052] In this regard, an embodiment of the present application provides a driving circuit which adds a control module to the output module described above, and controls the output module through the control module to adaptively enhance the slew rate of the output module. The slew rate refers to the maximum voltage change rate that can be output per unit time. The greater the slew rate, the faster the charging and discharging speed of the load capacitance, and the higher the refresh rate of the display panel. Therefore, by enhancing the slew rate, the refresh rate of the display panel is improved, and the total power consumption of the driving circuit is reduced without depending on the TCON module and having low design complexity.

[0053] It should be noted that, compared with the additional power consumption generated by increasing the bias current in the related art, the additional power consumption generated by the control module added in the embodiment of the present application is lower. That is, although the control module added in the embodiment of the present application generates additional power consumption, since it is not necessary to increase the bias current in the driving circuit as in the related art, the additional power consumption saved is more considerable, thereby reducing the total power consumption of the driving circuit.

[0054] Exemplarily, the driving circuit provided by the embodiment of the present application is applied to a source driving module. The source driving module includes a plurality of channels, each of which corresponds to a pixel column on the display panel. Some or all of the plurality of channels each include the driving circuit provided by the embodiment of the present application.

[0055] As shown in Figure 4 The driving circuit provided by the embodiment of the present application includes a control module and an output module. The control module is connected with the output module, and the output module is connected with the display panel. The control module is configured to generate a control signal in a case where an absolute value of a first voltage difference between an input first signal and a second signal output by the output module is greater than a reference threshold. The output module is configured to output a driving signal according to the control signal. An absolute value of a second voltage difference between the first signal and the driving signal is less than the absolute value of the first voltage difference. The driving signal is used to drive a pixel on the display panel to emit light.

[0056] The control module can detect the input first signal and the second signal output by the output module. The voltage difference between the voltage of the first signal and the voltage of the second signal is recorded as the first voltage difference. In a case where the absolute value of the first voltage difference is greater than the reference threshold, the control module automatically generates the control signal. Accordingly, according to the control signal, the output module quickly adjusts the voltage of the second signal to obtain the driving signal. The absolute value of the second voltage difference between the first signal and the driving signal is less than the absolute value of the first voltage difference, that is, the voltage of the driving signal is closer to the voltage of the first signal than the voltage of the second signal. The driving signal is used to drive the pixel on the display panel to emit light.

[0057] It can be seen that the control module in the embodiment of the present application automatically generates the control signal according to the first voltage difference, and the output module quickly adjusts the voltage of the output signal according to the control signal, thereby realizing adaptive enhancement of the slew rate of the output module. Further, the speed of charging and discharging the load capacitance is improved, and the refresh rate of the display panel is improved.

[0058] Exemplarily, the driving circuit provided by the embodiment of the present application is located in a channel of a source driving module, the channel further comprises a DAC, and the channel corresponds to a pixel column on a display panel. An output terminal of the DAC is connected to the control module through a positive input terminal VIN+, the first signal is an analog signal (for example, an analog voltage) obtained by digital-to-analog conversion of the DAC, and the first signal is input to the control module through the positive input terminal VIN+. The output module is connected to a load capacitor corresponding to the pixel column through an output terminal VOUT and a data line, and the second signal and the driving signal are output by the output module through the output terminal VOUT and transmitted to the load capacitor corresponding to the pixel column through the data line, so as to charge or discharge the load capacitor, thereby driving each pixel in the pixel column to emit light. In addition, the output terminal VOUT is also connected to a negative input terminal VIN-, forming a negative feedback, thereby improving the stability of the driving circuit.

[0059] In the exemplary embodiment, the first voltage difference is a voltage difference obtained by subtracting the voltage of the second signal from the voltage of the first signal. In the case where the first voltage difference is positive, it indicates that the voltage of the first signal is greater than the voltage of the second signal, and the control module needs to control the output module to increase the voltage of the signal output by the output module, so as to charge the load capacitor and increase the brightness of the pixel emitting light. In the case where the first voltage difference is negative, it indicates that the voltage of the first signal is less than the voltage of the second signal, and the control module needs to control the output module to reduce the voltage of the signal output by the output module, so as to discharge the load capacitor and reduce the brightness of the pixel emitting light.

[0060] In the embodiment of the present application, the control module controls the output module to charge or discharge the load capacitor through different control units. For example, the control module comprises a first control unit and a second control unit, and the first control unit and the second control unit are respectively connected to the output module.

[0061] The first control unit is configured to generate a control signal indicating voltage increase according to the first voltage difference. The output module is configured to output the driving signal according to the control signal indicating voltage increase, and the driving signal is the third signal, and the voltage of the third signal is greater than the voltage of the second signal.

[0062] In a case that the first voltage difference is positive and an absolute value of the first voltage difference is greater than the reference threshold, the first control unit can control the output module to increase the voltage of the signal output by the output module, that is, send a control signal indicating voltage increase to the output module, so as to charge the load capacitance. The driving signal output by the output module according to the control signal indicating voltage increase is the third signal, and the voltage of the third signal is greater than the voltage of the second signal. For example, the output module includes an output end, and the output end is used for the output module to output the second signal, the third signal or the fourth signal. In a case that the third signal is output through the output end, that is, the voltage of the driving signal output by the output end is increased compared with the voltage of the second signal, the voltage of the third signal is used to charge the load capacitance on the display panel, so as to drive the pixel corresponding to the load capacitance to emit light and increase the brightness. In this way, the charging of the load capacitance is realized, and the brightness of the pixel is increased.

[0063] The second control unit is configured to generate a control signal indicating voltage decrease according to the first voltage difference. The output module is configured to output a driving signal according to the control signal indicating voltage decrease, and the driving signal is a fourth signal, and the voltage of the fourth signal is less than the voltage of the second signal.

[0064] In a case that the first voltage difference is negative and an absolute value of the first voltage difference is greater than the reference threshold, the second control unit can control the output module to decrease the voltage of the signal output by the output module, that is, send a control signal indicating voltage decrease to the output module, so as to discharge the load capacitance. The driving signal output by the output module according to the control signal indicating voltage decrease is the fourth signal, and the voltage of the fourth signal is less than the voltage of the second signal. For example, the output module includes an output end, and the output end is used for the output module to output the second signal, the third signal or the fourth signal. In a case that the fourth signal is output through the output end, that is, the voltage of the driving signal output by the output end is decreased compared with the voltage of the second signal, the voltage of the fourth signal is used to discharge the load capacitance on the display panel, so as to drive the pixel corresponding to the load capacitance to emit light and decrease the brightness. In this way, the discharging of the load capacitance is realized, and the brightness of the pixel is decreased.

[0065] Next, the connection relationship between the output module and the first control unit, and the connection relationship between the output module and the second control unit will be described in combination with Figure 5 and Figure 6 . Figure 6 is Figure 5 an equivalent circuit diagram. To avoid redundancy, Figure 6 the connection relationship between VOUT and VIN- is not shown, and Figure 6 the two VIN+ shown represent the same positive input terminal VIN+. In addition, Figure 6The detailed structure (composed of transistors and circuits) of the devices of VIN+, VIN-, current source X, current source Y and floating voltage source F is shown, Figure 6 The V BIAS2 to V BIAS5 The bias voltage provided for the bias voltage module in the display driver is not described herein again.

[0066] In the exemplary embodiment, the output module comprises a first transistor and a second transistor, the gate of the first transistor and the gate of the second transistor are connected, the gate of the first transistor is further connected with the second control unit, the gate of the second transistor is further connected with the first control unit, the drain of the first transistor and the drain of the second transistor are respectively connected with the output end (see the above description for details), the source of the first transistor is connected with the positive power supply, and the source of the second transistor is connected with the analog ground.

[0067] The first transistor is a P-type transistor, and the second transistor is an N-type transistor. For example, see Figure 5 , the first transistor is PM1, and the second transistor is NM1. The gate of the first transistor PM1 and the gate of the second transistor NM1 are connected through a floating voltage source (i.e. Figure 5 , F shown in the above description). Figure 2 The floating voltage source F is used to avoid the simultaneous conduction of PM1 and NM1, which is not described herein again.

[0068] There is a first point on the connection circuit between the gate of the first transistor PM1 and the second control unit, for example, see Figure 5 , the first point is point A, and the output module is connected with the second control unit through point A. There is a second point on the connection circuit between the gate of the second transistor NM1 and the first control unit, for example, see Figure 5 , the second point is point B, and the output module is connected with the first control unit through point B.

[0069] The drain of the first transistor PM1 and the drain of the second transistor NM1 are respectively connected with the output end VOUT, the source of the first transistor PM1 is connected with the positive power supply VSP, and the source of the second transistor NM1 is connected with the analog ground AVSS.

[0070] Optionally, see Figure 5 , the output module further comprises a capacitor CC1 and a capacitor CC2, the capacitor CC1 is connected in parallel with the gate and the drain of the first transistor PM1, and the capacitor CC2 is connected in parallel with the gate and the drain of the second transistor NM1. The capacitor CC1 and the capacitor CC2 are used to play a role of phase compensation in the operational amplifier loop, and the role of the capacitor CC1 and the capacitor CC2 is not limited in the present application.

[0071] Since the gate of the first transistor and the gate of the second transistor are connected, the gate of the second transistor is also connected with the first control unit, and the first control unit is used to generate a control signal indicating voltage increase, so that the first transistor is used to receive the control signal indicating voltage increase through the gate of the second transistor, and is turned on according to the control signal indicating voltage increase, so that the output driving signal is the third signal, and the voltage of the third signal is greater than the voltage of the second signal.

[0072] For example, since there is a second point B point on the connection circuit between the gate of the second transistor NM1 and the first control unit, the control signal indicating voltage increase is received by the first transistor PM1 through the second point B point. Wherein, the control signal indicating voltage increase can be transmitted to the first point A point through the second point B point and the floating voltage source F, so as to be received by the first transistor PM1. Since the gate of the first transistor PM1 is used to control whether the first transistor PM1 is turned on or not, the first transistor PM1 is turned on according to the control signal indicating voltage increase at the first point A point.

[0073] Alternatively, in the case that the first control unit pulls down the voltage at the second point B point, there is a control signal indicating voltage increase at the second point B point. The second point B point pulls down the voltage at the first point A point through the floating voltage source F, so as to realize that the control signal indicating voltage increase is transmitted to the first point A point through the floating voltage source F. Since the voltage at the first point A point is pulled down, which is equivalent to that the voltage at the gate of the first transistor PM1 is reduced, so that the first transistor PM1 is turned on. For example, in the case that the voltage difference obtained by subtracting the voltage at the gate of the first transistor PM1 from the voltage at the source of the first transistor PM1 is greater than the absolute value of the threshold voltage of the first transistor PM1, the first transistor PM1 is turned on.

[0074] In the case that the first transistor PM1 is turned on, the current flows from the positive power supply VSP to VOUT through the source and the drain of the first transistor PM1, and the voltage of the signal output by VOUT increases, so that the voltage of the third signal is greater than the voltage of the second signal, to realize the charging of the load capacitor.

[0075] In the process of charging the load capacitor, the first point A point can be affected by the control signal indicating voltage increase generated by the first control unit, and the voltage at the first point A point changes at a relatively fast speed, that is, the establishment time of the first point A point is relatively short, so that the first transistor PM1 is quickly turned on, the voltage of the signal output by VOUT increases quickly, the pressure swing rate is enhanced, the speed of charging the load capacitor is improved, and the refresh rate of the display panel is improved.

[0076] Since the gate of the first transistor and the gate of the second transistor are connected, the gate of the first transistor is also connected with the second control unit, and the second control unit is used to generate a control signal indicating voltage reduction, so that the second transistor is used to receive the control signal indicating voltage reduction through the gate of the first transistor, and is turned on according to the control signal indicating voltage reduction, so that the output driving signal is the fourth signal, and the voltage of the fourth signal is less than the voltage of the second signal.

[0077] For example, since there is a first point A on the connection circuit between the gate of the first transistor PM1 and the second control unit, the control signal indicating voltage reduction is received by the second transistor NM1 through the first point A. Wherein, the control signal indicating voltage reduction can be transmitted to the second point B through the first point A and the floating voltage source F, so as to be received by the second transistor NM1. Since the gate of the second transistor NM1 is used to control whether the second transistor NM1 is turned on or not, the second transistor NM1 is turned on according to the control signal indicating voltage reduction at the second point B.

[0078] Alternatively, in the case that the second control unit pulls up the voltage at the first point A, there is a control signal indicating voltage reduction at the first point A. The first point A pulls up the voltage at the second point B through the floating voltage source F, realizing that the control signal indicating voltage reduction is transmitted to the second point B through the floating voltage source F. Since the voltage at the second point B is pulled up, which is equivalent to the voltage at the gate of the second transistor NM1 being raised, so the second transistor NM1 is turned on. For example, in the case that the voltage difference obtained by subtracting the voltage at the source of the second transistor NM1 from the voltage at the gate of the second transistor NM1 is greater than the threshold voltage of the second transistor NM1, the second transistor NM1 is turned on.

[0079] In the case that the second transistor NM1 is turned on, the current flows from VOUT to the analog ground AVSS through the drain and the source of the second transistor NM1, the voltage of the signal output by VOUT is reduced, so that the voltage of the fourth signal is less than the voltage of the second signal, to realize discharging of the load capacitor.

[0080] In the process of discharging the load capacitor, the second point B can be affected by the control signal indicating voltage reduction generated by the second control unit, the voltage at the second point B changes quickly, that is, the rise time of the second point B is short, so that the second transistor NM1 is quickly turned on, the voltage of the signal output by VOUT is quickly reduced, the pressure drop rate is enhanced, the speed of discharging the load capacitor is improved, which is beneficial to improve the refresh rate of the display panel.

[0081] Next, the first control unit is described.

[0082] For example, the first control unit is used to generate a control signal indicating voltage increase, so that the first transistor PM1 is used to receive the control signal indicating voltage increase through the gate of the first transistor PM1, and is turned on according to the control signal indicating voltage increase, so that the output driving signal is the first signal, and the voltage of the first signal is greater than the voltage of the second signal. Figure 5As shown, the first control unit comprises a first trigger unit 51, a first inverter 52 and a first generating unit 53. The first trigger unit 51 is connected with the first inverter 52. The first inverter 52 is further connected with the first generating unit 53. The first generating unit 53 is further connected with a first current source grounded and an output module respectively.

[0083] The first trigger unit 51 is configured to generate a first trigger signal according to the first voltage difference. The first inverter 52 is configured to generate a first inverted signal according to the first trigger signal. The first generating unit 53 is configured to generate a control signal indicating voltage increase according to the first inverted signal.

[0084] Exemplarily, the first generating unit 53 comprises a third transistor. The third transistor is an N-type transistor, see Figure 5 for example, the third transistor NM4. The source of the third transistor NM4 is connected with the first current source I1 grounded. The drain of the third transistor NM4 is connected with the output module. For example, the drain of the third transistor NM4 is connected with the second point B. The first inverter 52 is connected with the gate of the third transistor. The source of the third transistor is connected with the first current source grounded. The drain of the third transistor is connected with the output module.

[0085] The first trigger unit 51 is configured to generate the first trigger signal in the case that the first voltage difference is positive and the absolute value of the first voltage difference is greater than a reference threshold. The first inverter 52 is configured to generate the first inverted signal according to the first trigger signal. The third transistor is configured to conduct according to the first inverted signal, so as to generate the control signal indicating voltage increase at the drain of the third transistor.

[0086] Since the first trigger unit 51 is connected with the first inverter 52, the first inverter 52 can detect the first trigger signal generated by the first trigger unit 51, so as to generate the first inverted signal according to the first trigger signal. Since the first inverter 52 is connected with the gate of the third transistor NM4, and the gate of the third transistor NM4 is configured to control whether the third transistor NM4 conducts or not, the third transistor NM4 conducts according to the first inverted signal, so as to generate the control signal indicating voltage increase at the drain of the third transistor NM4. Thus, the control signal indicating voltage increase exists at the second point B.

[0087] Optionally, in the case that the first trigger unit 51 pulls the voltage at the input end of the first inverter 52 low, the first inverter 52 confirms that the first trigger signal is detected. The voltage at the input end of the first inverter 52 is opposite to the voltage at the output end of the first inverter 52, and thus the voltage at the output end of the first inverter 52 is pulled high. Such first inverter signal makes the voltage at the gate of the third transistor NM4 also pulled high, and thus the third transistor NM4 is turned on. For example, in the case that the voltage difference between the voltage at the gate of the third transistor NM4 and the voltage at the source of the third transistor NM4 is greater than the threshold voltage of the third transistor NM4, the third transistor NM4 is turned on.

[0088] For example, the first inverter 52 is a charge pump inverter. For example, refer to Figure 5 The first inverter 52 includes a current source 1, a first switch and a current source 2. The current source 1 and the current source 2 are shown as circles with arrows in Figure 5 The first switch is shown as a triangle with a circle at the vertex in Figure 5 The relative position relationship between the current source 1 and the current source 2 is not limited in the embodiments of the present application.

[0089] The first switch is used to select the current source 1 to be in communication with the output end of the first inverter 52 or the current source 2 to be in communication with the output end of the first inverter 52 according to the voltage at the input end of the first inverter 52. When the current source 1 is in communication with the output end of the first inverter 52, the current source 1 charges the output end of the first inverter 52, so that the voltage at the output end of the first inverter 52 is pulled high to turn on the third transistor NM4, which facilitates charging the load capacitor. Alternatively, when the current source 2 is in communication with the output end of the first inverter 52, the current source 2 is discharged by the output end of the first inverter 52, so that the voltage at the output end of the first inverter 52 is pulled low, thereby avoiding the third transistor NM4 from being turned on (for example, in the process of discharging the load capacitor, it is necessary to avoid the third transistor NM4 from being turned on).

[0090] In the case that the third transistor NM4 is turned on, the current flows from the drain and the source of the third transistor NM4 to the first current source I1 grounded, so that the voltage at the drain of the third transistor NM4 is lowered, thereby pulling the voltage at the second point B low, and thus charging the load capacitor can be achieved.

[0091] For example, refer to Figure 5The first trigger unit 51 comprises a fourth transistor and a fifth transistor. The gate of the fourth transistor is connected with the input end for inputting the first signal. The source of the fourth transistor is connected with the output end (see the above description for the function). The drain of the fourth transistor is connected with the drain of the fifth transistor. The source of the fifth transistor is connected with the positive power supply. The gate and the drain of the fifth transistor are connected with the first inverter 52 respectively. The fourth transistor is used to be turned on when the first voltage difference is positive and the absolute value of the first voltage difference is greater than the reference threshold value. The fifth transistor is used to generate the first trigger signal at the gate and the drain of the fifth transistor when the fourth transistor is turned on.

[0092] The fourth transistor is an N-type transistor and the fifth transistor is a P-type transistor, for example, in Figure 5 , the fourth transistor is NM2 and the fifth transistor is PM3. The gate of the fourth transistor NM2 is connected with the positive input end VIN+. The source of the fourth transistor NM2 is connected with the output end VOUT. The drain of the fourth transistor NM2 is connected with the drain of the fifth transistor PM3. The source of the fifth transistor PM3 is connected with the positive power supply VSP. The gate and the drain of the fifth transistor PM3 are connected with the input end of the first inverter 52 respectively.

[0093] The threshold voltage of the fourth transistor NM2 is denoted as VTH NM2 , and VTH NM2 is the reference threshold value in the process of charging the load capacitor. The first voltage difference is the difference between the voltage of the input first signal (the voltage at VIN+) and the voltage of the output second signal (the voltage at VOUT). When the first voltage difference is positive and the absolute value is greater than VTH NM2 , the fourth transistor NM2 is turned on. Therefore, the current flows from the drain to the source of the fourth transistor NM2, the voltage at the drain of the fourth transistor NM2 is pulled down, and the voltage at the gate and the drain of the fifth transistor PM3 is also pulled down. The voltage at the input end of the first inverter 52 is also pulled down accordingly, thereby generating the first trigger signal.

[0094] Based on the above description of the first control unit, the process of the first control unit controlling the output module to rapidly charge the load unit is described in whole, in combination with Figure 5 .

[0095] At a certain moment, the voltage of the first signal input by the positive input end VIN+ and the voltage of the second signal output by the output end VOUT are both 0.2V. The brightness corresponding to 0.2V is gray level 0. The voltage of 0.2V is transmitted to the load capacitor through the data line, so that the pixel corresponding to the load capacitor emits light according to the gray level 0.

[0096] At the next moment, the voltage of the first signal input by the positive input end VIN+ jumps from 0.2V to 5.3V, and the corresponding brightness of 5.3V is gray scale 255, and the voltage of the second signal output by the output end VOUT is still temporarily 0.2V, so the Self_SRB function needs to be turned on to quickly increase the voltage of the signal output by the output end VOUT, so that the voltage of the second signal output by the output end VOUT quickly rises to 5.3V, thereby quickly charging the load capacitor, so that the pixel corresponding to the load capacitor is quickly switched to emit light according to gray scale 255, so as to provide a higher refresh rate.

[0097] wherein the first voltage difference obtained by subtracting the voltage of the second signal from the voltage of the first signal is 5.1V, and the first voltage difference 5.1V is greater than the reference threshold VTH NM2 , which is the threshold voltage of the fourth transistor NM2, so the fourth transistor NM2 is turned on, and the Self_SRB function is turned on.

[0098] In the case where the fourth transistor NM2 is turned on, the current flows from the drain to the source of the fourth transistor NM2, quickly pulling down the voltage at the drain of the fourth transistor NM2, and the voltage at the gate and drain of the fifth transistor PM3 is also quickly pulled down, and the voltage at the input end of the first inverter 52 is also quickly pulled down, and the voltage at the output end of the first inverter 52 is quickly pulled up.

[0099] Then, the voltage at the gate of the third transistor NM4 is also quickly pulled up, the third transistor NM4 is turned on, and the current flows from the drain and source of the third transistor NM4 to the first current source I1 grounded, so that the voltage at the drain of the third transistor NM4 is quickly reduced, thereby quickly pulling down the voltage at the second point B, and the first point A is quickly pulled down by the floating voltage source F, and the voltage at the gate of the first transistor PM1 is quickly reduced, so that the first transistor PM1 is quickly turned on. Thus, the current flows from the positive power supply VSP through the source and drain of the first transistor PM1 to VOUT, and the voltage of the signal output by VOUT is quickly increased. The voltage of the signal output by VOUT is denoted as a third signal, and the voltage of the third signal is greater than the voltage of the second signal, which can achieve fast charging of the load capacitor.

[0100] The voltage of the third signal will continue to increase. In the case where the second voltage difference obtained by subtracting the voltage of the third signal from the voltage of the first signal is equal to the reference threshold VTH NM2 , the fourth transistor NM2 is turned off, and the Self_SRB function is turned off.

[0101] When the fourth transistor NM2 is turned off, current no longer flows from the drain to the source of the fourth transistor NM2, thereby increasing the voltage at the drain of the fourth transistor NM2. This, in turn, increases the voltage at the gate and drain of the fifth transistor PM3. This, in turn, increases the voltage at the input of the first inverter 52, lowers the voltage at the output of the first inverter 52, and lowers the voltage at the gate of the third transistor NM4, turning the third transistor NM4 off. Consequently, the voltage at the second point B increases, which in turn increases the voltage at the first point A via the floating voltage source F, and the first transistor PM1 remains on.

[0102] Even if the third transistor NM4 is turned off, a bias current still exists in the output module. This bias current can cause the voltage of the third signal to continue to increase after the Self_SRB function is turned off, until the voltage of the third signal is equal to the voltage of the first signal, 5.3V. Therefore, after the Self_SRB function is turned off, the load capacitor can continue to be charged (although the charging speed at this time is slower than the charging speed when the Self_SRB function is turned on) until the pixel corresponding to the load capacitor switches to emit light according to the grayscale 255 corresponding to 5.3V. When the voltage of the third signal is equal to the voltage of the first signal, the first transistor PM1 remains on and is in a subthreshold operating state (in this operating state, the static current is very small), so that the pixel corresponding to the load capacitor stably emits light according to the grayscale 255 corresponding to 5.3V.

[0103] like Figure 7 As shown, the horizontal axis represents time, and the unit of time is microseconds (us), and the vertical axis represents voltage, and the unit of voltage is V. Among them, the dotted line represents the change in the voltage of the first signal input at the positive input terminal VIN+. The voltage of the first signal jumps from 0.2V to 5.3V at 6.0us. The solid line represents the change in the voltage of the signal output at the output terminal VOUT. At 6.0us, the Self_SRB function is turned on, and the voltage of the signal output by VOUT starts to increase rapidly from 0.2V, quickly charging the load capacitor. When VIN-VOUT=VTH NM2 At the moment (ie, the second voltage difference is equal to the reference threshold VTH NM2 (At the moment of OFF), the Self_SRB function is turned off, and the voltage of the signal output by VOUT slowly increases until it reaches 5.3V, slowly charging the load capacitor.

[0104] Optionally, the first trigger signal is generated in a case that a transistor included in the first trigger unit is in a conducting state, and a source of the transistor included in the first trigger unit is connected to a substrate. For example, the transistor included in the first trigger unit refers to the fourth transistor, and the source of the fourth transistor is also connected to the substrate of the fourth transistor, so as to reduce the reference threshold value. For example, refer to Figure 8 , Figure 8 The source of the fourth transistor NM2 is connected to the substrate of the fourth transistor NM2. In this way, the reference threshold value VTH NM2 can be reduced, so that the time point of VIN-VOUT=VTH NM2 is delayed, the Self_SRB function is turned on later, and the time length of the Self_SRB function is prolonged, and the time length of the fast charging of the load capacitance is prolonged, which is beneficial to further improve the refresh rate of the display panel.

[0105] In addition, as described above, the Self_SRB function is turned on in a case that the first voltage difference is greater than the reference threshold value VTH NM2 . By reducing the reference threshold value VTH NM2 , the first voltage difference can be more easily greater than the reference threshold value VTH NM2 . In other words, the voltage of the first signal input by the positive input terminal VIN+ only needs to be increased by a small amplitude, and the condition that the first voltage difference is greater than the reference threshold value VTH NM2 is met, so that the Self_SRB function is turned on, that is, the time point of turning on the Self_SRB function is more advanced, and the time length of turning on the Self_SRB function is also prolonged, and the time length of the fast charging of the load capacitance is prolonged, which is beneficial to further improve the refresh rate of the display panel.

[0106] The source of the fourth transistor NM2 is connected to the substrate of the fourth transistor NM2, which can reduce the reference threshold value VTH NM2 . The reason is as follows. Due to the body effect of the NMOS, the greater the voltage difference 1 between the voltage output by the output terminal VOUT and the voltage at the substrate of the fourth transistor NM2, the greater the reference threshold value VTH NM2 . By connecting the source of the fourth transistor NM2 to the substrate of the fourth transistor NM2, the voltage difference 1 can be reduced, so that the reference threshold value VTH NM2 is reduced.

[0107] In the source driving module, the NMOS is a medium voltage device. For example, refer to Figure 9The medium-voltage device NMOS is arranged in a deep n-well to be mutually isolated from a p-substrate used by the high-voltage device. The NMOSs with different substrate potentials can be arranged in the same deep n-well, because no short circuit occurs between the corresponding p-well and the deep n-well of the NMOS, and the p+ in the p-well represents a heavily doped P-type semiconductor, and the n+ in the p-well represents a heavily doped N-type semiconductor.

[0108] Therefore, even if the source of the fourth transistor NM2 is connected with the substrate of the fourth transistor NM2, causing the substrate potential of the fourth transistor NM2 to be different from the substrate potentials of the other NMOSs in the driving circuit, the fourth transistor NM2 and the other NMOSs can still be arranged in the same deep n-well, which is more practical, avoids increasing the size of the driving circuit, and further avoids increasing the size of the channel and the size of the source driving module.

[0109] Exemplarily, the gear of the first current source is adjustable, and the gear of the first current source is used to control the generation speed of the control signal indicating the voltage increase, and further affect the charging speed of the load capacitor, thereby facilitating the adaptation to various refresh rate requirements. The embodiments of the present application do not limit the way of adjusting the gear of the first current source.

[0110] For example, referring to Figure 10 , the gear of the first current source I1 includes OFF, ON1, ON2 and ON3. In the case of OFF, the first control unit is not started, and the Self_SRB function is not enabled. In the case of ON1, ON2 and ON3 respectively, the current provided by the first current source I1 increases in turn, so that the generation speed of the control signal indicating the voltage increase increases in turn (i.e., the speed of pulling down the voltage at the second point B increases in turn), the charging speed of the load capacitor increases in turn (i.e., the slope of the rising phase shown in Figure 10 increases in turn), and the refresh rate that can be provided increases in turn.

[0111] As shown in (a) of Figure 11 , the positive input end VIN+ is marked as ①, the output end VOUT is marked as ②, the gate and drain of the fifth transistor PM3 are marked as ③, the gate of the third transistor NM4 is marked as ④, the second point B is marked as ⑤, and the first point A is marked as ⑥. Based on this, in combination with (b) of Figure 11 , the voltage changes of ① to ⑥ in the process of charging the load capacitor are explained. Among them, the horizontal coordinate axis represents time, the unit of time is us, and the vertical coordinate axis represents voltage, the unit of voltage is V. The process of charging the load capacitor corresponds to the period between 6.0us and 12.0us (excluding the endpoint 12.0us).

[0112] For ① at the positive input VIN+, the voltage at ① jumps from 0.2V to 5.3V at 6.0us, causing the fourth transistor NM2 to turn on, and the Self_SRB function to turn on.

[0113] For ③ at the gate and drain of the fifth transistor PM3, the voltage at ③ is quickly pulled low due to the fourth transistor NM2 turning on.

[0114] For ④ at the gate of the third transistor NM4, the voltage at ④ is quickly pulled high after being processed by the first inverter 52, causing the third transistor NM4 to turn on, due to the voltage at ③ being quickly pulled low.

[0115] For ⑤ at the second point B, the voltage at ⑤ is quickly pulled low, but the magnitude of the pull-down is small (essentially unchanged) due to the current source Y being in parallel with ⑤, with the third transistor NM4 turning on.

[0116] For ⑥ at the first point A, the voltage at ⑥ is quickly pulled low by the floating current source F, causing the first transistor PM1 to quickly turn on, due to the voltage at ⑤ being quickly pulled low.

[0117] For ② at the output VOUT, the voltage at ② is quickly increased, until the second voltage difference between the voltage at ① and the voltage at ② equals the reference threshold VTH NM2 , with the fourth transistor NM2 turning off, and the Self_SRB function turning off.

[0118] For ③ at the gate and drain of the fifth transistor PM3, the voltage at ③ is pulled high and remains stable, due to the fourth transistor NM2 turning off.

[0119] For ④ at the gate of the third transistor NM4, the voltage at ④ is pulled low and remains stable after being processed by the first inverter 52, causing the third transistor NM4 to turn off, due to the voltage at ③ being pulled high.

[0120] For ⑤ at the second point B, the voltage at ⑤ is also pulled high and remains stable, with the third transistor NM4 turning off.

[0121] For ⑥ at the first point A, the voltage at ⑥ is pulled high by the floating current source F, and remains stable when the voltage at ② is approximately equal to the voltage at ①, causing the first transistor PM1 to remain on, with a bias current still present in the drive circuit, due to the voltage at ⑤ being pulled high.

[0122] For ② at the output VOUT, the voltage at ② is slowly increased based on the bias current, and remains stable when the voltage at ② is the same as the voltage at ①, due to the bias current still present in the drive circuit.

[0123] Next, the second control unit will be described.

[0124] like Figure 4 As shown, the second control unit includes a second trigger unit 54, a second inverter 55 and a second generating unit 56. The second trigger unit 54 is connected to the second inverter 55, and the second inverter 55 is also connected to the second generating unit 56. The second generating unit 56 is also connected to the second current source and the output module connected to the positive power supply respectively.

[0125] The second trigger unit 54 is configured to generate a second trigger signal according to the first voltage difference. The second inverter 55 is configured to generate a second inverted signal according to the second trigger signal. The second generating unit 56 is configured to generate a control signal indicating a voltage reduction according to the second inverted signal.

[0126] Exemplarily, the second generation unit 56 includes a sixth transistor. The sixth transistor is a P-type transistor, see ​ The sixth transistor is, for example, PM4. The source of the sixth transistor PM4 is connected to the second current source I0 connected to the positive power supply VSP, and the drain of the sixth transistor PM4 is connected to the output module. For example, the drain of the sixth transistor PM4 is connected to the first point A. The second inverter 55 is connected to the gate of the sixth transistor, the source of the sixth transistor is connected to the second current source connected to the positive power supply, and the drain of the sixth transistor is connected to the output module.

[0127] The second trigger unit 54 is configured to generate a second trigger signal when the first voltage difference is negative and the absolute value of the first voltage difference is greater than a reference threshold. The second inverter 55 is configured to generate a second inverted signal based on the second trigger signal. The sixth transistor is configured to be turned on based on the second inverted signal to generate a control signal at the drain of the sixth transistor indicating a voltage decrease.

[0128] Because the second trigger unit 54 is connected to the second inverter 55, the second inverter 55 can detect the second trigger signal generated by the second trigger unit 54 and generate a second inverted signal based on the second trigger signal. Since the second inverter 55 is connected to the gate of the sixth transistor PM4, and the gate of the sixth transistor PM4 is used to control whether the sixth transistor PM4 is turned on, the sixth transistor PM4 is turned on according to the second inverted signal, thereby generating a control signal indicating a voltage decrease at the drain of the sixth transistor PM4, so that the control signal indicating a voltage decrease is present at the first point A.

[0129] Optionally, in the case that the second trigger unit 54 pulls up the voltage at the input end of the second inverter 55, the second inverter 55 confirms that the second trigger signal is detected. The voltage at the input end of the second inverter 55 is opposite to the voltage at the output end of the second inverter 55, thus the voltage at the output end of the second inverter 55 is pulled down. Such second inverter signal makes the voltage at the gate of the sixth transistor PM4 also pulled down, thus making the sixth transistor PM4 conductive. For example, in the case that the voltage difference between the voltage at the source of the sixth transistor PM4 and the voltage at the gate of the sixth transistor PM4 is greater than the absolute value of the threshold voltage of the sixth transistor PM4, the sixth transistor PM4 is conductive.

[0130] For example, the second inverter 55 is a charge pump inverter. For example, refer to ​ , the second inverter 55 includes a current source 3, a second switch and a current source 4, the current source 3 and the current source 4 are shown as circles with arrows in ​ , the second switch is shown as a triangle with a circle at the vertex in ​ , and the relative position relationship between the current source 3 and the current source 4 is not limited in the embodiments of the present application.

[0131] The second switch is used to select the current source 3 to be in communication with the output end of the second inverter 55 according to the voltage at the input end of the second inverter 55, or to select the current source 4 to be in communication with the output end of the second inverter 55. When the current source 3 is in communication with the output end of the second inverter 55, the current source 3 charges the output end of the second inverter 55, so that the voltage at the output end of the second inverter 55 is pulled up, thereby avoiding the sixth transistor PM4 from being conductive (for example, during the process of charging the load capacitor, it is necessary to avoid the sixth transistor PM4 from being conductive). Alternatively, when the current source 4 is in communication with the output end of the second inverter 55, the current source 4 is discharged by the output end of the second inverter 55, so that the voltage at the output end of the second inverter 55 is pulled down to make the sixth transistor PM4 conductive, thereby facilitating the discharge of the load capacitor.

[0132] In the case that the sixth transistor PM4 is conductive, the current flows from the positive power supply VSP to the source and the drain of the sixth transistor PM4, so that the voltage at the drain of the sixth transistor PM4 is raised, thereby pulling up the voltage at the first point A, and thus being able to realize the discharge of the load capacitor.

[0133] For example, refer to ​The second trigger unit 54 comprises a seventh transistor and an eighth transistor. The gate of the seventh transistor is connected with an input terminal for inputting a first signal. The source of the seventh transistor is connected with an output terminal (see the above description). The drain of the seventh transistor is connected with the drain of the eighth transistor. The source of the eighth transistor is connected with an analog ground. The gate and the drain of the eighth transistor are connected with the second inverter 55. The seventh transistor is used to be turned on when the first voltage difference is negative and the absolute value of the first voltage difference is greater than a reference threshold value. The eighth transistor is used to generate a second trigger signal at the gate and the drain of the eighth transistor when the seventh transistor is turned on.

[0134] The seventh transistor is a P-type transistor and the eighth transistor is an N-type transistor, for example, in ​ , the seventh transistor is PM2 and the eighth transistor is NM3. The gate of the seventh transistor PM2 is connected with the positive input terminal VIN+. The source of the seventh transistor PM2 is connected with the output terminal VOUT. The drain of the seventh transistor PM2 is connected with the drain of the eighth transistor NM3. The source of the eighth transistor NM3 is connected with the analog ground AVSS. The gate and the drain of the eighth transistor NM3 are connected with the input terminal of the second inverter 55.

[0135] The threshold voltage of the seventh transistor PM2 is VTH PM2 , and the absolute value |VTH PM2 | of VTH PM2 is a reference threshold value in the process of discharging the load capacitor. The second voltage difference is the difference between the voltage of the input first signal (the voltage at VIN+) and the voltage of the output second signal (the voltage at VOUT). When the second voltage difference is negative and the absolute value is greater than VTH PM2 , the seventh transistor PM2 is turned on. Therefore, the current flows from the source to the drain of the seventh transistor PM2, the voltage at the drain of the seventh transistor PM2 is pulled up, and the voltage at the gate and the drain of the eighth transistor NM3 is also pulled up. The voltage at the input terminal of the second inverter 55 is also pulled up, thereby generating the second trigger signal.

[0136] Based on the above description of the second control unit, the process of the second control unit controlling the output module to quickly discharge the load unit will be described in detail. ​

[0137] At a certain moment, the voltage of the first signal input by the positive input terminal VIN+ and the voltage of the second signal output by the output terminal VOUT are both 5.3V, which corresponds to the gray scale 255. The voltage of 5.3V is transmitted to the load capacitor through the data line, so that the pixel corresponding to the load capacitor emits light according to the gray scale 255.​

[0138] At the next moment, the voltage of the first signal input by the positive input terminal VIN+ jumps from 5.3V to 0.2V, and the corresponding brightness of 0.2V is gray level 0, and the voltage of the second signal output by the output terminal VOUT is still temporarily 5.3V, so the Self_SRB function needs to be turned on to quickly reduce the voltage of the signal output by the output terminal VOUT, so that the voltage of the second signal output by the output terminal VOUT quickly decreases to 0.2V, thereby quickly discharging the load capacitor, so that the pixel corresponding to the load capacitor is quickly switched to emit light according to gray level 0, so as to provide a higher refresh rate.

[0139] Wherein, the second voltage difference obtained by subtracting the voltage of the second signal from the voltage of the first signal is -5.1V, and the absolute value of the second voltage difference -5.1V is greater than the reference threshold |VTH PM2 |, which is the absolute value of the threshold voltage of the seventh transistor PM2, so the seventh transistor PM2 is turned on, and the Self_SRB function is turned on.

[0140] In the case that the seventh transistor PM2 is turned on, the current flows from the source to the drain of the seventh transistor PM2, quickly pulling up the voltage at the drain of the seventh transistor PM2, and the voltage at the gate and drain of the eighth transistor NM3 is also quickly pulled up, and the voltage at the input terminal of the second inverter 55 is also quickly pulled up, and the voltage at the output terminal of the second inverter 55 is quickly pulled down.

[0141] Then, the voltage at the gate of the sixth transistor PM4 is also quickly pulled down, the sixth transistor PM4 is turned on, and the current flows from the second current source I0 connected to the positive power supply VSP to the source and drain of the sixth transistor PM4, so that the voltage at the drain of the sixth transistor PM4 is quickly raised, thereby quickly pulling up the voltage at the first point A, and the second point B is quickly pulled up by the floating voltage source F, and the voltage at the gate of the second transistor NM1 is quickly raised, so that the second transistor NM1 is quickly turned on. Thus, the current flows from the output terminal VOUT to the drain and source of the second transistor NM1, and the voltage of the signal output by VOUT is quickly reduced. The voltage of the signal output by VOUT is denoted as the fourth signal, and the voltage of the fourth signal is less than the voltage of the second signal, which can achieve quick discharge of the load capacitor.

[0142] The voltage of the fourth signal will continue to decrease. In the case that the absolute value of the second voltage difference obtained by subtracting the voltage of the fourth signal from the voltage of the first signal is equal to the reference threshold |VTH PM2 |, the seventh transistor PM2 is turned off, and the Self_SRB function is turned off.

[0143] When the seventh transistor PM2 is turned off, current no longer flows from the source to the drain of the seventh transistor PM2, thereby lowering the voltage at the drain of the seventh transistor PM2. Consequently, the voltages at the gate and drain of the eighth transistor NM3 are also lowered, and the voltage at the input of the second inverter 55 is correspondingly lowered. The voltage at the output of the second inverter 55 is also raised, and the voltage at the gate of the sixth transistor PM4 is also raised, turning the sixth transistor PM4 off. Consequently, the voltage at the first point A is lowered, and the first point A also lowers the voltage at the second point B via the floating voltage source F, while the second transistor NM1 remains on.

[0144] Even if the sixth transistor PM4 is turned off, there is still a bias current in the output module. This bias current can cause the voltage of the fourth signal to continue to decrease after the Self_SRB function is turned off, until the voltage of the fourth signal is equal to the voltage of the first signal, 0.2V. Therefore, after the Self_SRB function is turned off, the load capacitor can continue to be discharged (but the discharge speed at this time is slower than the discharge speed when the Self_SRB function is turned on) until the pixel corresponding to the load capacitor is switched to emit light according to the grayscale 0 corresponding to 0.2V. When the voltage of the fourth signal is equal to the voltage of the first signal, the second transistor NM1 remains on and is in a subthreshold working state (in this working state, the static current is very small), so that the pixel corresponding to the load capacitor stably emits light according to the grayscale 0 corresponding to 0.2V.

[0145] like ​ As shown in the figure, the dotted line represents the voltage change of the first signal input at the positive input terminal VIN+. The voltage of the first signal jumps from 5.3V to 0.2V at 12.0us. The solid line represents the voltage change of the signal output at the output terminal VOUT. At 12.0us, the Self_SRB function is turned on, and the voltage of the signal output from VOUT starts to decrease rapidly from 5.3V, quickly discharging the load capacitor. When |VIN-VOUT|=|VTH PM2 | moment (ie, the absolute value of the second voltage difference is equal to the reference threshold value |VTH PM2 |) The Self_SRB function is turned off, and the voltage of the signal output by VOUT slowly decreases until it equals 0.2V, slowly discharging the load capacitor.

[0146] Optionally, the second trigger signal is generated when the transistor included in the second trigger unit is in the on state, and the source of the transistor included in the second trigger unit is connected to the well potential. For example, if the transistor included in the second trigger unit is a seventh transistor, the source of the seventh transistor is also connected to the well potential of the seventh transistor to reduce the above-mentioned reference threshold. For example, see ​ , ​The source of the seventh transistor PM2 is connected to the well potential of the seventh transistor PM2. In this way, the reference threshold VTH can be reduced. PM2 |, thus delaying |VIN-VOUT|=|VTH PM2 | moment, which makes the Self_SRB function closed later, thereby extending the time when the Self_SRB function is turned on and the time for quickly discharging the load capacitor, which is beneficial to further improve the refresh rate of the display panel.

[0147] In addition, as mentioned above, the Self_SRB function is activated when the absolute value of the first voltage difference is greater than the reference threshold value |VTH PM2 By lowering the reference threshold |VTH PM2 |, it can also make the absolute value of the first voltage difference more likely to be greater than the reference threshold value |VTH PM2 In other words, the voltage of the first signal input to the positive input terminal VIN+ only needs to be slightly reduced to satisfy the absolute value of the first voltage difference being greater than the reference threshold value |VTH PM2 | condition, the Self_SRB function is turned on, that is, the time when the Self_SRB function is turned on is earlier, which also extends the time when the Self_SRB function is turned on and the time for quickly discharging the load capacitor, which is beneficial to further improve the refresh rate of the display panel.

[0148] The reference threshold VTH can be lowered by connecting the source of the seventh transistor PM2 to the well potential of the seventh transistor PM2. PM2 The reason is as follows. Affected by the PMOS tube body effect, the greater the voltage difference 2 between the voltage outputted by the output terminal VOUT and the voltage at the well potential of the seventh transistor PM2, the greater the reference threshold value |VTH PM2 | is also larger, and by connecting the source of the seventh transistor PM2 to the well potential of the seventh transistor PM2, the voltage difference 2 can be reduced, thereby reducing the reference threshold value | VTH PM2 |.

[0149] In the source driver module, PMOS is a medium voltage device. ​ The medium-voltage PMOS device is placed in a deep n-well to isolate it from the p-substrate used by the high-voltage devices. Only PMOS devices with one well potential can be placed in the same deep n-well; PMOS devices with different well potentials cannot be placed in the same deep n-well because this would cause a short circuit between the n-well (n-well) corresponding to the PMOS and the deep n-well. The p+ in the n-well represents a heavily doped P-type semiconductor, while the n+ in the n-well represents a heavily doped N-type semiconductor.

[0150] In one example, if the source of the seventh transistor PM2 is connected to the well potential of the seventh transistor PM2, resulting in the well potential of the seventh transistor PM2 being different from the well potential of other PMOS in the driving circuit, the seventh transistor PM2 needs to be arranged in a separate deep n-well, and the spacing between different deep n-wells needs to meet the requirements of design rule check (DRC), although the size of the driving circuit, and the size of the channel where the driving circuit is located and the size of the source driving module may be slightly increased, the increased size is tolerable.

[0151] In another example, if the source of the seventh transistor PM2 is connected to the well potential of the seventh transistor PM2, but the well potential of the seventh transistor PM2 is still the same as the well potential of other PMOS in the driving circuit, the seventh transistor PM2 and other PMOS can be arranged in the same deep n-well. Thus, not only is the reference threshold |VTH PM2 | reduced, but also the size of the driving circuit, and the size of the channel where the driving circuit is located and the size of the source driving module are relatively small.

[0152] Exemplarily, the gear of the second current source can be adjusted, and the gear of the second current source is used to control the generation speed of the control signal indicating the voltage reduction, and then affect the speed of discharging the load capacitance, thereby facilitating the adaptation to various refresh rate requirements. The embodiments of the present application do not limit the way of adjusting the gear of the second current source.

[0153] For example, referring to ​ , the gear of the second current source I0 includes OFF, ON1, ON2 and ON3. In the case of OFF, the second control unit is not started, and the Self_SRB function is not enabled. In the case of ON1, ON2 and ON3 respectively, the current provided by the second current source I0 increases in turn, so that the generation speed of the control signal indicating the voltage reduction increases in turn (i.e., the speed of pulling up the voltage at the first point A increases in turn), the speed of discharging the load capacitance increases in turn (i.e., the slope of the falling phase shown in ​ increases in turn), and the refresh rate that can be provided increases in turn.

[0154] As shown in (a) of ​ , mark ① at the positive input end VIN+, mark ② at the output end VOUT, mark ③ at the gate and drain of the fifth transistor PM3, mark ④ at the gate of the third transistor NM4, mark ⑤ at the second point B, and mark ⑥ at the first point A. Based on this, in combination with (b) of ​ , the voltage changes of ① to ⑥ in the process of discharging the load capacitance are explained. The process of discharging the load capacitance corresponds to the period after 12.0us (including 12.0us as an endpoint).

[0155] For ① at the positive input terminal VIN+, the voltage at ① jumps from 5.3V to 0.2V at 12.0us, causing the seventh transistor PM2 to turn on, and the Self_SRB function to turn on.

[0156] For ③ at the gate and drain of the fifth transistor PM3, and for ④ at the gate of the third transistor NM4, the voltage does not change because they belong to the first control unit.

[0157] For the gate and drain of the eighth transistor NM3, the voltage at the gate and drain of the eighth transistor NM3 is pulled up quickly because the seventh transistor PM2 is turned on.

[0158] For the gate of the sixth transistor PM4, the voltage at the gate of the sixth transistor PM4 is pulled down quickly after processing by the second inverter 55 because the voltage at the gate and drain of the eighth transistor NM3 is pulled up quickly, and the sixth transistor PM4 is turned on.

[0159] For ⑥ at the first point A, the current source X is in parallel with ⑥ when the sixth transistor PM4 is turned on, and the voltage at ⑥ is pulled up quickly but with a small amplitude (essentially unchanged) because of the parallel connection.

[0160] For ⑤ at the second point B, the voltage at ⑤ is pulled up quickly by the floating current source F because the voltage at ⑥ is pulled up quickly, causing the second transistor NM1 to turn on quickly.

[0161] For ② at the output terminal VOUT, the voltage at ② is pulled down quickly because the second transistor NM1 is turned on quickly, until the absolute value of the second voltage difference between the voltage at ① and the voltage at ② is equal to the reference threshold |VTH PM2 |, the seventh transistor PM2 is turned off, and the Self_SRB function is turned off.

[0162] For ③ at the gate and drain of the fifth transistor PM3, and for ④ at the gate of the third transistor NM4, the voltage does not change because they belong to the first control unit.

[0163] For the gate and drain of the eighth transistor NM3, the voltage at the gate and drain of the eighth transistor NM3 is pulled down and remains stable because the seventh transistor PM2 is turned off.

[0164] For the gate of the sixth transistor PM4, the voltage at the gate of the sixth transistor PM4 is pulled up and remains stable after processing by the second inverter 55 because the voltage at the gate and drain of the eighth transistor NM3 is pulled down, and the sixth transistor PM4 is turned off.

[0165] For the first point A, the voltage of ⑥ is also pulled low and remains stable when the sixth transistor PM4 is off.

[0166] For the second point B, the voltage of ⑤ is pulled low by the floating current source F due to the voltage of ⑥, and remains stable when the voltage of ② is equal to the voltage of ①, and the second transistor NM1 remains on, and the bias current still exists in the driving circuit.

[0167] For the output terminal VOUT, the voltage of ② is slowly reduced based on the bias current due to the bias current still existing in the driving circuit, and remains stable when the voltage of ② is equal to the voltage of ①.

[0168] In summary, the control module in the embodiment of the present application can automatically generate a control signal, and the output module quickly adjusts the voltage of the output signal according to the control signal, so as to realize adaptive enhancement of the slew rate of the output module. For example, in the case that the absolute value of the first voltage difference between the input first signal and the output second signal is greater than the reference threshold value, the control module automatically generates a control signal, and the SELF_SRB function is enabled, so that the slew rate of the output module is adaptively enhanced, the voltage of the second signal is quickly changed, and the output driving signal is formed. In the case that the absolute value of the second voltage difference between the input first signal and the output driving signal is equal to or less than the reference threshold value, the control module stops generating the control signal, and the SELF_SRB function is disabled, so that the slew rate of the output module returns to normal, and the voltage of the driving signal is slowly changed until it is equal to the input first signal. Thus, without relying on the TCON module, the design complexity is reduced, the total power consumption of the driving circuit is reduced, the charging and discharging speed of the load capacitor is improved, and the refresh rate of the display panel is improved.

[0169] Exemplarily, the embodiment of the present application also provides a display driving chip, which comprises any one of the driving circuits described above.

[0170] In an exemplary embodiment, the embodiment of the present application also provides an electronic device, which comprises a display panel and a display driving chip described above. The connection relationship between the display panel and the driving circuit in the display driving chip can be referred to ​ , which will not be repeated here.

[0171] It should be noted that the terms "first", "second", and the like, as used in the description and in the claims, are used to describe various objects and are not necessarily used to denote an order or sequence, unless otherwise indicated by the context. It will be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of use in either order. The embodiments described in the following examples have not necessarily been described with reference to their critical, required, or even optional elements, in order not to unnecessarily obscure the description of the application. The following examples are merely exemplary embodiments of how the application can be made, practiced, or implemented and are not intended to limit the application in any way.

[0172] It should be understood that "a plurality of" as referred to herein means two or more. The above-mentioned sequence of the embodiments of the application is only for description, and does not represent the advantages and disadvantages of the embodiments.

[0173] The above description is merely exemplary embodiments of the application, and is not intended to limit the application. Any modification, equivalent replacement, improvement, etc. made within the principles of the application shall be included in the protection scope of the application.

Claims

1. A driving circuit, characterized in that: The driving circuit includes a control module and an output module, the control module is connected to the output module, and the output module is connected to the display panel; The control module is configured to generate a control signal when an absolute value of a first voltage difference between an input first signal and a second signal output by the output module is greater than a reference threshold; The output module is used to output a driving signal according to the control signal, the absolute value of the second voltage difference between the first signal and the driving signal is smaller than the absolute value of the first voltage difference, and the driving signal is used to drive the pixels on the display panel to emit light.

2. The driving circuit according to claim 1, wherein: The control module includes a first control unit and a second control unit, the first control unit and the second control unit are respectively connected to the output module, and the first voltage difference is a voltage difference obtained by subtracting the voltage of the second signal from the voltage of the first signal; The first control unit is configured to generate a control signal indicating a voltage increase according to the first voltage difference; The output module is configured to output the driving signal according to the control signal indicating a voltage increase, wherein the driving signal is a third signal, and a voltage of the third signal is greater than a voltage of the second signal; the second control unit is configured to generate a control signal indicating a voltage reduction according to the first voltage difference; The output module is configured to output the driving signal according to the control signal indicating a voltage reduction, wherein the driving signal is a fourth signal, and a voltage of the fourth signal is lower than a voltage of the second signal.

3. The driving circuit according to claim 2, wherein: The output module includes an output terminal, and the output terminal is used for the output module to output the second signal, the third signal or the fourth signal; In the case where the third signal is output through the output terminal, the voltage of the third signal is used to charge the load capacitor on the display panel, so as to drive the pixel corresponding to the load capacitor to emit light and increase the brightness; In the case where the fourth signal is output through the output terminal, the voltage of the fourth signal is used to discharge the load capacitor on the display panel, so as to drive the pixel corresponding to the load capacitor to emit light with reduced brightness.

4. The driving circuit according to claim 2, wherein: The first control unit includes a first trigger unit, a first inverter, and a first generating unit, wherein the first trigger unit is connected to the first inverter, the first inverter is further connected to the first generating unit, and the first generating unit is further connected to a grounded first current source and the output module respectively; The first trigger unit is configured to generate a first trigger signal according to the first voltage difference; The first inverter is configured to generate a first inverted signal according to the first trigger signal; The first generating unit is configured to generate the control signal indicating voltage increase according to the first inverted signal.

5. The driving circuit according to claim 4, wherein: The gear of the first current source is adjustable, and the gear of the first current source is used to control the generation speed of the control signal indicating voltage increase.

6. The driving circuit according to claim 4, wherein: The first trigger signal is generated when the transistor included in the first trigger unit is in an on state, and the source of the transistor included in the first trigger unit is connected to the substrate.

7. The driving circuit according to any one of claims 2 to 6, characterized in that: The second control unit includes a second trigger unit, a second inverter and a second generating unit, the second trigger unit is connected to the second inverter, the second inverter is further connected to the second generating unit, and the second generating unit is further connected to a second current source connected to a positive power supply and the output module respectively; The second trigger unit is configured to generate a second trigger signal according to the first voltage difference; The second inverter is configured to generate a second inverted signal according to the second trigger signal; The second generating unit is configured to generate the control signal indicating voltage reduction according to the second inverted signal.

8. The driving circuit according to claim 7, wherein: The gear of the second current source is adjustable, and the gear of the second current source is used to control the generation speed of the control signal indicating voltage reduction.

9. The driving circuit according to claim 7, wherein: The second trigger signal is generated when the transistor included in the second trigger unit is in an on state, and the source of the transistor included in the second trigger unit is connected to the well potential.

10. A display driver chip, characterized in that: The display driver chip includes the driver circuit according to any one of claims 1 to 9.

11. An electronic device, characterized in that: The electronic device comprises a display panel and the display driver chip according to claim 10.

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