Method, device and equipment for balancing ECC (Error Correction Code) error correction capability of flash memory and storage medium

Abstract

The invention discloses a method, device and equipment for balancing the ECC error correction capability of a flash memory and a storage medium, and the method comprises the steps: obtaining the reading speed of the flash memory in a preset time period, and obtaining a plurality of first reading speeds; acquiring the working voltage of the flash memory in the preset time period to obtain a plurality of working voltages; determining a first ECC error correction algorithm according to the plurality of first reading speeds; determining a first algorithm control parameter of the first ECC error correction algorithm according to the plurality of working voltages; and controlling the flash memory to perform ECC error correction processing according to the first ECC error correction algorithm and the first algorithm control parameter. By adopting the embodiment of the invention, a balance can be found between the reading speed of the flash memory and the ECC (Error Correction Code) performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage or the technical field of computer, in particular to a method and device for balancing ECC error correction capability of flash memory, equipment and a storage medium. BACKGROUND

[0002] In practical applications, the read speed of flash memory will have a certain impact on ECC in error detection, error repair and system architecture stability. Further, in order to ensure the effective work of ECC, it is necessary to find a balance between the read speed of flash memory and the performance of ECC to ensure that ECC can accurately detect and repair data errors, and protect the reliability and integrity of data in flash memory. Therefore, the problem of how to find a balance between the read speed of flash memory and the performance of ECC needs to be solved. SUMMARY

[0003] The embodiments of the present application provide a method and device for balancing ECC error correction capability of flash memory, equipment and a storage medium, which can find a balance between the read speed of flash memory and the performance of ECC, thereby improving the intelligence of flash memory.

[0004] In a first aspect, the embodiments of the present application provide a method for balancing ECC error correction capability of flash memory, the method comprising:

[0005] obtaining the read speed of flash memory in a preset time period to obtain a plurality of first read speeds;

[0006] obtaining the working voltage of the flash memory in the preset time period to obtain a plurality of working voltages;

[0007] determining a first ECC error correction algorithm according to the plurality of first read speeds;

[0008] determining a first algorithm control parameter of the first ECC error correction algorithm according to the plurality of working voltages;

[0009] controlling the flash memory to perform ECC error correction processing according to the first ECC error correction algorithm and the first algorithm control parameter.

[0010] In a second aspect, the embodiments of the present application provide a device for balancing ECC error correction capability of flash memory, the device comprising an obtaining unit, a determining unit and a controlling unit, wherein:

[0011] The obtaining unit is configured to obtain the read speed of flash memory in a preset time period to obtain a plurality of first read speeds, and obtain the working voltage of the flash memory in the preset time period to obtain a plurality of working voltages.

[0012] The determining unit is configured to determine a first ECC correction algorithm according to the plurality of first reading speeds, and determine a first algorithm control parameter of the first ECC correction algorithm according to the plurality of working voltages.

[0013] The control unit is configured to control the flash memory to perform ECC correction processing according to the first ECC correction algorithm and the first algorithm control parameter.

[0014] In a third aspect, an embodiment of the present application provides an electronic device, which includes a processor, a memory, a communication interface, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor, and the programs include instructions for performing the steps in the first aspect of the present application.

[0015] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program for electronic data exchange, wherein the computer program causes a computer to perform some or all of the steps described in the first aspect of the present application.

[0016] In a fifth aspect, an embodiment of the present application provides a computer program product, which includes a non-transitory computer readable storage medium storing a computer program, and the computer program is operable to cause a computer to perform some or all of the steps described in the first aspect of the present application. The computer program product can be a software installation package.

[0017] By implementing the embodiments of the present application, the following beneficial effects are achieved:

[0018] It can be seen that, in the balancing flash memory ECC correction capability method, device, equipment and storage medium described in the embodiments of the present application, the reading speed of the flash memory in a preset time period is obtained, a plurality of first reading speeds are obtained, the working voltage of the flash memory in the preset time period is obtained, a plurality of working voltages are obtained, a first ECC correction algorithm is determined according to the plurality of first reading speeds, a first algorithm control parameter of the first ECC correction algorithm is determined according to the plurality of working voltages, and the flash memory is controlled to perform ECC correction processing according to the first ECC correction algorithm and the first algorithm control parameter. Since the plurality of first reading speeds reflect the working load change of the flash memory to some extent, that is, the working condition of the flash memory, the plurality of working voltages reflect the working state of the flash memory and the working stability of the flash memory to some extent, and then, on the one hand, the ECC correction capability is consistent with the working condition of the flash memory, and on the other hand, the ECC correction capability is further consistent with the working state and the working stability of the flash memory, so that a balance between the flash memory reading speed and the ECC performance can be found, and thus the intelligence of the flash memory is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 This is a flow chart of a method for balancing the ECC error correction capability of a flash memory provided by an embodiment of the present application;

[0021] Figure 2 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0022] Figure 3 This is a schematic diagram illustrating a scenario of a method for balancing the ECC error correction capability of a flash memory provided by an embodiment of the present application;

[0023] Figure 4 is a structural diagram of another electronic device provided in an embodiment of the present application;

[0024] Figure 5 This is a block diagram of the functional units of a device for balancing the ECC error correction capability of a flash memory provided by an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0026] The terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0027] Reference to an "embodiment" in this document means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. As will be apparent to those of ordinary skill in the art, embodiments described herein can be combined with other embodiments.

[0028] In the present application, the electronic device can be a device with storage function, for example, a handheld device, a wearable device (smart glasses, smart bracelet, smart watch, etc.), a solid state disk, a smart home device, a server, an Internet of Things device, a vehicle-mounted device (in-vehicle camera, vehicle recorders, vehicle-mounted sound box, etc.), a computing device or other processing device connected to a wireless modem, and various forms of user equipment (UE), mobile station (MS), terminal device, etc.

[0029] In the embodiments of the present application, a good block refers to a storage block in the flash memory that can normally perform read or write operations. A bad block specifically refers to a storage block in the flash memory that cannot normally perform read or write operations.

[0030] In the embodiments of the present application, Error Checking and Correction (ECC) is a technology for detecting and repairing data bit-level errors through redundant check information to ensure the reliability of data stored in the flash memory.

[0031] In specific implementations, bad blocks can be generated in the production and use of the flash memory, and the ECC can correct some error bits to avoid mislabeling repairable blocks as bad blocks, thereby prolonging the service life of the storage medium.

[0032] In the embodiments of the present application, the ECC error correction algorithm of the flash memory can include at least one of the following: LDPC (Low-Density Parity-Check) algorithm, BCH (Bose-Chaudhuri-Hocquenghem) algorithm, RS code (Reed-Solomon) algorithm, etc., without limitation.

[0033] In the embodiments of the present application, the median of the curve segment can be understood as, in mathematics and data analysis, the median of the curve segment generally refers to the median of the values of all points on the given curve segment.

[0034] The embodiments of the present application will be described in detail below.

[0035] Please refer to Figure 1 ,Figure 1 : This is a flow chart of a method for balancing the ECC error correction capability of a flash memory provided by an embodiment of the present application. The method for balancing the ECC error correction capability of a flash memory includes:

[0036] 101. Obtain a read speed of a flash memory within a preset time period to obtain a plurality of first read speeds.

[0037] In specific implementation, such as Figure 2 As shown, the electronic device may include a flash memory, which may be a part of the electronic device, or, as shown in FIG. Figure 3 As shown, the electronic device can be communicatively connected with the flash memory, that is, the electronic device and the flash memory are two independent devices.

[0038] The preset time period can be pre-set or set by system default. In a specific implementation, the read speed of the flash memory within the preset time period can be obtained to obtain multiple first read speeds. The length of the preset time period can be related to the properties of the flash memory, or the length of the preset time period can be related to the workload of the flash memory, wherein the workload of the flash memory can be understood as the amount of tasks and pressure borne by the flash memory during operation.

[0039] In a specific implementation, the read speed of the flash memory can be collected at a first preset time interval, thereby obtaining multiple first read speeds. The first preset time interval can be pre-set or set by system default. The first preset time interval can be related to the properties of the flash memory, or the first preset time interval can also be related to the workload of the flash memory. The multiple first read speeds reflect, to a certain extent, the workload changes of the flash memory, that is, the working status of the flash memory.

[0040] 102. Obtain the operating voltage of the flash memory within the preset time period to obtain multiple operating voltages.

[0041] In a specific implementation, the operating voltage of the flash memory may be collected at a second preset time interval, thereby obtaining multiple operating voltages. The second preset time interval may be pre-set or set by system default. The second preset time interval may be related to the properties of the flash memory, or the second preset time interval may also be related to the workload of the flash memory.

[0042] In an embodiment of the present application, the operating voltage of the flash memory within a preset time period can be obtained to obtain multiple operating voltages. The multiple operating voltages reflect the working status of the flash memory and the working stability of the flash memory to a certain extent.

[0043] 103. Determine a first ECC error correction algorithm according to the multiple first reading speeds.

[0044] In specific implementation, since the plurality of first read speeds reflect the workload change of the flash memory, i.e., the working condition of the flash memory to some extent, the first ECC correction algorithm can be determined according to the plurality of first read speeds, so that the ECC correction capability is consistent with the working condition of the flash memory, which helps to find a balance between the flash memory read speed and the ECC performance, thereby improving the intelligence of the flash memory.

[0045] Optionally, the step 103 of determining the first ECC correction algorithm according to the plurality of first read speeds can be implemented in the following manner:

[0046] determining a mean value of the plurality of first read speeds, to obtain a first mean value;

[0047] fitting according to the plurality of first read speeds to obtain a first fitting curve; the horizontal axis of the first fitting curve is time, and the vertical axis is read speed;

[0048] determining a preset time length corresponding to the first mean value;

[0049] intercepting a curve segment of the first fitting curve with the preset time length starting from the current time;

[0050] determining a median value of the curve segment;

[0051] determining the first ECC correction algorithm according to the median value.

[0052] In specific implementation, a mean value of the plurality of first read speeds can be determined to obtain a first mean value, which reflects the average working condition of the flash memory in a preset time period. Then, the plurality of first read speeds can be fitted to obtain a first fitting curve, the horizontal axis of the first fitting curve is time, and the vertical axis is read speed, i.e., since each read speed in the plurality of first read speeds corresponds to a collection time, the plurality of first read speeds and the corresponding collection times can be regarded as a plurality of coordinate points, the horizontal axis of the coordinate system in which the plurality of coordinate points are located is time, and the vertical axis is read speed, and then the plurality of coordinate points can be used for curve fitting to obtain the first fitting curve.

[0053] Next, the mapping relationship between the preset mean value and the time length can also be pre-stored, and then the preset time length corresponding to the first mean value can be determined based on the mapping relationship, and the curve segment of the first fitting curve with the preset time length starting from the current time is intercepted to determine the median of the curve segment. The mapping relationship between the preset median and the ECC correction algorithm can also be pre-stored, and the first ECC correction algorithm corresponding to the median of the curve segment is determined based on the mapping relationship. First, since the first mean value reflects the average working condition of the flash memory in the preset time period, the preset time length is a period of time after the current time, which considers the adaptability of the ECC correction capability in the next period of time, so that the adaptability in the next period of time is consistent with the current working condition, and the ECC correction capability is smoothly adjusted. Second, the median of the curve segment reflects the working condition of the flash memory in the next period of time to some extent, and the corresponding ECC correction algorithm is determined, that is, the continuity of the curve change is utilized to ensure that the flash memory can always find a balance between the flash memory reading speed and the ECC performance in a period of time after the current time.

[0054] 104. determining a first algorithm control parameter of the first ECC correction algorithm according to the plurality of working voltages.

[0055] In a specific implementation, since the plurality of working voltages reflect the working state and the working stability of the flash memory to some extent, the first algorithm control parameter of the first ECC correction algorithm can be further determined according to the plurality of working voltages, so that the ECC correction capability is further consistent with the working state and the working stability of the flash memory, which helps to find a balance between the flash memory reading speed and the ECC performance, thereby improving the intelligence of the flash memory.

[0056] The first algorithm control parameter of the first ECC correction algorithm is used to control the correction effect of the ECC correction algorithm, which can include at least one of the following: correction speed, correction ratio, correction degree, and the like, which are not limited herein.

[0057] Optionally, the step 104 of determining a first algorithm control parameter of the first ECC correction algorithm according to the plurality of working voltages can be implemented in the following manner:

[0058] fitting according to the plurality of working voltages to obtain a first fitting straight line and a first fitting curve segment corresponding to the preset time period; the horizontal axis of the first fitting straight line is time, and the vertical axis is voltage; the horizontal axis of the first fitting curve segment is time, and the vertical axis is voltage;

[0059] determining the absolute value of the slope of the first fitting straight line to obtain a first absolute value;

[0060] determining a first standard deviation of the first fitting curve segment;

[0061] determine a first algorithm control parameter of the first ECC correction algorithm according to the first standard deviation and the first absolute value.

[0062] In specific implementations, each of the plurality of working voltages can correspond to a collection time, and the plurality of working voltages and the corresponding collection times can be regarded as a plurality of coordinate points, a horizontal axis of a coordinate system in which the plurality of coordinate points are located being time and a vertical axis being voltage. A first fitting straight line is obtained by performing linear fitting based on the plurality of coordinate points, and correspondingly, a first fitting curve segment in the preset time period is obtained by performing curve fitting based on the plurality of coordinate points.

[0063] Further, an absolute value of a slope of the first fitting straight line can be determined to obtain a first absolute value, the first absolute value representing working stability of the flash memory. The first fitting curve segment can also be sampled to obtain a plurality of sampling points, and a first standard deviation is obtained by performing standard deviation operation based on the plurality of sampling points, the first standard deviation reflecting working stability of the flash memory in the preset time period.

[0064] Finally, a first algorithm control parameter of the first ECC correction algorithm can be determined according to the first standard deviation and the first absolute value, that is, since the first absolute value represents long-term stability of the flash memory and the first standard deviation reflects short-term stability of the flash memory in the preset time period, the current stability of the flash memory can be evaluated based on the short-term stability and the long-term stability, and the first algorithm control parameter that is deeply adapted to the current stability is determined, which helps to find a balance between the flash memory reading speed and the ECC performance, thereby improving the intelligence of the flash memory.

[0065] Optionally, the step of determining a first algorithm control parameter of the first ECC correction algorithm according to the first standard deviation and the first absolute value can be implemented in the following manner:

[0066] determining a first stability score value corresponding to the first absolute value;

[0067] determining a second stability score value corresponding to the first standard deviation;

[0068] determining a first weight pair according to the first stability score value and the second stability score value, the first weight pair including a first weight and a second weight, a sum of the first weight and the second weight being 1;

[0069] determining a target stability score value according to the first stability score value, the second stability score value, and the first weight pair;

[0070] determining a first algorithm control parameter of the first ECC correction algorithm corresponding to the target stability score value.

[0071] In a specific implementation, a first mapping relationship between a preset absolute value and a stability score value can be pre-stored, that is, a first stability score value corresponding to a first absolute value can be determined based on the first mapping relationship. Correspondingly, a second mapping relationship between a preset standard deviation and a stability score value can also be pre-stored, and a second stability score value corresponding to a first standard deviation can be determined based on the second mapping relationship. The score mechanisms corresponding to the above stability score values are all percentage values, and the higher the score, the better the stability.

[0072] Further, a first weight pair including a first weight and a second weight can be determined according to the first stability score value and the second stability score value, a sum of the first weight and the second weight is 1, the first weight = the first stability score value / (the first stability score value + the second stability score value), and the second weight = the second stability score value / (the first stability score value + the second stability score value). In this way, the higher the stability score value of different stages, the greater the corresponding weight, which can make the weight distribution more reasonable. Then, a target stability score value is determined according to the first stability score value, the second stability score value, and the first weight pair, that is, the target stability score value = the first stability score value x the first weight + the second stability score value x the second weight. A mapping relationship between a preset stability score value and an algorithm control parameter of a first ECC error correction algorithm can also be pre-stored, and a first algorithm control parameter of the first ECC error correction algorithm corresponding to the target stability score value can be determined based on the mapping relationship. That is, since the first absolute value represents the working stability (long-term stability) of the flash memory, and the first standard deviation reflects the working stability (short-term stability) of the flash memory in a preset time period, the current stability of the flash memory can be evaluated based on the short-term stability and the long-term stability, and the higher the stability score value of different stages, the greater the corresponding weight, which can make the weight distribution more reasonable, and the first algorithm control parameter that is deeply adapted to the current stability is determined, which helps to find a balance between the flash memory read speed and the ECC performance, thereby improving the intelligence of the flash memory.

[0073] 105. Controlling the flash memory to perform ECC error correction processing according to the first ECC error correction algorithm and the first algorithm control parameter.

[0074] In the embodiments of the present application, the flash memory can be controlled to perform ECC error correction processing according to the first ECC error correction algorithm and the first algorithm control parameter, that is, on the one hand, the ECC error correction capability is consistent with the working condition of the flash memory, and on the other hand, the ECC error correction capability is further consistent with the working state and the working stability of the flash memory. In this way, a balance between the flash memory read speed and the ECC performance can be found, thereby improving the intelligence of the flash memory.

[0075] Optionally, after the ECC correction processing of the flash memory is performed according to the first ECC correction algorithm and the first algorithm control parameter in step 105, the method further comprises the following steps:

[0076] obtaining a plurality of second read speeds by obtaining read speeds in a first time period, the first time period being a time period after the current time;

[0077] determining a second average value by determining an average of the plurality of second read speeds;

[0078] determining a first deviation between the second average value and the first average value;

[0079] determining m free good blocks in the flash memory when the first deviation is greater than a preset threshold, m being an integer greater than 1;

[0080] obtaining m residual erase times by determining a residual erase time of each of the m free good blocks;

[0081] determining an average residual erase time of the m residual erase times;

[0082] determining a first optimization parameter corresponding to the average residual erase time;

[0083] optimizing the first algorithm control parameter to obtain a second algorithm control parameter according to the first optimization parameter;

[0084] performing the ECC correction processing of the flash memory according to the first ECC correction algorithm and the second algorithm control parameter.

[0085] The preset threshold can be pre-set or system default. For example, the preset threshold is greater than 0.

[0086] In a specific implementation, a plurality of second read speeds can be obtained by obtaining read speeds in a first time period, the first time period being a time period after the current time. Then, a second average value can be determined by determining an average of the plurality of second read speeds. A first deviation can be determined between the second average value and the first average value, the first deviation = (second average value-first average value) / first average value. When the first deviation is greater than a preset threshold, it indicates that the read speed suddenly increases. When the read speed of the flash memory suddenly increases, the ECC correction difficulty increases and the error probability rises. If the ECC capability cannot adapt to the change, the number of errors of the flash memory may increase dramatically after reaching the nominal P / E number.

[0087] Next, the free good blocks in the flash memory can be determined to obtain m free good blocks, m being an integer greater than 1, the remaining erase times of each of the m free good blocks can be determined to obtain m remaining erase times, the remaining erase times of the storage block reflecting the health status and expected life of the storage device, i.e., reflecting the performance of the storage block, and then the average remaining erase times of the m remaining erase times can be determined, the average remaining erase times reflecting the overall performance of the storage block, i.e., the mapping relationship between the preset remaining erase times and the optimization parameter can be stored in advance, the value range of the optimization parameter can be set in advance or by default, for example, the value range of the optimization parameter is -0.02~0.02, i.e., the first optimization parameter corresponding to the average remaining erase times can be determined based on the mapping relationship, and then part or all of the algorithm control parameters in the first algorithm control parameter are optimized according to the first optimization parameter to obtain the second algorithm control parameter, for example, the second algorithm control parameter = the first algorithm control parameter x (1+ the first optimization parameter), and finally, the flash memory can be controlled for ECC error correction processing according to the first ECC correction algorithm and the second algorithm control parameter, so that the overall performance of the storage block can be further dynamically and deeply optimized based on the algorithm control parameter when the flash memory read speed suddenly becomes large, a balance between the flash memory read speed and the ECC performance can be further found, and thus the intelligence of the flash memory is improved.

[0088] It can be seen that the method for balancing the ECC correction capability of the flash memory described in the embodiments of the present application obtains the read speed of the flash memory in a preset time period to obtain a plurality of first read speeds, obtains the working voltage of the flash memory in the preset time period to obtain a plurality of working voltages, determines a first ECC correction algorithm according to the plurality of first read speeds, determines a first algorithm control parameter of the first ECC correction algorithm according to the plurality of working voltages, and controls the flash memory for ECC error correction processing according to the first ECC correction algorithm and the first algorithm control parameter. Since the plurality of first read speeds reflect the working load change of the flash memory to some extent, i.e., the working condition of the flash memory, and the plurality of working voltages reflect the working state and the working stability of the flash memory to some extent, on the one hand, the ECC correction capability is consistent with the working condition of the flash memory, and on the other hand, the ECC correction capability is further consistent with the working state and the working stability of the flash memory, so that a balance between the flash memory read speed and the ECC performance can be found, and thus the intelligence of the flash memory is improved.

[0089] Please refer to Figure 4 , Figure 4Fig. 2 is a structural schematic diagram of another electronic device provided in an embodiment of the present application. The electronic device includes a processor, a memory, a communication interface, and one or more programs. The one or more programs are stored in the memory and configured to be executed by the processor. In the embodiment of the present application, the program includes instructions for performing the following steps:

[0090] obtaining a plurality of first read speeds of the flash memory in a preset time period;

[0091] obtaining a plurality of working voltages of the flash memory in the preset time period;

[0092] determining a first ECC correction algorithm according to the plurality of first read speeds;

[0093] determining a first algorithm control parameter of the first ECC correction algorithm according to the plurality of working voltages;

[0094] controlling the flash memory to perform ECC correction processing according to the first ECC correction algorithm and the first algorithm control parameter.

[0095] Optionally, in the aspect of determining the first ECC correction algorithm according to the plurality of first read speeds, the program includes instructions for performing the following steps:

[0096] determining a first mean value of the plurality of first read speeds;

[0097] fitting the plurality of first read speeds to obtain a first fitting curve; the horizontal axis of the first fitting curve is time, and the vertical axis is read speed;

[0098] determining a preset time length corresponding to the first mean value;

[0099] cutting a curve segment of the first fitting curve with the preset time length as a starting point from a current time point;

[0100] determining a median value of the curve segment;

[0101] determining the first ECC correction algorithm according to the median value.

[0102] Optionally, in the aspect of determining the first algorithm control parameter of the first ECC correction algorithm according to the plurality of working voltages, the program includes instructions for performing the following steps:

[0103] fitting the plurality of working voltages to obtain a first fitting straight line and a first fitting curve segment corresponding to the preset time period; the horizontal axis of the first fitting straight line is time, and the vertical axis is voltage; the horizontal axis of the first fitting curve segment is time, and the vertical axis is voltage;

[0104] determining an absolute value of the slope of the first fitted straight line, to obtain a first absolute value;

[0105] determining a first standard deviation of the first fitted curve segment;

[0106] determining a first algorithm control parameter of the first ECC correction algorithm according to the first standard deviation and the first absolute value.

[0107] Optionally, in the aspect of determining the first algorithm control parameter of the first ECC correction algorithm according to the first standard deviation and the first absolute value, the program includes instructions for performing the following steps:

[0108] determining a first stability score value corresponding to the first absolute value;

[0109] determining a second stability score value corresponding to the first standard deviation;

[0110] determining a first weight pair including a first weight and a second weight according to the first stability score value and the second stability score value, a sum of the first weight and the second weight being 1;

[0111] determining a target stability score value according to the first stability score value, the second stability score value and the first weight pair;

[0112] determining the first algorithm control parameter of the first ECC correction algorithm corresponding to the target stability score value.

[0113] Optionally, after the flash memory is controlled to perform the ECC correction processing according to the first ECC correction algorithm and the first algorithm control parameter, the program further includes instructions for performing the following steps:

[0114] obtaining read speeds in a first time period to obtain a plurality of second read speeds; the first time period is a time period after the current time;

[0115] determining a second mean value of the plurality of second read speeds;

[0116] determining a first deviation degree between the second mean value and the first mean value;

[0117] when the first deviation degree is greater than a preset threshold, determining m idle good blocks in the flash memory, m being an integer greater than 1;

[0118] determining a remaining erase count of each of the m idle good blocks to obtain m remaining erase counts;

[0119] determine an average remaining erase number of the m remaining erase numbers;

[0120] determine a first optimization parameter corresponding to the average remaining erase number;

[0121] optimize the first algorithm control parameter according to the first optimization parameter to obtain a second algorithm control parameter;

[0122] control the flash memory to perform ECC error correction processing according to the first ECC error correction algorithm and the second algorithm control parameter.

[0123] It can be seen that the electronic device described in the embodiments of the present application obtains the read speed of the flash memory in a preset time period to obtain a plurality of first read speeds, obtains the working voltage of the flash memory in the preset time period to obtain a plurality of working voltages, determines a first ECC error correction algorithm according to the plurality of first read speeds, determines a first algorithm control parameter of the first ECC error correction algorithm according to the plurality of working voltages, and controls the flash memory to perform ECC error correction processing according to the first ECC error correction algorithm and the first algorithm control parameter. Since the plurality of first read speeds reflect the working load change of the flash memory to some extent, that is, the working condition of the flash memory, and the plurality of working voltages reflect the working state and the working stability of the flash memory to some extent, on the one hand, the ECC error correction capability is consistent with the working condition of the flash memory, and on the other hand, the ECC error correction capability is further consistent with the working state and the working stability of the flash memory. In this way, a balance between the read speed of the flash memory and the ECC performance can be found, so that the intelligence of the flash memory is improved.

[0124] Figure 5 is a functional unit composition block diagram of a balancing flash memory ECC error correction capability device 500 involved in the embodiments of the present application. The balancing flash memory ECC error correction capability device 500 includes an acquisition unit 501, a determination unit 502, and a control unit 503, wherein,

[0125] The acquisition unit 501 is configured to obtain the read speed of the flash memory in a preset time period to obtain a plurality of first read speeds, and obtain the working voltage of the flash memory in the preset time period to obtain a plurality of working voltages.

[0126] The determination unit 502 is configured to determine a first ECC error correction algorithm according to the plurality of first read speeds, and determine a first algorithm control parameter of the first ECC error correction algorithm according to the plurality of working voltages.

[0127] The control unit 503 is configured to control the flash memory to perform ECC error correction processing according to the first ECC error correction algorithm and the first algorithm control parameter.

[0128] Optionally, in the aspect of determining the first ECC correction algorithm according to the plurality of first reading speeds, the determining unit 502 is specifically configured to:

[0129] determine a mean value of the plurality of first reading speeds, to obtain a first mean value;

[0130] fit according to the plurality of first reading speeds, to obtain a first fitting curve; the horizontal axis of the first fitting curve is time, and the vertical axis is reading speed;

[0131] determine a preset time length corresponding to the first mean value;

[0132] cut a curve segment of the first fitting curve with the preset time length starting from the current time;

[0133] determine a median value of the curve segment;

[0134] determine the first ECC correction algorithm according to the median value.

[0135] Optionally, in the aspect of determining the first algorithm control parameter of the first ECC correction algorithm according to the plurality of working voltages, the determining unit 502 is specifically configured to:

[0136] fit according to the plurality of working voltages, to obtain a first fitting straight line and a first fitting curve segment corresponding to the preset time period; the horizontal axis of the first fitting straight line is time, and the vertical axis is voltage; the horizontal axis of the first fitting curve segment is time, and the vertical axis is voltage;

[0137] determine an absolute value of the slope of the first fitting straight line, to obtain a first absolute value;

[0138] determine a first standard deviation of the first fitting curve segment;

[0139] determine the first algorithm control parameter of the first ECC correction algorithm according to the first standard deviation and the first absolute value.

[0140] Optionally, in the aspect of determining the first algorithm control parameter of the first ECC correction algorithm according to the first standard deviation and the first absolute value, the determining unit 502 is specifically configured to:

[0141] determine a first stability score value corresponding to the first absolute value;

[0142] determine a second stability score value corresponding to the first standard deviation;

[0143] determine a first weight pair according to the first stability score value and the second stability score value, the first weight pair including a first weight and a second weight, and the sum of the first weight and the second weight is 1.

[0144] determining a target stability score value according to the first stability score value, the second stability score value and the first weight value;

[0145] determining a first algorithm control parameter of the first ECC error correction algorithm corresponding to the target stability score value.

[0146] Optionally, after the flash memory is controlled to perform ECC error correction processing according to the first ECC error correction algorithm and the first algorithm control parameter, the balanced flash memory ECC error correction capability device 500 is specifically used for:

[0147] obtaining a plurality of second read speeds by obtaining read speeds in a first time period; the first time period is a time period after the current time;

[0148] determining a second average value by determining an average value of the plurality of second read speeds;

[0149] determining a first deviation between the second average value and the first average value;

[0150] when the first deviation is greater than a preset threshold, determining m idle good blocks in the flash memory, m being an integer greater than 1;

[0151] determining m residual erase times of each of the m idle good blocks, to obtain m residual erase times;

[0152] determining an average residual erase time of the m residual erase times;

[0153] determining a first optimization parameter corresponding to the average residual erase time;

[0154] optimizing the first algorithm control parameter according to the first optimization parameter to obtain a second algorithm control parameter;

[0155] controlling the flash memory to perform ECC error correction processing according to the first ECC error correction algorithm and the second algorithm control parameter.

[0156] It can be seen that the balanced flash memory ECC error correction capability device described in the embodiment of the application obtains the read speed of the flash memory in a preset time period, obtains a plurality of first read speeds, obtains the working voltage of the flash memory in the preset time period, obtains a plurality of working voltages, determines a first ECC error correction algorithm according to the plurality of first read speeds, determines a first algorithm control parameter of the first ECC error correction algorithm according to the plurality of working voltages, and controls the flash memory to perform ECC error correction processing according to the first ECC error correction algorithm and the first algorithm control parameter. Since the plurality of first read speeds reflect the working load change of the flash memory to some extent, that is, the working condition of the flash memory, and the plurality of working voltages reflect the working state and the working stability of the flash memory to some extent, on the one hand, the ECC error correction capability is consistent with the working condition of the flash memory, and on the other hand, the ECC error correction capability is further consistent with the working state and the working stability of the flash memory. In this way, a balance between the flash memory read speed and the ECC performance can be found, and thus the intelligence of the flash memory is improved.

[0157] It can be understood that the functions of the program modules of the balanced flash memory ECC error correction capability device of the embodiment can be specifically implemented according to the methods in the above method embodiments, and the specific implementation process can be referred to the related description of the above method embodiments, which will not be described here.

[0158] The embodiment of the application further provides a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, and the computer program causes the computer to execute part or all steps of any method described in the above method embodiments.

[0159] The embodiment of the application further provides a computer program product, and the computer program product includes a non-transitory computer readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute part or all steps of any method described in the above method embodiments. The computer program product can be a software installation package.

[0160] It should be noted that, for each of the above method embodiments, in order to simply describe, each is described as a combination of a series of actions, but those skilled in the art should know that the application is not limited by the order of the actions described, because according to the application, certain steps can be performed in other order or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily required by the application.

[0161] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0162] In several embodiments provided in the present application, it should be understood that the disclosed apparatus can be implemented in other manners. For example, the division of the apparatus embodiments described above is merely illustrative, and the division of the units can be changed according to actual needs. For example, the units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0163] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0164] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically, or two or more units can be integrated into one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0165] When the integrated unit is realized in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store program codes.

[0166] Those of ordinary skill in the art can understand that all or part of the steps of the various methods in the above embodiments can be completed by a program instructing relevant hardware, and the program can be stored in a computer readable storage medium, which can include a flash disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, etc.

[0167] The above has introduced the embodiments of the present application in detail, and the principle and implementation mode of the present application are described by applying specific examples; the above embodiment description is only for helping to understand the method of the present application and its core idea; meanwhile, for the general technical personnel in the art, according to the idea of the present application, the specific implementation mode and application range will have changes; and in view of the above, the content of the specification should not be understood as the limitation of the present application.

Claims

1. A method for balancing the ECC error correction capability of a flash memory, characterized in that: The method comprises: Obtaining a read speed of the flash memory within a preset time period to obtain a plurality of first read speeds; Acquire the operating voltage of the flash memory within the preset time period to obtain multiple operating voltages; determining a first ECC error correction algorithm according to the plurality of first reading speeds; determining a first algorithm control parameter of the first ECC error correction algorithm according to the multiple operating voltages; The flash memory is controlled to perform ECC error correction processing according to the first ECC error correction algorithm and the first algorithm control parameters.

2. The method for balancing the ECC error correction capability of a flash memory according to claim 1, wherein: The determining a first ECC error correction algorithm according to the plurality of first reading speeds includes: Determine an average of the plurality of first reading speeds to obtain a first average; Performing fitting according to the plurality of first reading speeds to obtain a first fitting curve, wherein the horizontal axis of the first fitting curve is time and the vertical axis is reading speed; Determining a preset time duration corresponding to the first mean value; intercepting a curve segment of the preset duration starting from the current moment in the first fitting curve; determining a median value of the curve segment; The first ECC error correction algorithm is determined according to the median value.

3. The method for balancing the ECC error correction capability of a flash memory according to claim 2, wherein: The determining the first algorithm control parameter of the first ECC error correction algorithm according to the multiple operating voltages includes: Fitting is performed based on the multiple operating voltages to obtain a first fitting straight line and a first fitting curve segment corresponding to the preset time period; the horizontal axis of the first fitting straight line is time, and the vertical axis is voltage; the horizontal axis of the first fitting curve segment is time, and the vertical axis is voltage; determining an absolute value of the slope of the first fitting straight line to obtain a first absolute value; determining a first standard deviation of the first fitted curve segment; A first algorithm control parameter of the first ECC error correction algorithm is determined according to the first standard deviation and the first absolute value.

4. The method for balancing the ECC error correction capability of a flash memory according to claim 3, wherein: Determining a first algorithm control parameter of the first ECC error correction algorithm according to the first standard deviation and the first absolute value includes: determining a first stability score corresponding to the first absolute value; determining a second stability score corresponding to the first standard deviation; determining a first weight pair according to the first stability score and the second stability score, wherein the first weight pair includes a first weight and a second weight, and a sum of the first weight and the second weight is 1; determining a target stability score value according to the first stability score value, the second stability score value, and the first weight pair; A first algorithm control parameter of the first ECC error correction algorithm corresponding to the target stability score value is determined.

5. The method for balancing the ECC error correction capability of a flash memory according to any one of claims 2 to 4, characterized in that: After controlling the flash memory to perform ECC error correction processing according to the first ECC error correction algorithm and the first algorithm control parameters, the method further includes: Obtaining a reading speed in a first time period to obtain a plurality of second reading speeds; wherein the first time period is a time period after the current moment; determining an average of the plurality of second reading speeds to obtain a second average; determining a first deviation between the second mean and the first mean; When the first deviation is greater than a preset threshold, determining free good blocks in the flash memory to obtain m free good blocks, where m is an integer greater than 1; Determine the remaining number of erasures of each of the m idle good blocks to obtain m remaining number of erasures; Determining an average remaining number of erasures of the m remaining number of erasures; determining a first optimization parameter corresponding to the average remaining number of erasures; Optimizing the first algorithm control parameter according to the first optimization parameter to obtain a second algorithm control parameter; The flash memory is controlled to perform ECC error correction processing according to the first ECC error correction algorithm and the second algorithm control parameters.

6. A device for balancing the ECC error correction capability of a flash memory, characterized in that: The device includes: an acquisition unit, a determination unit and a control unit, wherein: The acquisition unit is configured to acquire a read speed of the flash memory within a preset time period to obtain a plurality of first read speeds; and acquire an operating voltage of the flash memory within the preset time period to obtain a plurality of operating voltages; The determining unit is configured to determine a first ECC error correction algorithm according to the multiple first reading speeds; and determine a first algorithm control parameter of the first ECC error correction algorithm according to the multiple operating voltages; The control unit is used to control the flash memory to perform ECC error correction processing according to the first ECC error correction algorithm and the first algorithm control parameters.

7. The device for balancing the ECC error correction capability of a flash memory according to claim 6, wherein: In determining the first ECC error correction algorithm according to the multiple first reading speeds, the determining unit is specifically configured to: Determine an average of the plurality of first reading speeds to obtain a first average; Performing fitting according to the plurality of first reading speeds to obtain a first fitting curve, wherein the horizontal axis of the first fitting curve is time and the vertical axis is reading speed; Determining a preset time duration corresponding to the first mean value; intercepting a curve segment of the preset duration starting from the current moment in the first fitting curve; determining a median value of the curve segment; The first ECC error correction algorithm is determined according to the median value.

8. The device for balancing the ECC error correction capability of a flash memory according to claim 7, wherein: In determining the first algorithm control parameter of the first ECC error correction algorithm according to the multiple operating voltages, the determining unit is specifically configured to: Fitting is performed based on the multiple operating voltages to obtain a first fitting straight line and a first fitting curve segment corresponding to the preset time period; the horizontal axis of the first fitting straight line is time, and the vertical axis is voltage; the horizontal axis of the first fitting curve segment is time, and the vertical axis is voltage; determining an absolute value of the slope of the first fitting straight line to obtain a first absolute value; determining a first standard deviation of the first fitted curve segment; A first algorithm control parameter of the first ECC error correction algorithm is determined according to the first standard deviation and the first absolute value.

9. An electronic device, characterized in that: The electronic device includes a processor, a memory, a communication interface, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor, and the programs include instructions for executing the steps in the method according to any one of claims 1 to 5.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and the computer program is executed by a processor to implement the method according to any one of claims 1 to 5.

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