Power semiconductor structure and manufacturing method thereof

Abstract

The invention provides a power semiconductor structure and a manufacturing method thereof. The power semiconductor structure includes: a substrate; the epitaxial layer is arranged above the substrate; the groove extends into the epitaxial layer; the doped region is arranged below the groove; a contact member disposed over the doped region or partially surrounded by the doped region; and a barrier layer disposed over the epitaxial layer and in the recess wherein a lateral distance between a sidewall of the recess and an outer sidewall of the contact member and around the contact member is uniform.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a power semiconductor structure and a method of manufacturing the same, and more particularly, to a junction barrier Schottky (JBS) diode and a method of manufacturing the same, and even more particularly, to a planar or trench type junction barrier Schottky (JBS) diode and a method of manufacturing the same. BACKGROUND

[0002] A junction barrier Schottky (JBS) diode is a power semiconductor device that combines the characteristics of a Schottky diode and a junction barrier diode, has a high-voltage working capability, and provides a high-voltage element application. The junction barrier Schottky (JBS) diode generally has an ohmic contact at the interface between a metal material and a semiconductor material, thereby achieving low resistance and high efficient current flow, and thus the ohmic contact is important to the performance and function of the junction barrier Schottky diode. Unfortunately, in the manufacturing process of the junction barrier Schottky (JBS) diode, the positioning of the ohmic contact is difficult to form at a predetermined position due to the current process limitations, and misalignment can occur at an undesired position, thereby causing problems such as leakage.

[0003] Therefore, the prior art junction barrier Schottky diode needs to be further improved to address the leakage problem to achieve a more ideal high power and low loss. SUMMARY

[0004] Embodiments of the present disclosure relate to a power semiconductor structure. The power semiconductor structure includes a substrate, an epitaxial layer over the substrate, a recess extending into the epitaxial layer, a doped region disposed under the recess, a contact member disposed over the doped region or partially surrounded by the doped region, and a barrier layer disposed over the epitaxial layer and in the recess, wherein a lateral distance between a sidewall of the recess and an outer sidewall of the contact member and around the contact member is uniform.

[0005] Embodiments of the present disclosure relate to a method of manufacturing a power semiconductor structure. The method includes forming an epitaxial layer over a substrate; forming an opening extending into the epitaxial layer; implanting dopants to the epitaxial layer exposed from the opening to form a doped region of the epitaxial layer; filling the opening with a sacrificial member to cover the doped region; disposing a first dielectric layer over the epitaxial layer; removing the sacrificial member from the opening; disposing a second dielectric layer over the first dielectric layer and the doped region, and the second dielectric layer is conformal to sidewalls of the opening; removing a first portion of the second dielectric layer to expose a portion of the doped region; disposing a contact material over the portion of the doped region; forming a contact member from the contact material and the portion of the doped region; and removing the first dielectric layer and remaining portions of the second dielectric layer.

[0006] Embodiments of the present disclosure relate to a power semiconductor structure. The power semiconductor structure includes a substrate; an epitaxial layer on the substrate; a doped region extending into the epitaxial layer; a contact member disposed on the doped region or partially surrounded by the doped region; and a barrier layer disposed on the epitaxial layer and the doped region and surrounding the contact member, wherein a width of an interface between the doped region and the barrier layer and around the contact member is uniform.

[0007] Embodiments of the present disclosure relate to a method of manufacturing a power semiconductor structure. The method includes forming an epitaxial layer over a substrate; disposing a patterned mask over the epitaxial layer; implanting dopants to the epitaxial layer exposed from the patterned mask to form a doped region of the epitaxial layer; disposing a sacrificial member to cover the doped region; disposing a first dielectric layer over the epitaxial layer; removing the sacrificial member to form an opening surrounded by the first dielectric layer and exposing the doped region; disposing a second dielectric layer over the first dielectric layer and the doped region, the second dielectric layer is conformal to sidewalls of the opening; removing a first portion of the second dielectric layer to expose a portion of the doped region; disposing a contact material over the portion of the doped region; forming a contact member from the contact material and the portion of the doped region; and removing the first dielectric layer and remaining portions of the second dielectric layer. BRIEF DESCRIPTION OF DRAWINGS

[0008] Aspects of the present disclosure can be best understood with reference to the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various structures can not be drawn to scale. In fact, the dimensions of the various structures can be arbitrarily expanded or reduced for the sake of discussion.

[0009] Figure 1 A cross-sectional view of a power semiconductor structure according to certain embodiments of the present disclosure is shown;

[0010] Figure 2 Fig. 2 shows a cross-sectional view of a power semiconductor structure according to some embodiments of the present case along the indicated A-A' tangent; Figure 1 Fig. 2 shows a cross-sectional view of a power semiconductor structure according to some embodiments of the present case along the indicated A-A' tangent;

[0011] Figure 3 Fig. 3 shows a cross-sectional view of a power semiconductor structure according to some other embodiments of the present case;

[0012] Figure 4 Fig. 3 shows a cross-sectional view of a power semiconductor structure according to some other embodiments of the present case;

[0013] Figure 5 Fig. 3 shows a cross-sectional view of a power semiconductor structure according to some other embodiments of the present case;

[0014] Figures 6 to 26 Fig. 4 shows one or more stages of a manufacturing method of a power semiconductor structure according to some embodiments of the present case;

[0015] Figures 27 to 46 Fig. 4 shows one or more stages of a manufacturing method of a power semiconductor structure according to some other embodiments of the present case.

[0016] The same or similar components are identified by the same reference numbers in the drawings and detailed description. Embodiments of the present disclosure will be readily understood from the following detailed description in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and configurations are described below. These are, of course, merely examples and are in no way limiting of the scope of this disclosure. In the present disclosure, reference to a layer or feature being formed, grown, created, or otherwise formed "over" or "on" another layer or feature can include embodiments in which the layer or feature can be formed directly on the other layer or feature or intervening layers can also be present. In addition, the present disclosure can repeat reference numerals and / or letters in each figure to indicate different embodiments of the same elements. This repetition is for the purpose of simplicity and clarity and is not intended to be a limitation of the scope of the present disclosure.

[0018] Embodiments of the present disclosure are discussed in detail below. While specific implementations are discussed, it should be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific

[0019] The present disclosure provides a power semiconductor structure and a method of manufacturing the same. The power semiconductor structure of the present disclosure is formed with a contact member on a portion of a doped region exposed by a patterned mask. The power semiconductor structure of the present disclosure is formed with a contact member on a specific position on a doped region in a self-alignment manner by controlling a thickness of the patterned mask, using the thickness of the patterned mask to define the position of the contact member on the doped region, preferably on a central position on the doped region, thereby reducing reverse leakage current and allowing the power semiconductor structure of the present disclosure to withstand a larger surge current for a short time without damage, and thus allowing the power semiconductor structure of the present disclosure to be used in high voltage applications.

[0020] Figure 1 FIG. 1 shows a cross-sectional view of a power semiconductor structure 100 according to some embodiments of the present disclosure, Figure 2 FIG. 1 shows a cross-sectional view of a power semiconductor structure 100 according to some embodiments of the present disclosure, Figure 1 FIG. 1 shows a cross-sectional view of a power semiconductor structure 100 according to some embodiments of the present disclosure, Figure 1 FIG. 1 shows a cross-sectional view of a power semiconductor structure 100 according to some embodiments of the present disclosure,

[0021] The substrate 101 includes a substrate 101a and an epitaxial layer 101b over the substrate 101a. In some embodiments, the substrate 101a includes, for example, silicon, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), or other semiconductor materials. The epitaxial layer 101b includes, for example, silicon, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), or other semiconductor materials. In some embodiments, the substrate 101a and the epitaxial layer 101b both include silicon carbide.

[0022] In some embodiments, the substrate 101a is an N-type or P-type semiconductor material, and the epitaxial layer 101b is an N-type or P-type semiconductor material. In some embodiments, the substrate 101a and the epitaxial layer 101b have the same conductivity type doping, for example, both the substrate 101a and the epitaxial layer 101b are N-type. In some embodiments, the substrate 101a is part of a silicon carbide wafer. In some embodiments, the substrate 101a has a higher doping concentration than the epitaxial layer 101b. Both the substrate 101a and the epitaxial layer 101b contain N-type dopants, which can be, for example, phosphorus (P) or arsenic (As).

[0023] In some embodiments, the thickness of the epitaxial layer 101b is greater than the thickness of the substrate 101a. In some embodiments, the thickness of the epitaxial layer 101b is greater than or equal to 6 pm. The greater the thickness of the epitaxial layer 101b, the better the power semiconductor structure 100 is for use in high voltage (e.g., 650 volts (V) to 3000 V) applications.

[0024] The base 101 includes a recess 101d extending into the epitaxial layer 101b. The recess has sidewalls 101f extending into the epitaxial layer 101b. Below the recess 101d is a doped region 101c in the epitaxial layer 101b, extending within the epitaxial layer 101b. In some embodiments, the doped region 101c is at the bottom of the recess 101d. The doped region 101c has a different conductivity type than the epitaxial layer 101b. In some embodiments, the doped region 101c has a P-type, while the epitaxial layer 101b has an N-type. The doped region 101c includes a P-type dopant, which can be, for example, boron, aluminum, gallium, indium, etc. In some embodiments, the doped region 101c includes aluminum as the P-type dopant. The recess 101d has a width W2 and a central axis C2. The doped region 101c has a width W4. In some embodiments, the width W2 of the recess 101d is substantially equal to the width W4 of the doped region 101c. In some embodiments, the central axis C2 of the recess 101d passes through about half of the width W2 of the recess 101d.

[0025] The power semiconductor structure 100 includes a contact member 101e disposed above the doped region 101c or partially surrounded by the doped region 101c. The contact member 101e is disposed within the recess 101d and is partially surrounded by the epitaxial layer 101b and in contact with the doped region 101c. The contact member 101e has an outer sidewall 101g, a width Wl, and a central axis Cl. In some embodiments, the central axis Cl of the contact member 101e passes through about half of the width Wl of the contact member 101e.

[0026] In some embodiments, the contact member 101e is in ohmic contact with the doped region 101c. The interface between the contact member 101e and the doped region 101c forms an ohmic contact. The contact member 101e includes a semiconductor material and a metal. In some embodiments, the contact member 101e includes the same semiconductor material as the epitaxial layer. In some embodiments, the contact member 101e includes a silicide. In some embodiments, the contact member 101e includes nickel (Ni), titanium (Ti), cobalt (Co), platinum (Pt), tantalum (Ta), tungsten (W), or other metals. In some embodiments, the contact member 101e includes nickel silicide (NiSi), titanium silicide (TiSi), cobalt silicide (CoSi), platinum silicide (PtSi), tantalum silicide (TaSi), tungsten silicide (WSi), or other silicide metals.

[0027] In some embodiments, the lateral distance D between the sidewall 101f of the recess 101d and the outer sidewall 101g of the contact member 101e. In some embodiments, the lateral distance D is around the contact member 101e. In some embodiments, the lateral distance D between the sidewall 101f of the recess 101d and the outer sidewall 101g of the contact member 101e and around the contact member 101e is uniform. In some embodiments, the central axis C2 of the recess 101d is common with the central axis C1 of the contact member 101e. In some embodiments, the width W2 of the recess 101d is substantially equal to twice the lateral distance D plus the width W1 of the contact member 101e. In some embodiments, the lateral distance D is substantially less than or substantially equal to the width W1 of the contact member 101e. In some embodiments, the contact member 101e is disposed at a central location of the recess 101d. In some embodiments, the contact member 101e is disposed at a central location of the surface of the doped region 101c.

[0028] The power semiconductor structure 100 includes a barrier layer 102. The barrier layer 102 is disposed over the epitaxial layer 101b and in the recess 101d. The barrier layer 102 extends at least partially to the doped region 101c, the barrier layer 102 surrounds and covers the contact member 101e, and the barrier layer 102 is in contact with the doped region 101c and the contact member 101e. In some embodiments, the barrier layer 102 contacts a surface of the doped region 101c, an outer sidewall 101g of the contact member 101e, and a sidewall 101f of the recess 101d. In some embodiments, a Schottky contact is formed between the barrier layer 102 and the doped region 101c. In some embodiments, a Schottky contact is formed at an interface between the barrier layer 102 and the epitaxial layer 101b. In some embodiments, a Schottky contact is formed at an interface between the barrier layer 102 and the doped region 101c. In some embodiments, a Schottky contact is formed at an interface between the sidewall 101f of the recess 101d and the barrier layer 102. The barrier layer 102 includes a metallic material or a Schottky metal, such as platinum (Pt), titanium (Ti), nickel (Ni), palladium (Pd), molybdenum (Mo), and the like. The barrier layer 102 is a Schottky barrier.

[0029] In some embodiments, a portion of the barrier layer 102 surrounding the contact member 101e has a width W3. In some embodiments, the width W3 of the portion of the barrier layer 102 surrounding the contact member 101e is substantially uniform. In some embodiments, a lateral distance D between the sidewall 101f of the recess 101d and the outer sidewall 101g of the contact member 101e and surrounding the contact member 101e is substantially equal to the width W3 of the portion of the barrier layer 102 surrounding the contact member 101e. In some embodiments, a ratio of the width W1 of the contact member 101e to the width W3 of the portion of the barrier layer 102 surrounding the contact member 101e is about 1:1 to about 5:1.

[0030] The power semiconductor structure 100 also includes a first electrode 103 disposed on the barrier layer 102. In some embodiments, the power semiconductor structure 100 also includes a second electrode 113 disposed under the substrate 101. In some embodiments, the first electrode 103 and the second electrode 113 are disposed on an upper side and a lower side, respectively, of the power semiconductor structure 100. The first electrode 103 covers the barrier layer 102, and the first electrode 103 is in contact with the barrier layer 102. The second electrode 113 covers and contacts the substrate 101a. The first electrode 103 and the second electrode 113 each include an electrically conductive material, such as a metallic material, such as copper (Cu), silver (Ag), gold (Au), and the like.

[0031] In some embodiments, the first electrode 103 is an anode or positive electrode, and the second electrode 113 is a cathode or negative electrode. In some embodiments, current can flow from the first electrode 103 through the barrier layer 102 or the contact member 101e, through the substrate 101 to the second electrode 113. In some embodiments, current can flow from the first electrode 103 through the barrier layer 102 to the second electrode 113 through the epitaxial layer 101b. In some embodiments, current can flow from the first electrode 103 through the barrier layer 102 and the contact member 101e to the second electrode 113 through the doped region 101c and the epitaxial layer 101b. In some embodiments, the current flowing from the first electrode 103 through the barrier layer 102 and the contact member 101e to the epitaxial layer 101b is greater than the current flowing from the first electrode 103 through the barrier layer 102 to the epitaxial layer 101b.

[0032] Because the lateral distance D between the sidewall 101f of the recess 101d and the outer sidewall 101g of the contact member 101e and around the contact member 101e is uniform, the contact member 101e is disposed at a central location on the surface of the doped region 101c, and thus, reverse leakage current between the first electrode 103 and the second electrode 113 of the power semiconductor structure 100 is reduced or even avoided. Moreover, the power semiconductor structure 100 can sustain a greater current flowing from the first electrode 103 through the barrier layer 102 and the contact member 101e to the epitaxial layer 101b.

[0033] Figure 3 FIG. 3 shows a cross-sectional view of another power semiconductor junction 300 according to some embodiments. In particular, the power semiconductor structure 300 has a similar configuration as the power semiconductor structure 100 shown in FIG. 1, except that the power semiconductor structure 300 has a contact member 301e that is recessed into the epitaxial layer 301b, such that a portion of the contact member 301e is surrounded by the doped region 301c and another portion of the contact member 301e is surrounded by the barrier layer 302. Figure 1 FIG. 3 shows a cross-sectional view of another power semiconductor junction 300 according to some embodiments. In particular, the power semiconductor structure 300 has a similar configuration as the power semiconductor structure 100 shown in FIG. 1, except that the power semiconductor structure 300 has a contact member 301e that is recessed into the epitaxial layer 301b, such that a portion of the contact member 301e is surrounded by the doped region 301c and another portion of the contact member 301e is surrounded by the barrier layer 302. Figure 3 In some embodiments, a portion of the doped region 101c around the contact member 101e has a width W5. In some embodiments, the lateral distance D between the sidewall 101f of the recess 101d and the outer sidewall 101g of the contact member 101e and around the contact member 101e is substantially equal to the width W5 of the portion of the doped region 101c around the contact member 101e. In some embodiments, the width W5 of the portion of the doped region 101c around the contact member 101e is substantially uniform.

[0034] Figure 4 FIG. 3 shows a cross-sectional view of another power semiconductor junction 300 according to some embodiments. In particular, the power semiconductor structure 300 has a similar configuration as the power semiconductor structure 100 shown in FIG. 1, except that the power semiconductor structure 300 has a contact member 301e that is recessed into the epitaxial layer 301b, such that a portion of the contact member 301e is surrounded by the doped region 301c and another portion of the contact member 301e is surrounded by the barrier layer 302. Figure 1The power semiconductor structure 100 shown differs in that the power semiconductor structure 300 is a planar power semiconductor structure 300 that does not include the recess 101d in the power semiconductor structure 100, and the contact member 101e and the barrier layer 102 of the power semiconductor structure 300 are not within the recess 101d. Figure 4 As shown, the contact member 101e in the power semiconductor structure 300 is disposed on the doped region 101c, and the barrier layer 102 is disposed on the epitaxial layer 101b and the doped region 101c and covers and surrounds the contact member 101e. In some embodiments, there is an interface 111 between the doped region 101c and the barrier layer 102, and the interface 111 has a width W6. In some embodiments, the width W6 of the interface 111 between the doped region 101c and the barrier layer 102 and around the contact member 101e is uniform. In some embodiments, the width W4 of the doped region 101c is approximately equal to twice the width W6 of the interface 111 plus the width W1 of the contact member 101e. In some embodiments, the ratio of the width W1 of the contact member 101e to the width W6 of the interface 111 around the contact member 101e is approximately 1 : 1 to approximately 5: 1.

[0035] Figure 5 Shown is a cross-sectional view of another power semiconductor junction 400 according to certain embodiments of the present disclosure. In particular, the power semiconductor structure 400 has a planar power semiconductor structure 400 that does not include the recess 101d in the power semiconductor structure 200, and the contact member 101e and the barrier layer 102 of the power semiconductor structure 400 are not within the recess 101d. Figure 3 The power semiconductor structure 200 shown differs in that the power semiconductor structure 400 is a planar power semiconductor structure 400 that does not include the recess 101d in the power semiconductor structure 200, and the contact member 101e and the barrier layer 102 of the power semiconductor structure 400 are not within the recess 101d. Figure 5 As shown, a portion of the contact member 101e of the power semiconductor structure 400 is recessed into the epitaxial layer 101b, such that a portion of the contact member 101e is surrounded by the doped region 101c and another portion of the contact member 101e is surrounded by the barrier layer 102. In some embodiments, a portion of the doped region 101c around the contact member 101e has a width W5. In some embodiments, the width W5 of the portion of the doped region 101c around the contact member 101e is approximately equal to the width W6 of the interface 111. In some embodiments, the width W5 of the portion of the doped region 101c around the contact member 101e is approximately uniform.

[0036] Figures 6 to 22 Shown are one or more stages in a method of fabricating a power semiconductor structure 100 according to certain embodiments of the present disclosure. At least some of these figures have been simplified to better understand the aspects of the present disclosure.

[0037] Referring toFigure 6 The manufacturing method includes forming an epitaxial layer 101b over the substrate 101a. The substrate 101a and the epitaxial layer 101b each include a semiconductor material, such as silicon carbide (SiC). In some embodiments, the substrate 101a is an N-type or P-type semiconductor material. Epitaxial growth is performed on the substrate 101a to form the epitaxial layer 101b. In some embodiments, the epitaxial growth is performed concurrently with a dopant implantation, which implants an N-type dopant, such as phosphorus (P) or arsenic (As), to form an N-type epitaxial layer 112. In some embodiments, the substrate 101a and the epitaxial layer 101b have the same conductivity type doping, such as both the substrate 101a and the epitaxial layer 101b being N-type. In some embodiments, the substrate 101a has a substantially greater doping concentration than the epitaxial layer 101b.

[0038] Referring to Figure 7 In some embodiments, the manufacturing method includes disposing a patterned mask 104 over the epitaxial layer 101b. In some embodiments, the patterned mask 104 includes a photoresist or an oxide, among others. The patterned mask 104 has an opening 104a through which the epitaxial layer 101b is at least partially exposed.

[0039] Referring to Figure 8 The manufacturing method includes forming an opening 101d or a recess 101d extending into the epitaxial layer 101b. An etching process is performed on the epitaxial layer 101b through the patterned mask 104 to form the opening 101d. In some embodiments, the etching process is performed on the epitaxial layer 101b exposed from the opening 104a of the patterned mask 104. The etching process is performed on the epitaxial layer 101b exposed from the patterned mask 104 to remove portions of the epitaxial layer 101b exposed from the patterned mask 104. In some embodiments, the etching process can be a plasma dry etching process or other etching process.

[0040] Referring to Figure 9The manufacturing method includes implanting dopants into the epitaxial layer 101b exposed from the opening 101d to form a doped region 101c of the epitaxial layer 101b. The doped region 101c can be formed by a diffusion or ion implantation process through the surface of the epitaxial layer 101b exposed via the opening 104a of the self-patterned mask 104 and the opening 101d of the epitaxial layer 101. In some embodiments, the doped region 101c is formed at the bottom of the opening 101d. The conductivity type of the substrate 101a and the conductivity type of the epitaxial layer 101b are different from the conductivity type of the doped region 101c. In some embodiments, the doped region 101c has a P-type, and the epitaxial layer 101b has an N-type. The doped region 101c includes P-type dopants, which can be, for example, boron, aluminum, gallium, indium, etc. In some embodiments, the doped region 101c includes aluminum as the P-type dopant.

[0041] Referring to Figure 10 In some embodiments, the patterned mask 104 is removed after the diffusion or ion implantation process. In some embodiments, the patterned mask 104 is removed by an etching process, such as a plasma dry etching process.

[0042] Referring to Figure 11 In some embodiments, the manufacturing method includes forming a protective layer 105 on the epitaxial layer 101b to protect the epitaxial layer 101b and the doped region 101c during an anneal process. In some embodiments, the protective layer 105 is formed on the surface of the epitaxial layer 101b after the patterned mask 104 is removed. In some embodiments, the protective layer 105 includes carbon. After the protective layer 105 is formed, an anneal process, such as a rapid thermal anneal (RTA) or a laser anneal, is performed on the doped region 101c to activate the dopant ions in the doped region 101c.

[0043] Referring to Figure 12 After the anneal process, the protective layer 104 can be removed by a dry thermal oxidation, a plasma dry etching, or other etching processes.

[0044] Referring to Figure 13 The manufacturing method includes filling the opening 101d with a sacrificial member 106 to cover the doped region 101c. The sacrificial member 106 is used to protect the doped region 101c from reacting with other materials in subsequent processes. In some embodiments, the sacrificial member 106 is deposited or otherwise formed on the doped region 101c to fill the opening 101d. In some embodiments, the sacrificial member 106 is in contact with the sidewall 101f of the opening 101d. In some embodiments, the sacrificial member 106 includes an insulating material, such as nitride, oxynitride, silicon nitride (SiN), etc.

[0045] Referring to Figure 14 The fabrication method includes disposing a first dielectric layer 107 over the epitaxial layer 101b. In some embodiments, the first dielectric layer 107 is formed on a surface of the epitaxial layer 101b, covering the surface of the epitaxial layer 101b. The first dielectric layer 107 comprises a dielectric material, such as an oxide, silicon oxide (SiO2), etc. In some embodiments, the first dielectric layer 107 is disposed by thermal oxidation. In some embodiments, the first dielectric layer 107 is formed by thermal oxidation or other deposition methods. In some embodiments, the formation of the first dielectric layer 107 includes oxidizing the semiconductor material of the surface of the epitaxial layer 101b by thermal oxidation to form the first dielectric layer 107. In some embodiments, the formation of the first dielectric layer 107 includes depositing a dielectric material on the epitaxial layer 101b by other deposition methods, and then performing an etching process on part of the dielectric material to remove part of the dielectric material to form the opening 107a. The sacrificial member 106 is exposed from the opening 107a of the first dielectric layer 107. In some embodiments, the first dielectric layer 107 is not disposed on the sacrificial member 106.

[0046] Referring to Figure 15 The fabrication method includes removing the sacrificial member 106 from the opening 101d. In some embodiments, the sacrificial member 106 is removed after the formation of the first dielectric layer 107. In some embodiments, the sacrificial member 106 is removed by performing an etching process, such as a plasma dry etching process, on the sacrificial member 106. After the removal of the sacrificial member 106, the doped region 101c is exposed from the opening 107a of the first dielectric layer 107.

[0047] Referring to Figure 16 The fabrication method includes disposing a second dielectric layer 108 over the first dielectric layer 107 and the doped region 101c. In some embodiments, the second dielectric layer 108 is formed on the surface and the exposed surfaces of the side wall of the first dielectric layer 107, the side wall 101f of the opening 101d, and the doped region 101c, covering the exposed portions of the first dielectric layer 107 and the epitaxial layer 101b. In some embodiments, the doped region 101c is completely covered by the second dielectric layer 108. In some embodiments, the second dielectric layer 108 is conformal to the side wall 101f of the opening 101d. In some embodiments, the second dielectric layer 108 conformal to the side wall 101f of the opening 101d has a uniform thickness W7 along the side wall 101f of the opening 101d. In some embodiments, the second dielectric layer 108 has a uniform thickness W9 along the upper surface of the first dielectric layer 107 at the upper surface of the first dielectric layer 107. In some embodiments, the thickness W7 is substantially greater than or equal to the thickness W9. In some embodiments, the thickness of the entire second dielectric layer 108 is uniform, i.e., the thickness W7 is substantially equal to the thickness W9.

[0048] The second dielectric layer 108 includes a dielectric material, such as an oxide, silicon oxide (SiO2), and the like. In some embodiments, the second dielectric layer 108 is provided by thermal oxidation. In some embodiments, the second dielectric layer 108 is formed by thermal oxidation or other deposition methods. In some embodiments, the formation of the second dielectric layer 108 includes oxidizing the semiconductor material of the surface of the epitaxial layer 101b by thermal oxidation to form the second dielectric layer 108. In some embodiments, the formation of the second dielectric layer 108 includes oxidizing the semiconductor material of the sidewall 101f of the opening 101d of the epitaxial layer 101b by thermal oxidation to form the second dielectric layer 108. In some embodiments, the second dielectric layer 108 is not formed on the upper surface of the first dielectric layer 107 or the sidewall of the first dielectric layer 107.

[0049] Referring to Figure 17 , the method of manufacturing includes removing a first portion of the second dielectric layer 108 to expose a portion of the doped region 101c. In some embodiments, an etching process, such as a plasma dry etching process, is performed on the first portion of the second dielectric layer 108 covering the doped region 101c to remove the first portion of the second dielectric layer 108. In some embodiments, during the removal of the first portion of the second dielectric layer 108, a second portion of the second dielectric layer 108 in contact with the first dielectric layer 107 is also removed. The second portion of the second dielectric layer 108 and the portion of the first dielectric layer 107 are removed simultaneously. In some embodiments, the first portion of the second dielectric layer 108 is removed while a portion of the first dielectric layer 107 on the upper surface of the epitaxial layer 101b, a portion of the second dielectric layer 108 on the first dielectric layer 107, and / or a portion of the second dielectric layer 108 on the sidewall 101f of the opening 101d of the epitaxial layer 101b are also removed simultaneously to form a remaining portion 109 of the first dielectric layer 107 and the second dielectric layer 108. In some embodiments, after the formation of the remaining portion 109, the doped region 101c is exposed from the remaining portion 109. In some embodiments, the remaining portion 109 of the first dielectric layer 107 and the second dielectric layer 108 has a uniform thickness W8 along the sidewall 101f of the opening 101d. In some embodiments, the thickness W7 is substantially greater than the thickness W8.

[0050] Referring to Figure 18The manufacturing method includes disposing a contact material 110 over a portion of the doped region 101c. The contact material 110 is disposed over a portion of the doped region 101c and over the remaining portion 109 of the first dielectric layer 107 and the second dielectric layer 108. During the disposing of the contact material 110 over the portion of the doped region 101c, the contact material 110 is disposed over the remaining portion 109 of the first dielectric layer 107 and the second dielectric layer 108. In some embodiments, the contact material 110 covers the remaining portion 109 and the portion of the doped region 101c exposed from the remaining portion 109. In some embodiments, the contact material 110 is deposited over the portion of the doped region 101c covering the remaining portion 109 and the portion of the doped region 101c exposed from the remaining portion 109 by electroplating, chemical vapor deposition (CVD), or other deposition methods. In some embodiments, the contact material 110 includes a metal material, such as nickel (Ni), titanium (Ti), cobalt (Co), platinum (Pt), tantalum (Ta), tungsten (W), or other metals.

[0051] Reference Figures 19 to 20 The manufacturing method includes forming a contact member 101e from a contact material 110 and a portion of a doped region 101c. Figure 19 After providing contact material 110 above the portion of doped region 101c exposed from remaining portion 109 and above remaining portion 109, rapid thermal processing (RTP) or other thermal treatment is performed on contact material 110 and doped region 101c to form contact member material 110'. In some embodiments, contact member material 110' comprises silicide. In some embodiments, contact member material 110' comprises nickel silicide (NiSi), titanium silicide (TiSi), cobalt silicide (CoSi), platinum silicide (PtSi), tantalum silicide (TaSi), tungsten silicide (WSi), or other silicide metals.

[0052] Reference Figure 20The manufacturing method includes removing the remaining portion 109. During the removing of the remaining portion 109, the contact material 110 above the remaining portion 109 is removed. In some embodiments, after the contact member material 110' is formed, the remaining portion 109 and the contact material 110 outside the contact member material 110' are removed to form the contact member 101e. In some embodiments, an etching process, such as a plasma dry etching process, is performed on the remaining portion 109 and the contact material 110 outside the contact member material 110' to remove the remaining portion 109 and the contact material 110 outside the contact member material 110'. In some embodiments, the contact member 101e includes a silicide. In some embodiments, the contact member 101e includes nickel silicide (NiSi), titanium silicide (TiSi), cobalt silicide (CoSi), platinum silicide (PtSi), tantalum silicide (TaSi), tungsten silicide (WSi), or other silicide metal. In some embodiments, the contact member 101e is formed after a rapid thermal process (RTP) is performed on the contact material 110 and the partially doped region 101c.

[0053] Referring to Figure 21 In some embodiments, the manufacturing method includes forming a barrier layer 102 above the epitaxial layer 101b, the contact member 101e, and the doped region 101c. In some embodiments, the barrier layer 102 covers the epitaxial layer 101b and the doped region 101c, and covers and surrounds the contact member 101e. In some embodiments, forming the barrier layer 102 includes a barrier material of the barrier layer 102 being deposited by electroplating, chemical vapor deposition (CVD), or other deposition method on the epitaxial layer 101b, the contact member 101e, and the doped region 101c. The barrier material includes a metal material or a Schottky metal, such as platinum (Pt), titanium (Ti), nickel (Ni), palladium (Pd), molybdenum (Mo), and the like.

[0054] Referring to Figure 22In some embodiments, the manufacturing method includes forming the first electrode 103 over the barrier layer 102. In some embodiments, the first electrode 103 is formed after the barrier layer 102 is formed. In some embodiments, forming the first electrode 103 includes electrode material of the first electrode 103 being deposited, e.g., electroplated, chemical vapor deposition (CVD), or other deposition method, over the barrier layer 102. In some embodiments, the manufacturing method includes forming the second electrode 113 under the substrate 101a. In some embodiments, the second electrode 113 is formed after the barrier layer 102 is formed. In some embodiments, forming the second electrode 113 includes electrode material of the second electrode 113 being deposited, e.g., electroplated, chemical vapor deposition (CVD), or other deposition method, under the substrate 101a. In some embodiments, the electrode material includes electrically conductive material, e.g., metallic material such as copper (Cu), silver (Ag), gold (Au), etc. In some embodiments, the first electrode 103 is an anode or positive electrode, and the second electrode 113 is a cathode or negative electrode. Figure 22 A power semiconductor structure 100 is shown. Figure 1

[0055] Figures 6 to 18 Figures 23 to 26 A manufacturing method of a power semiconductor structure 200 according to some embodiments is shown. Specifically, the manufacturing method of the power semiconductor structure 200 is similar to the manufacturing method of the power semiconductor structure 100 shown, except that the contact member 101e formed by the contact material 110 and the partially doped region 101c is partially surrounded by the doped region 101c, as shown. Figures 6 to 18 Figures 23 to 26

[0056] Referring to Figure 23 , the manufacturing method includes forming the contact member 101e from the contact material 110 and the partially doped region 101c. After disposing the contact material 110 over the partially doped region 101c exposed from the remaining portion 109 and over the remaining portion 109, the contact material 110 and the doped region 101c are subjected to a rapid thermal process (RTP) or other heat treatment, causing the contact material 110 and the partially doped region 101c in contact with the contact material 110 to form the contact member material 110'.

[0057] Referring to Figure 24 ​​​​The manufacturing method includes removing the remaining portion 109 and the contact material 110 above the remaining portion 109, forming a contact member 101e. The contact member 101e is at least partially surrounded by the doped region 101c, and is at least partially on the epitaxial layer 101b or the doped region 101c. In some embodiments, an etching process, such as a plasma dry etching process, is performed on the contact material 110 except for the remaining portion 109 and the contact member material 110', removing the contact material 110 except for the remaining portion 109 and the contact member material 110'. In some embodiments, the contact member 101e includes a silicide. In some embodiments, the contact member 101e includes nickel silicide (NiSi), titanium silicide (TiSi), cobalt silicide (CoSi), platinum silicide (PtSi), tantalum silicide (TaSi), tungsten silicide (WSi), or other silicide metal.

[0058] Referring to Figure 25 In some embodiments, the manufacturing method includes forming a barrier layer 102 above the epitaxial layer 101b, the contact member 101e, and the doped region 101c. In some embodiments, the barrier layer 102 covers the epitaxial layer 101b and the doped region 101c, and covers and surrounds part of the contact member 101e. Referring to Figure 26 In some embodiments, the manufacturing method includes forming a first electrode 103 above the barrier layer 102 and a second electrode 113 below the substrate 101a. Figure 26 A power semiconductor structure 200 is shown. Figure 3 A power semiconductor structure 300 is shown.

[0059] Figures 27 to 42 A manufacturing method of a power semiconductor structure 300 according to certain embodiments of the present disclosure is shown. At least some of the figures in these drawings have been simplified to better understand aspects of the present disclosure.

[0060] Referring to Figure 27 The manufacturing method includes forming an epitaxial layer 101b above a substrate 101a. The substrate 101a and the epitaxial layer 101b include a semiconductor material, such as silicon carbide (SiC), for example. In some embodiments, the substrate 101a is an N-type or P-type semiconductor material. Epitaxial growth is performed on the substrate 101a, forming the epitaxial layer 101b. In some embodiments, the epitaxial growth is performed simultaneously with a dopant implant, implanting an N-type dopant, which can be phosphorus (P) or arsenic (As) for example, to form an N-type epitaxial layer 112. In some embodiments, the substrate 101a and the epitaxial layer 101b have the same conductivity type doping, such as both the substrate 101a and the epitaxial layer 101b being N-type. In some embodiments, the substrate 101a has a doping concentration substantially greater than the doping concentration of the epitaxial layer 101b.

[0061] Referring to Figure 28 In some embodiments, the manufacturing method includes disposing a patterned mask 104 over the epitaxial layer 101b. In some embodiments, the patterned mask 104 comprises photoresist or oxide, etc. The patterned mask 104 has openings 104a through which the epitaxial layer 101b is at least partially exposed.

[0062] Referring to Figure 29 The manufacturing method includes implanting dopants into the epitaxial layer 101b exposed from the patterned mask 104 to form a doped region 101c. The doped region 101c can be formed via a diffusion or ion implantation process from the surface of the epitaxial layer 101b exposed from the openings 104a of the patterned mask 104. The conductivity type of the substrate 101a and the conductivity type of the epitaxial layer 101b are different from the conductivity type of the doped region 101c. In some embodiments, the doped region 101c has a P-type, while the epitaxial layer 101b has an N-type. The doped region 101c comprises P-type dopants, which can be, for example, boron, aluminum, gallium, indium, etc. In some embodiments, the doped region 101c comprises boron as the P-type dopant.

[0063] Referring to Figure 30 In some embodiments, the patterned mask 104 is removed after the diffusion or ion implantation process. In some embodiments, the patterned mask 104 is removed by an etching process, such as a plasma dry etching process.

[0064] Referring to Figure 31 In some embodiments, the manufacturing method includes forming a protective layer 105 over the epitaxial layer 101b to protect the epitaxial layer 101b and the doped region 101c during an anneal process. In some embodiments, the protective layer 105 is formed over the surface of the epitaxial layer 101b after the patterned mask 104 is removed. In some embodiments, the protective layer 105 comprises carbon. After the protective layer 105 is formed, an anneal process, such as a rapid thermal anneal (RTA) or a laser anneal, is performed on the doped region 101c to activate the dopant ions in the doped region 101c.

[0065] Referring to Figure 32 After the anneal process, the protective layer 104 can be removed by a dry thermal oxidation, a plasma dry etching, or other etching processes.

[0066] Referring to Figure 33The manufacturing method includes disposing a sacrificial member 106 to cover the doped region 101c. The sacrificial member 106 is used to protect the doped region 101c from reacting with other materials in subsequent processes. The sacrificial member 106 protrudes from the epitaxial layer 101b. In some embodiments, the sacrificial member 106 is deposited or otherwise formed over the doped region 101c. In some embodiments, the sacrificial member 106 comprises an insulating material, such as nitride, oxynitride, silicon nitride (SiN), or the like.

[0067] Referring to Figure 34 The manufacturing method includes disposing a first dielectric layer 107 over the epitaxial layer 101b. In some embodiments, the first dielectric layer 107 is formed on a surface of the epitaxial layer 101b to cover the surface of the epitaxial layer 101b. The first dielectric layer 107 comprises a dielectric material, such as oxide, silicon oxide (SiO2), or the like. In some embodiments, the first dielectric layer 107 is disposed by thermal oxidation. In some embodiments, the first dielectric layer 107 is formed by thermal oxidation or other deposition methods. In some embodiments, the formation of the first dielectric layer 107 includes oxidizing the semiconductor material of the surface of the epitaxial layer 101b by thermal oxidation to form the first dielectric layer 107. In some embodiments, the first dielectric layer 107 is not disposed on the sacrificial member 106.

[0068] Referring to Figure 35 The manufacturing method includes removing the sacrificial member 106 to form an opening 107a surrounded by the first dielectric layer 107 and exposing the doped region. In some embodiments, the sacrificial member 106 is removed after the formation of the first dielectric layer 107. In some embodiments, the sacrificial member 106 is etched, such as by a plasma dry etching process, to remove the sacrificial member 106. After the removal of the sacrificial member 106, the doped region 101c is exposed from the opening 107a of the first dielectric layer 107.

[0069] Referring to Figure 36The fabrication method includes disposing a second dielectric layer 108 over the first dielectric layer 107 and over the doped region 101c. In some embodiments, the second dielectric layer 108 is conformal to the sidewall 107b of the opening 107a. In some embodiments, the second dielectric layer 108 disposed conformal to the sidewall 107b of the opening 107a has a uniform thickness W7 along the sidewall 107b of the opening 107a. In some embodiments, the second dielectric layer 108 along the upper surface of the first dielectric layer 107 has a uniform thickness W9 along the upper surface of the first dielectric layer 107. In some embodiments, the thickness W7 is substantially greater than or equal to the thickness W9. In some embodiments, the thickness of the entire second dielectric layer 108 is uniform, i.e., the thickness W7 is substantially equal to the thickness W9. The second dielectric layer 108 comprises a dielectric material, such as an oxide, silicon oxide (SiO2), or the like. In some embodiments, the second dielectric layer 108 is disposed by thermal oxidation. In some embodiments, the second dielectric layer 108 is formed by thermal oxidation or other deposition methods. In some embodiments, the formation of the second dielectric layer 108 includes oxidizing the semiconductor material of the surface of the epitaxial layer 101b by thermal oxidation to form the second dielectric layer 108.

[0070] Referring to Figure 37 The fabrication method includes removing a first portion of the second dielectric layer 108 to expose the portion of the doped region 101c. In some embodiments, an etching process, such as a plasma dry etching process, is performed on the first portion of the second dielectric layer 108 covering the doped region 101c to remove the first portion of the second dielectric layer 108. In some embodiments, during the removal of the first portion of the second dielectric layer 108, a second portion of the second dielectric layer 108 in contact with the first dielectric layer 107 is also removed. The second portion of the second dielectric layer 108 and the portion of the first dielectric layer 107 are simultaneously removed, thereby forming a remaining portion 109 of the first dielectric layer 107 and the second dielectric layer 108. In some embodiments, after the formation of the remaining portion 109, the doped region 101c is exposed from the remaining portion 109.

[0071] Referring to Figure 38 The fabrication method includes disposing a contact material 110 over the portion of the doped region 101c. The contact material 110 is disposed over the portion of the doped region 101c and over the remaining portion 109. In some embodiments, the contact material 110 covers the remaining portion 109 and the portion of the doped region 101c exposed from the remaining portion 109. In some embodiments, the contact material 110 is deposited by electroplating, chemical vapor deposition (CVD), or other deposition methods to cover the remaining portion 109 and the portion of the doped region 101c exposed from the remaining portion 109. In some embodiments, the contact material 110 comprises a metallic material, such as nickel (Ni), titanium (Ti), cobalt (Co), platinum (Pt), tantalum (Ta), tungsten (W), or other metals.

[0072] Referring to Figures 39 to 40 The fabrication method includes forming a contact member 101e from the contact material 110 and the partially doped region 101c. Referring to Figure 39 After disposing the contact material 110 over the partially doped region 101c exposed from the remaining portion 109 and over the remaining portion 109, the contact material 110 and the doped region 101c are subjected to a rapid thermal process (RTP) or other thermal process to cause the contact material 110 and the partially doped region 101c in contact with the contact material 110 to form a contact member material 110'. In some embodiments, the contact member material 110' includes a silicide. In some embodiments, the contact member material 110' includes nickel silicide (NiSi), titanium silicide (TiSi), cobalt silicide (CoSi), platinum silicide (PtSi), tantalum silicide (TaSi), tungsten silicide (WSi), or other silicide metal.

[0073] Referring to Figure 40 The fabrication method includes removing the remaining portion 109. During the removal of the remaining portion 109, the contact material 110 above the remaining portion 109 is removed. In some embodiments, after the formation of the contact member material 110', the remaining portion 109 and the contact material 110 outside of the contact member material 110' are removed to form the contact member 101e. In some embodiments, an etching process, such as a plasma dry etching process, is performed on the remaining portion 109 and the contact material 110 outside of the contact member material 110' to remove the remaining portion 109 and the contact material 110 outside of the contact member material 110'. In some embodiments, the contact member 101e includes a silicide. In some embodiments, the contact member 101e includes nickel silicide (NiSi), titanium silicide (TiSi), cobalt silicide (CoSi), platinum silicide (PtSi), tantalum silicide (TaSi), tungsten silicide (WSi), or other silicide metal. In some embodiments, the contact member 101e is formed after the rapid thermal process (RTP) on the contact material 110 and the partially doped region 101c.

[0074] Referring to Figure 41In some embodiments, the manufacturing method includes forming a barrier layer 102 over the epitaxial layer 101b, the contact member 101e, and the doped region 101c. In some embodiments, the barrier layer 102 covers the epitaxial layer 101b and the doped region 101c, and covers and surrounds the contact member 101e. In some embodiments, forming the barrier layer 102 includes depositing a barrier material of the barrier layer 102 by electroplating, chemical vapor deposition (CVD), or other deposition methods over the epitaxial layer 101b, the contact member 101e, and the doped region 101c. The barrier material includes a metallic material or a Schottky metal, such as platinum (Pt), titanium (Ti), nickel (Ni), palladium (Pd), molybdenum (Mo), and the like.

[0075] Referring to Figure 42 In some embodiments, the manufacturing method includes forming a first electrode 103 over the barrier layer 102. In some embodiments, the first electrode 103 is formed after forming the barrier layer 102 on the barrier layer 102. In some embodiments, forming the first electrode 103 includes depositing an electrode material of the first electrode 103 by electroplating, chemical vapor deposition (CVD), or other deposition methods over the barrier layer 102. In some embodiments, the manufacturing method includes forming a second electrode 113 under the substrate 101a. In some embodiments, the second electrode 113 is formed after forming the barrier layer 102 under the substrate 101a. In some embodiments, forming the second electrode 113 includes depositing an electrode material of the second electrode 113 by electroplating, chemical vapor deposition (CVD), or other deposition methods under the substrate 101a. In some embodiments, the electrode material includes a conductive material, such as a metallic material, such as copper (Cu), silver (Ag), gold (Au), and the like. In some embodiments, the first electrode 103 is an anode or a positive electrode, and the second electrode 113 is a cathode or a negative electrode. Figure 42 A power semiconductor structure 300 is shown. Figure 4 In some embodiments, the manufacturing method includes forming a contact member 101e from the contact material 110 and the partially doped region 101c. In some embodiments, the contact member 101e is formed after forming the doped region 101c from the epitaxial layer 101b and the contact material 110. In some embodiments, the contact member 101e is formed by electroplating, chemical vapor deposition (CVD), or other deposition methods.

[0076] Figures 27 to 38 In some embodiments, the manufacturing method includes forming a contact member 101e from the contact material 110 and the partially doped region 101c. In some embodiments, the contact member 101e is formed after forming the doped region 101c from the epitaxial layer 101b and the contact material 110. In some embodiments, the contact member 101e is formed by electroplating, chemical vapor deposition (CVD), or other deposition methods. Figures 43 to 46 A manufacturing method of a power semiconductor structure 400 according to some embodiments of the present disclosure is shown. Specifically, the manufacturing method of the power semiconductor structure 400 is similar to the manufacturing method of the power semiconductor structure 300 shown in Figures 27 to 38 In some embodiments, the manufacturing method includes forming a contact member 101e from the contact material 110 and the partially doped region 101c. In some embodiments, the contact member 101e is formed after forming the doped region 101c from the epitaxial layer 101b and the contact material 110. In some embodiments, the contact member 101e is formed by electroplating, chemical vapor deposition (CVD), or other deposition methods. Figures 43 to 46

[0077] Referring to Figures 43 to 44 In some embodiments, the manufacturing method includes forming a contact member 101e from the contact material 110 and the partially doped region 101c. In some embodiments, the contact member 101e is formed after forming the doped region 101c from the epitaxial layer 101b and the contact material 110. In some embodiments, the contact member 101e is formed by electroplating, chemical vapor deposition (CVD), or other deposition methods. Figure 43 ​After disposing the contact material 110 over the portion of the doped region 101c exposed from the remaining portion 109 and over the remaining portion 109, the contact material 110 and the doped region 101c are subjected to a rapid thermal process (RTP) or other thermal process, causing the contact material 110 and the portion of the doped region 101c in contact with the contact material 110 to form a contact member material 110'.

[0078] Referring to Figure 44 , the method of manufacturing includes removing the remaining portion 109 and the contact material 110 over the remaining portion 109 to form a contact member 101e. The contact member 101e is at least partially surrounded by the doped region 101c and is at least partially on the epitaxial layer 101b or the doped region 101c. In some embodiments, an etching process, such as a plasma dry etching process, is performed on the contact material 110 other than the remaining portion 109 and the contact member material 110' to remove the contact material 110 other than the remaining portion 109 and the contact member material 110'. In some embodiments, the contact member 101e includes a silicide. In some embodiments, the contact member 101e includes nickel silicide (NiSi), titanium silicide (TiSi), cobalt silicide (CoSi), platinum silicide (PtSi), tantalum silicide (TaSi), tungsten silicide (WSi), or other metal silicide.

[0079] Referring to Figure 45 In some embodiments, the method of manufacturing includes forming a barrier layer 102 over the epitaxial layer 101b, the contact member 101e, and the doped region 101c. In some embodiments, the barrier layer 102 covers the epitaxial layer 101b and the doped region 101c and covers and surrounds a portion of the contact member 101e. Referring to Figure 46 In some embodiments, the method of manufacturing includes forming a first electrode 103 over the barrier layer 102 and a second electrode 113 under the substrate 101a. Figure 46 The power semiconductor structure 400 is shown in Figure 5 .

[0080] Since the remaining portion 109 of the first dielectric layer 107 and the second dielectric layer 108 has a uniform thickness W8 along the sidewall 101f of the opening 101d (as shown in Figure 17 , the contact member 101e is disposed at a central location of the surface of the doped region 101c (as shown in Figure 20 , 24, 40, 44), thus, the reverse leakage current between the first electrode 103 and the second electrode 113 of the power semiconductor structure 100, 200, 300, 400 is reduced or even avoided. Moreover, the power semiconductor structure 100, 200, 300, 400 can withstand a higher current flow from the first electrode 103 through the barrier layer 102 and the contact member 101e to the epitaxial layer 101b.

[0081] According to the structure and process of the present disclosure as described above, under the same purpose and concept, the steps in the above process can be adjusted or the order can be replaced to achieve the same or similar semiconductor structure.

[0082] Spatially relative terms such as "under", "below", "lower", "above", "upper", "left", "right", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms can be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be understood that, when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected or coupled to the other element or one or more intervening elements can be present.

[0083] As used herein, the terms "about", "substantially", "essentially", and "approximately" are used to describe and account for small variations. When used in connection with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs exactly, as well as instances in which the event or circumstance occurs approximately. As used herein in reference to a given value or range, the term "approximately" generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein include the endpoints, unless otherwise indicated. The term "substantially co-planar" can refer to a position difference of two surfaces positioned along the same plane being within a number of micrometers (pm), such as within 10 pm, within 5 pm, within 1 pm, or within 0.5 pm. When a value or characteristic is referred to as "substantially" the same, the term can refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of the value.

[0084] The foregoing outlines features of several embodiments and a detailed description of the disclosure. The embodiments described in the disclosure can be readily used as a basis for the design or modification of other processes and structures for carrying out the same or similar purposes and / or achieving the same or similar advantages of the embodiments presented herein. Such equivalent constructions do not depart from the spirit and scope of the disclosure and are to be covered thereby. Changes, substitutions, and alterations can be variously made to the details of the embodiments without departing from the spirit and scope of the disclosure.

Claims

1. A method for manufacturing a power semiconductor structure, comprising: forming an epitaxial layer over the substrate; forming an opening extending into the epitaxial layer; implanting dopants into the epitaxial layer exposed from the opening to form a doped region of the epitaxial layer; filling the opening with a sacrificial member to cover the doped region; Disposing a first dielectric layer above the epitaxial layer; removing the sacrificial member from the opening; Disposing a second dielectric layer above the first dielectric layer and the doped region, wherein the second dielectric layer is conformal to the sidewall of the opening; removing a first portion of the second dielectric layer to expose a portion of the doped region; disposing a contact material over the portion of the doped region; forming a contact member from the contact material and the portion of the doped region; and Remaining portions of the first dielectric layer and the second dielectric layer are removed. 2 . The manufacturing method according to claim 1 , wherein the second dielectric layer conforming to the sidewall of the opening has a uniform thickness along the sidewall of the opening. 3 . The manufacturing method according to claim 1 , wherein the remaining portions of the first dielectric layer and the second dielectric layer have a uniform thickness along the sidewalls of the opening. The manufacturing method according to claim 1 , wherein the sacrificial member is removed after providing the first dielectric layer. 5 . The method of claim 1 , wherein during the step of disposing the contact material over the portion of the doped region, the contact material is disposed over the remaining portions of the first and second dielectric layers. 6 . The manufacturing method of claim 5 , wherein during the removing of the remaining portions of the first dielectric layer and the second dielectric layer, the contact material over the remaining portions of the first dielectric layer and the second dielectric layer is removed. 7 . The manufacturing method according to claim 1 , wherein during the removal of the first portion of the second dielectric layer, a second portion of the second dielectric layer contacting the first dielectric layer is removed. 8 . The manufacturing method of claim 7 , wherein the second portion of the second dielectric layer and the portion of the first dielectric layer are removed simultaneously. 9 . The method of claim 1 , wherein the contact material is disposed over the portion of the doped region and over the remaining portions of the first dielectric layer and the second dielectric layer. 10 . The manufacturing method according to claim 1 , wherein the first dielectric layer and the second dielectric layer are provided by thermal oxidation, and the first portion of the second dielectric layer is removed by dry etching. 11 . The manufacturing method according to claim 1 , wherein the contact member comprises silicide and is formed after performing rapid thermal processing (RTP) on the contact material and the portion of the doping region.

12. The manufacturing method according to claim 1, further comprising: forming a barrier layer over the epitaxial layer, the doped region, and the contact member; An electrode is formed on the barrier layer.

13. A power semiconductor structure comprising: substrate; an epitaxial layer overlying the substrate; a recess extending into the epitaxial layer; a doped region disposed below the groove; a contact member disposed above the doped region or partially surrounded by the doped region; and a barrier layer disposed above the epitaxial layer and in the recess, The lateral distance between the side wall of the groove and the outer side wall of the contact member and around the contact member is uniform. 14 . The power semiconductor structure of claim 13 , wherein a width of the recess is equal to twice the lateral distance plus a width of the contact member. 15 . The power semiconductor structure of claim 13 , wherein a width of a portion of the barrier layer surrounding the contact member is uniform. The power semiconductor structure of claim 13 , wherein a central axis of the recess is common to a central axis of the contact member. 17 . The power semiconductor structure of claim 13 , wherein a width of a portion of the doped region surrounding the contact member is uniform.

18. The power semiconductor structure according to claim 13, wherein the contact member (101e) is in ohmic contact with the doped region, and the barrier layer is a Schottky barrier.

19. The power semiconductor structure according to claim 13, further comprising an electrode disposed on the barrier layer. 20 . The power semiconductor structure of claim 19 , wherein a current flowing from the electrode through the barrier layer and the contact member to the epitaxial layer is greater than a current flowing from the electrode through the barrier layer to the epitaxial layer.

21. A method for manufacturing a power semiconductor structure, comprising: forming an epitaxial layer over the substrate; disposing a patterned mask over the epitaxial layer; implanting dopants into the epitaxial layer exposed from the patterned mask to form a doped region of the epitaxial layer; disposing a sacrificial member to cover the doped region; disposing a first dielectric layer above the epitaxial layer; removing the sacrificial member to form an opening surrounded by the first dielectric layer and exposing the doped region; Disposing a second dielectric layer above the first dielectric layer and the doped region, wherein the second dielectric layer is conformal to the sidewall of the opening; removing a first portion of the second dielectric layer to expose a portion of the doped region; disposing a contact material over the portion of the doped region; forming a contact member from the contact material and the portion of the doped region; and Remaining portions of the first dielectric layer and the second dielectric layer are removed. 22 . The manufacturing method according to claim 21 , wherein the second dielectric layer conformally disposed with the sidewall of the opening has a uniform thickness along the sidewall of the opening. The manufacturing method according to claim 21 , wherein the sacrificial member protrudes from the epitaxial layer. 24 . The manufacturing method of claim 21 , wherein the second portion of the second dielectric layer contacts the first dielectric layer and is removed during the removal of the first portion of the second dielectric layer.

25. The manufacturing method according to claim 21, further comprising: forming a barrier layer above the epitaxial layer and the doped region and surrounding the contact member; An electrode is formed over the barrier layer.

26. A power semiconductor structure comprising: substrate; an epitaxial layer on the substrate; extending into a doped region in the epitaxial layer; a contact member disposed on the doped region or partially surrounded by the doped region; and a barrier layer disposed on the epitaxial layer and the doped region and surrounding the contact member, The width of the interface between the doped region and the barrier layer and surrounding the contact member is uniform. 27 . The power semiconductor structure of claim 26 , wherein a width of the portion of the doped region surrounding the contact member is uniform.

28. The power semiconductor structure of claim 26, wherein a width of the doped region is equal to twice the width of the interface plus a width of the contact member.

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