Ceramic packaging structure preparation method and ceramic packaging structure

Abstract

The invention provides a ceramic packaging structure preparation method and a ceramic packaging structure, and belongs to the technical field of semiconductor devices.The ceramic packaging structure preparation method comprises the steps that a through hole is machined in a substrate, and a metalized seed layer is formed on the surface of the substrate and the inner wall of the through hole; coating a photoresist layer on the surface of the substrate, processing the substrate by adopting a photoetching process, and forming a stress buffer layer on the seed layer; coating a photoresist layer on the surface of the substrate, processing the substrate by adopting a photoetching process to obtain an electroplating pattern, and processing the electroplating pattern to form a thickened metallization layer; forming a box dam pattern by adopting a photoresist layer and exposure twice in sequence, and respectively forming a stress buffer layer and a metallization layer; and removing the photoresist material to expose the seed layer, and removing the seed layer outside the electroplating pattern to expose the substrate. According to the preparation method of the ceramic packaging structure provided by the invention, the silk-screen precision and the thickness consistency of the horizontal conductor layer are improved, and the adverse effect of the conductor layer problem on the high-frequency characteristic is reduced.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor devices, and more particularly to a ceramic packaging structure preparation method and ceramic packaging structure. BACKGROUND

[0002] With the continuous development of radio frequency three-dimensional integration technology, advanced packaging technology for radio frequency is continuously developed. 2D, 2.5D and 3D wafer level packaging are very popular, but in the high frequency field, ceramic packaging still occupies a large market share. Currently, ceramic packaging mostly adopts LTCC or HTCC packaging, but due to the process characteristics of sintering after lamination, the relative position of the vertical metal interconnection hole is dislocated due to the deformation of sintering shrinkage, the silk screen precision of the horizontal conductor layer is low, and the thickness consistency is poor, which leads to significant deterioration of the high frequency characteristics of the packaging. SUMMARY

[0003] The present application aims to provide a ceramic packaging structure preparation method and ceramic packaging structure to solve the technical problems of inconvenient operation and low safety of semiconductor devices in the prior art.

[0004] To achieve the above-mentioned purpose, the technical solution adopted by the present application is to provide a ceramic packaging structure preparation method, comprising:

[0005] S1: processing a through hole on a substrate, and forming a metalized seed layer on the substrate surface and the inner wall of the through hole;

[0006] S2: coating a photoresist layer on the substrate surface, processing the substrate using a photolithography process, and forming a stress buffer layer on the seed layer;

[0007] S3: removing the photoresist layer to expose the seed layer;

[0008] S4: coating a photoresist layer on the substrate surface, processing the substrate using a photolithography process to obtain an electroplating pattern, and processing the electroplating pattern to form a thickened metalized layer;

[0009] S5: forming a dam pattern using a photoresist layer and exposure, and forming a stress buffer layer on the metalized layer;

[0010] S6: forming a dam pattern using a photoresist layer and exposure on the stress buffer layer to form a metalized layer;

[0011] S7: removing the photoresist material to expose the seed layer, and removing the seed layer outside the electroplating pattern to expose the substrate.

[0012] In a possible implementation, the stress buffer layer in step S2 is a three-layer structure arranged from bottom to top, the bottom layer is copper plating with a thickness of 2-15 μm, the middle layer is a buffer metal with a thickness of 0.5-25 μm, and the top layer is copper with a thickness of 2-15 μm.

[0013] In a possible implementation, steps S2 and S4 use spin coating or film coating and hot pressing to coat the photoresist layer on the surface of the substrate.

[0014] In a possible implementation, the deposition method is used in step S4 to fill the through hole to the surface protrusion, and there is no cavity inside the through hole; the deposition method uses pulse plating and direct current plating.

[0015] In a possible implementation, the metal layer in step S4 is thinned and surface treated.

[0016] In a possible implementation, the stress buffer layer in step S5 is a three-layer structure arranged from bottom to top, the bottom layer is copper plating with a thickness of 2-15 μm, the middle layer is a buffer metal with a thickness of 5-125 μm, and the top layer is copper with a thickness of 2-15 μm.

[0017] In a possible implementation, before the seed layer is formed in step S1, the substrate is cleaned, and the deposition method is used to form the seed layer on the substrate; the seed layer is Ti / Cu with a thickness of 50 nm-5000 nm.

[0018] In a possible implementation, in step S1, the ratio of the thickness of the substrate to the aperture of the through hole is 3:1 to 4:1.

[0019] In a possible implementation, in step S7, the surface metal pattern area is covered and protected by using chemical nickel-gold plating.

[0020] The ceramic packaging structure preparation method has the advantages that, compared with the prior art, the ceramic packaging structure preparation method first selects a substrate as a bottom surface supporting material of the ceramic packaging, processes a through hole on the substrate, and forms a metallized seed layer on the surface of the substrate and the inner wall of the through hole, the processing of the through hole provides a channel for subsequent vertical interconnection, and the metallized seed layer lays a foundation for the growth of a subsequent metallized layer. Then, a photoresist layer is coated on the surface of the substrate, the substrate is processed by using a photolithography process, and a stress buffer layer is formed on the seed layer; the coating of the photoresist layer and the photolithography process can accurately determine a processing area, and the formation of the stress buffer layer can effectively relieve stress that may be generated in a subsequent process, so as to avoid damage to the substrate and the metallized structure. Then, the photoresist layer is removed to expose the seed layer, so as to prepare for the next operation. Next, the photoresist layer and the photolithography process are used again to more accurately determine an electroplating area, and a thickened metallized layer formed can improve the conductivity and structural strength of the metal interconnection, and also can improve the thickness consistency of the horizontal conductor layer. Then, the photoresist layer and exposure are used twice to form dam patterns, respectively form stress buffer layers on the metallized layer, and then form metallized layers on the stress buffer layers; the formation of the dam patterns can limit subsequent material deposition, so as to ensure the accuracy of the structure, and the re-setting of the stress buffer layers further enhances the stress resistance of the structure; and the metallized layers are formed on the stress buffer layers, which is a further improvement and optimization of the structure. Finally, the photoresist material is removed to expose the seed layer, and the seed layer outside the electroplating pattern is removed to expose the substrate, so that the entire packaging structure is more simple and accurate. In this way, from the vertical direction, the stress buffer layers and other measures formed in the process effectively solve the problem of dislocation of the relative positions of the metal interconnection holes caused by sintering shrinkage deformation in the traditional process, improve the accuracy and reliability of the vertical interconnection, and thus improve the high-frequency characteristics of the packaging. In the horizontal direction, the photolithography process and the electroplating process are used to form the metallized layer, instead of the traditional silk screen process, which greatly improves the silk screen accuracy and thickness consistency of the horizontal conductor layer, and reduces the adverse effects of the conductor layer on the high-frequency characteristics.

[0021] Another object of the present application is to provide a ceramic packaging structure processed by any one of the ceramic packaging structure preparation methods, comprising a substrate, a through hole and a seed layer arranged on the surface of the substrate and filled in the through hole are arranged on the substrate, a stress buffer layer is arranged in the seed layer, and a plurality of stress buffer layers and metallized layers formed by dam patterns are arranged on the seed layer.

[0022] The ceramic packaging structure provided by the application takes a substrate as a core carrier, and a through hole is processed on the substrate for realizing vertical interconnection between layers. The surface of the substrate and the inner wall of the through hole are covered with a metallization seed layer, which provides an electrically conductive base and interface bonding force for subsequent metal deposition. The seed layer is internally and externally provided with a plurality of stress buffer layers constructed through photolithography and electroplating processes. The stress buffer layers are designed in three layers from bottom to top to relieve interface stress during sintering or thermal cycling. The metallization layer is defined in a region through a dam pattern and thickened and filled through pulse plating and direct current plating processes to ensure that the through hole is free of cavities and the surface is smooth, and the line width precision and thickness consistency of the horizontal conductor layer are significantly improved. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0024] Figure 1 The schematic diagram corresponding to S1 in the ceramic packaging structure preparation method provided by the embodiment of the application Figure 1 ;

[0025] Figure 2 The schematic diagram corresponding to S1 in the ceramic packaging structure preparation method provided by the embodiment of the application Figure 2 ;

[0026] Figure 3 The schematic diagram corresponding to S2 in the ceramic packaging structure preparation method provided by the embodiment of the application

[0027] Figure 4 The schematic diagram corresponding to S3 in the ceramic packaging structure preparation method provided by the embodiment of the application

[0028] Figure 5 The schematic diagram corresponding to S4 in the ceramic packaging structure preparation method provided by the embodiment of the application

[0029] Figure 6 The schematic diagram corresponding to S5 in the ceramic packaging structure preparation method provided by the embodiment of the application

[0030] Figure 7 The schematic diagram corresponding to S6 in the ceramic packaging structure preparation method provided by the embodiment of the application

[0031] Figure 8 The schematic diagram corresponding to S7 in the ceramic packaging structure preparation method provided by the embodiment of the application

[0032] In the drawings, reference numerals:

[0033] 10 substrate; 11 via hole; 12 seed layer; 13 photoresist layer; 14 stress buffer layer; 15 metallization layer. DETAILED DESCRIPTION

[0034] In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects more clearly, the present application will be further described in detail below in combination with the drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application and not to limit the present application.

[0035] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0036] It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0037] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0038] Please refer to Figures 1 to 8 The preparation method of the ceramic packaging structure provided by the present application will be described. A preparation method of a ceramic packaging structure, comprising:

[0039] S1: machining a via hole 11 on a substrate 10, and forming a metallized seed layer 12 on the surface of the substrate 10 and the inner wall of the via hole 11;

[0040] S2: coating a photoresist layer 13 on the surface of the substrate 10, machining the substrate 10 using a photoetching process, and forming a stress buffer layer 14 on the seed layer 12;

[0041] S3: removing the photoresist layer 13 to expose the seed layer 12;

[0042] S4: coating photoresist layer 13 on the surface of substrate 10, processing substrate 10 by photolithography to obtain plating pattern, and processing the plating pattern to form thickened metallization layer 15;

[0043] S5: forming dam pattern by photoresist layer 13 and exposure, and forming stress buffer layer 14 on metallization layer 15;

[0044] S6: forming dam pattern by photoresist layer 13 and exposure again, and forming metallization layer 15 on stress buffer layer 14;

[0045] S7: removing photoresist material to expose seed layer 12, and removing seed layer 12 outside the plating pattern to expose substrate 10.

[0046] The ceramic packaging structure preparation method provided by the application, compared with the prior art, firstly selects a substrate 10 as a bottom surface supporting material of the ceramic packaging, processes a through hole 11 on the substrate 10, and forms a metallized seed layer 12 on the surface of the substrate 10 and the inner wall of the through hole 11, the processing of the through hole 11 provides a channel for subsequent vertical interconnection, and the metallized seed layer 12 lays a foundation for the growth of a subsequent metallized layer 15. Then, a photoresist layer 13 is coated on the surface of the substrate 10, the substrate 10 is processed by using a photolithography process, and a stress buffer layer 14 is formed on the seed layer 12; the coating of the photoresist layer 13 and the photolithography process can accurately determine the processing area, and the formation of the stress buffer layer 14 can effectively alleviate the stress that may be generated in the subsequent process, so as to avoid damage to the substrate 10 and the metallized structure. Then, the photoresist layer 13 is removed, and the seed layer 12 is exposed, so as to prepare for the next operation. Next, the photoresist layer 13 and the photolithography process are used again, the electroplating area can be more accurately determined, the thickened metallized layer 15 formed can improve the conductivity and structural strength of the metal interconnection, and can also improve the thickness consistency of the horizontal conductor layer. Then, the photoresist layer 13 and exposure are used twice to form a dam pattern, the stress buffer layer 14 is formed on the metallized layer 15, and then the metallized layer 15 is formed on the stress buffer layer 14; the formation of the dam pattern can limit the subsequent material deposition, so as to ensure the accuracy of the structure, and the re-setting of the stress buffer layer 14 further enhances the stress resistance of the structure; and the metallized layer 15 is formed on the stress buffer layer 14, which is a further improvement and optimization of the structure. Finally, the photoresist material is removed to expose the seed layer 12, and the seed layer 12 outside the electroplating pattern is removed to expose the substrate 10, so that the entire packaging structure is more simple and accurate. In this way, from the vertical direction, through the measures of forming the stress buffer layer 14 and the like in the process, the problem of dislocation of the relative positions of the metal interconnection holes caused by sintering shrinkage deformation in the traditional process is effectively solved, the accuracy and reliability of the vertical interconnection are improved, and the high-frequency characteristics of the packaging are improved. In the horizontal direction, the photolithography process and the electroplating process are used to form the metallized layer 15, instead of the traditional silk screen process, the silk screen accuracy and thickness consistency of the horizontal conductor layer are greatly improved, and the adverse effects of the conductor layer on the high-frequency characteristics are reduced.

[0047] See Figure 1 and Figure 2As a specific embodiment of the ceramic packaging structure preparation method provided by the application, the stress buffer layer 14 in step S2 is a three-layer structure arranged from bottom to top, the bottom layer is copper plating and has a thickness of 2-15 μm, the middle layer is a buffer metal and has a thickness of 0.5-25 μm, and the top layer is copper and has a thickness of 2-15 μm. After the through hole 11 processing of the substrate 10 and the metalization of the seed layer 12 are completed, the surface of the substrate 10 is coated with a photoresist material and a specific pattern area is formed by a photoetching process, so as to expose the surface of the seed layer 12 which needs to build the stress buffer layer 14; then, by using electroplating or physical vapor deposition technology, a bottom copper plating layer is first deposited on the seed layer 12, and the thickness is controlled to be 2-15 μm, which on the one hand forms a good metallurgical bond with the seed layer 12, and on the other hand provides a uniform substrate for the middle layer; then, a middle buffer metal layer is plated on the surface of the bottom copper layer, and materials such as chromium and nickel which have excellent ductility and high matching degree of the thermal expansion coefficient with the ceramic substrate 10 can be selected, and the thickness ranges from 0.5 to 25 μm, and the stress buffering capacity can be accurately controlled by adjusting the thickness of the layer; finally, a top copper plating layer is deposited on the surface of the buffer metal layer, and the thickness is also controlled to be 2-15 μm, forming a symmetrical “copper-buffer metal-copper” sandwich structure. After the three-layer deposition is completed, the photoresist layer 13 is removed, so that the stress buffer layer 14 is only retained in the functional area defined by the photoetching, thereby providing a stable substrate for the subsequent electroplating and thickening of the metalization layer 15.

[0048] Please refer to Figures 1 to 5 As a specific embodiment of the ceramic packaging structure preparation method provided by the application, steps S2 and S4 adopt spin coating or film coating and hot pressing to coat the photoresist layer 13 on the surface of the substrate 10. In the preparation process of the high-frequency ceramic packaging structure, the coating precision of the photoresist layer 13 directly affects the resolution of the photoetching pattern and the forming quality of the subsequent metalization layer 15. In view of the problems such as uneven thickness and edge blur existing in the traditional silk screen coating, spin coating or film coating and hot pressing, two high-precision coating processes are adopted in steps S2 and S4, and the uniformity and patterning precision of the photoresist layer 13 are improved through differentiated coating mechanisms. The spin coating process has high uniformity, and the thickness error of the photoresist layer 13 is small; the film coating and hot pressing process avoids the edge accumulation problem that may occur when liquid spin coating is used for thick film. The uniform thickness of the photoresist layer 13 directly determines the edge neatness and surface roughness of the subsequent metalization layer 15, and significantly improves the high-frequency signal integrity of the packaging structure. In addition, the two coating processes have high precision, and random error introduced by manual operation is avoided. The introduction of the spin coating and film coating and hot pressing processes solves the precision bottleneck of the traditional photoresist coating through precise coating control and process adaptation, lays a foundation for the high-precision forming of the stress buffer layer 14 and the metalization layer 15, and fundamentally improves the high-frequency electrical performance and reliability of the ceramic packaging structure, and becomes a key process link for breaking through the technical barriers of high-frequency packaging.

[0049] Please refer to Figure 5As a specific embodiment of the ceramic packaging structure preparation method provided by the application, the through hole 11 is filled to protrude from the surface by deposition in step S4, and the through hole 11 is free of cavities; the deposition method adopts pulse plating and direct current plating; the deposition process combining pulse plating and direct current plating is used to realize the cavity-free filling and surface protruding forming of the through hole 11 by using a differentiated current control strategy. Specifically, the pulse plating fills the through hole 11 and the direct current plating thickens the surface, the metal deposition rate is kept uniform on the inner wall and bottom of the through hole 11, the segmented control of pulse plating and direct current plating realizes the balance between precision and speed, the pulse plating focuses on deep hole filling to ensure that the micro hole is free of defects; the direct current plating is used for surface thickening to improve the overall production efficiency. The deposition process combining pulse plating and direct current plating realizes the cavity-free filling and surface protruding forming of the through hole 11.

[0050] Please refer to Figure 5 As a specific embodiment of the ceramic packaging structure preparation method provided by the application, the metallized layer 15 in step S4 is thinned and surface treated; the thinned and surface treated process is innovatively used for the thickened metallized layer 15 to solve the high-frequency loss and reliability problems of traditional thick film metallization by precisely controlling the thickness and surface properties. The precise thickness control significantly reduces the characteristic impedance fluctuation caused by the thickness consistency of the horizontal conductor layer, and the thickness reduction balances the thermal expansion difference, the local precise thinning meets the high-density interconnection precision requirement, and the smoothness and yield are improved by the surface treatment operation.

[0051] Please refer to Figure 6As a specific embodiment of the ceramic packaging structure preparation method provided by the application, the stress buffer layer 14 in step S5 is a three-layer structure arranged from bottom to top, the bottom layer is copper plating and has a thickness of 2-15 μm, the middle layer is a buffer metal and has a thickness of 5-125 μm, and the top layer is copper and has a thickness of 2-15 μm. The three-layer stress buffer layer 14 is designed from bottom to top, the bottom layer and the top layer are 2-15 μm copper plating layers, and the middle layer is a 5-125 μm buffer metal layer (such as chromium, nickel, etc.), through differential material combination and thickness control, stress balance and high-frequency performance optimization between the multi-layer structure are realized. First, a photoresist material is coated on the surface of the metallization layer 15, a dam pattern area is formed through exposure and development, and the deposition range of the stress buffer layer 14 is limited; then, through electroplating or physical vapor deposition technology, a 2-15 μm bottom layer copper plating layer is prepared on the metallization layer 15, the layer forms good metallurgical bonding with the underlying metallization layer 15, and at the same time provides a flat substrate for the middle layer; then, a 5-125 μm thick buffer metal layer is deposited, according to the packaging requirements, a material with high ductility and a thermal expansion coefficient matched with the ceramic substrate 10 is selected, and the stress buffering capacity is accurately controlled through thickness adjustment; finally, a 2-15 μm top layer copper layer is plated on the surface of the buffer metal layer, forming a symmetrical “copper-buffer metal-copper” sandwich structure, after photoresist removal treatment, the buffer layer is only retained in the dam pattern area, providing stable support for the subsequent upper metallization layer 15.

[0052] As a specific embodiment of the ceramic packaging structure preparation method provided by the application, before step S1 of forming the seed layer 12, the substrate 10 is cleaned, and the seed layer 12 is formed on the substrate 10 by deposition; the seed layer 12 is Ti / Cu, and the thickness is 50 nm-5000 nm. In order to ensure the reliable combination of the metallization layer 15 and the substrate 10, the substrate 10 is pretreated before forming the seed layer 12, and a high-performance Ti / Cu seed layer 12 (thickness 50 nm-5000 nm) is used. Specifically, first, the ceramic substrate 10 is cleaned in multiple steps, through ultrasonic-assisted acid-base alternating cleaning, surface oil stains, oxides and nanoscale contaminants are completely removed, the surface roughness of the substrate 10 is reduced, and a clean substrate is provided for seed layer 12 deposition. Then, through physical vapor deposition (PVD, such as magnetron sputtering) or chemical vapor deposition (CVD) technology, a Ti layer is first deposited, and then a Cu layer is deposited on the Ti layer to construct the Ti / Cu seed layer 12.

[0053] Optionally, in step S1, the ratio of the thickness of the substrate 10 to the aperture of the through hole 11 is 3:1 to 4:1; through precise constraint of geometric parameters, an optimal balance is achieved between the through hole 11 processing feasibility, metallization filling quality, high-frequency signal transmission performance and mechanical reliability, which provides an ideal physical basis for subsequent key processes such as seed layer 12 deposition, pulse plating filling, etc.

[0054] Please refer toFigure 8 As a specific embodiment of the ceramic packaging structure preparation method provided by the application, in step S7, the surface metal pattern area is covered and protected by adopting a chemical nickel-gold plating method; in order to improve the environmental tolerance and functional reliability of the surface metal pattern, the chemical nickel-gold plating process is adopted to cover and protect the surface metal pattern, so as to realize multi-dimensional optimization of oxidation resistance, solderability and high-frequency performance.

[0055] Please refer to Figure 8 The application further provides a ceramic packaging structure processed by the ceramic packaging structure preparation method according to any one of the application, which comprises a substrate 10, wherein the substrate 10 is provided with a through hole 11 and a seed layer 12 arranged on the surface of the substrate 10 and filled in the through hole 11, the seed layer 12 is internally provided with a stress buffer layer, and the seed layer 12 is provided with a plurality of stress buffer layers and a metallization layer 15 formed by a dam pattern.

[0056] The ceramic packaging structure provided by the application takes the substrate 10 as a core carrier, the substrate 10 is processed with a through hole 11 penetrating through the substrate 10, which is used for realizing vertical interconnection between layers. The surface of the substrate 10 and the inner wall of the through hole 11 are covered with a metallization seed layer 12, which provides an electrically conductive base and interface bonding force for subsequent deposition of the metallization layer 15. The seed layer 12 is internally and externally provided with a plurality of stress buffer layers 14 constructed by a photoetching and electroplating process. The stress buffer layer 14 adopts a three-layer design from bottom to top (bottom layer of copper plating 2-15 μm, middle buffer metal 0.5-25 μm, top layer of copper plating 2-15 μm), which effectively relieves the interface stress in the sintering or thermal cycling process through gradient matching of material ductility and thermal expansion coefficient. The metallization layer 15 is defined by a dam pattern to limit the area, and is thickened and filled by adopting a pulse plating and direct current plating process, so as to ensure that the through hole 11 is free of hollow and the surface is smooth, and the line width precision and thickness consistency of the horizontal conductor layer are significantly improved.

[0057] The above is only a preferred embodiment of the application, and is not used to limit the application, and any modification, equivalent replacement and improvement made within the spirit and principle of the application shall be included in the protection scope of the application.

Claims

1. A method for preparing a ceramic packaging structure, characterized in that: include: S1: Processing a through hole on the substrate and forming a metallized seed layer on the substrate surface and the inner wall of the through hole; S2: coating a photoresist layer on the surface of the substrate, processing the substrate using a photolithography process, and forming a stress buffer layer on the seed layer; S3: remove the photoresist layer to expose the seed layer; S4: coating a photoresist layer on the surface of the substrate, processing the substrate using a photolithography process to obtain an electroplating pattern, and processing the electroplating pattern to form a thickened metallization layer; S5: forming a dam pattern by using a photoresist layer and exposure, and forming a stress buffer layer on the metallization layer; S6: forming a dam pattern by using a photoresist layer and exposure, and forming a metallization layer on the stress buffer layer; S7: removing the photoresist material to expose the seed layer, and removing the seed layer outside the electroplating pattern to expose the substrate.

2. The method for preparing a ceramic packaging structure according to claim 1, wherein: The stress buffer layer in step S2 is a three-layer structure arranged from bottom to top, with the bottom layer being copper-plated with a thickness of 2-15 μm, the middle layer being buffer metal with a thickness of 0.5-25 μm, and the top layer being copper with a thickness of 2-15 μm.

3. The method for preparing a ceramic packaging structure according to claim 1, wherein: In steps S2 and S4, the photoresist layer is coated on the surface of the substrate by spin coating or lamination and hot pressing.

4. The method for preparing a ceramic packaging structure according to claim 1, wherein: In step S4, a deposition method is used to fill the through hole until the surface is protruding and there is no void inside the through hole; the deposition method uses two methods: pulse plating and direct current plating.

5. The method for preparing a ceramic packaging structure according to claim 4, wherein: The metallization layer in step S4 is thinned and surface treated.

6. The method for preparing a ceramic packaging structure according to claim 1, wherein: The stress buffer layer in step S5 is a three-layer structure arranged from bottom to top, with the bottom layer being copper-plated with a thickness of 2-15 μm, the middle layer being buffer metal with a thickness of 5-125 μm, and the top layer being copper with a thickness of 2-15 μm.

7. The method for preparing a ceramic packaging structure according to claim 1, wherein: Before forming the seed layer in step S1, the substrate is cleaned and a seed layer is formed on the substrate by deposition; the seed layer is Ti / Cu and has a thickness of 50nm-5000nm.

8. The method for preparing a ceramic packaging structure according to claim 7, wherein: In step S1 , the ratio of the thickness of the substrate to the aperture of the through hole is 3:1 to 4:

1.

9. The method for preparing a ceramic packaging structure according to claim 1, wherein: In step S7, the surface metal pattern area is covered and protected by chemical nickel-gold plating.

10. A ceramic packaging structure, characterized in that: The ceramic packaging structure is processed using the method for preparing the ceramic packaging structure according to any one of claims 1 to 9, and includes a substrate, the substrate being provided with a through hole and a seed layer arranged on the surface of the substrate and filling the through hole, a buffer stress layer being provided inside the seed layer, and the seed layer being provided with multiple buffer stress layers and metallization layers formed by dam patterns.

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