Method for improving bump defect of copper interconnection metal layer
By forming a nitrogen-doped silicon carbide layer on the copper interconnect metal layer and mitigating stress release, the problem of protrusion defects in the copper interconnect metal layer is solved, thereby improving the reliability and current stability of the device.
Patent Information
- Application Number
- CN202510783327.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-11
- Publication Date
- 2025-10-17
AI Technical Summary
Copper interconnect metal layers oxidize in air to form protrusion defects, which lead to copper diffusion and interconnect failure during device manufacturing, affecting device performance.
A nitrogen-doped silicon carbide layer is formed on the copper interconnect metal layer as a copper diffusion barrier layer, and stress release is alleviated by reducing the activity of ammonia gas, and the deposition process is optimized to reduce protrusion defects.
It effectively reduces the number of protrusion defects in the copper interconnect metal layer, improves leakage current between copper interconnects, and enhances product reliability.
Smart Images
Figure CN120809675A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a method for improving hillock defects of copper interconnection metal layer. BACKGROUND
[0002] With the continuous shrinkage of semiconductor manufacturing process nodes, damascene process is widely used in copper interconnection technology, but copper is easy to be oxidized when exposed to air, and the oxide formed will diffuse into the dielectric layer to cause damage to the dielectric layer or generate hillock defects as shown in Figure 1 The defects will cause copper diffusion during device manufacturing and lead to interconnection failure. SUMMARY
[0003] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a method for improving hillock defects of copper interconnection metal layer, which is used to solve the problem that hillock defects of copper interconnection metal layer seriously affect the performance of devices in the prior art.
[0004] To achieve the above-mentioned purpose and other related purposes, the present application provides a method for improving hillock defects of copper interconnection metal layer, comprising:
[0005] Step one, providing a substrate, forming a bottom structure on the substrate, the bottom structure comprising a copper interconnection metal layer and an interlayer dielectric layer, the copper interconnection metal layer being embedded in the interlayer dielectric layer;
[0006] Step two, forming a nitrogen-doped silicon carbide layer as a copper diffusion barrier layer on the top surface of the bottom structure by a deposition process, the precursor gas for nitrogen doping of the deposition process being ammonia gas;
[0007] Step three, introducing nitrogen gas into the chamber in which the deposition process is implemented to alleviate the release of stress of the nitrogen-doped silicon carbide layer by reducing the activity of ammonia gas.
[0008] Preferably, the flow rate of nitrogen gas is 1000sccm-4000sccm, and the processing time is 2s-5s.
[0009] Preferably, the precursor gas of the deposition process implemented in step two further comprises a silicon precursor gas and a carbon precursor gas.
[0010] Preferably, the silicon precursor gas comprises a chlorinated compound such as dichlorosilane.
[0011] Preferably, the carbon precursor gas comprises a hydrocarbon such as acetylene.
[0012] Preferably, the carrier gas of the deposition process implemented in step two is helium.
[0013] Preferably, the deposition process implemented in step two is plasma enhanced chemical vapor deposition.
[0014] Preferably, the interlayer dielectric layer is formed on the substrate by another deposition process.
[0015] Preferably, the step of forming the copper interconnect metal layer in the interlayer dielectric layer comprises: forming a patterned mask layer on the interlayer dielectric layer by a photolithography and etching process; forming a via / trench in the interlayer dielectric layer by an etching process with the mask layer as a mask; and filling the via / trench with the copper interconnect metal layer after removing the mask layer.
[0016] As described above, the method for improving the protrusion defects of the copper interconnect metal layer provided by the present application has the following beneficial effects: the number of the protrusion defects of the copper interconnect metal layer is reduced by optimizing the growth process of the copper diffusion barrier layer, so as to improve the interline leakage current of the copper interconnect and improve the reliability of the product. BRIEF DESCRIPTION OF DRAWINGS
[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the specific embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without making creative efforts.
[0018] Figure 1 An electron photo showing the protrusion defects of the copper interconnect metal layer;
[0019] Figure 2 A flow chart showing the method for improving the protrusion defects of the copper interconnect metal layer provided by the embodiments of the present application. DETAILED DESCRIPTION
[0020] The technical solutions in the embodiments of the present application will be described below by specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in the present specification. The present application can also be implemented or applied by different specific embodiments, and the details in the present specification can be modified or changed based on different views and applications without departing from the spirit of the present application.
[0021] The technical solutions in the embodiments of the present application will be described below by specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in the present specification. The present application can also be implemented or applied by different specific embodiments, and the details in the present specification can be modified or changed based on different views and applications without departing from the spirit of the present application.
[0022] In the description of the present application, it should be explained that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0023] In the description of the present application, it should be explained that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements, it can be wireless connection, or it can be wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0024] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict between them.
[0025] Nitrogen-doped silicon carbide (NDC) is widely used as a material for copper diffusion barrier layer. The inventors have found through experimental research that the deposition process flow of nitrogen-doped silicon carbide plays a crucial role in the size and density of copper interconnection metal layer bump defects.
[0026] Please refer to Figure 2 , which shows the flowchart of the method for improving copper interconnection metal layer bump defects provided by the embodiments of the present application.
[0027] As Figure 2 shown, the method for improving copper interconnection metal layer bump defects comprises the following steps:
[0028] Step one, providing a substrate, forming a bottom structure on the substrate, the bottom structure comprising a copper interconnection metal layer and an interlayer dielectric layer, the copper interconnection metal layer being embedded in the interlayer dielectric layer;
[0029] Step two, forming a nitrogen-doped silicon carbide layer as a copper diffusion barrier layer on the top surface of the bottom structure by a deposition process, the precursor gas used for nitrogen doping in the deposition process being ammonia gas;
[0030] Step three, introducing nitrogen gas into the chamber in which the deposition process is carried out to alleviate the release of stress of the nitrogen-doped silicon carbide layer by reducing the activity of ammonia gas.
[0031] In step one, the substrate can be a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc. Alternatively, the substrate can also be made of other materials, such as a gallium arsenide or other III-V compound. Those skilled in the art can select the material of the substrate according to the type of the device structure formed on the substrate, and therefore the type of the substrate should not limit the scope of the present application.
[0032] The substrate is formed with a plurality of isolation components, which divide the substrate into a plurality of regions. The isolation components can be made of any insulating material, such as silicon dioxide (SiO2), or a "high-K" dielectric with a high dielectric constant, which can be higher than 3.9, for example. In some cases, the isolation components can be made of an oxide material. The materials suitable for making the isolation components can include, for example, silicon dioxide (SiO2), hafnium oxide (HfO2), alumina (Al2O3), yttria (Y2O3), tantalum oxide (Ta2O5), titanium dioxide (TiO2), praseodymium oxide (Pr2O3), zirconium oxide (ZrO2), erbium oxide (ErOx), and other materials with similar properties that are currently known or later developed.
[0033] The isolation components are formed, for example, by a shallow trench isolation (STI) process, which can include, but is not limited to, a shallow trench etching, an oxide filling, and an oxide planarization.
[0034] The shallow trench etching can include, but is not limited to, an isolation oxide layer, a nitride deposition, a shallow trench isolation with a mask, and an STI shallow trench etching. The STI oxide filling can include, but is not limited to, a trench liner oxide silicon, a trench CVD (chemical vapor deposition) oxide filling, or a PVD (physical vapor deposition) oxide filling. The planarization of the surface of the silicon wafer can be achieved by various methods. The planarization of the silicon wafer can be achieved by filling the gap with SOG (spin-on-glass), which can be composed of 80% solvent and 20% silicon dioxide. After deposition, the SOG is baked to evaporate the solvent and leave the silicon dioxide in the gap. The entire surface can also be etched back to reduce the thickness of the entire silicon wafer. The planarization can also be effectively achieved by a CMP process (also known as a chemical mechanical polishing process), which can include, but is not limited to, polishing the trench oxide (which can be achieved by chemical mechanical polishing) and removing the nitride.
[0035] The different regions of the substrate are formed with various semiconductor devices, such as MOS transistors, diodes, etc.
[0036] As an example, the interlayer dielectric layer is formed on the substrate by a deposition process, and the material of the interlayer dielectric layer is, for example, but not limited to, silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2(FSG), hydrogenated carbon silicon oxide (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxide (i.e., organosilicate glass) including silicon (Si), carbon (C), oxygen (O), and / or hydrogen (H) atoms, thermoset polyarylene ether, or other low dielectric constant (<3.9) materials.
[0037] As an example, the step of forming the copper interconnection metal layer in the interlayer dielectric layer includes: forming a patterned mask layer on the interlayer dielectric layer by a photolithography and etching process; forming a via / trench in the interlayer dielectric layer by an etching process with the mask layer as a mask; and filling the via / trench with the copper interconnection metal layer after removing the mask layer.
[0038] In step two, the precursor gases of the deposition process implemented include a silicon precursor gas, a carbon precursor gas, and a precursor gas for nitrogen doping, wherein the silicon precursor gas includes a chlorinated compound, in particular dichlorosilane, trichlorosilane, or tetrachlorosilane; the carbon precursor gas includes a hydrocarbon, in particular propane, ethylene, acetylene, or methane; and the precursor gas for nitrogen doping is ammonia gas, because ammonia gas can achieve good uniformity of nitrogen doping. The carrier gas of the deposition process implemented is helium gas.
[0039] As an example, the deposition process implemented is preferably plasma-enhanced chemical vapor deposition.
[0040] In step three, the flow rate of the nitrogen gas is 1000-4000 sccm, and the processing time is 2-5 s.
[0041] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The shapes, number, and proportions of the components in actual implementation can be arbitrarily changed, and the layout pattern of the components can be more complex.
[0042] In summary, the method for improving the protrusion defects of the copper interconnection metal layer provided by the present application reduces the number of protrusion defects of the copper interconnection metal layer by optimizing the growth process of the copper diffusion barrier layer, so as to improve the interconnection line leakage current of copper and improve the reliability of the product. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.
[0043] The above embodiments are only illustrative of the principles of the present application and its effects, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.
Claims
1. A method for improving copper interconnect metal layer protrusion defects, characterized in that: The method comprises: Step 1: providing a substrate, and forming a bottom layer structure on the substrate, wherein the bottom layer structure includes a copper interconnect metal layer and an interlayer dielectric layer, and the copper interconnect metal layer is embedded in the interlayer dielectric layer; Step 2: forming a nitrogen-doped silicon carbide layer as a copper diffusion barrier layer on the top surface of the underlying structure by a deposition process, wherein the precursor gas for nitrogen doping in the deposition process is ammonia; Step three: nitrogen gas is introduced into the chamber where the deposition process is performed, so as to reduce the activity of the ammonia gas and thereby relieve the stress release of the nitrogen-doped silicon carbide layer.
2. The method according to claim 1, characterized in that The flow rate of the nitrogen gas is 1000 sccm-4000 sccm, and the processing time is 2s-5s.
3. The method according to claim 1, characterized in that The precursor gas of the deposition process implemented in step 2 further includes a silicon precursor gas and a carbon precursor gas.
4. The method according to claim 3, characterized in that The silicon precursor gas includes chlorinated compounds including dichlorosilane.
5. The method according to claim 3, characterized in that The carbon precursor gas includes hydrocarbons including acetylene.
6. The method according to claim 1, characterized in that The carrier gas for the deposition process implemented in step 2 is helium.
7. The method according to claim 1, characterized in that The deposition process implemented in the step 2 is plasma enhanced chemical vapor deposition.
8. The method according to claim 1, characterized in that The interlayer dielectric layer is formed on the substrate by another deposition process.
9. The method according to claim 1, characterized in that The steps of forming a copper interconnect metal layer in the interlayer dielectric layer include: forming a patterned mask layer on the interlayer dielectric layer by photolithography and etching processes; using the mask layer as a mask, forming through holes / grooves in the interlayer dielectric layer by etching processes; after removing the mask layer, filling the through holes / grooves with the copper interconnect metal layer.