Damascus process method
By controlling the height of the through-hole protection layer and removing the fence defects through the sputtering process, the problems of abnormal through-hole morphology and fence defects in the Damascus process are solved, and the morphological uniformity and electromigration performance of the through-hole are improved.
Patent Information
- Application Number
- CN202510811960.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-17
- Publication Date
- 2025-10-17
AI Technical Summary
In the Damascus process, the uneven height of the through-hole protection layer leads to abnormal through-hole morphology and fence defects, affecting metal connection and electrical performance.
By controlling the height of the through-hole protection layer and performing a sputtering process to remove fence defects after the trench body is etched, it is ensured that the height of the protection layer is high enough and remains at the bottom of the dielectric layer after the trench is etched, thereby preventing the through-hole from expanding and eliminating the fence defects through the sputtering process.
The morphology uniformity and electromigration performance of the through-hole are improved, while the formation of fence defects is avoided, ensuring the smooth progress of subsequent metal filling.
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Figure CN120809679A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a semiconductor integrated circuit manufacturing method, in particular to a damascene process method. BACKGROUND
[0002] With the feature size of integrated circuit decreasing and the integration density increasing, the area proportion of back-end metal connection in the chip is also increasing. According to the principle of equal proportion size reduction of semiconductor devices, with the feature size of the device decreasing, the loading of structures at different positions and with different densities during etching is different, and some structures may appear abnormal profile during etching, which affects the metal connection and electrical properties.
[0003] For a full via first damascene copper interconnection process, generally, a bottom anti-reflective coating (BARC) coating and BARC etch back process are used to protect the via before trench etching. However, the BARC remain height after BARC etch back has an important influence on the via profile. When the BARC remain is low, the protection of the via is not enough, the critical dimension (CD) of the via is abnormally increased, the profile is abnormal, and the electromigration (EM) is poor. That is, if the BARC remain is low, the protection of the via is not enough during trench liner removal (LRM) etching, which leads to abnormal etching via profile. The abnormal via profile mainly shows that the CD is large and the uniformity is difficult to control, and in addition, the turning point of the via profile is not smooth, which also leads to poor EM performance.
[0004] When the BARC remain is high, fence defects appear, which affect the deposition of the barrier layer and the seed layer (Barrier seed Dep). After the BARC remain is increased, during the main etching of the trench, because the BARC remain is high, the etching rate of the oxide layer far from the via is fast, for example, increased by about 30%. This is because the polymer near the via is heavy, which causes the etching rate of the oxide layer near the via to be lower than that of the oxide layer far from the via, and then leads to the residual of the oxide layer near the via, that is, the appearance of fence defects, which affects the subsequent Barrier seed Dep.
[0005] As Figures 1A-1GFIG. 1 is a schematic diagram of the device structure of each step in the existing Damascus process method when the height of the through-hole protection layer is relatively low; the existing Damascus process method includes the following steps:
[0006] like Figure 1A As shown, nitrogen-doped silicon carbide (NDC) 103, a first interlayer film 104, a silicon nitride layer 105 and a second interlayer film 106 are sequentially formed on the surface of the underlying structure.
[0007] The bottom structure includes a bottom interlayer film 101 and a bottom metal line 102 .
[0008] The subsequently formed via opening 109 is located directly above a portion of the bottom metal line 102 .
[0009] The photolithographic process defines selected areas for via etching, including:
[0010] like Figure 1A As shown, a dielectric anti-reflective (DARC) layer 107 is formed.
[0011] A first photoresist layer 108 is formed.
[0012] Exposure and development are performed to pattern the first photoresist layer 108 . The patterned first photoresist layer 108 opens the formation area of the through-hole opening 109 and covers the area outside the through-hole opening 109 .
[0013] like Figure 1B As shown, through-hole etching is performed in a selected area and stops at the nitrogen-doped silicon carbide 103 to form a through-hole opening 109 . The through-hole opening 109 passes through the second interlayer film 106 , the silicon nitride layer 105 and the first interlayer film 104 .
[0014] Afterwards, the first photoresist layer 108 is removed.
[0015] like Figure 1C As shown, the through-hole protection layer 110 is formed to completely fill the through-hole opening 109 and extend to the surface outside the through-hole opening 109 .
[0016] Typically, the through hole protection layer 110 is made of BARC and is formed through a coating process.
[0017] like Figure 1DAs shown, a first etch-back is performed to remove the through-hole protection layer 110 outside the through-hole opening 109 and to lower the top surface of the through-hole protection layer 110 within the through-hole opening 109. In existing methods, it is not easy to control the height of the through-hole protection layer 110 within the through-hole opening 109 during the first etch-back. Problems will arise if the height of the through-hole protection layer 110 is too high or too low. In existing methods, as the process node decreases, the load effect of the first etch-back increases, causing the height of the through-hole protection layer 110 to vary, with some areas being too high and some areas being too low, thus failing to meet process requirements.
[0018] The problem caused by the via protection layer 110 being too low will be described first.
[0019] like Figure 1F As shown, the trench body etching is performed in the selected area, and the trench body etching stops on the silicon nitride layer 105 and forms a groove 112. The through-hole protection layer 110 will be lost during the trench body etching. Since the height of the through-hole protection layer 110 is relatively low before the trench body etching, the top surface of the through-hole protection layer 110 is located below the bottom surface of the silicon nitride layer 105 after the trench body etching.
[0020] Typically, the selected areas where the trench body is etched are defined by a photolithographic process. Figure 1E As shown, the photolithography process forms a photoresist pattern 111. The open area of the photoresist pattern 111 is the formation area of the groove 112, that is, the selected area for etching the groove body.
[0021] like Figure 1G As shown, a liner remove (LRM) process is performed to remove the silicon nitride layer 105, the via protection layer 110, and the nitrogen-doped silicon carbide 103 at the bottom of the trench 112. During the LRM process, since there are exposed areas on the sides of the via opening 109 at the bottom of the silicon nitride layer 105, the exposed areas will be lateral etched, causing the width of the via opening 109 to expand, that is, the CD to expand, as shown by the dotted circle 113. Moreover, due to the loading effect, the height of the via protection layer 110 in each area will be different, resulting in different increases in the width of the via opening 109, and ultimately, the CD uniformity of the via opening 109 will be reduced.
[0022] like Figures 2A-2G , which is a schematic diagram of the device structure of each step in the existing Damascus process when the height of the through-hole protection layer is low; Figures 2A-2C The corresponding sum Figures 1A-1G The corresponding steps are exactly the same. Figure 2D The corresponding steps and Figure 1DThe difference is that, Figure 2D In the process, the height of the remaining via protection layer 110 is too high, so that, in the process of Figure 2F In the corresponding trench main etching process, the via protection layer 110 will affect the etching rate of the trench main etching process, the etching rate of the area near the via protection layer 110 will be lower, and finally a fence defect 114a will be formed on the bottom surface of the trench 112 on the side of the via opening 109.
[0023] As shown in the figure, after the LRM is completed, the fence defect 114a will be transferred downward, and the fence defect after the downward transfer is indicated by a separate mark 114. The fence defect 114 is not conducive to the subsequent metal filling, such as the deposition of the barrier layer and the seed layer. Figure 1G SUMMARY
[0024] The technical problem to be solved by the present application is to provide a damascene process method which can improve the morphology of the via and at the same time avoid the formation of a fence defect on the side of the via.
[0025] To solve the above technical problem, the damascene process method provided by the present application comprises the following steps:
[0026] A first dielectric layer, a first interlayer film, a second dielectric layer and a second interlayer film are sequentially formed on the surface of the bottom layer structure.
[0027] A via etching process is performed on the selected area to stop on the first dielectric layer and form a via opening, and the via opening passes through the second interlayer film, the second dielectric layer and the first interlayer film.
[0028] A first protection layer is formed to completely fill the via opening and extend to the surface outside the via opening.
[0029] A first etching-back process is performed to remove the first protection layer outside the via opening and control the top surface of the first protection layer inside the via opening to be at a first position.
[0030] A trench main etching process is performed on the selected area to stop on the second dielectric layer and form a trench, and the first protection layer will be lost in the trench main etching process, and the top surface of the first protection layer after the loss is ensured to be above the bottom surface of the second dielectric layer by the first position; the via opening is located in a part of the trench, and the first position will also cause a fence defect to be formed on the bottom surface of the trench on the side of the via opening.
[0031] A liner etching process is performed to remove the second dielectric layer at the bottom of the trench, and then the first protection layer is removed, and the fence defect is transferred downward to the surface of the first interlayer film.
[0032] The barrier defects are removed by a sputtering process.
[0033] The first dielectric layer at the bottom of the via opening is removed.
[0034] A further improvement is that the material of the first ILD includes silicon dioxide or low-k material.
[0035] The material of the second ILD includes silicon dioxide or low-k material.
[0036] A further improvement is that the material of the first dielectric layer includes nitrogen-doped silicon carbide.
[0037] A further improvement is that the material of the second dielectric layer includes silicon nitride.
[0038] A further improvement is that the selected area of the via etching is defined by a lithography process, including:
[0039] A DARC layer is formed.
[0040] A first photoresist layer is formed.
[0041] The first photoresist layer is patterned by exposure and development, and the patterned first photoresist layer opens the area where the via opening is formed and covers the area outside the via opening.
[0042] In the via etching, the DARC layer is etched first, and then the second ILD is etched.
[0043] After the via opening is formed, the first photoresist layer is removed.
[0044] A further improvement is that the selected area of the trench body etching is defined by a lithography process.
[0045] A further improvement is that the material of the first protective layer includes BARC, and the first protective layer is formed by a coating process.
[0046] A further improvement is that the sputtering gas of the sputtering process includes AR.
[0047] A further improvement is that the bottom structure includes a bottom ILD and a bottom metal line.
[0048] The via opening is directly above a part of the bottom metal line.
[0049] A further improvement is that the method further includes the following steps:
[0050] filling the metal material in the via opening and the trench simultaneously, forming a via from the metal material filled in the via opening, and forming a metal line from the metal material filled in the trench.
[0051] A further improvement is that the metal material forming the via and the metal line includes copper.
[0052] A further improvement is that the material of the bottom metal line includes copper.
[0053] A further improvement is that the bottom interlayer film and the bottom metal line are formed on a semiconductor substrate in which a semiconductor device is formed.
[0054] A further improvement is that the semiconductor substrate includes a silicon substrate.
[0055] A further improvement is that the step of filling the metal material in the via opening and the trench simultaneously includes:
[0056] forming a barrier layer.
[0057] forming a copper seed layer.
[0058] electroplating to form a copper layer.
[0059] The present application controls the etching back process, i.e. the first etching back, for filling the via opening to control the position of the top surface of the first protective layer, i.e. the first position, so that the height of the first protective layer is high enough and the top surface of the first protective layer which is lost after the main etching of the trench is still above the bottom surface of the second dielectric layer. Thus, the first protective layer can protect the first interlayer film well in the subsequent liner etching, and the first interlayer film will not be etched to expand the top of the via opening in the first interlayer film, so that the appearance of the via can be improved, the uniformity of the size of the via can be increased, and the EM performance can also be improved.
[0060] After the height of the first protective layer is increased, the fence defect will inevitably be formed on the bottom surface of the trench around the via opening after the main etching of the trench. The present application specially sets the liner etching to remove the second dielectric layer at the bottom of the trench first, and then remove the first protective layer. Thus, the first protective layer can protect the first interlayer film in the process of removing the second dielectric layer to prevent the expansion of the top of the via opening as described above. After the first protective layer is removed and before the first dielectric layer is removed, a sputtering process is further added to remove the fence defect, so that the fence defect can be eliminated, and thus the fence defect formed after the height of the first protective layer is increased can be eliminated. Therefore, the present application can improve the appearance of the via and avoid the formation of the fence defect around the via.
[0061] Meanwhile, since the first dielectric layer at the bottom of the via opening is retained when the sputtering process is performed, the sputtering process does not adversely affect the bottom structure, for example, does not affect the bottom metal line in the bottom structure, so that the sputtering process is added but the adverse effects caused by the sputtering process are avoided. BRIEF DESCRIPTION OF DRAWINGS
[0062] The application will be further described below in combination with the drawings and specific embodiments:
[0063] Figures 1A-1G is a device structure diagram of each step of the existing damascene process method when the height of the via protection layer is low;
[0064] Figures 2A-2G is a device structure diagram of each step of the existing damascene process method when the height of the via protection layer is high;
[0065] Figure 3 is a flowchart of the damascene process method of the embodiment of the application;
[0066] Figures 4A-4H is a device structure diagram of each step of the damascene process method of the embodiment of the application. DETAILED DESCRIPTION
[0067] As shown in Figure 3 , it is a flowchart of the damascene process method of the embodiment of the application; as shown in Figures 4A-4H , it is a device structure diagram of each step of the damascene process method of the embodiment of the application; the damascene process method of the embodiment of the application comprises the following steps:
[0068] Step S101, as shown in Figure 4A , a first dielectric layer 203, a first interlayer film 204, a second dielectric layer 205 and a second interlayer film 206 are sequentially formed on the surface of the bottom structure.
[0069] In the embodiment of the application, the bottom structure comprises a bottom interlayer film 201 and a bottom metal line 202.
[0070] The subsequently formed via opening 209 is located directly above a part of the region of the bottom metal line 202.
[0071] The bottom interlayer film 201 and the bottom metal line 202 are formed on a semiconductor substrate (not shown), and a semiconductor device (not shown) is formed in the semiconductor substrate.
[0072] In some embodiments, the semiconductor substrate comprises a silicon substrate.
[0073] The material of the first interlayer film 204 is silicon oxide, such as undoped silicon glass (USG). In other embodiments, the material of the first interlayer film 204 can also be a low dielectric material.
[0074] The material of the second interlayer film 206 is silicon oxide, such as USG. In other embodiments, the material of the second interlayer film 206 can also be a low-dielectric material.
[0075] The material of the first dielectric layer 203 includes nitrogen-doped silicon carbide.
[0076] The material of the second dielectric layer 205 includes silicon nitride.
[0077] Step S102: Figure 4B As shown, through-hole etching is performed in selected areas and stops at the first dielectric layer 203 to form a through-hole opening 209 . The through-hole opening 209 passes through the second interlayer film 206 , the second dielectric layer 205 and the first interlayer film 204 .
[0078] In an embodiment of the present invention, defining the selected area for etching the through hole by a photolithography process includes:
[0079] like Figure 4A As shown, a DARC layer 207 is formed.
[0080] A first photoresist layer 208 is formed.
[0081] Exposure and development are performed to pattern the first photoresist layer 208 . The patterned first photoresist layer 208 opens the formation area of the through-hole opening 209 and covers the area outside the through-hole opening 209 .
[0082] like Figure 4B As shown, in the through hole etching, the DARC layer 207 is etched first, and then the second interlayer film 206 is etched.
[0083] After the through hole opening 209 is formed, the process further includes: removing the first photoresist layer 208 .
[0084] Step S103: Figure 4C As shown, the first protection layer 210 is formed to completely fill the through-hole opening 209 and extend to the surface outside the through-hole opening 209 .
[0085] In some embodiments, the material of the first protection layer 210 includes BARC, and the first protection layer 210 is formed by a coating process.
[0086] Step S104: Figure 4DAs shown, the first protective layer 210 outside the via opening 209 is removed by the first etch-back, and the top surface of the first protective layer 210 inside the via opening 209 is controlled at a first position.
[0087] Step S105, as shown, Figure 4F As shown, the trench body etching is performed in the selected region, the trench body etching is stopped on the second dielectric layer 205 and forms a trench 212, the first protective layer 210 is lost in the trench body etching, and the first position ensures that the top surface of the first protective layer 210 after the loss is above the bottom surface of the second dielectric layer 205; the via opening 209 is located in a part of the region of the trench 212, and the first position will also form a fence defect 213a on the bottom surface of the trench 212 located at the periphery of the via opening 209.
[0088] In the embodiment of the present application, the selected region of the trench body etching is defined by a photolithography process. As shown, Figure 4E The photolithography process forms a photoresist pattern 211, and the opening region of the photoresist pattern 211 is the forming region of the trench 212, that is, the selected region of the trench body etching.
[0089] Step S106, as shown, Figure 4G As shown, the liner etching is performed to remove the second dielectric layer 205 at the bottom of the trench 212, and then the first protective layer 210 is removed, the fence defect 213a is transferred downward to the surface of the first interlayer film 204, and after the liner etching, the fence defect transferred downward is marked separately as a mark 213.
[0090] Step S107, as shown, Figure 4H As shown, the fence defect 213 is removed by a sputtering process.
[0091] In some embodiments, the sputtering gas of the sputtering process includes AR.
[0092] Step S108, as shown, Figure 4H As shown, the first dielectric layer 203 at the bottom of the via opening 209 is removed.
[0093] Further comprising the following steps:
[0094] The metal material is filled in the via opening 209 and the trench 212 at the same time, the metal material filled in the via opening 209 forms a via, and the metal material filled in the trench 212 forms a metal line.
[0095] In some embodiments, the metal material forming the via and the metal line includes copper.
[0096] The material of the bottom metal line 202 includes copper.
[0097] The step of filling the metal material in the via opening 209 and the trench 212 simultaneously includes:
[0098] A barrier layer is formed. In some embodiments, the barrier layer is formed by a TaN layer and a Ta layer. Both the TaN layer and the Ta layer are formed by a PVD process.
[0099] A copper seed layer is formed. In some embodiments, the copper seed layer is formed by a PVD process.
[0100] A copper layer is formed by electroplating.
[0101] The embodiment of the present application realizes a method for optimizing the profile of a copper interconnection via. By increasing the BARC Remain height to ensure a normal Via Profile, and then adding an AR sputter before the NDC Open, the Via Fence Defect is eliminated, and a required via profile is obtained. Since the added AR sputter is before the NDC Open, the lower Cu layer is not damaged. The embodiment of the present application can obtain a required via profile by increasing the BARC Remain height + adding an AR sputter before the NDC Open.
[0102] The embodiment of the present application controls the first etching back process, i.e., the first etching back, to control the position of the top surface of the first protective layer 210, i.e., the first position. The first position is high enough to ensure that the top surface of the first protective layer 210 is still above the bottom surface of the second dielectric layer 205 after the main etching of the trench is completed. In the subsequent liner etching, the first protective layer 210 can well protect the first interlayer film 204, and the first interlayer film 204 is prevented from being etched to expand the top of the via opening 209 in the first interlayer film 204, so that the profile of the via is improved, the uniformity of the size of the via is increased, and the EM performance is also improved. Figure 4H As shown in the figure, the via opening 209 is in the first interlayer film 204, and the top trench 212 is in the second interlayer film 206. It can be seen that the width of the top of the via opening 209 is uniform, and the profile is good.
[0103] After the height of the first protective layer 210 is increased, a fence defect 213a will inevitably be formed on the bottom surface of the trench 212 around the via opening 209 after the main body of the trench is etched. The present embodiment makes special settings for the liner etching, i.e. the second dielectric layer 205 at the bottom of the trench 212 is removed first, and then the first protective layer 210 is removed. In this way, the first protective layer 210 will protect the first interlayer film 204 during the removal of the second dielectric layer 205, preventing the top of the via opening 209 from expanding as described above. After the first protective layer 210 is removed and before the first dielectric layer 203 is removed, a sputtering process is added to remove the fence defect 213, so that the fence defect 213 can be eliminated, thereby eliminating the fence defect that will be formed after the height of the first protective layer 210 is increased. Therefore, the present embodiment can improve the morphology of the via and at the same time avoid the formation of the fence defect 213 around the via. As shown in FIG. 8, the elimination of the fence defect 213 is conducive to the formation of the barrier layer and the copper seed layer subsequently. Figure 4H
[0104] At the same time, since the first dielectric layer 203 at the bottom of the via opening 209 is still retained when the sputtering process is performed, the sputtering process will not adversely affect the bottom structure, for example, it will not affect the bottom metal line 202 in the bottom structure. Therefore, the present embodiment adds the sputtering process but can avoid the adverse effects caused by the sputtering process.
[0105] The present application has been described in detail by specific embodiments, but these do not constitute a limitation on the present application. Those skilled in the art can make many modifications and improvements without departing from the principles of the present application, and these should also be considered as falling within the scope of protection of the present application.
Claims
1. A Damascus process, characterized in that: Including steps: forming a first dielectric layer, a first interlayer film, a second dielectric layer and a second interlayer film in sequence on the surface of the underlying structure; Performing through-hole etching in a selected area and stopping at the first dielectric layer to form a through-hole opening, wherein the through-hole opening passes through the second interlayer film, the second dielectric layer and the first interlayer film; forming a first protective layer to completely fill the through-hole opening and extend to the surface outside the through-hole opening; Performing a first back etching to remove the first protection layer outside the through hole opening and controlling the top surface of the first protection layer inside the through hole opening to a first position; A trench body is etched in a selected area, the trench body etching stops on the second dielectric layer and a trench is formed. The first protective layer is lost during the trench body etching, and the first position ensures that the top surface of the first protective layer after loss is located above the bottom surface of the second dielectric layer. The through hole opening is located in a portion of the trench, and the first position simultaneously forms a fence defect on the bottom surface of the trench located around the through hole opening. Performing liner etching to remove the second dielectric layer at the bottom of the trench, and then removing the first protection layer, so that the fence defect is transferred downward to the surface of the first interlayer film; removing the fence defects by a sputtering process; The first dielectric layer at the bottom of the through hole opening is removed.
2. The Damascus process according to claim 1, wherein: The material of the first interlayer film includes silicon dioxide or a low dielectric material; The second interlayer film is made of silicon dioxide or a low dielectric material.
3. The Damascus process according to claim 2, wherein: The material of the first dielectric layer includes nitrogen-doped silicon carbide.
4. The Damascus process according to claim 3, wherein: The material of the second dielectric layer includes silicon nitride.
5. The Damascus process according to claim 1, wherein: Defining selected areas of the through-hole etching by a photolithography process, comprising: forming a DARC layer; forming a first photoresist layer; Performing exposure and development to pattern the first photoresist layer, wherein the patterned first photoresist layer opens the formation area of the through hole opening and covers the area outside the through hole opening; In the through hole etching, the DARC layer is etched first, and then the second interlayer film is etched; After the through hole opening is formed, the method further includes: removing the first photoresist layer.
6. The Damascus process according to claim 1, wherein: Selected areas of the trench body etching are defined by a photolithographic process.
7. The Damascus process according to claim 1, wherein: The material of the first protection layer includes BARC, and the first protection layer is formed by a coating process.
8. The Damascus process according to claim 1, wherein: The sputtering gas of the sputtering process includes AR.
9. The damascene process according to claim 1, wherein: The bottom structure includes a bottom interlayer film and a bottom metal line; The through hole opening is located directly above a portion of the bottom metal line.
10. The Damascus process according to claim 9, wherein: The following steps are also included: Metal materials are simultaneously filled in the through-hole opening and the trench. The metal material filled in the through-hole opening forms a through-hole, and the metal material filled in the trench forms a metal line.
11. The damascene process according to claim 10, wherein: The metal material constituting the via and the metal line includes copper.
12. The damascene process according to claim 10, wherein: The material of the bottom metal line includes copper.
13. The damascene process according to claim 9, wherein: The underlying interlayer film and the underlying metal line are formed on a semiconductor substrate in which a semiconductor device is formed.
14. The damascene process according to claim 13, wherein: The semiconductor substrate includes a silicon substrate.
15. The damascene process according to claim 10, wherein: The sub-step of simultaneously filling the through-hole opening and the trench with the metal material comprises: forming a barrier layer; forming a copper seed layer; The copper layer is formed by electroplating.