Multi-chip packaging structure and packaging method

Abstract

The invention provides a multi-chip packaging structure and a packaging method, and relates to the technical field of semiconductor packaging, the multi-chip packaging structure comprises a substrate, the substrate is provided with a groove, a first chip is inversely arranged in the groove, the first chip is provided with a TVC conversion plate, the TVC conversion plate is electrically connected with the first chip, the TVC conversion plate is provided with a conductive connecting piece, and the conductive connecting piece is electrically connected with the first chip. A second chip is inversely arranged on the TVC conversion plate, the second chip is electrically connected with the conductive connecting piece, a third chip is arranged on the second chip, the third chip is electrically connected with the conductive connecting piece, and the conductive connecting piece is electrically connected with the substrate. According to the invention, through the first chip and the second chip which are inversely arranged, the number of the conductive wires can be effectively reduced, so that the probability that the conductive wires are broken by a plastic package material during plastic package is reduced; through the arrangement of the groove, the thickness of the packaging structure can be effectively reduced, the impact strength of the plastic packaging material on the upper layer chip and the welding point due to gravity and flow inertia is reduced, the practicability is higher, and the yield is higher.

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