Stress release through hole structure and preparation method thereof

Abstract

The invention discloses a stress relief through hole structure which comprises a through hole formed in a substrate, the side wall of the through hole is a periodic curved surface arranged in the depth direction, and the curved surface is an arc-shaped curved surface sunken in the direction away from the center line of a deep hole; the side wall of the through hole is provided with a functional layer, and the remaining part in the through hole is filled with a conductive material. The invention also discloses a preparation method of the composition. According to the periodic curved surface through hole, the structural thermal stress can be reduced by reducing the constraint degree on the internal deformation of the material, the thermal mechanical stability of the through hole is improved, and on the other hand, the manufacturing difficulty of traditional etching of the vertical side wall is reduced.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductors, and particularly relates to a stress release via structure and a preparation method thereof. BACKGROUND

[0002] With Moore's Law approaching the physical limit, three-dimensional integrated circuit technology has become one of the core development directions of the semiconductor industry by vertically stacking chips to achieve high integration and performance improvement. Via technology, especially the commonly used through-silicon via (TSV), is a kind of vertical interconnection structure penetrating the substrate, which realizes the three-dimensional stacking interconnection of chips in three-dimensional integrated circuits (3D IC) through the cross-layer transmission of electrical signals or current. As a key structure for realizing interlayer interconnection in 3D IC, the reliability, electrical performance and thermal mechanical stability of the via directly determine the overall performance of the packaged device.

[0003] Via technology forms a via in the chip and fills it with conductive material to directly penetrate different chip layers to achieve efficient transmission of electrical signals, power and heat between multi-layer stacked chips. Traditional vias are usually cylindrical straight hole structures, which realize conductive channels through chemical vapor deposition (CVD), copper plating and other processes.

[0004] Deep hole etching usually adopts the Bosch process in deep reactive ion etching (DRIE). The rough sidewall surface formed during via etching has micron or nanometer level concave-convex structures, which on the one hand will become stress concentration points, leading to non-uniform nucleation during metal plating (such as copper deposition), and local area filling discontinuity. On the other hand, sharp protrusions or depressions will also cause uneven thickness of the insulating layer during deposition, and even uncoated areas. Non-uniform material deposition or filling may increase the probability of electron scattering, change the electric field distribution, and cause the current path to twist. At the same time, it will also cause the failure of the device, such as the defects of via surface protrusion, cracking and delamination, and filling cavity, which will damage the wafer and pose a potential risk to the electrical interconnection of the chip stacking structure.

[0005] In order to reduce the thermal stress caused by the roughness of the deep hole sidewall in the actual process, researchers continue to adjust the preparation process and parameters of the through-silicon via to form a deep hole with high surface flatness and small roughness. Correspondingly, the manufacturing process difficulty of deep hole etching is increased, the manufacturing process cycle is prolonged, and the manufacturing cost is also increased. In order to balance the electrical performance, mechanical reliability and process cost of the via, how to realize the miniaturization and integration of the device while ensuring the reliability of its performance has become a problem to be solved. SUMMARY

[0006] The present application provides a stress release via structure and a preparation method thereof to solve the problems in the prior art.

[0007] To achieve the above object, the technical scheme of the present application is as follows:

[0008] A stress release via-hole structure comprises a via-hole formed in a substrate, the sidewall of the via-hole is a periodic curved surface arranged along the depth direction, the curved surface is an arc-shaped curved surface concave in the direction away from the center line of the deep via-hole; a functional layer is arranged on the sidewall of the via-hole; the remaining part in the via-hole is filled with conductive material.

[0009] Optionally, the via-hole penetrates the substrate in the thickness direction of the substrate, the depth H is 5 μm-500 μm; the aspect ratio H / W of the via-hole is 1-50. The width W mentioned herein refers to the maximum width, i.e. the width of the maximum concave part of the curved surface.

[0010] Preferably, the aspect ratio H / W is 10-30, for example 30, 25, 20, 18, 16, 14, 12, 10, or a value between any two of the above; preferably, the depth H is 100 μm-300 μm, for example 300 μm, 240 μm, 200 μm, 180 μm, 150 μm, 120 μm, 100 μm, or a value between any two of the above.

[0011] Optionally, the chord length direction of the arc-shaped curved surface coincides with the depth direction of the via-hole, the chord length h is 1 μm-50 μm; the bow height direction coincides with the radial direction of the via-hole, the bow height L is 0.5 μm-25 μm; the tangent line of the arc-shaped end and the depth direction forms an angle α of 0°<α≤90°.

[0012] The chord length h is preferably 1 μm-20 μm, for example 20 μm, 15 μm, 10 μm, 8 μm, 6 μm, 3.5 μm, 3 μm, 2.5 μm, 2 μm, 1.5 μm, 1 μm, or a value between any two of the above; the bow height L is preferably 0.5 μm-10 μm, for example 10 μm, 8 μm, 6 μm, 4 μm, 3 μm, 2.5 μm, 2 μm, 1.5 μm, 1 μm, 0.5 μm, or a value between any two of the above; the angle α is preferably 30°-70°, for example 70°, 60°, 55°, 50°, 45°, 40°, 35°, 30°, or a value between any two of the above.

[0013] Optionally, the functional layer comprises a buffer layer, an insulating layer and a barrier layer arranged in sequence on the sidewall, the materials of the buffer layer and the insulating layer are different, the buffer layer can be used to form a stress release space on one hand, and can improve the deposition effect of the subsequent functional layer as a deposition interface of the subsequent functional layer on the other hand.

[0014] Optionally, the material of the buffer layer comprises silicon dioxide (SiO2), silicon nitride (Si x Ny ), polymethyl methacrylate (PMMA), polypropylene carbonate (PPC), polyimide (PI), benzocyclobutene (BCB), phenol formaldehyde resin composite, acrylic polymer, silicone-polyaniline copolymer, polysiloxane and porous material, and the thickness is 0.8 μm-5 μm.

[0015] Optionally, the buffer layer is an air gap layer filled with air or inert gas, and the thickness is 0.8 μm-5 μm.

[0016] Optionally, the material of the insulating layer is a stack of one or more of silicon dioxide (SiO2), silicon nitride (Si x N y ), polyimide (PI), aluminum oxide (Al2O3), hafnium dioxide (HfO2), silicone polymer, and the thickness is 100 nm-3000 nm; the material of the barrier layer is a stack of one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), ruthenium (Ru), cobalt (Co), and the thickness is 5 nm-100 nm.

[0017] Optionally, the material of the substrate includes at least one of silicon (Si), silicon dioxide (SiO2), silicon carbide (SiC), glass, ceramic and the like.

[0018] A preparation method of a stress release via hole structure, comprising the following steps:

[0019] 1) forming a deep hole in a substrate, the sidewall of the deep hole is a periodic curved surface arranged along the depth direction, and the curved surface is an arc-shaped curved surface concave in the direction away from the center line of the deep hole;

[0020] 2) forming a functional layer on the sidewall of the deep hole;

[0021] 3) filling the remaining part of the deep hole with a conductive material;

[0022] 4) thinning the back surface of the substrate to expose the bottom of the deep hole to form a via hole structure.

[0023] Optionally, the process of forming a deep hole on the substrate comprises:

[0024] a) gradually performing different etching cycles to etch a periodic curved surface;

[0025] b) passivating the surface of the periodic curved surface formed by etching;

[0026] c) repeating a) and b) to process the next periodic curved surface until the deep hole is formed.

[0027] Optionally, the substrate is a silicon-based material, the etching gas in step a) is sulfur hexafluoride, and the passivation gas in step b) is octafluorocyclobutane.

[0028] Optionally, forming the functional layer includes depositing a buffer layer on the sidewall of the deep hole, depositing an insulating layer on the buffer layer, and forming a barrier layer on the insulating layer.

[0029] After step 4), a step of removing the buffer layer to form an air gap is further included. Further, the air gap is filled with inert gas to provide more space to release thermal stress, while further preventing leakage of electrical signals.

[0030] Optionally, the preparation method of the buffer layer can be one or more of a combination of plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), electrochemical deposition (ECD), magnetron sputtering, evaporation, chemical grafting, spin coating, thermal curing, in-situ polymerization, and thermal imidization.

[0031] The preparation method of the insulating layer and the barrier layer is one or more of a combination of physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), spin coating, and spray coating.

[0032] The conductive material includes one or more of a combination of conductive metals (copper, tungsten, aluminum, etc.), or non-metallic conductive materials such as conductive polymers, carbon-based materials, conductive oxides or their composites, transition metal carbides or nitrides, metal MOF framework materials, heavily doped silicon materials, etc.; and the preparation method includes physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, electroless plating, nano-paste sintering, and printing, etc.

[0033] Optionally, after filling the conductive material, a step of annealing to eliminate stress, improve the conductivity and density of the via is further included.

[0034] Optionally, a step of performing chemical mechanical polishing (CMP) to remove excess conductive material on the surface and planarize the substrate surface is further included.

[0035] The buffer layer can serve as a stress release space on one hand, and can be selectively formed into an air gap to provide a stress release space on the other hand. Meanwhile, as a buffer layer, it can improve the deposition effect of subsequent functional layers; the insulating layer and the barrier layer are used to electrically isolate the substrate and the conductive material, and prevent metal atoms from penetrating to cause performance degradation or even failure of the packaged device.

[0036] The application range of the stress release via-hole structure includes 3D integrated circuits (3D IC) and advanced packaging, memory technology, MEMS and sensors, optoelectronic devices and photonic integration, power electronics and automotive electronics, radio frequency and microwave devices, biomedical and microsystems, etc.

[0037] The beneficial effects of the present application are:

[0038] (1) The manufacturing difficulty of vertical sidewalls is reduced: the roughness of the sidewalls formed by the Bosch process deep hole etching is enlarged to form a periodic curved surface, which can reduce the manufacturing difficulty of traditional etching vertical sidewalls on the one hand, and reduce the structural thermal stress by reducing the degree of constraint on the internal deformation of the material on the other hand, thereby increasing the thermal mechanical stability of the via.

[0039] (2) More space is provided to release thermal stress: a buffer layer is deposited inside the via, which can guarantee the subsequent deposition of high-quality functional layers on the one hand, and form a stress release space on the other hand, which can also be released thermally to form an air gap as needed to provide more space to release thermal stress, while further preventing the leakage of electrical signals.

[0040] Other features and beneficial effects of the present application will be described in the subsequent description, and some will become apparent from the description, or be understood through the implementation of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 The step flow chart of the manufacturing method of the stress release via structure of Example 1;

[0042] Figure 2 The process flow chart of the manufacturing method of the stress release via structure of Example 1;

[0043] Figure 3 The longitudinal sectional view of the periodic curved surface deep hole of Example 1;

[0044] Figure 4 The partial enlarged view in Figure 3 ;

[0045] Figure 5 The thermodynamic simulation stress distribution diagram of Example 1 (a) and Comparative Example 1 (b) under large temperature difference change;

[0046] Figure 6 The thermodynamic simulation stress distribution diagram of different stress release via structures of Example 2;

[0047] Figure 7 The maximum stress change diagram of different stress release via structures of Example 2;

[0048] Figure 8A flow chart of the method of fabricating the stress release via structure of Example 3;

[0049] Figure 9 A flow chart of the method of fabricating the stress release via structure of Example 3;

[0050] Figure 10 A longitudinal sectional view of the stress release via structure of Example 3;

[0051] Figure 11 A thermodynamic simulation stress distribution map of Example 3(a) and Comparative Example 3(b) under large temperature difference change. DETAILED DESCRIPTION

[0052] The present application will be further described by the following embodiments with reference to the drawings. The drawings of the present application are only schematic and are non-limiting according to the scope of the present application. The proportions in the figures do not correspond exactly to the proportions in reality since depending on the drawing the components described with reference thereto can have been minimized to fit within the figure. The relative dimensions of the individual components in the figures can therefore not be to scale. The definitions of up / down, back / front and / or side of a component as mentioned herein should therefore be treated as relative and not as absolute unless it is otherwise indicated and / or is readily apparent from the figures themselves. The individual features of the figures can of course be implemented in any of the possible hardware and / or software configurations, which will be readily apparent to persons skilled in the art. The same reference numerals in different figures represent identical or at least similar components.

[0053] Example 1

[0054] Please refer to Figure 1 and Figure 2 , the following specific description of the method of fabricating the stress release via structure of Example 1, for the sake of illustration, the figure with a via structure as an example, the actual can be according to the demand at the same time form multiple via structure.

[0055] Step (1), cleaning the silicon substrate 1 with a thickness of 500 μm, the method of cleaning the substrate is organic cleaning, first using acetone and isopropyl alcohol ultrasonic cleaning substrate, 10 minutes each time, then washed with deionized water, blow dry the substrate.

[0056] Step (2), depositing a layer of sacrificial layer 2 on the surface of the substrate 1, the material of the sacrificial layer 2 is silicon dioxide, formed by thermal oxidation method, the thickness is 1 μm ~ 3 μm.

[0057] Step (3), spin coating a layer of photoresist 3 on the sacrificial layer 2.

[0058] Step (4), the photoresist 3 is selectively exposed to define the position and size of the via, the material of the mask used for exposure is quartz substrate plated with chromium, and the exposure mode is projection type through the reduction lens.

[0059] Step (5), after developing photoresist 3, using the patterned photoresist as a mask, etching the patterned sacrificial layer 2, and then removing the photoresist; the developing solution is an organic solvent (such as propylene glycol methyl ether acetate), and the developing is performed using a spraying method. After developing, post-baking is required at 100-120°C to improve the etch resistance of the photoresist.

[0060] Step (6), using the patterned sacrificial layer 2 as a mask, a modified Bosch process is used to etch the periodic curved surface deep hole 11 on the substrate 1. First, different etching cycles are gradually performed to etch the required curved surface angle. After the formation of a periodic curved surface, the surface is passivated. Next, the above steps are repeated to process the next periodic curved surface structure. This is repeated until the deep hole is completed. After that, the etched periodic curved surface deep hole is cleaned to remove etching residues and ensure the cleanliness of the hole wall. For each curved surface:

[0061] 1) Etching stage. Sulfur hexafluoride (SF6) is used to generate fluorine radicals (F + ), which react with the substrate silicon to generate volatile SiF4 to etch a hole with a curved sidewall to a certain depth;

[0062] 2) Passivation stage. Switch to octafluorocyclobutane (C4F8) to deposit fluorocarbon polymer (passivation layer) on the hole wall and bottom to control the lateral etching depth.

[0063] Referring to Figure 3 and Figure 4 , the deep hole 11 formed has a periodic regular arrangement of curved surface structures along the depth direction. Each periodic curved surface unit is an arc-shaped curved surface 11a that is recessed in a direction away from the center line of the deep hole. The adjacent arc-shaped curved surfaces 11a are connected end to end. In this embodiment, the depth H of the deep hole is 100 μm. The width W (at the maximum width) is 5 μm, and the aspect ratio H / W is 20. The periodic curved surfaces are etched in sequence along the depth direction. The chord length direction of each arc-shaped curved surface 11a coincides with the depth direction of the deep hole 11, the chord length h (i.e. the height of one periodic curved surface) is 3.5 μm; the bow height direction coincides with the radial direction of the deep hole, the bow height L (i.e. the maximum lateral etching depth of one periodic curved surface) is 1 μm; the tangent line of the arc-shaped end and the depth direction forms an angle α of 60°. The regular periodic curved surface is formed by the modified Bosch process, which can reduce the manufacturing difficulty of traditional etching vertical sidewalls on the one hand, and can reduce the structural thermal stress by reducing the degree of constraint on the internal deformation of the material on the other hand.

[0064] Step (7), a layer of insulating layer 5 (functional layer 1) is deposited on the sidewall of the deep hole 11. The material of the insulating layer 5 is silicon dioxide, which is formed by plasma enhanced chemical vapor deposition, and the thickness is 100 nm.

[0065] Step (8), depositing a barrier layer 6 (functional layer 2) on the insulating layer 5, material is tantalum nitride, formed by atomic layer deposition method, thickness is 10 nm.

[0066] Step (9), filling the remaining space in the deep hole 11 with conductive metal 7, for example, using an electroplating process, first depositing a copper seed layer on the surface of the barrier layer 6 by chemical vapor deposition method, then electroplating copper. Then a heat treatment process is carried out to eliminate the lattice defects of electroplated copper, reduce the resistivity, release the thermal stress of the through silicon via, and at the same time promote the grain growth and improve the mechanical strength of the through silicon via. Among them:

[0067] 1) Pre-annealing. In a low temperature environment of 150-200℃, the processing time is 30-60 minutes, and the atmosphere is high-purity nitrogen (N2) or vacuum;

[0068] 2) Main annealing. In a high temperature of 300-450℃ (typical value 400℃) for 30-120 minutes, and in a reducing hydrogen (H2) atmosphere with a concentration of >90%;

[0069] 3) Gradient cooling. Slowly reduce the wafer to room temperature under nitrogen (N2) protection at a rate of ≤5℃ / min.

[0070] Step (10), grinding the surface of the substrate 1 after filling the conductive metal to improve the surface flatness, and the grinding method is chemical mechanical planarization grinding (CMP).

[0071] Step (11), bonding the temporary wafer 8 on the flat substrate surface.

[0072] Step (12), grinding the surface of the substrate (back of the deep hole) without temporary wafer bonding to expose the filled conductive metal 7, and the grinding method is chemical mechanical planarization grinding.

[0073] Step (13), removing the temporary wafer bonding of the substrate to obtain a conductive via structure.

[0074] The stress release via structure formed includes a via formed in the substrate, the sidewall of the via is a periodic curved surface arranged in the depth direction; the sidewall of the via is sequentially provided with an insulating layer and a barrier layer, and the remaining part in the via is filled with a conductive metal. The stress release via structure can provide more space for the via to release thermal stress and reduce the manufacturing difficulty of the vertical sidewall of the via.

[0075] Comparative Example 1

[0076] The difference between Comparative Example 1 and Example 1 is that it uses a via structure with vertical sidewalls, and the rest refers to Example 1.

[0077] Thermodynamic simulation test was carried out on the through-hole structure of Example 1 and Comparative Example 1, and the thermodynamic simulation stress distribution diagram under large temperature difference change is as follows Figure 5 It can be seen from the figure that the maximum stress of the stress release through-hole structure caused by large temperature difference change is 1052 MPa, which is located at the junction of SiO2 insulating layer and silicon substrate, compared with the maximum stress of 1551 MPa of the traditional through-hole structure, the two form a contrast to highlight the effect of stress release through-hole structure on reducing thermal stress.

[0078] Example 2

[0079] Compared with Example 1, the angle α of the tangent of the arc-shaped end of each curved surface unit and the depth direction and the length h of the chord are adjusted by changing the length, power and other parameters of the etching process, as well as the length ratio of it and the side wall protection process, wherein the range of angle α is 0°-90°, and the range of chord length h is 1 μm-4.5 μm, and a plurality of examples are set in this range, and the rest are referred to Example 1. Thermodynamic simulation test was carried out on the through-hole structure of each example, wherein:

[0080] The thermodynamic simulation stress distribution diagram of the through-hole structure with chord length h of 3.5 μm and angle α of 50° arc-shaped curved surface is as follows Figure 6 (a);

[0081] The thermodynamic simulation stress distribution diagram of the through-hole structure with chord length h of 3.5 μm and angle α of 40° arc-shaped curved surface is as follows Figure 6 (b);

[0082] The thermodynamic simulation stress distribution diagram of the through-hole structure with chord length h of 3.5 μm and angle α of 70° arc-shaped curved surface is as follows Figure 6 (c);

[0083] The thermodynamic simulation stress distribution diagram of the through-hole structure with chord length h of 3.5 μm and angle α of 80° arc-shaped curved surface is as follows Figure 6 (d);

[0084] The thermodynamic simulation stress distribution diagram of the through-hole structure with chord length h of 3 μm and angle α of 60° arc-shaped curved surface is as follows Figure 6 (e);

[0085] The thermodynamic simulation stress distribution diagram of the through-hole structure with chord length h of 2.5 μm and angle α of 60° arc-shaped curved surface is as follows Figure 6 (f);

[0086] The thermodynamic simulation stress distribution diagram of the through-hole structure with chord length h of 4 μm and angle α of 60° arc-shaped curved surface is as follows Figure 6 (g);

[0087] The stress distribution diagram corresponding to the thermal simulation of the through-hole structure with the arc surface having a chord length h of 4.5 μm and an included angle α of 60° is as shown in FIG. 3. Figure 6 (h).

[0088] The maximum stress change curves of the respective structures are as shown in FIGS. 2(a) and 2(b). Figure 7 As can be seen from the figures, the maximum stress gradually decreases with the increase of the included angle α (or the chord length h), and it can be seen that the through-hole structure with the arc surface can effectively reduce the thermal stress; the change trend is not obvious after 60°, and the included angle α is preferably in the range of 30° to 70° in consideration of the difficulty of processing; the change trend is not obvious after 2 μm, and the chord length h is preferably in the range of 2 μm to 3.5 μm in consideration of the difficulty of processing.

[0089] Example 3

[0090] Please refer to Figure 8 and Figure 9 , and the following will specifically describe the manufacturing method of the stress release through-hole structure of Example 3. For the convenience of description, one through-hole structure is taken as an example in the figures, and actually a plurality of through-hole structures can be formed at the same time according to the requirements.

[0091] Step (1), cleaning the silicon substrate 1 with a thickness of 500 μm, the method for cleaning the substrate is organic cleaning, first using acetone and isopropyl alcohol to ultrasonically clean the substrate for 10 minutes each time, then rinsing with deionized water, and blowing dry the substrate.

[0092] Step (2), depositing a layer of sacrificial layer 2 on the surface of the substrate 1, the material of the sacrificial layer 2 is silicon dioxide, which is formed by thermal oxidation, and the thickness is 1 μm to 3 μm.

[0093] Step (3), spin-coating a layer of photoresist 3 on the sacrificial layer 2.

[0094] Step (4), defining the position and size of the through-hole by selectively exposing the photoresist 3, the material of the mask plate used for exposure is quartz substrate plated with chromium, and the exposure mode is projection type through a reduction lens.

[0095] Step (5), after developing the photoresist 3, using the patterned photoresist as a shielding layer, etching the patterned sacrificial layer 2, and then removing the photoresist; the developing solution is an organic solvent (such as propylene glycol methyl ether acetate), and the developing is carried out by spraying method, and after developing, post-baking at 100°C to 120°C is needed to improve the etching resistance of the photoresist.

[0096] Step (6), using the patterned sacrificial layer 2 as a mask, a modified Bosch process is used to etch the periodic curved surface deep hole 11 on the substrate 1. First, different etching cycles are performed step by step to etch the required curved surface angle. After the formation of a periodic curved surface, the surface is passivated for protection. Then the above steps are repeated to process the next periodic curved surface structure. This process is repeated until the deep hole is completed. After that, the etched periodic curved surface deep hole is cleaned to remove etching residues and ensure the cleanliness of the hole wall. For each curved surface:

[0097] (1) Etching phase. Sulfur hexafluoride (SF6) is used to generate fluorine radicals (F + ), which react with the substrate silicon to generate volatile SiF4 to etch a hole with a curved sidewall to a certain depth;

[0098] (2) Passivation phase. Switch to octafluorocyclobutane (C4F8) to deposit fluorocarbon polymer (passivation layer) on the hole wall and bottom to control the lateral etching depth.

[0099] Referring to Figure 4 and Figure 5 , the deep hole 11 formed along the depth direction has a periodic and regular curved surface structure on the sidewall. Each periodic curved surface unit is an arc-shaped curved surface 11a that is recessed away from the center line of the deep hole. The adjacent arc-shaped curved surfaces 11a are connected end to end. In this embodiment, the depth H of the deep hole is 100 μm. The width W (at the maximum width) is 5 μm, and the aspect ratio H / W is 20. The periodic curved surface is etched sequentially downward along the depth direction. The chord length direction of each arc-shaped curved surface 11a coincides with the depth direction of the deep hole 11. The chord length h (i.e. the height of one periodic curved surface) is 3.5 μm. The bow height direction coincides with the radial direction of the deep hole. The bow height L (i.e. the maximum lateral etching depth of one periodic curved surface) is 1 μm. The tangent line of the arc-shaped end and the depth direction forms an angle α of 60°. The regular periodic curved surface is formed by the modified Bosch process. On the one hand, the process can reduce the manufacturing difficulty of traditional etching vertical sidewalls. On the other hand, the structure can reduce structural thermal stress by reducing the degree of constraint on internal material deformation.

[0100] Step (7), a buffer layer 4 is deposited on the sidewall of the periodic curved surface deep hole 11 to form a stress release space. The material of the buffer layer is polymethyl methacrylate, which is formed by spin coating, and the thickness is 1 μm. Polymethyl methacrylate forms a stress release space through its four mechanisms of low modulus flexible deformation, adjustable thermal expansion coefficient, high toughness and strong adhesion.

[0101] Step (8), an insulating layer 5 (functional layer 1) is deposited on the buffer layer. The material of the insulating layer 5 is silicon dioxide, which is formed by plasma enhanced chemical vapor deposition, and the thickness is 500 nm. The buffer layer covering the surface of the periodic curved surface deep hole can ensure the deposition of high-quality insulating layer.

[0102] Step (9), depositing a barrier layer 6 (functional layer 2) on the insulating layer 5, material is tantalum nitride, formed by atomic layer deposition method, thickness is 10 nm.

[0103] Step (10), filling the remaining space in the deep hole 11 with conductive metal 7, for example, using an electroplating process, first depositing a copper seed layer on the surface of the barrier layer 6 by chemical vapor deposition method, then electroplating copper. Then a heat treatment process is carried out to eliminate the lattice defects of electroplated copper, reduce the resistivity, release the thermal stress of the through silicon via, at the same time promote the grain growth, improve the mechanical strength of the through silicon via. Among them:

[0104] 1) Pre-annealing. In a low temperature environment of 150-200℃, the processing time is 30-60 minutes, and the atmosphere is high-purity nitrogen (N2) or vacuum;

[0105] 2) Main annealing. In a high temperature of 300-450℃ (typical value 400℃) for 30-120 minutes, and in a reducing hydrogen (H2) atmosphere with a concentration of >90%;

[0106] 3) Gradient cooling. Slowly reduce the wafer to room temperature under nitrogen (N2) protection at a rate of ≤5℃ / min.

[0107] Step (11), grinding the surface of the substrate 1 after filling the conductive metal to improve the surface flatness, the grinding method is chemical mechanical planarization grinding (CMP).

[0108] Step (12), bonding the temporary wafer 8 on the flat substrate surface.

[0109] Step (13), grinding the surface of the substrate (back surface of the deep hole) without temporary wafer bonding to expose the filled conductive metal 7, the grinding method is chemical mechanical planarization grinding.

[0110] Step (14), removing the temporary wafer bonding of the substrate to obtain a conductive via structure.

[0111] Step (15), selectively etching the buffer layer 4 deposited on the periodic curved surface sidewall as needed, the removal method is thermal release. After the removal of the buffer layer 4, an air gap is formed, which can provide free space for the radial thermal expansion of the filled conductive metal copper, thereby reducing the thermal stress caused by the thermal expansion of the conductive metal copper, and further forming a stress release space.

[0112] The stress release via structure formed is referred to Figure 10, including a through hole 11' formed in the substrate 1, the sidewall of the through hole 11' is a periodic curved surface 11a arranged along the depth direction; the sidewall of the through hole 11' is sequentially provided with a buffer layer 4, an insulating layer 5 and a barrier layer 6, and the remaining part in the through hole is filled with a conductive metal 7. Depositing a buffer layer in the through hole can guarantee the subsequent deposition of high-quality functional layers, and on the other hand, it can form a stress release space and provide more space for releasing thermal stress of the through hole.

[0113] Comparative Example 3

[0114] The difference between Comparative Example 3 and Example 3 is that the through hole structure of Comparative Example 3 does not use a polymethyl methacrylate buffer layer, and the rest refers to Example 3.

[0115] Thermodynamic simulation test was carried out on the through hole structure of Example 3 and Comparative Example 3, and the thermodynamic simulation stress distribution diagram under large temperature difference change is as follows Figure 11 It can be seen from the figure that the maximum stress of the stress release through hole structure of Example 3 caused by large temperature difference change is 904.6 MPa, compared with the maximum stress of the through hole structure of Comparative Example 3, which is 988.7 MPa, and the two are compared to highlight the effect of the buffer layer on reducing thermal stress.

[0116] The above examples are only used to further illustrate a stress release through hole structure and a preparation method thereof, but the present application is not limited to the examples, and any simple modification, equivalent change and modification according to the technical essence of the present application to the above examples all fall within the protection scope of the technical scheme of the present application.

Claims

1. A stress relief through-hole structure, characterized in that: It includes a through hole formed in the substrate, the side wall of the through hole is a periodic curved surface arranged along the depth direction, and the curved surface is an arc-shaped curved surface concave in the direction away from the center line of the deep hole; a functional layer is provided on the side wall of the through hole, and the remaining part of the through hole is filled with conductive material.

2. The stress relief through-hole structure according to claim 1, wherein: The through hole penetrates the substrate in the thickness direction of the substrate, and has a depth H of 5 μm to 500 μm; and an aspect ratio H / W of the through hole is 1 to 50.

3. The stress relief through-hole structure according to claim 1, wherein: The chord length direction of the arc surface coincides with the depth direction of the through hole, and the chord length h is 1μm~50μm; the bow height direction coincides with the radial direction of the through hole, and the bow height L is 0.5μm~25μm; the angle α between the tangent of the arc end and the depth direction is 0°<α≤90°.

4. The stress relief through-hole structure according to claim 1, wherein: The functional layer includes a buffer layer, an insulating layer and a barrier layer sequentially arranged on the sidewall. The buffer layer and the insulating layer are made of different materials. The buffer layer is used to form a stress release space and a subsequent functional layer deposition interface.

5. The stress relief through-hole structure according to claim 4, wherein: The material of the buffer layer includes a stack of one or more of silicon dioxide, silicon nitride, polymethyl methacrylate, polymethyl ethylene carbonate, polyimide, styrene-cyclobutene, phenolic resin composite material, acrylic polymer, organosilicon-polyaniline copolymer, polysiloxane and porous material, with a thickness of 0.8μm to 5μm.

6. The stress relief through-hole structure according to claim 4, wherein: The buffer layer is an air gap layer filled with air or inert gas and has a thickness of 0.8 μm to 5 μm.

7. The stress relief through-hole structure according to claim 4, wherein: The material of the insulating layer is a stack of one or more of silicon dioxide, silicon nitride, polyimide, aluminum oxide, hafnium dioxide, and organic silicon polymer, with a thickness of 100nm to 3000nm; the material of the barrier layer is a stack of one or more of titanium nitride, tantalum nitride, tantalum, titanium, ruthenium, and cobalt, with a thickness of 5nm to 100nm.

8. A method for preparing a stress relief through-hole structure, characterized in that: The following steps are involved: 1) forming a deep hole in a substrate, wherein the sidewall of the deep hole is a periodic curved surface arranged along the depth direction, and the curved surface is an arc-shaped curved surface concave in a direction away from the center line of the deep hole; 2) forming a functional layer on the sidewall of the deep hole; 3) Fill the remaining portion of the deep hole with conductive material; 4) The back side of the substrate is thinned until the bottom of the deep hole is exposed to form a through-hole structure.

9. The method for preparing a stress relief through-hole structure according to claim 8, wherein: The substrate is a laminate of one or more of silicon, silicon dioxide, silicon carbide, glass, ceramic, etc.; the process of forming the deep hole on the substrate includes: 1) gradually performing different etching cycles to etch a periodic surface; 2) passivation protection of the periodic curved surface formed by etching; 3) Repeat 1) and 2) to process the next periodic curved surface until the deep hole is formed.

10. The method for preparing a stress relief through-hole structure according to claim 8, wherein: The forming of the functional layer in step 2) includes: depositing a buffer layer on the sidewall of the deep hole, depositing an insulating layer on the buffer layer, and forming a barrier layer on the insulating layer; after step 4), the buffer layer can be selectively removed.

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