A static converter remote control method, device and system

Abstract

The application relates to the technical field of digital information transmission, in particular to a static converter remote control method, equipment and system, the method comprising the following steps: determining a one-way internal processing time delay based on the time interval between the reception of an analog signal and the generation of an empty PWM instruction in each PTP bidirectional handshake process of each converter, determining a corrected clock deviation of each PTP bidirectional handshake of each converter for clock deviation correction, driving a digital phase-locked loop to align the clock of each converter with that of a central control unit; and correcting the residual phase deviation of each converter based on the difference between the residual phase deviations between each converter and neighbors. The application considers the communication time delay of remote control in a distributed scenario and the device heterogeneity between static converters, solves the problem of control lag, and enhances the adaptability of static converter remote control in a large-scale cluster.

Description

Technical Field

[0001] This application relates to the field of digital information transmission technology, specifically to a method, device, and system for remote control of a static converter. Background Technology

[0002] A static converter is an electronic device without rotating parts used to convert alternating current (AC) to direct current (DC) or vice versa, enabling energy conversion and adaptation between different power systems. It uses electronic components such as thyristors, diodes, and power transistors to control and convert electrical energy. In AC transmission systems, the static converter converts AC to DC and stores charge in capacitors; when needed, it converts the DC back to AC for output. Its basic principle is to utilize the on and off states of switching elements to achieve the transmission and conversion of electrical energy.

[0003] In distributed scenarios involving grid-connected renewable energy sources or energy storage clusters, multiple static converters (SPCs) are needed to convert DC to AC power. Traditional methods for remotely controlling multiple SPCs typically employ wired industrial buses and fixed communication protocols, with a central controller collecting the status of each converter and issuing unified control commands for parameter adjustment. However, these traditional methods fail to consider the communication latency and heterogeneity among SPCs in distributed scenarios, leading to clock asynchrony between master and slave controllers and resulting in delayed control response. This makes them unsuitable for remote control of SPCs in large-scale clusters. Summary of the Invention

[0004] In a first aspect, embodiments of this application provide a remote control method for a static converter, the method comprising the following steps:

[0005] During each PTP bidirectional handshake between the central control unit and each converter, the uplink and downlink delays between the central control unit and each converter are recorded.

[0006] Based on the changes in uplink and downlink delays during a preset number of PTP bidirectional handshakes before each PTP bidirectional handshake between the central control unit and each converter, a directional adjustment factor is constructed for each converter during each PTP bidirectional handshake to determine the clock deviation for each converter during each PTP bidirectional handshake. Based on the time interval between each converter receiving an analog signal and generating an empty PWM command during each PTP bidirectional handshake, the single-pass internal processing delay for each converter during each PTP bidirectional handshake is determined to correct the clock deviation and determine the corrected clock deviation for each converter during each PTP bidirectional handshake. Based on the corrected clock deviation, a digital phase-locked loop is driven to align the clock of each converter with that of the central control unit.

[0007] After each converter is aligned with the central control unit, the residual phase deviation of each converter is obtained. Based on the difference in residual phase deviation between each converter and its neighbor, the residual phase deviation of each converter is corrected to adjust the phase of each converter.

[0008] Preferably, the method for determining the directional adjustment factor for each converter during each PTP bidirectional handshake is as follows:

[0009] The ratio of the uplink delay to the downlink delay during each PTP bidirectional handshake between the central control unit and each converter is denoted as the delay factor.

[0010] The time delay factor of a preset number of bidirectional handshake processes before each PTP bidirectional handshake between the central control unit and each converter is used as the input of the sliding filter algorithm, and the output predicted value is used as the directional adjustment factor for each PTP bidirectional handshake of each converter.

[0011] Preferably, the expression for the clock offset during each PTP bidirectional handshake of each converter is: In the formula, This represents the clock deviation during the k-th PTP bidirectional handshake of the i-th converter. , These represent the uplink and downlink delays between the central control unit and the i-th converter during the k-th PTP bidirectional handshake process, respectively. This represents the directional adjustment factor of the i-th converter during the k-th bidirectional handshake.

[0012] Preferably, the single-pass internal processing delay of each converter in each PTP bidirectional handshake is half the time interval between the receiving of the analog signal and the generation of the empty PWM command during each PTP bidirectional handshake.

[0013] Preferably, the expression for the corrected clock offset for each PTP bidirectional handshake of each converter is: In the formula, , Let $\mathbf{i}$ and $\mathbf{i}$ represent the corrected clock offset and clock offset, respectively, for the $k$-th PTP bidirectional handshake of the $i$-th converter. This represents the single-pass internal processing delay of the k-th PTP bidirectional handshake of the i-th converter.

[0014] Preferably, the driving digital phase-locked loop aligns the clock of each converter with that of the central control unit, including:

[0015] The corrected clock offset for each PTP bidirectional handshake of each converter is written into the digital phase-locked loop, which drives the digital phase-locked loop to align the clock of each converter with that of the central control unit.

[0016] Preferably, the residual phase deviation of each converter is the deviation between the local clock of each converter and the PTPGrandmaster time axis.

[0017] Preferably, the correction of the residual phase deviation for each converter includes:

[0018] Residual phase deviation correction value of the i-th converter The expression is: In the formula, This represents the residual phase deviation of the i-th converter; This represents the residual phase deviation of the nth neighbor of the i-th converter; This represents the number of all neighbors of the i-th converter; This indicates the preset convergence step size factor.

[0019] Secondly, embodiments of this application provide a remote control device for a static converter, wherein the device stores a computer program, and when the computer program is executed by a processor, it implements a remote control method for a static converter as described in any of the above claims.

[0020] Thirdly, embodiments of this application also provide a remote control system for a static converter, including a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, it implements any one of the above-described methods for remote control of a static converter.

[0021] As can be seen from the above embodiments, the remote control method for a static converter provided in this application has at least the following beneficial effects:

[0022] This application effectively compensates for synchronization errors caused by network asymmetry by constructing a directional adjustment factor based on historical bidirectional handshake delays and combining it with a sliding filter algorithm for prediction optimization. Simultaneously, it improves the accuracy of clock deviation by measuring and correcting the internal processing delay of the converter online. Furthermore, it uses the corrected clock deviation to drive a digital phase-locked loop, achieving high-precision clock synchronization between the converter and the central control unit, which has the advantages of strong robustness, good real-time performance, and applicability to large-scale clusters. Furthermore, this application uses a distributed consensus algorithm to converge the residual phase deviations of each converter within the cluster to global consistency, achieving synchronous frequency and phase in a large-scale static converter cluster, effectively suppressing control lag, improving the robustness and control accuracy of the static converter control system, and enhancing the adaptability of remote control of static converters in large-scale clusters. Attached Figure Description

[0023] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A flowchart illustrating the steps of a remote control method for a static converter provided in one embodiment of this application;

[0025] Figure 2 This is a schematic diagram of a corrected clock deviation extraction process provided in one embodiment of this application. Detailed Implementation

[0026] To further illustrate the technical means and effects adopted by this application to achieve the intended inventive purpose, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of a remote control method, device, and system for a static converter according to this application. In the following description, different "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics in one or more embodiments can be combined in any suitable form.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0028] The following description, in conjunction with the accompanying drawings, details a specific scheme for a remote control method, device, and system for a static converter provided in this application.

[0029] Please see Figure 1 The diagram illustrates a flowchart of a remote control method for a static converter according to an embodiment of this application. The method includes the following steps:

[0030] S1: During each PTP bidirectional handshake between the central control unit and each converter, record the uplink and downlink delays between the central control unit and each converter.

[0031] In this embodiment, the remote control device for the static converter includes:

[0032] Grandmaster Clock: Deployed in the central control unit, it provides a reference clock for GPS synchronization.

[0033] Boundary Clock Module: Deployed in the remote control unit, it integrates the IEEE 1588 PTP protocol stack and hardware timestamp chip to achieve time synchronization with the master clock.

[0034] Voltage monitoring module: Includes ADC sampling channel and filter calculation unit, which collects DC bus voltage in real time and calculates the relative rate of change, with a sampling frequency of 50kHz;

[0035] Clock correction module: Includes a digital phase-locked loop (DPLL) for adjusting the local clock phase and frequency.

[0036] TSN scheduling module: Issues gating tables in the TSN switch to ensure that traffic does not conflict.

[0037] The remote control system includes:

[0038] Central control unit: also known as the main controller, is equipped with dual Grandmaster clocks, which automatically switch through the BMCA algorithm and serve as the system's time base.

[0039] Remote control unit: also known as a slave controller, deployed at each static converter node for local clock correction, voltage monitoring and control command execution.

[0040] Multi-level TSN switching network: Supports IEEE 802.1AS synchronization for distributing the time base of the master controller; supports 802.1Qbv gated tables for converters to broadcast to their neighbors.

[0041] In this embodiment, the master controller and slave controller exchange timestamps bidirectionally via the PTP protocol to calculate the bidirectional latency of network transmission, thereby eliminating the impact of network latency on time synchronization. The traditional PTP protocol usually assumes that the downlink latency from the master controller and the uplink latency from the slave controller to the master controller are the same. However, due to the diversity of communication links between the master controller and the slave controller, the uplink and downlink latency are usually different. If calculated directly, the asymmetrical communication latency may be mistakenly identified as clock skew, resulting in inaccurate clock synchronization.

[0042] This embodiment is based on the boundary clock behavior in the PTP protocol. By exchanging PTP messages between the master controller and the slave controller and recording the sending and receiving times of the messages, and taking into account the asymmetry of uplink and downlink delays in the communication network, the initial clock offset between the master and slave clocks is calculated. This eliminates the difference caused by the asymmetry of uplink and downlink delays in the network communication link between the master controller and the slave controller, and thus accurately calculates the initial deviation between the master and slave clocks, providing a basis for subsequent clock synchronization.

[0043] The following timestamps are recorded during each PTP bidirectional handshake between the central control unit and each converter:

[0044] The timestamp of the PTP Sync message sent by the main controller, i.e., the central control unit, to the slave controller;

[0045] : The timestamp of the PTP Sync message received from the controller, i.e., the converter;

[0046] : The timestamp of the Delay_Req message sent by the converter to the central control unit;

[0047] : The timestamp at which the central control unit receives the Delay_Req message.

[0048] Considering only network latency, uplink latency downlink latency .

[0049] S2: Based on the changes in uplink and downlink delays during a preset number of PTP bidirectional handshakes before each PTP bidirectional handshake between the central control unit and each converter, a directional adjustment factor is constructed for each converter during each PTP bidirectional handshake to determine the clock deviation for each converter during each PTP bidirectional handshake; based on the time interval between each converter receiving the analog signal and generating the empty PWM command during each PTP bidirectional handshake, the single-pass internal processing delay of each converter during each PTP bidirectional handshake is determined to correct the clock deviation and determine the corrected clock deviation for each converter during each PTP bidirectional handshake; based on the corrected clock deviation, a digital phase-locked loop is driven to align the clock of each converter with that of the central control unit.

[0050] To address the synchronization error caused by asymmetric uplink and downlink delays in PTP clock synchronization, this embodiment constructs a directional adjustment factor for each converter during each PTP bidirectional handshake based on the changes in uplink and downlink delays during a preset number of PTP bidirectional handshakes prior to each PTP bidirectional handshake between the central control unit and each converter. Specifically:

[0051] In this embodiment, the ratio of uplink delay to downlink delay in each PTP bidirectional handshake process between the central control unit and each converter is denoted as the delay factor.

[0052] The delay factor of a preset number of bidirectional handshakes before each PTP bidirectional handshake between the central control unit and each converter is used as the input of the sliding filter algorithm. In this embodiment, the sliding coefficient is set to 0.2. In order to avoid the delay factor from being abnormal due to excessive network fluctuations, its value is limited to between 0.5 and 1.5. If it is outside the range, the delay factor of the previous PTP bidirectional handshake is used. Finally, the predicted value is output and used as the directional adjustment factor for each PTP bidirectional handshake of each converter.

[0053] It should be noted that the preset quantity is set manually. In this embodiment, the preset quantity is 60. In actual application, as other implementation methods, implementers can also set it according to specific circumstances. This embodiment does not impose any special restrictions.

[0054] It should be noted that there are many commonly used sliding filter algorithms. This embodiment uses the sliding mean filter algorithm. In practical applications, implementers may also use other sliding filter algorithms depending on the specific circumstances. This embodiment does not impose any special restrictions on the selection of sliding filter algorithms.

[0055] The moving average filtering algorithm is a well-known technique, and the specific process of using it to smoothly predict the time delay factor will not be elaborated here.

[0056] Furthermore, this embodiment determines the clock offset for each PTP bidirectional handshake of each converter based on the directional adjustment factor during each PTP bidirectional handshake, specifically as follows:

[0057] In this embodiment, the clock deviation during the k-th PTP bidirectional handshake of the i-th converter is... The expression is: In the formula, , These represent the uplink and downlink delays between the central control unit and the i-th converter during the k-th PTP bidirectional handshake process, respectively. This represents the directional adjustment factor of the i-th converter during the k-th bidirectional handshake.

[0058] Thus, based on the PTP clock synchronization protocol and the directional adjustment factor, the clock deviation of each converter relative to the central control unit during each bidirectional handshake was obtained.

[0059] However, traditional methods generally only consider network latency and do not take into account the processing latency inside the static converter, which leads to inaccurate latency calculation. After receiving the control command issued by the main controller, the static converter first samples the DC bus voltage through the voltage monitoring module using an ADC to obtain the relative rate of change. Then, it sends the sample to the DSP processor core to calculate the PWM duty cycle and writes the result to the PWM register to finally obtain the power pulse. Therefore, the processing latency inside the converter includes three parts: ADC sampling latency, DSP calculation latency, and PWM update latency.

[0060] Because static converters exhibit device-specific characteristics, i.e., batch differences, variations in component tolerances and PCB trace lengths can lead to differences in their internal processing latency. In large-scale clusters, it is difficult to calibrate the processing latency of each converter. Furthermore, changes in the operating environment, such as fluctuations in temperature and voltage, can also affect the internal processing latency of the converter during actual operation. Therefore, it is necessary to perform online measurement of the processing latency of each static converter.

[0061] In step S1, It can represent the software layer latency, that is, the time from the PTP Sync message arriving at the Media Access Control (MAC) layer to the time from the Delay_Req message being sent from the application layer. It includes the software time spent on Sync message parsing, protocol stack processing, and Delay_Req message encapsulation. However, this latency only reflects the processing time of the PTP message in the protocol stack and is unrelated to the power control of the converter. Therefore, it cannot represent the internal processing latency of the static converter.

[0062] This embodiment constructs a loopback path locally in each static converter to measure its internal processing latency online: during the intervals between processing tasks, the ADC is triggered to sample the bus voltage and record a timestamp. The DSP generates an empty PWM instruction, i.e., a zero duty cycle test frame with a 0% duty cycle. After sampling, it is executed according to the above process to obtain the zero duty cycle gate drive edge, i.e., no power pulse is generated. Then, the gate flip edge is sampled again to obtain the time when the PWM instruction takes effect, and the timestamp is recorded. Calculate the round-trip time delay between the time each converter receives the analog signal and the time between the generation of the empty PWM command during each PTP bidirectional handshake process. The time interval between receiving the analog signal and generating the empty PWM command during each PTP bidirectional handshake process for each converter is taken as the single-pass internal processing delay, i.e., the single-pass internal processing delay. The expression is: Because each sampling in this process reuses a physical link, the round-trip time of the task can be the same. Finally, after being updated by the same sliding filter in step one, it is used for clock compensation.

[0063] Since the zero duty cycle test frame does not drive the power stage, the bus current and grid-connected power remain unchanged. Moreover, the loop path uses the internal task idle interval of the static converter to measure the time delay, which neither occupies the bandwidth of the real-time control loop nor changes the output duty cycle of the PWM. Therefore, it will not affect the local control of the static converter.

[0064] Therefore, it is necessary to subtract the internal processing delay of the static converter from the master-slave clock skew to obtain the final corrected clock skew. That is, in this embodiment, the corrected clock skew for each PTP bidirectional handshake is determined based on the one-way internal processing delay of each converter for each PTP bidirectional handshake. Specifically:

[0065] In this embodiment, the corrected clock offset for the k-th PTP bidirectional handshake of the i-th converter The expression is: In the formula, Let $\mathbf{i}$ and $\mathbf{i}$ represent the corrected clock offset and clock offset, respectively, for the $k$-th PTP bidirectional handshake of the $i$-th converter. This represents the single-pass internal processing delay of the k-th PTP bidirectional handshake of the i-th converter.

[0066] Preferably, the schematic diagram of the clock deviation extraction process provided in this embodiment is as follows: Figure 2 As shown.

[0067] Furthermore, based on the aforementioned clock skew correction, this embodiment drives a digital phase-locked loop to align the clock of each converter with that of the central control unit. Specifically:

[0068] In this embodiment, the corrected clock deviation of each PTP bidirectional handshake for each converter is written into the digital phase-locked loop. If the corrected clock deviation of the i-th converter in the k-th PTP bidirectional handshake is... This indicates that the converter's clock is lagging behind the central control unit's master clock, and the digital phase-locked loop needs to reduce the local crystal oscillator's frequency division ratio; if the correction clock deviation of the i-th converter's k-th PTP bidirectional handshake... If the clock speed of the converter is faster than the master clock of the central control unit, the digital phase-locked loop needs to increase the local crystal oscillator division ratio; if the clock deviation of the k-th PTP bidirectional handshake of the i-th converter is corrected... If the clock is synchronized with the main clock of the central control unit, then the digital phase-locked loop does not need to adjust the local crystal oscillator frequency division ratio.

[0069] The process of driving the digital phase-locked loop to align the clock of each converter with that of the central control unit is a well-known technology and will not be described in detail here.

[0070] Subsequently, each time the converter receives a PTP Sync message, the phase loop calculates the instantaneous phase error and outputs a phase correction value using the PI controller to correct the phase. Using the interval between two PTP Sync message arrivals as the period, the frequency loop uses a local counter to calculate the frequency deviation between the local crystal oscillator and the master clock, and outputs a frequency correction value using the PI controller to correct the frequency. When the phase error for three consecutive Sync cycles is less than or equal to 20ns, and the frequency error for 30 seconds is less than 0.1ppm, master-slave clock synchronization is considered complete.

[0071] Thus, this embodiment effectively compensates for the synchronization error caused by network asymmetry by constructing a directional adjustment factor based on historical bidirectional handshake delays and combining it with a sliding filter algorithm to optimize prediction. At the same time, by measuring and correcting the internal processing delay of the converter online, the accuracy of clock deviation is further improved. Finally, the corrected clock deviation is used to drive the digital phase-locked loop, achieving high-precision clock synchronization between the converter and the central control unit. This approach has the advantages of strong robustness, good real-time performance, and suitability for large-scale clusters.

[0072] S3: After each converter is aligned with the central control unit, the residual phase deviation of each converter is obtained. Based on the difference in residual phase deviation between each converter and its neighbor, the residual phase deviation of each converter is corrected to adjust the phase of each converter.

[0073] The above steps solve the clock synchronization problem between the master controller and a slave controller. However, the other static converters in the cluster operate independently, and residual errors may still exist between them. These residual errors can vector-superimpose, causing resonance and resulting in DC bus voltage oscillation. Therefore, after compensating for network and internal processing delays between the master and slave controllers, it is also necessary to eliminate residual errors between the individual converters in the cluster to ensure clock synchronization of the entire cluster at the same frequency and in phase.

[0074] This embodiment uses a distributed consensus algorithm. Each converter only needs to exchange phase deviations with its local neighbors discovered by the TSN layer 2 topology. Through weighted average iterative convergence, the phase deviations of the static converters in the cluster converge to the same global average value, achieving synchronous frequency and phase.

[0075] Each converter periodically sends LLDP messages through the TSN port, automatically collects the MAC address and link delay of one-hop neighbors according to the protocol, generates a neighbor table, and removes a neighbor from the neighbor table when the neighbor's response times out for three cycles.

[0076] The method for obtaining the neighbor table is a well-known technique, and its specific acquisition process will not be elaborated here. The attribute of the neighbor is also a converter.

[0077] Furthermore, in this embodiment, after each converter is aligned with the central control unit, the residual phase deviation of each converter is obtained. Based on the difference in residual phase deviation between each converter and its neighbor, the residual phase deviation of each converter is corrected to adjust the phase of each converter. Specifically:

[0078] In this embodiment, the deviation between the local clock of each converter and the PTP Grandmaster time axis is used as the residual phase deviation of each converter. The local clock and the PTP Grandmaster time axis are well-known technologies and will not be described in detail here.

[0079] Furthermore, based on the difference in residual phase deviation between each converter and its neighbor, the residual phase deviation of each converter is corrected to adjust the phase of each converter. Specifically:

[0080] In this embodiment, the residual phase deviation correction value of the i-th converter The expression is: In the formula, This represents the residual phase deviation of the i-th converter; This represents the residual phase deviation of the nth neighbor of the i-th converter; This represents the number of all neighbors of the i-th converter; This indicates the preset convergence step size factor.

[0081] It should be noted that the preset convergence step size factor is set manually. In this embodiment, the preset convergence step size factor is 0.1. In actual application, the implementer can also set it according to the specific situation. This embodiment does not impose any special restrictions. It should be noted that the value range of the convergence step size factor is generally 0.05~0.2. The larger the number of neighbors, the larger the value.

[0082] Furthermore, in this embodiment, the residual phase deviation of each converter is written into the digital phase-locked loop, which drives the digital phase-locked loop to correct the phase of each converter, so that the phase of each converter is synchronized with the phase of the central control unit.

[0083] The process of using a digital phase-locked loop for phase correction is a well-known technique and will not be described in detail here.

[0084] It should be noted that PTP clock synchronization technology is a well-known technology, and the protocol messages involved are all publicly known content, so they will not be listed and elaborated on one by one.

[0085] Thus, this embodiment compensates for the asymmetry of uplink and downlink delays by constructing a directional adjustment factor, corrects clock deviations by combining online measurement of the converter's internal processing delay, and uses a digital phase-locked loop to achieve high-precision alignment of master and slave clocks. Subsequently, a distributed consensus algorithm is used to converge the residual phase deviations of each converter in the cluster to global consistency, ultimately achieving synchronous operation of a large-scale static converter cluster with the same frequency and phase. This effectively suppresses control lag and voltage oscillations, improves the robustness and control accuracy of the static converter control system, and enhances the adaptability of remote control of static converters in large-scale clusters.

[0086] Based on the same inventive concept as the above method, this application embodiment also provides a static converter remote control device, wherein the device stores a computer program, and when the computer program is executed by a processor, it implements a static converter remote control method as described above.

[0087] Based on the same inventive concept as the above methods, this application also provides a remote control system for a static converter, including a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, it implements the steps of any one of the above-described remote control methods for a static converter.

[0088] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, specific embodiments of this specification have been described above. Additionally, the processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired results. In some implementations, multitasking and parallel processing are possible or may be advantageous.

[0089] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0090] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A method of remotely controlling a static converter, characterized by, The method comprises the following steps: During each PTP bidirectional handshake process between the central control unit and each converter, the uplink and downlink time delays between the central control unit and each converter are recorded; Based on the changes of the uplink and downlink time delays in a preset number of PTP bidirectional handshake processes before each PTP bidirectional handshake process between the central control unit and each converter, a directional adjustment factor for each PTP bidirectional handshake process of each converter is constructed to determine the clock bias of each PTP bidirectional handshake process of each converter; based on the time interval between the reception of an analog signal and the generation of an empty PWM instruction during each PTP bidirectional handshake process of each converter, a one-way internal processing time delay of each PTP bidirectional handshake process of each converter is determined to correct the clock bias and determine the corrected clock bias of each PTP bidirectional handshake process of each converter; based on the corrected clock bias, a digital phase-locked loop is driven to align the clock of each converter with that of the central control unit; After each converter is aligned with the central control unit, the residual phase bias of each converter is obtained, and the residual phase bias of each converter is corrected based on the difference between the residual phase biases between each converter and its neighbors to adjust the phase of each converter.

2. The method of claim 1, wherein the remote control of the static converter is performed by a remote control device. The determination method of the directional adjustment factor for each PTP bidirectional handshake process of each converter comprises: The ratio of the uplink time delay to the downlink time delay during each PTP bidirectional handshake process between the central control unit and each converter is denoted as a time delay factor; The time delay factors of a preset number of PTP bidirectional handshake processes before each PTP bidirectional handshake process between the central control unit and each converter are taken as the input of a sliding filter algorithm, and the predicted value of the output is taken as the directional adjustment factor for each PTP bidirectional handshake process of each converter.

3. The method of claim 1, wherein the remote control of the static converter is performed by a remote control device. The expression of the clock bias of each converter at each PTP bidirectional handshake is: ; wherein, represents the clock bias of the i-th converter at the k-th PTP bidirectional handshake; , respectively represent the uplink and downlink time delays of the central control unit and the i-th converter in the k-th PTP bidirectional handshake process; represents the directional adjustment factor of the i-th converter at the k-th bidirectional handshake.

4. The method of claim 1, wherein the remote control of the static converter is performed by a remote control device. The one-way internal processing time delay of each PTP bidirectional handshake process of each converter is half of the time interval between the reception of an analog signal and the generation of an empty PWM instruction during each PTP bidirectional handshake process of each converter.

5. The method of claim 1, wherein the remote control of the static converter is performed by a remote control device. The expression of the modified clock deviation of each PTP two-way handshake of each converter is: ; in the formula, , respectively represent the modified clock deviation and the clock deviation of the kth PTP two-way handshake of the ith converter; represent the one-way internal processing time delay of the kth PTP two-way handshake of the ith converter.

6. The method of claim 1, wherein the remote control of the static converter is performed by a remote control device. The driving of the digital phase-locked loop to align the clock of each converter with that of the central control unit comprises: The corrected clock bias of each PTP bidirectional handshake process of each converter is written into the digital phase-locked loop, and the digital phase-locked loop is driven to align the clock of each converter with that of the central control unit.

7. The method of claim 1, wherein the remote control of the static converter is performed by a remote control device. The residual phase bias of each converter is the deviation between the local clock of each converter and the PTP Grandmaster time axis.

8. The method of claim 1, wherein the static converter is a static frequency converter. The correction of the residual phase bias of each converter comprises: Residual phase deviation correction value of the i-th converter The expression is: ; in which, represents the residual phase deviation of the i-th converter; represents the residual phase deviation of the n-th neighbor of the i-th converter; represents the number of all neighbors of the i-th converter; represents a preset convergence step factor.

9. A static power converter remote control device, in which a computer program is stored, characterized in that, The computer program is executed by the processor to implement the static converter remote control method according to any one of claims 1-8.

10. A static converter remote control system comprising a memory, a processor and a computer program stored in the memory and running on the processor, characterized in that The processor executes the computer program to implement the steps of the static converter remote control method according to any one of claims 1-8.

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