An output adjustable reference voltage source integrated circuit

Abstract

The application provides an output-adjustable reference voltage source integrated circuit, which comprises a substrate control voltage circuit and an adjustable voltage output circuit; the substrate control voltage circuit generates a variable bias voltage and outputs the variable bias voltage to the adjustable voltage output circuit to change a substrate voltage of a related MOS transistor; and the MOS transistor in the adjustable voltage output circuit works in a sub-threshold region and generates different reference voltages based on the variable substrate voltage of the MOS transistor without changing a system circuit structure and a MOS transistor size, so as to meet the reference voltage requirements of different modules in the same system.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to an integrated circuit with an adjustable output reference voltage source. Background Technology

[0002] In integrated circuit systems, bandgap voltage references are commonly used. However, bandgap voltage reference circuits require high operating voltages and are not suitable for low-power, low-operating-voltage integrated circuit systems. Furthermore, even noise from low-operating-voltage power supplies can significantly impact the accuracy of the reference voltage output. It is also important to note that large integrated circuit systems typically include multiple different voltage references to meet the system's needs for various reference standards, greatly increasing the power consumption, complexity, and design difficulty of the integrated circuit system. Summary of the Invention

[0003] The problem solved by this invention is to propose an integrated circuit with an adjustable output reference voltage source. Based on a MOS transistor operating in the subthreshold region, it generates an adjustable MOS transistor substrate voltage to produce different reference voltages without changing the system circuit structure and MOS transistor size, thereby meeting the reference voltage requirements of different modules in the same system, simplifying the circuit structure and reducing system power consumption.

[0004] To address the aforementioned problems, the present invention provides an integrated circuit for an adjustable reference voltage source, comprising a substrate control voltage circuit and an adjustable voltage output circuit.

[0005] The substrate control voltage circuit is connected to the adjustable voltage output circuit. The substrate control voltage circuit receives a control signal, generates a variable bias voltage, and outputs it to the substrate of the corresponding MOSFET in the adjustable voltage output circuit, forming the substrate voltage of that MOSFET. Based on the variable substrate voltage of the MOSFET, the adjustable voltage output circuit generates and outputs various reference voltages.

[0006] The substrate control voltage circuit includes port VCDY, and the adjustable voltage output circuit includes ports VBOY and VREF. Port VCDY is connected to port VBOY and is used to transmit voltage Vby. Port VREF is used to output voltage Vref.

[0007] The substrate control voltage circuit includes a drive voltage circuit and a controllable voltage divider circuit.

[0008] The driving voltage circuit is connected to the controllable voltage divider circuit. The driving voltage circuit generates a driving voltage Vdx that is unaffected by power supply voltage fluctuations. The controllable voltage divider circuit divides the driving voltage Vdx according to the received 5 control signals and outputs the corresponding substrate control voltage Vby.

[0009] The adjustable voltage output circuit includes a stabilization circuit and a reference voltage circuit.

[0010] The stabilization circuit is connected to the reference voltage circuit. The stabilization circuit ensures that the relevant branches of the reference voltage circuit have a stable voltage drop and low power supply noise current, thereby improving the linear regulation and power supply rejection ratio of the adjustable voltage output circuit. The reference voltage circuit generates and outputs different reference voltages Vref based on a variable substrate control voltage Vby.

[0011] Compared with existing technologies, the advantages of this invention are as follows: This invention proposes an integrated circuit for an adjustable reference voltage source, including a substrate control voltage circuit and an adjustable voltage output circuit. The substrate control voltage circuit receives a control signal, generates a variable bias voltage, and outputs it to the substrate of the corresponding MOSFET in the adjustable voltage output circuit, forming the substrate voltage of that MOSFET. Most of the MOSFETs in the adjustable voltage output circuit operate in the subthreshold region, and based on the variable MOSFET substrate voltage, different reference voltages are generated without changing the system circuit structure and MOSFET size, to meet the reference voltage requirements of different modules in the same system, thereby simplifying the circuit structure and reducing system power consumption. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the system structure of the present invention;

[0013] Figure 2 This is a schematic diagram of the principle structure of the substrate control voltage circuit of the present invention;

[0014] Figure 3 This is a schematic diagram of the adjustable voltage output circuit of the present invention.

[0015] Explanation of reference numerals in the attached figures:

[0016] 1-Substrate control voltage circuit; 2-Adjustable voltage output circuit; 11-Drive voltage circuit; 12-Controllable voltage divider circuit; 21-Stabilization and adjustment circuit; 22-Reference voltage circuit. Detailed Implementation

[0017] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0018] like Figure 1 As shown, an integrated circuit with an adjustable output reference voltage source includes a substrate control voltage circuit 1 and an adjustable voltage output circuit 2.

[0019] The substrate control voltage circuit 1 is connected to the adjustable voltage output circuit 2. The substrate control voltage circuit 1 receives a control signal, generates a variable bias voltage, and outputs it to the substrate of the corresponding MOSFET in the adjustable voltage output circuit 2 to form the substrate voltage of that MOSFET. The adjustable voltage output circuit 2 generates and outputs various reference voltages based on the variable substrate voltage of the MOSFET.

[0020] The substrate control voltage circuit 1 includes port VCDY, and the adjustable voltage output circuit 2 includes port VBOY and port VREF. Port VCDY is connected to port VBOY and is used to transmit voltage Vby. Port VREF is used to output voltage Vref.

[0021] like Figure 1 As shown, the substrate control voltage circuit 1 includes a drive voltage circuit 11 and a controllable voltage divider circuit 12.

[0022] The driving voltage circuit 11 is connected to the controllable voltage divider circuit 12. The driving voltage circuit 11 generates a driving voltage Vdx that is not affected by power supply voltage fluctuations. The controllable voltage divider circuit 12 divides the driving voltage Vdx according to the received 5 control signals and outputs the corresponding substrate control voltage Vby.

[0023] like Figure 1 As shown, the adjustable voltage output circuit 2 includes a stabilization circuit 21 and a reference voltage circuit 22.

[0024] The stabilization circuit 21 is connected to the reference voltage circuit 22. The stabilization circuit 21 ensures that the relevant branches of the reference voltage circuit 22 have a stable voltage drop and a small power supply noise current, thereby improving the linear regulation and power supply rejection ratio of the adjustable voltage output circuit 2. The reference voltage circuit 22 generates and outputs different reference voltages Vref based on a variable substrate control voltage Vby.

[0025] like Figure 2 As shown, the driving voltage circuit 11 includes a voltage generation circuit 111 and a voltage regulator circuit 112;

[0026] The voltage generation circuit 111 is connected to the voltage regulator circuit 112. The voltage generation circuit 111 generates a driving voltage at the driving voltage node VDX. The voltage regulator circuit 112 makes the driving voltage node VDX unaffected by power supply voltage fluctuations and maintains the stable operation of the voltage generation circuit 111 under various process corner conditions by extracting the current in the driving voltage node VDX.

[0027] The voltage generation circuit 111 includes MOSFETs M4, M6, and M9.

[0028] The source of MOSFET M4 is connected to the power supply VDD, the gate of MOSFET M4 is connected to the source of MOSFET M4, and the drain of MOSFET M4 is connected to the source of MOSFET M5. The drain of MOSFET M6 is connected to the drain of MOSFET M5, the gate of MOSFET M6 is connected to the drain of MOSFET M8, the source of MOSFET M6 is connected to the drain of MOSFET M7, and the substrate of MOSFET M6 is grounded. The drain of MOSFET M9 is connected to the source of MOSFET M4, the gate of MOSFET M9 is connected to the drain of MOSFET M5, the source of MOSFET M9 is connected to the source of MOSFET MA1, and the substrate of MOSFET M9 is grounded.

[0029] MOSFET M9 is a small-sized MOSFET, which reduces power consumption and parasitic capacitance, thereby improving the power supply rejection ratio of the voltage generation circuit 111. MOSFETs M4, M6, and M9 are connected to form an adjustment loop. At the intersection of the source of MOSFET M9 and the source of MOSFET MA1, i.e., the drive voltage node VDX, a drive voltage Vdx is generated to drive the controllable voltage divider circuit 12 to generate a controllable substrate control voltage Vby. The drive voltage Vdx is inversely proportional to the absolute temperature and can be adjusted by changing the dimensions of MOSFETs M4 and M6.

[0030] The voltage regulator circuit 112 includes MOSFETs M1, M2, M3, M5, M7, and M8, and capacitors C1, C2, and C3.

[0031] The source of MOSFET M1 is connected to the gate of MOSFET M4, the gate of MOSFET M1 is connected to the drain of MOSFET M4, and the drain of MOSFET M1 is connected to the source of MOSFET M2. The source of MOSFET M2 is connected to the gate of MOSFET M5, the gate of MOSFET M2 is connected to the source of MOSFET M2, and the drain of MOSFET M2 is connected to the source of MOSFET M3. The source of MOSFET M3 is connected to the drain of MOSFET M2, the gate of MOSFET M3 is connected to the drain of MOSFET M3, and the drain of MOSFET M3 is grounded.

[0032] The source of MOSFET M5 is connected to the gate of MOSFET M1, the gate of MOSFET M5 is connected to the gate of MOSFET M2, and the drain of MOSFET M5 is connected to the drain of MOSFET M6. The drain of MOSFET M7 is connected to the source of MOSFET M6, the gate of MOSFET M7 is connected to the drain of MOSFET M7, and the source of MOSFET M7 is grounded. The drain of MOSFET M8 is connected to the source of MOSFET M9, the gate of MOSFET M8 is connected to the drain of MOSFET M8, and the source of MOSFET M8 is grounded. The upper end of capacitor C1 is connected to the drain of MOSFET M5, and the lower end of capacitor C1 is grounded. The upper end of capacitor C2 is connected to the source of MOSFET M4, and the lower end of capacitor C2 is connected to the gate of MOSFET M9. The upper end of capacitor C3 is connected to the gate of MOSFET M6, and the lower end of capacitor C3 is grounded.

[0033] The circuit connection structure of MOSFETs M1, M2, M3, and M5 gives the drive voltage node VDX a high power supply rejection ratio, thereby improving the stability of the system output reference voltage. The circuit connection structure of MOSFETs M6, M7, and M8 functions as a current source, drawing a subthreshold current Ia from the drive voltage node VDX, enabling the regulation loop formed by MOSFETs M4, M6, and M9 to operate stably under various process corner conditions. The circuit structure of capacitors C1, C2, and C3 increases the phase margin of the drive voltage circuit 11, improving its stability over a wide frequency range. Based on the interaction of the voltage regulator circuit 112 and the voltage generation circuit 111, the expression for the drive voltage Vdx generated at the drive voltage node VDX is shown below.

[0034] ;

[0035] In the formula, Gds9 is the conductance of MOSFET M9, Gds6 is the conductance of MOSFET M6, Gm9 is the transconductance of MOSFET M9, Gm6 is the transconductance of MOSFET M6, Gds4 is the conductance of MOSFET M4, Gds2 is the conductance of MOSFET M2, Gm1 is the transconductance of MOSFET M1, and Vdd is the circuit power supply voltage.

[0036] like Figure 2 As shown, the controllable voltage divider circuit 12 includes a voltage divider circuit 121 and an output control circuit 122.

[0037] The voltage divider circuit 121 is connected to the output control circuit 122. The voltage divider circuit 121 performs series voltage division on the driving voltage Vdx. Based on its connection structure with the voltage divider circuit 121 and according to the control signal received at its port, the output control circuit 122 changes the path structure of the controllable voltage divider circuit 12, thereby generating different substrate control voltages Vby.

[0038] The voltage divider circuit 121 includes MOSFETs MA1, MA2, MA3, MA4, and MA5.

[0039] The source of MOSFET MA1 is connected to the drain of MOSFET M8, and the gate of MOSFET MA1 is connected to the drain of MOSFET MA1. The drain of MOSFET MA1 is connected to the source of MOSFET MA2. The source of MOSFET MA2 is connected to the gate of MOSFET MA1, and the gate of MOSFET MA2 is connected to the drain of MOSFET MA2. The drain of MOSFET MA2 is connected to the source of MOSFET MA3. The source of MOSFET MA3 is connected to the gate of MOSFET MA2, and the gate of MOSFET MA3 is connected to the drain of MOSFET MA3. The drain of MOSFET MA3 is connected to the source of MOSFET MA4.

[0040] The source of MOSFET MA4 is connected to the gate of MOSFET MA3, the gate of MOSFET MA4 is connected to the drain of MOSFET MA4, and the drain of MOSFET MA4 is connected to the source of MOSFET MA5. The source of MOSFET MA5 is connected to the gate of MOSFET MA4, the gate of MOSFET MA5 is connected to the drain of MOSFET MA5, and the drain of MOSFET MA5 is grounded.

[0041] MOSFETs MA1 through MA5 are all PMOS transistors, and are connected in series with a diode connection structure. MOSFETs MA1 through MA5 are fitted with medium threshold voltages to reduce leakage current caused by parasitic diodes in the PMOS transistors. The on-resistances of the diode connection structure of MOSFETs MA1 through MA5 are r1, r2, r3, r4, and r5, respectively. Their series superposition forms a voltage divider ladder structure, increasing the load impedance of the drive voltage circuit 11 and reducing the current flowing into the voltage divider ladder branch.

[0042] The output control circuit 122 includes MOSFETs MS1, MS2, MS3, MS4, and MS5, ports S1, S2, S3, S4, S5, and VCDY.

[0043] The drain of MOSFET MS1 is connected to the source of MOSFET MA1, the gate of MOSFET MS1 is connected to port S1, and the source of MOSFET MS1 is connected to port VCDY. The drain of MOSFET MS2 is connected to the source of MOSFET MA2, the gate of MOSFET MS2 is connected to port S2, and the source of MOSFET MS2 is connected to the source of MOSFET MS1. The drain of MOSFET MS3 is connected to the source of MOSFET MA3, the gate of MOSFET MS3 is connected to port S3, and the source of MOSFET MS3 is connected to the source of MOSFET MS2.

[0044] The drain of MOSFET MS4 is connected to the source of MOSFET MA4, the gate of MOSFET MS4 is connected to port S4, and the source of MOSFET MS4 is connected to the source of MOSFET MS3. The drain of MOSFET MS5 is connected to the source of MOSFET MA5, the gate of MOSFET MS5 is connected to port S5, and the source of MOSFET MS5 is connected to the source of MOSFET MS4.

[0045] MOSFETs MS1 to MS5 are connected to relevant circuit nodes of voltage divider circuit 121, forming a voltage divider control network. Ports S1 to S5 are connected to the gates of MOSFETs MS1 to MS5, respectively, and receive control signals Sa1, Sa2, Sa3, Sa4, and Sa5. When control signal Sa is high, the corresponding MOSFET MS is turned on. When control signal Sa is low, the corresponding MOSFET MS is turned off. Based on the high and low level combinations of the five control signals Sa1 to Sa5, controllable voltage divider circuit 12 has 32 voltage division forms. Controllable voltage divider circuit 12 divides the driving voltage Vdx and generates a substrate control voltage Vby. The substrate control voltage Vby is output to adjustable voltage output circuit 2 through port VCDY. The expression for substrate control voltage Vby is shown below.

[0046] ;

[0047] In the formula, Vdx is the output voltage of the driving voltage circuit 11, and Hb is the voltage division ratio generated by the controllable voltage divider circuit 12 based on the control signal.

[0048] like Figure 3 As shown, the stabilization circuit 21 includes MOSFET MT1, MOSFET MT2, MOSFET MT3, and capacitor C4.

[0049] The source of MOSFET MT1 is connected to the power supply VDD, the gate of MOSFET MT1 is connected to the drain of MOSFET MR1, and the drain of MOSFET MT1 is connected to the source of MOSFET MT2. The source of MOSFET MT2 is connected to the gate of MOSFET MT3, the gate of MOSFET MT2 is connected to the source of MOSFET MT2, and the drain of MOSFET MT2 is grounded. The source of MOSFET MT3 is connected to the gate of MOSFET MT1, the gate of MOSFET MT3 is connected to the drain of MOSFET MT1, and the drain of MOSFET MT3 is connected to the drain of MOSFET MR2. The upper end of capacitor C4 is connected to the gate of MOSFET MT3, and the lower end of capacitor C4 is grounded.

[0050] The interconnection structure of MOSFETs MT1, MT2, and MT3 ensures a constant voltage Vsdr1 across MOSFET MR1, with the drain voltage Vn1 equal to Vdd - Vsdr1. Because Vsdr1 remains constant, the drain-induced barrier reduction effect of MOSFET MR1 is effectively suppressed, thereby stabilizing the drain-source current flowing through MOSFET MR1. This significantly improves the DC linearity regulation of the system and makes the drain-source current of MOSFET MR1 unaffected by power supply voltage fluctuations.

[0051] Capacitor C4 is connected to the drain of MOSFET MT1 to maintain the stability of the circuit formed by the connection of MOSFETs MT1, MT2, and MT3, ensuring the system maintains 80° stability under all process corner conditions. o The phase margin above. MOSFET MT3 is made smaller so that the parasitic diode reverse-biased leakage current at the node of voltage Vn1 is negligible compared to the drain current of MOSFET MR1, thereby improving the temperature characteristics of the output reference voltage Vref.

[0052] The connection structure of MOSFETs MT1, MT2, and MT3 results in a voltage drop across MOSFET MR1 greater than 4Vt, where Vt is the thermal voltage. Both MOSFETs MR1 ​​and MT3 operate in the subthreshold region, ensuring a high drain-source resistance at the system output, thereby improving the system's power supply rejection ratio (PSRR). The minimum value of the system's operating power supply voltage Vdd is Vref + 8Vt.

[0053] Power supply noise enters the circuit system through the drain-source branch of MOSFET MR1, generating a power supply noise current Ie in this branch, which affects the system output reference voltage Vref. The power supply rejection ratio PSR1 is expressed as follows.

[0054] ;

[0055] In the formula, VXref is the change in the reference voltage Vref, VXdd is the noise of the power supply voltage Vdd, Gdsr1 is the conductance of MOSFET MR1, and Gmr2 is the transconductance of MOSFET MR2.

[0056] Based on the connection structure of MOSFETs MT1 and MT3, the power supply noise current Ia entering the system through the drain-source branch of MOSFET MT1 causes a reverse current Ib to be generated in the drain-source branch of MOSFET MT3. This reverse current Ib cancels out the power supply noise current Ie entering the system through the drain-source branch of MOSFET MT1, thereby improving the system's power supply rejection ratio (PSR). The expression for the final PSR2 of the system is shown below.

[0057] ;

[0058] In the formula, Gdsr1 is the conductance of MOSFET MR1, Gdst2 is the conductance of MOSFET MT2, Gmt1 is the transconductance of MOSFET MT1, and Gmr2 is the transconductance of MOSFET MR2.

[0059] Comparing the power supply rejection ratio (PSR1) with the final power supply rejection ratio (PSR2) of the system, it can be seen that the connection structure of MOSFETs MT1, MT2, and MT3 significantly improves the power supply rejection ratio of the system.

[0060] The reference voltage circuit 22 includes MOSFET MR1, MOSFET MR2, capacitor C5, port VBOY, and port VREF.

[0061] The source of MOSFET MR1 is connected to the power supply VDD, the gate of MOSFET MR1 is connected to the source of MOSFET MR1, and the drain of MOSFET MR1 is connected to the source of MOSFET MT3. The drain of MOSFET MR2 is connected to port VREF, the gate of MOSFET MR2 is connected to the drain of MOSFET MR2, the source of MOSFET MR2 is grounded, and the substrate of MOSFET MR2 is connected to port VBOY. The upper end of capacitor C5 is connected to port VREF, and the lower end of capacitor C5 is grounded.

[0062] MOSFET MR1 is a thin-gate oxide MOSFET, and MOSFET MR2 is a thick-gate oxide MOSFET. Capacitor C5 is the output filter capacitor. Both MOSFETs MR1 ​​and MR2 operate in the deep subthreshold region, and their channel lengths are both greater than 5µm to avoid the effects of short-channel effects. In the circuit structure, MOSFET MR1 is the subthreshold current source for PMOS transistors, and MOSFET MR2 is the current sink for NMOS transistors. The substrate of MOSFET MR2 is connected to port VBOY, and receives voltage Vby through port VBOY, using Vby as the substrate voltage of MOSFET MR2. Considering the body effect of MOSFET MR2, the expression for the threshold voltage Vthr2 of MOSFET MR2 is as follows.

[0063] ;

[0064] In the formula, T is temperature, Tr is room temperature, Vth2 is the threshold voltage of MOS transistor MR2 at room temperature, Kvr2 is the temperature coefficient of the threshold voltage of MOS transistor MR2, Rx is the bulk effect coefficient, Qs is the surface potential, Vby is the substrate voltage obtained by MOS transistor MR2 through the port, and Bts is the temperature coefficient of the substrate voltage Vby.

[0065] As shown in the formula above, the substrate voltage Vby is inversely proportional to the threshold voltage Vthr2 of the MOSFET MR2. When the substrate voltage Vby increases, the threshold voltage Vthr2 decreases. When the substrate voltage Vby decreases, the threshold voltage Vthr2 increases.

[0066] Based on the circuit connection structure of MOSFETs MR1, MT3, and MR2, a reference voltage Vref can be generated at the junction of the drains of MT3 and MR2. The value of the reference voltage Vref is affected by the substrate voltage Vby of MR2. The expression for the reference voltage Vref is shown below.

[0067] ;

[0068] In the formula, Vt is the thermal voltage, E2 is the subthreshold slope factor of MOS transistor MR2, Vthr2 is the threshold voltage of MOS transistor MR2, Vthr1 is the threshold voltage of MOS transistor MR1, E1 is the subthreshold slope factor of MOS transistor MR1, u1 is the electron mobility of MOS transistor MR1, cox1 is the gate oxide capacitance per unit area of ​​MOS transistor MR1, W1 is the conductive channel width of MOS transistor MR1, L2 is the conductive channel length of MOS transistor MR2, u2 is the electron mobility of MOS transistor MR2, cox2 is the gate oxide capacitance per unit area of ​​MOS transistor MR2, W2 is the conductive channel width of MOS transistor MR2, and L1 is the conductive channel length of MOS transistor MR1.

[0069] In the expression for the reference voltage Vref, VHM has an inverse proportional temperature coefficient, and Vt×lnSa has a direct proportional temperature coefficient. Therefore, zero temperature coefficient of the reference voltage Vref can be achieved through temperature compensation. Furthermore, the set threshold voltage Vthr2 is significantly greater than the threshold voltage Vthr1, so that the output reference voltage Vref is greater than 6 times the thermal voltage Vt.

[0070] From the expressions for the reference voltage Vref and the threshold voltage Vthr2, it can be seen that the substrate voltage Vby is inversely proportional to the reference voltage Vref. That is, as the substrate voltage Vby increases, the threshold voltage Vthr2 decreases, and consequently, the reference voltage Vref decreases. Conversely, as the substrate voltage Vby decreases, the threshold voltage Vthr2 increases, and consequently, the reference voltage Vref increases.

[0071] It can be seen that by changing the substrate voltage Vby of the MOS transistor MR2 in the adjustable voltage output circuit 2 through the substrate control voltage circuit 1, different reference voltages Vref can be generated without changing the system circuit structure and the size of the MOS transistor.

Claims

1. An output adjustable reference voltage source integrated circuit, characterized by, The substrate control voltage circuit (1) and the adjustable voltage output circuit (2); The substrate control voltage circuit (1) is connected with the adjustable voltage output circuit (2), and the substrate control voltage circuit (1) generates a variable bias voltage by accepting a control signal and outputs the variable bias voltage to the substrate of a corresponding MOS transistor in the adjustable voltage output circuit (2) to form a substrate voltage of the MOS transistor; the adjustable voltage output circuit (2) generates a plurality of reference voltages based on the variable substrate voltage of the MOS transistor and outputs the plurality of reference voltages; The substrate control voltage circuit (1) comprises a driving voltage circuit (11) and a controllable voltage dividing circuit (12); The driving voltage circuit (11) is connected with the controllable voltage dividing circuit (12), the driving voltage circuit (11) generates a driving voltage Vdx which is not affected by power voltage fluctuation; the controllable voltage dividing circuit (12) divides the driving voltage Vdx according to the received five control signals and outputs a corresponding substrate control voltage Vby; The adjustable voltage output circuit (2) comprises a stable adjustment circuit (21) and a reference voltage circuit (22); The stable adjustment circuit (21) is connected with the reference voltage circuit (22), the stable adjustment circuit (21) makes the related branch of the reference voltage circuit (22) have a stable voltage drop and a small power noise current, thereby improving the linear adjustment rate and the power supply rejection ratio of the adjustable voltage output circuit (2); the reference voltage circuit (22) generates different reference voltages Vref based on the variable substrate control voltage Vby and outputs the different reference voltages Vref; The stable adjustment circuit (21) comprises a MOS transistor MT1, a MOS transistor MT2, a MOS transistor MT3 and a capacitor C4; The source of the MOS transistor MT1 is connected with a power supply VDD, the gate of the MOS transistor MT1 is connected with the drain of a MOS transistor MR1, and the drain of the MOS transistor MT1 is connected with the source of the MOS transistor MT2; The source of the MOS transistor MT2 is connected with the gate of the MOS transistor MT3, the gate of the MOS transistor MT2 is connected with the source of the MOS transistor MT2, and the drain of the MOS transistor MT2 is grounded; the source of the MOS transistor MT3 is connected with the gate of the MOS transistor MT1, the gate of the MOS transistor MT3 is connected with the drain of the MOS transistor MT1, and the drain of the MOS transistor MT3 is connected with the drain of the MOS transistor MR2; the upper end of the capacitor C4 is connected with the gate of the MOS transistor MT3, and the lower end of the capacitor C4 is grounded; The reference voltage circuit (22) comprises a MOS transistor MR1, a MOS transistor MR2, a capacitor C5, a port VBOY and a port VREF; The source of the MOS transistor MR1 is connected with the power supply VDD, the gate of the MOS transistor MR1 is connected with the source of the MOS transistor MR1, and the drain of the MOS transistor MR1 is connected with the source of the MOS transistor MT3; The drain of the MOS transistor MR2 is connected with the port VREF, the gate of the MOS transistor MR2 is connected with the drain of the MOS transistor MR2, the source of the MOS transistor MR2 is grounded, and the substrate of the MOS transistor MR2 is connected with the port VBOY; the upper end of the capacitor C5 is connected with the port VREF, and the lower end of the capacitor C5 is grounded.

2. The output adjustable reference voltage source integrated circuit of claim 1, wherein, The driving voltage circuit (11) comprises a voltage generating circuit (111) and a voltage stabilizing circuit (112); The voltage generating circuit (111) is connected with the voltage stabilizing circuit (112), and the voltage generating circuit (111) generates a driving voltage on a driving voltage node VDX; The voltage stabilizing circuit (112) makes the driving voltage node VDX not affected by the power voltage fluctuation, and maintains the stable operation of the voltage generating circuit (111) under various process angle conditions by extracting the current in the driving voltage node VDX.

3. The output adjustable reference voltage source integrated circuit of claim 1, wherein, The controllable voltage dividing circuit (12) comprises a voltage dividing circuit (121) and an output control circuit (122); The voltage dividing circuit (121) is connected with the output control circuit (122), and the voltage dividing circuit (121) performs series voltage dividing processing on the driving voltage Vdx; The output control circuit (122) changes the path structure of the controllable voltage dividing circuit (12) based on the connection structure with the voltage dividing circuit (121) and according to the control signal received by the port, and then generates different substrate control voltages Vby.

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