Single event transient and single event upset resistant SR latch and storage unit

Abstract

The invention relates to a single event transient and single event upset resistant SR latch and a storage unit, two output ends of the SR latch are respectively and additionally provided with a corresponding filter circuit structure, when high-energy particles bombard a sensitive node, if the single event transient occurs at the output end of an NAND gate and the emission potential is upset, the single event upset of the output end of the NAND gate is delayed, and the single event upset of the output end of the NAND gate is delayed. If the output potential is not abnormal, signal filtering processing is carried out on the output potential through a filtering circuit connected with the output potential, and after abnormal potential overturning is filtered out, potential change generated by single-particle transient is filtered out and cannot be transmitted to the final output end of the branch, so that the potential state of the final output end is ensured not to be changed due to bombardment of high-energy particles; and the purpose of effectively resisting single event upset and single event transient is achieved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuit hardening design, and relates to an SR latch and a storage unit resistant to single event transient and single event upset. BACKGROUND

[0002] In a spacecraft electronic system and a high-reliability ground device, an SR (set-reset) latch as a core digital storage unit is of great importance in terms of state stability. However, high-energy charged particles (such as protons and heavy ions) and secondary particles (such as neutrons) existing in the cosmic space and high-altitude atmospheric environment pose a serious threat of single event effects to integrated circuits, and single event upset is one of the main reliability challenges faced by the SR latch.

[0003] When a high-energy particle penetrates into a sensitive node of the SR latch, a large number of electron-hole pairs are generated along the particle track by ionization, and under the action of a strong electric field of the reverse-biased PN junction, the charges will rapidly drift, diffuse and be collected. The collected charges will change the node potential and generate a transient pulse. When the abnormal node potential disturbance time is long enough, the disturbance can be transmitted to the complementary node through a feedback loop, finally destroying the original steady state of the SR latch and causing a single event upset event. Therefore, how to design the SR latch has become a technical problem to be solved. SUMMARY

[0004] In view of the problems in the prior art, the application provides an SR latch resistant to single event transient and single event upset and a data storage unit, which can effectively realize hardening design of the SR latch.

[0005] To achieve the above purpose, the embodiments of the application adopt the following technical solutions: On the one hand, an SR latch resistant to single event transient and single event upset is provided, which comprises a first NAND gate, a second NAND gate, a first filter circuit and a second filter circuit. The first NAND gate and the second NAND gate are cross-coupled to constitute the SR latch. The output end of the first NAND gate is connected to the feedback input end of the second NAND gate through the first filter circuit. The output end of the second NAND gate is connected to the feedback input end of the first NAND gate through the second filter circuit. The first filter circuit is used to filter out abnormal potentials in the output signal of the first NAND gate. The second filter circuit is used to filter out abnormal potentials in the output signal of the second NAND gate. The abnormal potentials are the potentials after the single event upset of the NAND gate caused by the bombardment of high-energy particles on the sensitive node of the NAND gate.

[0006] In one of the embodiments, the first filter circuit comprises a first capacitor, a second capacitor, a first NAND gate and a first tri-state gate. One end of the first capacitor is connected to the output of the first NAND gate and the first input of the first NOR gate, the other end of the first capacitor is grounded, the second input of the first NOR gate is connected to the output of the first NAND gate, one end of the second capacitor, and the input of the first tri-state gate, the output of the first NOR gate is connected to the enable end of the first tri-state gate, the output of the first tri-state gate is connected to the feedback input of the second NAND gate and as the output QN, the other end of the second capacitor is grounded.

[0007] In one of the embodiments, the second filter circuit comprises a third capacitor, a fourth capacitor, a second NOR gate, and a second tri-state gate. One end of the third capacitor is connected to the output of the second NAND gate and the first input of the second NOR gate, the other end of the third capacitor is grounded, the second input of the second NOR gate is connected to the output of the second NAND gate, one end of the fourth capacitor, and the input of the second tri-state gate, the output of the second NOR gate is connected to the enable end of the second tri-state gate, the output of the second tri-state gate is connected to the feedback input of the first NAND gate and as the output Q, the other end of the fourth capacitor is grounded.

[0008] In one of the embodiments, each capacitor is a MOS capacitor.

[0009] In another aspect, the application also provides a data storage unit comprising the SR latch against single event transient and single event upset as described in any of the above.

[0010] One of the above technical solutions has the following advantages and beneficial effects: The SR latch against single event transient and single event upset and the data storage unit, by adding the corresponding filter circuit structure at the two output ends of the SR latch, when a high-energy particle strikes the sensitive node, if the output end of the NAND gate emits a potential upset due to single event transient, the output potential is filtered by the filter circuit connected thereafter, the abnormal potential upset is filtered out, the potential change caused by the single event transient is filtered out and cannot be transmitted to the final output end of the branch, ensuring that the potential state of the final output end does not change due to high-energy particle strikes, achieving the purpose of effectively resisting single event upset and single event transient. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0012] Figure 1It is a structural diagram of a traditional SR latch circuit; Figure 2 Schematic diagram of the structure of an SR latch resistant to single event transients and single event upsets in one embodiment; Figure 3 is a schematic structural diagram of a first filtering circuit in one embodiment; Figure 4 FIG. 4 is a schematic structural diagram of a second filtering circuit in an embodiment. DETAILED DESCRIPTION

[0013] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the description of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0014] It should be noted that, when referred to in this document as an "embodiment", it means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be understood by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in this document refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0015] The following describes the implementation of the present invention in detail with reference to the accompanying drawings in the embodiments of the present invention.

[0016] The circuit structure of the traditional SR latch is as follows Figure 1 As shown, the NAND gate (QN) is a basic sequential logic circuit composed of two cross-coupled NAND gates. It is used to store 1 bit of binary information and often serves as the basis for more complex flip-flops. It does not include a filter circuit, the reset signal R is fixed high, and the set signal S is fixed low. The output terminal QN of the NAND gate is usually the inverse of the other output terminal Q of the NAND gate, and the two have opposite logical states.

[0017] In the traditional SR latch, when a high-energy particle strikes the sensitive node (such as the PMOS tube in the NAND gate at the R end) thereof, a large number of electron-hole pairs are generated at the sensitive node, and the hole drift will pull the potential of the output end QN from low to high. The potential change of the output end QN further affects the potential of another output end Q (from high to low), ultimately causing the storage value of the latch to be flipped by a single event.

[0018] To solve the single event upset problem caused by the single event transient of the SR latch, the circuit structure for solving the single event upset problem caused by the single event transient of the SR latch is improved, so that it can resist both single event upset and single event transient.

[0019] In one embodiment, as shown in Figure 2 , an SR latch resistant to single event transient and single event upset is provided, comprising a first NAND gate NAND1, a second NAND gate NAND2, a first filter circuit (i.e. filter circuit 1) and a second filter circuit (i.e. filter circuit 2), the first NAND gate NAND1 and the second NAND gate NAND2 being cross-coupled to constitute an SR latch, the output end of the first NAND gate NAND1 being connected to the feedback input end of the second NAND gate NAND2 through the first filter circuit, the output end of the second NAND gate NAND2 being connected to the feedback input end of the first NAND gate NAND1 through the second filter circuit, the first filter circuit being used to filter out abnormal potentials in the output signal of the first NAND gate NAND1, and the second filter circuit being used to filter out abnormal potentials in the output signal of the second NAND gate NAND2; the abnormal potential is the potential after the single event upset of the NAND gate caused by the high-energy particle striking the sensitive node of the NAND gate.

[0020] It can be understood that the embodiment eliminates the single event transient generated by the sensitive node being struck by a high-energy particle through filtering processing, thereby resisting single event upset and single event transient. Specifically, on the basis of the traditional SR latch, a filter circuit design is added, as shown in Figure 2 , under the same irradiation state, when the sensitive node is struck by a high-energy particle, the single event transient existing at the output end QN_1 of the NAND gate is processed by the filter circuit 1 connected thereto, and the potential change generated by the single event transient is filtered out and cannot be transmitted to the final output end QN of the branch, so that the potential state of the final output end QN does not change due to the high-energy particle strike. The above reinforced design effectively resists single event upset and single event transient. The composition of the filter circuit can be obtained by building a logic gate circuit according to actual engineering conditions, as long as it can provide the required filtering function.

[0021] The SR latch with anti-single event transient and anti-single event upset mentioned above, by adding corresponding filter circuit structures at the two output ends of the SR latch respectively, when high-energy particles bombard the sensitive node, if the output end of the NAND gate emits potential flip due to single event transient, then the output potential is subjected to signal filtering processing by the filter circuit connected thereafter, after filtering out the abnormal potential flip, the potential change caused by single event transient is filtered out and cannot be transmitted to the final output end of the branch, ensuring that the potential state of the final output end does not change due to high-energy particle bombardment, achieving the purpose of effectively resisting single event upset and single event transient.

[0022] In one embodiment, the first filter circuit includes a first capacitor C1, a second capacitor C2, a first XNOR gate XNOR1 and a first tri-state gate TP1. One end of the first capacitor C1 is connected to the output end of the first NAND gate NAND1 and the first input end of the first XNOR gate XNOR1 respectively, and the other end of the first capacitor C1 is grounded. The second input end of the first XNOR gate XNOR1 is connected to the output end of the first NAND gate NAND1, one end of the second capacitor C2 and the input end of the first tri-state gate TP1 respectively. The output end of the first XNOR gate XNOR1 is connected to the enable end of the first tri-state gate TP1, and the output end of the first tri-state gate TP1 is connected to the feedback input end of the second NAND gate NAND2 and serves as an output end QN, and the other end of the second capacitor C2 is grounded.

[0023] It can be understood that in the present embodiment, one kind of first filter circuit with simple and efficient structure is provided, which can achieve the required filtering function by relatively simple gate circuit and filter capacitor. Among them, the first tri-state gate TP1 is a high-level enabled tri-state buffer. For ease of description, the signal at the output end QN_1 is directly represented by QN_1 hereinafter; in detail, when QN_1 is delayed by the first capacitor C1 and the second capacitor C2, the delay of the second capacitor C2 needs to be greater than the delay of the first XNOR gate XNOR1, and the delay of the second capacitor C2 is less than the delay of the first capacitor C1 + the delay of the first XNOR gate XNOR1, in order to ensure the accuracy of subsequent output. After QN_1 is delayed by the first capacitor C1, it becomes QN_2, and QN_2 and QN_1 are output as QB by the first XNOR gate XNOR1. When the level state of QN_2 and QN_1 (delayed by the second capacitor C2) is the same, QB is high (corresponding to normal working condition), and at this time QN_1 (delayed by the second capacitor C2) is directly output to QN. When the level state of QN_2 and QN_1 (delayed by the second capacitor C2) is different, QB is low (corresponding to the working condition of high-energy particle bombardment), and at this time QN_1 (delayed by the second capacitor C2) cannot be output to QN. In this way, the potential state of the final output end QN cannot change due to high-energy particle bombardment, so that the circuit can filter out the transient pulse caused by single event transient.

[0024] In one embodiment, the second filter circuit includes a third capacitor C3, a fourth capacitor C4, a second XNOR gate XNOR2 and a second tri-state gate TP2. One end of the third capacitor C3 is connected to the output end of the second NAND gate NAND2 and the first input end of the second XNOR gate XNOR2 respectively, and the other end of the third capacitor C3 is grounded. The second input end of the second XNOR gate XNOR2 is connected to the output end of the second NAND gate NAND2, one end of the fourth capacitor C4 and the input end of the second tri-state gate TP2 respectively. The output end of the second XNOR gate XNOR2 is connected to the enable end of the second tri-state gate TP2, the output end of the second tri-state gate TP2 is connected to the feedback input end of the first NAND gate NAND1 and serves as the output end Q, and the other end of the fourth capacitor C4 is grounded.

[0025] It can be understood that in the embodiment, one of the simple and efficient second filter circuits is provided, which can achieve the required filtering function by using a relatively simple gate circuit in combination with a filter capacitor. The second tri-state gate TP2 is a high-level enabled tri-state buffer. For ease of description, the signal at the output end Q_1 is directly denoted as Q_1 hereinafter. Specifically, when Q_1 is delayed by the third capacitor C3 and the fourth capacitor C4, it is required that the delay of the fourth capacitor C4 is greater than the delay of the second XNOR gate XNOR2, and the delay of the fourth capacitor C4 is less than the delay of the third capacitor C3 + the delay of the second XNOR gate XNOR2. When Q_1 is delayed by the third capacitor C3 and becomes Q_2, Q_2 and Q_1 are output as QB through the third XNOR gate. When the level state of Q_2 and Q_1 (delayed by the fourth capacitor C4) is the same, QB is high (corresponding to a normal working condition), and at this time, Q_1 (delayed by the fourth capacitor C4) is directly output to Q. When the state of Q_2 and Q_1 (delayed by the fourth capacitor C4) is different, QB is low (corresponding to a working condition of high-energy particle bombardment), and at this time, Q_1 (delayed by the fourth capacitor C4) cannot be output to Q. In this way, the potential state of the final output end Q cannot be changed due to high-energy particle bombardment, so that the circuit can filter out the transient pulse caused by single event transient.

[0026] It can be understood that the second filter circuit in the embodiment is the same as the first filter circuit, which can further simplify the structure design of the circuit and improve the reliability of the circuit.

[0027] In one embodiment, each of the capacitors is a MOS capacitor. It can be understood that in a MOS transistor, the gate is separated from the substrate by a thin oxide insulating layer, and when a voltage is applied to the gate, an electric charge is induced in the semiconductor substrate below the gate, forming a capacitor, which is called a MOS capacitor, and the capacitance of the MOS capacitor is related to the gate area, the oxide insulating layer thickness, and the characteristics of the semiconductor material. Therefore, in the embodiment, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 can each be formed by a single MOS transistor or a plurality of MOS capacitors stacked and connected.

[0028] In one embodiment, a data storage unit is also provided, including any of the above SR latches resistant to single event transient and single event upset.

[0029] The data storage unit described above is constructed by using the SR latch resistant to single event transient and single event upset, effectively improving the single event upset and single event transient resistance of the storage unit, and providing the reliability of the storage unit in a high-energy particle radiation environment.

[0030] The technical features of the above embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features in the above embodiments are not described, but as long as the combinations of the technical features do not contradict, they should be considered as within the scope of the present disclosure.

[0031] The above embodiments only express several implementation manners of the present application, and the description is specific and detailed, but it should not be understood as a limitation on the protection scope of the present application. It should be pointed out that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application.

Claims

1. An SR latch resistant to single event transients and single event upsets, characterized in that: The invention comprises a first NAND gate, a second NAND gate, a first filtering circuit and a second filtering circuit. The first NAND gate and the second NAND gate are cross-coupled to form an SR latch. The output end of the first NAND gate is connected to the feedback input end of the second NAND gate through the first filtering circuit. The output end of the second NAND gate is connected to the feedback input end of the first NAND gate through the second filtering circuit. The first filtering circuit is used to filter out abnormal potentials in the output signal of the first NAND gate. The second filtering circuit is used to filter out abnormal potentials in the output signal of the second NAND gate. The abnormal potential is the potential after a single particle flip is caused by high-energy particles bombarding a sensitive node of the NAND gate.

2. The single event transient and single event upset resistant SR latch according to claim 1, characterized in that: The first filtering circuit includes a first capacitor, a second capacitor, a first XNOR gate and a first tri-state gate; One end of the first capacitor is respectively connected to the output end of the first NAND gate and the first input end of the first XNOR gate, the other end of the first capacitor is grounded, the second input end of the first XNOR gate is respectively connected to the output end of the first NAND gate, one end of the second capacitor and the input end of the first tri-state gate, the output end of the first XNOR gate is connected to the enable end of the first tri-state gate, the output end of the first tri-state gate is connected to the feedback input end of the second NAND gate and serves as the output end QN, and the other end of the second capacitor is grounded.

3. The SR latch resistant to single event transient and single event upset according to claim 1 or 2, characterized in that: The second filtering circuit includes a third capacitor, a fourth capacitor, a second XOR gate and a second tri-state gate; One end of the third capacitor is respectively connected to the output end of the second NAND gate and the first input end of the second XENOR gate, the other end of the third capacitor is grounded, the second input end of the second XENOR gate is respectively connected to the output end of the second NAND gate, one end of the fourth capacitor and the input end of the second three-state gate, the output end of the second XENOR gate is connected to the enable end of the second three-state gate, the output end of the second three-state gate is connected to the feedback input end of the first NAND gate and serves as the output end Q, and the other end of the fourth capacitor is grounded.

4. The single event transient and single event upset resistant SR latch according to claim 3, characterized in that: Each capacitor is a capacitor of MOS tube structure.

5. A data storage unit, characterized in that: The SR latch comprising the single event transient and single event upset resistance according to any one of claims 1 to 4.

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