Low power flip-flop circuit structure with asynchronous reset state controllable test circuit

Abstract

The application relates to the chip technical field, in particular to a low-power trigger circuit structure with a test circuit and controllable asynchronous reset state, which comprises a first selector, a second selector, a first trigger, a second trigger, a reset control gate, a set control gate and a NOT gate, wherein a first input port of the first selector is used for receiving a first test reset signal, a second input port of the first selector is used for receiving a first function reset signal, and an enable port of the first selector is used for receiving a test enable signal; a first input port of the second selector is used for receiving a second test reset signal, the second test reset signal is controlled by a test machine, a second input port of the second selector is used for receiving a second function reset signal, and an enable port of the second selector is used for receiving the test enable signal. The application can control the asynchronous reset state of the trigger according to application requirements, and can realize the test of the trigger circuit structure with the controllable asynchronous reset state.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a low-power trigger circuit structure with a controllable asynchronous reset state and a test circuit. Background Technology

[0002] The reset operation of a flip-flop can be performed synchronously or asynchronously, depending on design requirements. Synchronous reset relies on a clock signal, while asynchronous reset can take effect immediately at any time. The effective level of the reset signal also affects the behavior of the reset operation. An asynchronous reset signal can reset the flip-flop at any time, independent of the clock signal. Current technology fixes the asynchronous reset value of flip-flops; when the reset signal is active, the flip-flop is fixedly reset to 0 or 1, which is uncontrollable. However, in some applications, such as power management designs, it is necessary to reset the flip-flop to different values ​​at different application stages, rather than a fixed value. To achieve controllable asynchronous reset states, additional circuitry is usually required, but the more components added, the higher the chip's power consumption. Furthermore, to meet testing requirements, it is necessary to test the flip-flop circuit structure with controllable asynchronous reset states after adding circuitry. Therefore, providing a low-power flip-flop circuit structure with controllable asynchronous reset states and integrated testing circuitry is a pressing technical problem. Summary of the Invention

[0003] The purpose of this invention is to provide a low-power trigger circuit structure with controllable asynchronous reset state and test circuitry. This structure can control the asynchronous reset state of the trigger according to application requirements while minimizing power consumption, and can also perform tests on the trigger circuit structure with controllable asynchronous reset state.

[0004] This invention provides a low-power trigger circuit structure with a controllable asynchronous reset state and a test circuit, comprising a first selector, a second selector, a first flip-flop, a second flip-flop, a reset control gate, a set control gate, and a NOT gate, wherein...

[0005] The first input port of the first selector is used to receive the first test reset signal, and the second input port of the first selector is used to receive the first function reset signal. The first test reset signal is controlled by the test machine. The enable port of the first selector is used to receive the test enable signal. When the test enable signal is high, the first input port of the first selector is turned on, and when the test enable signal is low, the second input port of the first selector is turned on.

[0006] The first input port of the second selector is used to receive the second test reset signal, which is controlled by the test machine. The second input port of the second selector is used to receive the second function reset signal. The enable port of the second selector is used to receive the test enable signal. When the test enable signal is high, the first input port of the second selector is turned on. When the test enable signal is low, the second input port of the second selector is turned on.

[0007] The first trigger includes a first reset terminal, a first set terminal, and a first data terminal;

[0008] The second flip-flop includes a second reset terminal and a second output terminal;

[0009] The reset control gate includes a first reset input pin, a second reset input pin, and a reset output pin;

[0010] The set control gate includes a first set input pin, a second set input pin, and a set output pin;

[0011] The first reset input pin and the first set input pin are both connected to the output of the first selector, and the second reset pin is connected to the output of the second selector;

[0012] The NOT gate is set between the second output terminal and the second reset input pin, or the NOT gate is set between the second output terminal and the second set input pin;

[0013] The reset output pin is connected to the first reset terminal, and the set output pin is connected to the first set terminal.

[0014] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the low-power trigger circuit structure with controllable asynchronous reset state and test circuit provided by this invention achieves considerable technological advancement and practicality, and has broad industrial application value. It has at least the following beneficial effects:

[0015] This invention uses three simple logic gates—a reset control gate, a set control gate, and a NOT gate—in conjunction with a second flip-flop to control the reset and set of the first flip-flop, achieving controllable asynchronous reset state of the first flip-flop with minimal power consumption. Furthermore, this invention uses a first selector and a second selector to select different reset signals for the first and second flip-flops, making the low-power flip-flop circuit structure with controllable asynchronous reset state testable. This invention achieves both controllable asynchronous reset state of the flip-flops according to application requirements and meets the needs of low power consumption and testing. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a low-power trigger circuit with a test circuit that provides an asynchronous reset state controllable circuit according to Embodiment 1 of the present invention.

[0018] Figure 2 This is a schematic diagram of a low-power trigger circuit with a test circuit that provides an asynchronous reset state controllable circuit according to Embodiment 2 of the present invention.

[0019] Figure 3 This is a schematic diagram of a low-power trigger circuit with a test circuit that provides an asynchronous reset state controllable circuit according to Embodiment 3 of the present invention.

[0020] Figure 4 This is a schematic diagram of a low-power trigger circuit with a test circuit that provides an asynchronous reset state controllable circuit according to Embodiment 4 of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] This invention provides a low-power trigger circuit structure with a controllable asynchronous reset state and a test circuit, including a first selector, a second selector, a first flip-flop, a second flip-flop, a reset control gate, a set control gate, and a NOT gate.

[0023] The first input port (1) of the first selector is used to receive the first test reset signal, and the second input port (0) of the first selector is used to receive the first function reset signal. The first test reset signal is controlled by the test machine. The enable port of the first selector is used to receive the test enable signal. When the test enable signal is high, the first input port of the first selector is turned on, and when the test enable signal is low, the second input port of the first selector is turned on. It should be noted that the first test reset signal is the signal used to control the reset in test mode, and the first function reset signal is the signal used to control the reset in function mode.

[0024] The first input port (1) of the second selector is used to receive the second test reset signal, which is controlled by the test machine. The second input port (0) of the second selector is used to receive the second function reset signal. The enable port of the second selector is used to receive the test enable signal. When the test enable signal is high, the first input port of the second selector is turned on; when the test enable signal is low, the second input port of the second selector is turned on. It should be noted that the second test reset signal is the signal used to control the reset in test mode, and the second function reset signal is the signal used to control the reset in function mode. It should be noted that the first and second selectors can be set in the top-level global control module to make the circuit structure as simple as possible.

[0025] As one embodiment, the first test reset signal and the second test reset signal can be two independent signals or the same signal, depending on the specific requirements.

[0026] The first flip-flop includes a first reset terminal (R1), a first set terminal (S1), and a first data terminal (D1). It is understood that the first flip-flop also includes a first output port (Q1) and a clock port (not shown in the figure) for inputting the corresponding clock signal. The second flip-flop includes a second reset terminal (R2), a second output terminal (Q2), and a second data terminal (D2). It is understood that the second flip-flop also includes a clock port (not shown in the figure) for inputting the corresponding clock signal, and the second data terminal is connected to the combinational logic circuit.

[0027] The reset control gate includes a first reset input pin, a second reset input pin, and a reset output pin. The set control gate includes a first set input pin, a second set input pin, and a set output pin.

[0028] Both the first reset input pin and the first set input pin are connected to the output of the first selector to receive the reset signal output by the first selector. The second reset pin is connected to the output of the second selector to receive the reset signal output by the second selector. The second reset signal is used to set the initial value or reset value of the second flip-flop. When the second flip-flop is in normal operating condition, the value in the second flip-flop is determined by the clock signal and data port of the second flip-flop.

[0029] The NOT gate is positioned between the second output terminal and the second reset input pin, or the NOT gate is positioned between the second output terminal and the second set input pin; the reset output pin is connected to the first reset terminal, and the set output pin is connected to the first set terminal. The signals output by the reset output terminal and the signals output by the set output terminal are mutually exclusive. When the reset signal output by the first selector is valid, the first flip-flop is reset to 0 by the first reset terminal or set to 1 by the first set terminal. That is, when the reset signal output by the first selector is valid, only one of the signals output by the reset output terminal and the signal output by the set output terminal will affect the value of the first flip-flop. When the reset signal output by the first selector is invalid, the first flip-flop updates the value stored in the first flip-flop to the value input by the first data terminal when the rising edge of the clock connected to the first flip-flop arrives.

[0030] As one embodiment, the circuit structure may further include an output control circuit, the data terminal of which is connected to the second output terminal, and the output terminal of which is connected to the second reset data terminal and the second set data terminal. The output control circuit is used to adjust the value output by the second output terminal and transmit the adjusted value to the second reset data terminal and the second set data terminal, thereby increasing the flexibility of asynchronous reset state control.

[0031] As one embodiment, in test mode, the test enable signal is high, the first input port of the first selector is turned on, and both the first reset data terminal and the first set data terminal are controlled by the first test reset signal. The first input port of the second selector is turned on, and the second reset terminal of the second flip-flop is controlled by the second test reset signal.

[0032] During the test vector loading phase (Scan Shift) of the scan test, the value in the second trigger is controlled by the scan chain. During the response data capture phase (Scan Capture) of the scan test, the value in the second trigger remains in the last state of the scan chain or is controlled by the second test reset signal. Both the loading of the test vector and the second test reset signal are controlled by the test equipment. Each A... m The second reset data terminal and the second set data terminal are controlled by the output value of the second flip-flop.

[0033] It should be noted that, in test mode, both the first test reset signal and the second test reset signal are controlled by the test equipment, and the loading of the test vector is controlled by the test equipment (ATE). This makes the first and second reset data terminals of the reset setting module measurable, thereby making the fan-in path of the first reset terminal of the first flip-flop measurable. It also makes the first and second set data terminals of the set setting module measurable, thereby making the fan-in path of the first set terminal of the first flip-flop measurable. Furthermore, it makes the second reset terminal of the second flip-flop measurable. The circuit structure described in this embodiment of the invention enables the low-power flip-flop circuit structure with controllable asynchronous reset state to be measurable in test mode, improving test coverage, and eliminating the need for additional test bypass circuits, thus simplifying the circuit structure.

[0034] The first reset terminal and the first set terminal can be configured as asynchronous active-low ports or asynchronous active-high ports. An asynchronous active-low port refers to a port that is asynchronous and performs a reset or set operation when a low level is received. An asynchronous active-high port refers to a port that is asynchronous and performs a reset or set operation when a high level is received. If both the first reset terminal and the first set terminal are asynchronous active-low ports, then both the reset control gate and the set control gate are configured as OR gates; if both the first reset terminal and the first set terminal are asynchronous active-high ports, then both the reset control gate and the set control gate are configured as AND gates.

[0035] The following are some specific examples to illustrate this.

[0036] Example 1

[0037] like Figure 1 As shown, both the first reset terminal and the first set terminal are asynchronous low-level active ports, and both the reset control gate and the set control gate are configured as OR gates. The NOT gate is located between the second output terminal and the second reset input pin.

[0038] In functional mode, or during the response data capture phase in test mode, when the signal output by the first selector is low, if the value output by the second output is 0, then the first reset input pin inputs 0. The NOT gate converts 0 to 1 and inputs it to the reset control gate from the second reset input pin. The reset output pin outputs a high level, and no reset operation is performed. When both the first and second set input pins of the set control gate input 0, the set output pin outputs a low level, setting the first flip-flop to 1. It can be understood that, for the structure described in Embodiment 1, when both the first reset terminal and the first set terminal are asynchronous low-level active ports, in functional mode, or during the response data capture phase in test mode, if it is necessary to set the value in the first flip-flop to 1, then controlling the second flip-flop to output 0 is sufficient.

[0039] In functional mode, or during the response data capture phase in test mode, when the signal output by the first selector is low, if the value output by the second output terminal is 1, then the first reset input pin inputs 0. The NOT gate converts 1 to 0 and inputs it to the reset control gate from the second reset input pin. The reset output pin outputs a low level, resetting the first flip-flop to 0. When the first set input pin of the set control gate inputs 0, the second set input pin inputs 1, and the set output pin outputs a high level, no set operation is performed. It can be understood that, for the structure described in Embodiment 1, when both the first reset terminal and the first set terminal are asynchronous low-level active ports, in functional mode, or during the response data capture phase in test mode, if it is necessary to set the value in the first flip-flop to 0, then controlling the second flip-flop to output 1 is sufficient.

[0040] Example 2

[0041] like Figure 2 As shown, both the first reset terminal and the first set terminal are asynchronous low-level active ports, and both the reset control gate and the set control gate are configured as OR gates. The NOT gate is located between the second output terminal and the second set input pin.

[0042] In functional mode, or during the response data capture phase in test mode, when the signal output by the first selector is low, if the value output by the second output is 0, then the first set input pin inputs 0. The NOT gate converts 0 to 1 and inputs it to the set control gate from the second set input pin. The set output pin outputs a high level, and no set operation is performed. The first reset input pin and the second reset input pin of the reset control gate both input 0, and the reset output pin outputs a low level, resetting the first flip-flop to 0. It can be understood that, for the structure described in Embodiment 2, when both the first reset terminal and the first set terminal are asynchronous low-level active ports, in functional mode, or during the response data capture phase in test mode, if it is necessary to set the value in the first flip-flop to 0, then controlling the second flip-flop to output 0 is sufficient.

[0043] In functional mode, or during the response data capture phase in test mode, when the signal output by the first selector is low, if the value output by the second output is 1, then the first set input pin is 0. The NOT gate converts 1 to 0 and inputs it to the set control gate from the second set input pin. The set output pin outputs a low level, setting the first flip-flop to 1. The first reset input pin of the reset control gate is 0, the second reset input pin is 1, and the reset output pin outputs a high level, without performing a reset operation. It can be understood that, for the structure described in Embodiment 2, when both the first reset terminal and the first set terminal are asynchronous low-level active ports, in functional mode, or during the response data capture phase in test mode, if it is necessary to set the value in the first flip-flop to 1, then controlling the second flip-flop to output 1 is sufficient.

[0044] Example 3

[0045] like Figure 3 As shown, the first reset terminal and the first set terminal are both asynchronous high-level active ports. The reset control gate and the set control gate are both set as AND gates, and the NOT gate is set between the second output terminal and the second reset input pin.

[0046] In functional mode, or during the response data capture phase in test mode, when the signal output by the first selector is high, if the value output by the second output is 0, then the first reset input pin is 1. The NOT gate converts 0 to 1 and inputs it to the reset control gate from the second reset input pin. The reset output pin outputs a high level, resetting the first flip-flop to 0. When the first set input pin of the set control gate is 1, the second set input pin is 0, and the set output pin outputs a low level, no set operation is performed. It can be understood that, for the structure described in Embodiment 3, when both the first reset terminal and the first set terminal are asynchronous high-level active ports, in functional mode, or during the response data capture phase in test mode, if it is necessary to set the value in the first flip-flop to 0, then controlling the second flip-flop to output 0 is sufficient.

[0047] In functional mode, or during the response data capture phase in test mode, when the signal output by the first selector is high, if the value output by the second output terminal is 1, then the first reset input pin inputs 1. The NOT gate converts 1 to 0 and inputs it to the reset control gate from the second reset input pin. The reset output pin outputs a low level, and no reset operation is performed. When the first set input pin and the second set input pin of the set control gate input 1, the set output pin outputs a high level, setting the first flip-flop to 1. It can be understood that, for the structure described in Embodiment 3, when both the first reset terminal and the first set terminal are asynchronous high-level active ports, in functional mode, or during the response data capture phase in test mode, if it is necessary to set the value in the first flip-flop to 1, then controlling the second flip-flop to output 1 is sufficient.

[0048] Example 4

[0049] like Figure 4 As shown, the first reset terminal and the first set terminal are both asynchronous high-level active ports. The reset control gate and the set control gate are both set as AND gates, and the NOT gate is set between the second output terminal and the second set input pin.

[0050] In functional mode, or during the response data capture phase in test mode, when the signal output by the first selector is high, if the value output by the second output is 0, then the first set input pin is 1. The NOT gate converts 0 to 1 and inputs it to the set control gate from the second set input pin. The set output pin outputs a high level, setting the first flip-flop to 1. The first reset input pin of the reset control gate is 1, and both the second reset input pins are 0. The reset output pin outputs a low level, and no reset operation is performed. For the structure described in Embodiment 4, when both the first reset terminal and the first set terminal are asynchronous high-level active ports, in functional mode, or during the response data capture phase in test mode, if it is necessary to set the value in the first flip-flop to 1, then the second flip-flop can be controlled to output 0.

[0051] In functional mode, or during the response data capture phase in test mode, when the signal output by the first selector is high, if the value output by the second output is 1, then the first set input pin inputs 1. The NOT gate converts 1 to 0 and inputs it to the set control gate from the second set input pin. The set output pin outputs a low level, and no set operation is performed. The first reset input pin and the second reset input pin of the reset control gate input 1, and the reset output pin outputs a high level, resetting the first flip-flop to 0. For the structure described in Embodiment 4, when both the first reset terminal and the first set terminal are asynchronous high-level active ports, in functional mode, or during the response data capture phase in test mode, if it is necessary to set the value in the first flip-flop to 0, then the second flip-flop outputs 1.

[0052] This invention utilizes three simple logic gates—a reset control gate, a set control gate, and a NOT gate—in conjunction with a second flip-flop to control the reset and set of the first flip-flop, achieving controllable asynchronous reset state of the first flip-flop with minimal power consumption. Furthermore, this invention employs a first selector and a second selector to select different reset signals for the first and second flip-flops, making the low-power flip-flop circuit structure with controllable asynchronous reset state testable. This invention achieves both controllable asynchronous reset state of the flip-flops according to application requirements and meets the needs of low power consumption and testing.

[0053] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A low-power trigger circuit structure with controllable asynchronous reset state and a test circuit, characterized in that, It includes a first selector, a second selector, a first flip-flop, a second flip-flop, a reset control gate, a set control gate, and a NOT gate, wherein... The first input port of the first selector is used to receive the first test reset signal, the second input port of the first selector is used to receive the first function reset signal, and the enable port of the first selector is used to receive the test enable signal. When the test enable signal is high, the first input port of the first selector is turned on, and when the test enable signal is low, the second input port of the first selector is turned on. The first input port of the second selector is used to receive the second test reset signal, which is controlled by the test machine. The second input port of the second selector is used to receive the second function reset signal. The enable port of the second selector is used to receive the test enable signal. When the test enable signal is high, the first input port of the second selector is turned on. When the test enable signal is low, the second input port of the second selector is turned on. The first trigger includes a first reset terminal, a first set terminal, and a first data terminal; The second flip-flop includes a second reset terminal and a second output terminal; The reset control gate includes a first reset input pin, a second reset input pin, and a reset output pin; The set control gate includes a first set input pin, a second set input pin, and a set output pin; The first reset input pin and the first set input pin are both connected to the output of the first selector, and the second reset pin is connected to the output of the second selector; The NOT gate is set between the second output terminal and the second reset input pin, or the NOT gate is set between the second output terminal and the second set input pin; The reset output pin is connected to the first reset terminal, and the set output pin is connected to the first set terminal; The signals output from the reset output terminal and the signals output from the set output terminal are mutually exclusive. When the reset signal output from the first selector is valid, the first flip-flop is reset to 0 by the first reset terminal or set to 1 by the first set terminal. When the reset signal output from the first selector is invalid, the first flip-flop updates the value stored in the first flip-flop to the value input from the first data terminal when the rising edge of the clock connected to the first flip-flop arrives.

2. The circuit structure according to claim 1, characterized in that, In test mode, the test enable signal is high, the first input port of the first selector is turned on, and the first reset input pin and the first set input pin are both controlled by the first test reset signal; the first input port of the second selector is turned on, and the second reset terminal of the second flip-flop is controlled by the second test reset signal. During the test vector loading phase of the scan test, the value in the second flip-flop is controlled by the scan chain. During the response data capture phase of the scan test, the value in the second flip-flop remains in the last state of the scan chain or is controlled by the second test reset signal. The second reset input pin and the second set input pin are controlled by the output value of the second flip-flop.

3. The circuit structure according to claim 1, characterized in that, Both the first reset terminal and the first set terminal are asynchronous low-level active ports, and both the reset control gate and the set control gate are configured as OR gates.

4. The circuit structure according to claim 1, characterized in that, Both the first reset terminal and the first set terminal are asynchronous high-level active ports, and both the reset control gate and the set control gate are configured as AND gates.

5. The circuit structure according to claim 2, characterized in that, The first test reset signal, the second test reset signal, and the loading of the test vector are all controlled by the test machine.

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