Low power flip-flop circuit structure with controllable asynchronous reset state
By using a combinational logic gate structure consisting of a reset control gate, a set control gate, and a NOT gate, the problem of uncontrollable asynchronous reset state is solved, and a low-power flip-flop circuit structure is realized, meeting the requirements for flexible control.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 沐曦科技(成都)有限公司
- Filing Date
- 2025-07-16
- Publication Date
- 2026-04-24
AI Technical Summary
In existing technologies, the trigger reset state of asynchronous reset signals is fixed, which cannot be flexibly controlled according to application requirements, resulting in increased chip power consumption.
A combinational logic gate structure consisting of a reset control gate, a set control gate, and a NOT gate is adopted. The reset and set of the first flip-flop are controlled by the second flip-flop, thereby achieving the controllability of the asynchronous reset state and reducing power consumption through a simple logic gate structure.
It enables flexible control of the asynchronous reset state of the trigger under low power conditions according to application requirements, thus meeting the low power requirements of the circuit.
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Figure CN120811343B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip technology, and in particular to a low-power trigger circuit structure with controllable asynchronous reset state. Background Technology
[0002] The reset operation of a flip-flop can be performed synchronously or asynchronously, depending on design requirements. Synchronous reset relies on a clock signal, while asynchronous reset can take effect immediately at any time. The effective level of the reset signal also affects the behavior of the reset operation. An asynchronous reset signal can reset the flip-flop at any time, independent of the clock signal. Current technology fixes the asynchronous reset value of flip-flops; when the reset signal is active, the flip-flop is fixedly reset to 0 or 1, which is uncontrollable. However, in some applications, such as power management designs, it is necessary to reset the flip-flop to different values at different application stages, rather than a fixed value. To achieve controllable asynchronous reset states, it is usually necessary to add circuit structures, but the more components added, the higher the chip's power consumption. Therefore, how to provide a low-power flip-flop circuit structure with controllable asynchronous reset states has become an urgent technical problem to be solved. Summary of the Invention
[0003] The purpose of this invention is to provide a low-power trigger circuit structure with controllable asynchronous reset state, which can control the asynchronous reset state of the trigger according to application requirements while minimizing power consumption.
[0004] According to a first aspect of the present invention, a low-power flip-flop circuit structure with controllable asynchronous reset state is provided, comprising a first flip-flop, a second flip-flop, a reset control gate, a set control gate, and a NOT gate, wherein,
[0005] The first trigger includes a first reset terminal, a first set terminal, and a first data terminal;
[0006] The second flip-flop includes a second reset terminal and a second output terminal;
[0007] The reset control gate includes a first reset input pin, a second reset input pin, and a reset output pin;
[0008] The set control gate includes a first set input pin, a second set input pin, and a set output pin;
[0009] The first reset input pin and the first set input pin are both used to receive the first reset signal. The second reset input pin and the second set input pin are both connected to the second output terminal. The second reset terminal is used to receive the second reset signal.
[0010] The NOT gate is set between the second output terminal and the second reset input pin, or the NOT gate is set between the second output terminal and the second set input pin;
[0011] The reset output pin is connected to the first reset terminal, and the set output pin is connected to the first set terminal;
[0012] The signals output from the reset output terminal and the signals output from the set output terminal are mutually exclusive. When the first reset signal is valid, the first flip-flop is reset to 0 by the first reset terminal or set to 1 by the first set terminal. When the first reset signal is invalid, the first flip-flop updates the value stored in the first flip-flop to the value input from the first data terminal when the rising edge of the clock connected to the first flip-flop arrives.
[0013] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the low-power trigger circuit structure with controllable asynchronous reset state provided by this invention achieves considerable technological advancement and practicality, and has broad industrial application value. It has at least the following beneficial effects:
[0014] This invention uses three simple logic gates—a reset control gate, a set control gate, and a NOT gate—in conjunction with a second flip-flop to control the reset and set of a first flip-flop, achieving controllable asynchronous reset state of the first flip-flop with minimal power consumption. This invention achieves both asynchronous reset state control of the flip-flop according to application requirements and meets the low-power consumption requirements of the circuit. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 A schematic diagram of a low-power trigger circuit with controllable asynchronous reset state provided in Embodiment 1 of the present invention;
[0017] Figure 2 This is a schematic diagram of a low-power trigger circuit with controllable asynchronous reset state provided in Embodiment 2 of the present invention;
[0018] Figure 3 This is a schematic diagram of the low-power trigger circuit structure with controllable asynchronous reset state provided in Embodiment 3 of the present invention;
[0019] Figure 4 This is a schematic diagram of a low-power trigger circuit with controllable asynchronous reset state provided in Embodiment 4 of the present invention. Detailed Implementation
[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0021] This invention provides a low-power flip-flop circuit structure with controllable asynchronous reset state, including a first flip-flop, a second flip-flop, a reset control gate, a set control gate, and a NOT gate, wherein...
[0022] The first flip-flop includes a first reset terminal, a first set terminal, and a first data terminal; it is understood that the first flip-flop also includes a first output port (Q1) and a clock port (not shown in the figure) for inputting the corresponding clock signal. The second flip-flop includes a second reset terminal (R2), a second output terminal (Q2), and a second data terminal (D2); it is understood that the second flip-flop also includes a clock port (not shown in the figure) for inputting the corresponding clock signal.
[0023] The reset control gate includes a first reset input pin, a second reset input pin, and a reset output pin. The set control gate includes a first set input pin, a second set input pin, and a set output pin, and the second data terminal is connected to the combinational logic circuit.
[0024] Both the first reset input pin and the first set input pin are used to receive the first reset signal. Both the second reset input pin and the second set input pin are connected to the second output terminal. The second reset terminal is used to receive the second reset signal. The first reset signal and the second reset signal are different reset signals. The second reset signal is used to set the initial value or reset value of the second flip-flop. When the second flip-flop is in normal operating condition, the value in the second flip-flop is determined by the clock signal and data port of the second flip-flop.
[0025] The NOT gate is positioned between the second output terminal and the second reset input pin, or between the second output terminal and the second set input pin. The reset output pin is connected to the first reset terminal, and the set output pin is connected to the first set terminal. The signals output by the reset output terminal and the set output terminal are mutually exclusive. When the first reset signal is valid, the first flip-flop is reset to 0 by the first reset terminal or set to 1 by the first set terminal. That is, when the first reset signal is valid, only one of the signals output by the reset output terminal and the set output terminal will affect the value of the first flip-flop, thus realizing the controllable asynchronous reset state of the first flip-flop. When the first reset signal is invalid, the first flip-flop updates the value stored in the first flip-flop to the value input at the first data terminal when the rising edge of the clock connected to the first flip-flop arrives.
[0026] As one embodiment, the circuit structure may further include an output control circuit, the data terminal of which is connected to the second output terminal, and the output terminal of which is connected to the second reset data terminal and the second set data terminal. The output control circuit is used to adjust the value output by the second output terminal and transmit the adjusted value to the second reset data terminal and the second set data terminal, thereby increasing the flexibility of asynchronous reset state control.
[0027] The first reset terminal and the first set terminal can be configured as asynchronous active-low ports or asynchronous active-high ports. An asynchronous active-low port refers to a port that is asynchronous and performs a reset or set operation when a low level is received. An asynchronous active-high port refers to a port that is asynchronous and performs a reset or set operation when a high level is received. If both the first reset terminal and the first set terminal are asynchronous active-low ports, then both the reset control gate and the set control gate are configured as OR gates; if both the first reset terminal and the first set terminal are asynchronous active-high ports, then both the reset control gate and the set control gate are configured as AND gates.
[0028] The following are some specific examples to illustrate this.
[0029] Example 1
[0030] like Figure 1 In the example shown, both the first reset terminal and the first set terminal are asynchronous low-level active ports, and both the reset control gate and the set control gate are configured as OR gates. The NOT gate is located between the second output terminal and the second reset input pin.
[0031] When the first reset signal is low, if the value output by the second output terminal is 0, then the first reset input pin inputs 0. The NOT gate converts 0 to 1 and inputs it to the reset control gate from the second reset input pin. The reset output pin outputs a high level, and no reset operation is performed. When both the first and second set input pins of the set control gate input 0, the set output pin outputs a low level, setting the first flip-flop to 1. It can be understood that, for the structure described in Embodiment 1, when both the first reset terminal and the first set terminal are asynchronous low-level active ports, if it is necessary to set the value in the first flip-flop to 1, then controlling the second flip-flop to output 0 is sufficient.
[0032] When the first reset signal is low, if the value output by the second output terminal is 1, then the first reset input pin inputs 0. The NOT gate converts 1 to 0 and inputs it to the reset control gate from the second reset input pin. The reset output pin outputs a low level, resetting the first flip-flop to 0. When the first set input pin of the set control gate inputs 0, the second set input pin inputs 1, and the set output pin outputs a high level, no set operation is performed. It can be understood that, for the structure described in Embodiment 1, when both the first reset terminal and the first set terminal are asynchronous low-level active ports, if it is necessary to set the value in the first flip-flop to 0, then controlling the second flip-flop to output 1 is sufficient.
[0033] Example 2
[0034] like Figure 2 In the example shown, both the first reset terminal and the first set terminal are asynchronous low-level active ports, and both the reset control gate and the set control gate are configured as OR gates. The NOT gate is located between the second output terminal and the second set input pin.
[0035] When the first reset signal is low, if the value output by the second output terminal is 0, then the first set input pin inputs 0. The NOT gate converts 0 to 1 and inputs it to the set control gate from the second set input pin. The set output pin outputs a high level, and no set operation is performed. The first reset input pin and the second reset input pin of the reset control gate both input 0, and the reset output pin outputs a low level, resetting the first flip-flop to 0. It can be understood that, for the structure described in Embodiment 2, when both the first reset terminal and the first set terminal are asynchronous low-level active ports, if it is necessary to set the value in the first flip-flop to 0, then controlling the second flip-flop to output 0 is sufficient.
[0036] When the first reset signal is low, if the value output by the second output terminal is 1, then the first set input pin inputs 0. The NOT gate converts 1 to 0 and inputs it to the set control gate from the second set input pin. The set output pin outputs a low level, setting the first flip-flop to 1. The first reset input pin of the reset control gate inputs 0, the second reset input pin inputs 1, and the reset output pin outputs a high level, so no reset operation is performed. It can be understood that, for the structure described in Embodiment 2, when both the first reset terminal and the first set terminal are asynchronous low-level active ports, if it is necessary to set the value in the first flip-flop to 1, then controlling the second flip-flop to output 1 is sufficient.
[0037] Example 3
[0038] like Figure 3 In the example shown, both the first reset terminal and the first set terminal are asynchronous high-level active ports, both the reset control gate and the set control gate are set as AND gates, and the NOT gate is set between the second output terminal and the second reset input pin.
[0039] When the first reset signal is high, if the value output by the second output terminal is 0, then the first reset input pin inputs 1. The NOT gate converts 0 to 1 and inputs it to the reset control gate from the second reset input pin. The reset output pin outputs a high level, resetting the first flip-flop to 0. When the first set input pin of the set control gate inputs 1, the second set input pin inputs 0, and the set output pin outputs a low level, no set operation is performed. It can be understood that, for the structure described in Embodiment 3, when both the first reset terminal and the first set terminal are asynchronous high-level active ports, if it is necessary to set the value in the first flip-flop to 0, then controlling the second flip-flop to output 0 is sufficient.
[0040] When the first reset signal is high, if the value output by the second output terminal is 1, then the first reset input pin inputs 1. The NOT gate converts 1 to 0 and inputs it to the reset control gate from the second reset input pin. The reset output pin outputs a low level, and no reset operation is performed. When the first set input pin and the second set input pin of the set control gate input 1, the set output pin outputs a high level, setting the first flip-flop to 1. It can be understood that, for the structure described in Embodiment 3, when both the first reset terminal and the first set terminal are asynchronous high-level active ports, if it is necessary to set the value in the first flip-flop to 1, then controlling the second flip-flop to output 1 is sufficient.
[0041] Example 4
[0042] like Figure 4In the example shown, both the first reset terminal and the first set terminal are asynchronous high-level active ports, both the reset control gate and the set control gate are set as AND gates, and the NOT gate is set between the second output terminal and the second set input pin.
[0043] When the first reset signal is high, if the value output by the second output terminal is 0, then the first set input pin is 1. The NOT gate converts 0 to 1 and inputs it to the set control gate from the second set input pin. The set output pin outputs a high level, setting the first flip-flop to 1. The first reset input pin of the reset control gate is 1, the second reset input pin is 0, and the reset output pin outputs a low level, so no reset operation is performed. For the structure described in Embodiment 4, when both the first reset terminal and the first set terminal are asynchronous high-level active ports, if it is necessary to set the value in the first flip-flop to 1, then the second flip-flop outputs 0.
[0044] When the first reset signal is high, if the value output by the second output terminal is 1, then the first set input pin inputs 1. The NOT gate converts 1 to 0 and inputs it to the set control gate from the second set input pin. The set output pin outputs a low level, and no set operation is performed. The first reset input pin and the second reset input pin of the reset control gate input 1, and the reset output pin outputs a high level, resetting the first flip-flop to 0. For the structure described in Embodiment 4, when both the first reset terminal and the first set terminal are asynchronous high-level active ports, if it is necessary to set the value in the first flip-flop to 0, then controlling the second flip-flop to output 1 is sufficient.
[0045] This invention utilizes three simple logic gates—a reset control gate, a set control gate, and a NOT gate—in conjunction with a second flip-flop to control the reset and set of a first flip-flop. This achieves controllable asynchronous reset state of the first flip-flop with minimal power consumption. This invention both enables control of the asynchronous reset state of the flip-flop according to application requirements and meets the low-power consumption requirements of the circuit.
[0046] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A low-power trigger circuit structure with controllable asynchronous reset state, characterized in that, It includes a first flip-flop, a second flip-flop, a reset control gate, a set control gate, and a NOT gate, wherein, The first trigger includes a first reset terminal, a first set terminal, and a first data terminal; The second flip-flop includes a second reset terminal and a second output terminal; The reset control gate includes a first reset input pin, a second reset input pin, and a reset output pin; The set control gate includes a first set input pin, a second set input pin, and a set output pin; The first reset input pin and the first set input pin are both used to receive the first reset signal. The second reset input pin and the second set input pin are both connected to the second output terminal. The second reset terminal is used to receive the second reset signal. The NOT gate is set between the second output terminal and the second reset input pin, or the NOT gate is set between the second output terminal and the second set input pin; The reset output pin is connected to the first reset terminal, and the set output pin is connected to the first set terminal; The signals output from the reset output pin and the set output pin are mutually exclusive. When the first reset signal is valid, the first flip-flop is reset to 0 by the first reset terminal or set to 1 by the first set terminal. When the first reset signal is invalid, the first flip-flop updates the value stored in the first flip-flop to the value input from the first data terminal when the rising edge of the clock connected to the first flip-flop arrives.
2. The circuit structure according to claim 1, characterized in that, If both the first reset terminal and the first set terminal are asynchronous low-level active ports, then both the reset control gate and the set control gate are set as OR gates; if both the first reset terminal and the first set terminal are asynchronous high-level active ports, then both the reset control gate and the set control gate are set as AND gates.
3. The circuit structure according to claim 2, characterized in that, Both the first reset terminal and the first set terminal are asynchronous low-level active ports. The NOT gate is located between the second output terminal and the second reset input pin. When the first reset signal is low, if the value output by the second output terminal is 0, then the first reset input pin inputs 0. The NOT gate converts 0 to 1 and inputs it to the reset control gate from the second reset input pin. The reset output pin outputs a high level, and no reset operation is performed. The first set input pin and the second set input pin of the set control gate both input 0, and the set output pin outputs a low level, setting the first flip-flop to 1.
4. The circuit structure according to claim 2, characterized in that, Both the first reset terminal and the first set terminal are asynchronous low-level active ports. The NOT gate is located between the second output terminal and the second reset input pin. When the first reset signal is low, if the value output by the second output terminal is 1, then the first reset input pin inputs 0. The NOT gate converts 1 to 0 and inputs it to the reset control gate from the second reset input pin. The reset output pin outputs a low level, resetting the first flip-flop to 0. The first set input pin of the set control gate inputs 0, the second set input pin inputs 1, and the set output pin outputs a high level, so the set operation is not performed.
5. The circuit structure according to claim 2, characterized in that, Both the first reset terminal and the first set terminal are asynchronous low-level active ports. The NOT gate is located between the second output terminal and the second set input pin. When the first reset signal is low, if the value output by the second output terminal is 0, then the first set input pin inputs 0. The NOT gate converts 0 to 1 and inputs it to the set control gate from the second set input pin. The set output pin outputs a high level, and no set operation is performed. The first reset input pin and the second reset input pin of the reset control gate both input 0, and the reset output pin outputs a low level, resetting the first flip-flop to 0.
6. The circuit structure according to claim 2, characterized in that, Both the first reset terminal and the first set terminal are asynchronous low-level active ports. The NOT gate is located between the second output terminal and the second set input pin. When the first reset signal is low, if the value output by the second output terminal is 1, then the first set input pin inputs 0. The NOT gate converts 1 to 0 and inputs it to the set control gate from the second set input pin. The set output pin outputs a low level, setting the first flip-flop to 1. The first reset input pin of the reset control gate inputs 0, the second reset input pin inputs 1, and the reset output pin outputs a high level, so no reset operation is performed.
7. The circuit structure according to claim 2, characterized in that, Both the first reset terminal and the first set terminal are asynchronous high-level active ports. The NOT gate is located between the second output terminal and the second reset input pin. When the first reset signal is high, if the value output by the second output terminal is 0, then the first reset input pin inputs 1. The NOT gate converts 0 to 1 and inputs it to the reset control gate from the second reset input pin. The reset output pin outputs a high level, resetting the first flip-flop to 0. The first set input pin of the set control gate inputs 1, the second set input pin inputs 0, and the set output pin outputs a low level, so the set operation is not performed.
8. The circuit structure according to claim 2, characterized in that, Both the first reset terminal and the first set terminal are asynchronous high-level active ports. The NOT gate is located between the second output terminal and the second reset input pin. When the first reset signal is high, if the value output by the second output terminal is 1, then the first reset input pin inputs 1. The NOT gate converts 1 to 0 and inputs it to the reset control gate from the second reset input pin. The reset output pin outputs a low level, and no reset operation is performed. The first set input pin of the set control gate inputs 1, the second set input pin inputs 1, and the set output pin outputs a high level, setting the first flip-flop to 1.
9. The circuit structure according to claim 2, characterized in that, Both the first reset terminal and the first set terminal are asynchronous high-level active ports. The NOT gate is located between the second output terminal and the second set input pin. When the first reset signal is high, if the value output by the second output terminal is 0, then the first set input pin inputs 1. The NOT gate converts 0 to 1 and inputs it to the set control gate from the second set input pin. The set output pin outputs a high level, setting the first flip-flop to 1. The first reset input pin of the reset control gate inputs 1, the second reset input pin inputs 0, and the reset output pin outputs a low level, so no reset operation is performed.
10. The circuit structure according to claim 2, characterized in that, Both the first reset terminal and the first set terminal are asynchronous high-level active ports. The NOT gate is located between the second output terminal and the second set input pin. When the first reset signal is high, if the value output by the second output terminal is 1, then the first set input pin inputs 1. The NOT gate converts 1 to 0 and inputs it to the set control gate from the second set input pin. The set output pin outputs a low level, and no set operation is performed. The first reset input pin of the reset control gate inputs 1, the second reset input pin inputs 1, and the reset output pin outputs a high level, resetting the first flip-flop to 0.
Citation Information
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