Flip-flop circuit structure with test circuit and controllable asynchronous reset state

Abstract

The application relates to the chip technical field, in particular to a flip-flop circuit structure with a test circuit and an asynchronous reset state controllable, which comprises a first reset control circuit, a second reset control circuit, M groups of asynchronous reset state controllable flip-flop circuits {A1, A2,..., A m ,...,A M}, A m is the mth asynchronous reset state controllable flip-flop circuit; the first reset control circuit is used for providing a first test reset signal for each A m in a test mode and providing a first function reset signal for each A m in a function mode; the second reset control circuit is used for providing a second test reset signal for each A m in the test mode and providing a second function reset signal for each A m in the function mode. The application can control the asynchronous reset state of the flip-flop according to application requirements, and can realize the test of the asynchronous reset state controllable flip-flop circuit structure.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a trigger circuit structure with an asynchronous reset state controllable and a test circuit. Background Technology

[0002] The reset operation of a flip-flop can be performed synchronously or asynchronously, depending on the design requirements. Synchronous reset relies on a clock signal, while asynchronous reset can take effect immediately at any time. The effective level of the reset signal also affects the behavior of the reset operation. An asynchronous reset signal can reset the flip-flop at any time, independent of the clock signal. Current technology fixes the asynchronous reset value of flip-flops; when the reset signal is active, the flip-flop is fixedly reset to 0 or 1, which is uncontrollable. However, in some applications, such as power management designs, it is necessary to reset the flip-flop to different values ​​at different application stages, rather than a fixed value. To achieve controllable asynchronous reset state of the flip-flop, further circuitry is required. To meet testing requirements, it is also necessary to test the flip-flop circuit structure with controllable asynchronous reset state after adding the circuitry. Therefore, providing a flip-flop circuit structure with controllable asynchronous reset state and integrated testing circuitry is a pressing technical problem that needs to be solved. Summary of the Invention

[0003] The purpose of this invention is to provide a trigger circuit structure with controllable asynchronous reset state, which can control the asynchronous reset state of the trigger according to application requirements and can realize the testing of the trigger circuit structure with controllable asynchronous reset state.

[0004] This invention provides a controllable asynchronous reset state trigger circuit structure with a test circuit, including a first reset control circuit, a second reset control circuit, and M sets of controllable asynchronous reset state trigger circuits {A1, A2, ..., A...}. m ,...,A M},A m Let m be the m-th asynchronous reset state controllable flip-flop circuit, where m ranges from 1 to M, and M is the total number of asynchronous reset state controllable flip-flop circuits.

[0005] The first reset control circuit is used to reset each A in test mode. m Provides a first test reset signal, for each A in functional mode. m Provides a first function reset signal; the second reset control circuit is used to provide a reset signal for each A in test mode. m Provide a second test reset signal, for each A in functional mode. m Provides a second function reset signal;

[0006] The first reset control circuit includes a first selector. The first input port of the first selector is used to receive a first test reset signal, the second input port of the first selector is used to receive a first function reset signal, and the enable port of the first selector is used to receive a test enable signal. When the test enable signal is high, the first input port of the first selector is turned on, and when the test enable signal is low, the second input port of the first selector is turned on.

[0007] The second reset control circuit includes a second selector. The first input port of the second selector is used to receive a second test reset signal, the second input port of the second selector is used to receive a second function reset signal, and the enable port of the second selector is used to receive a test enable signal. When the test enable signal is high, the first input port of the second selector is turned on, and when the test enable signal is low, the second input port of the second selector is turned on.

[0008] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the asynchronous reset state controllable trigger circuit structure with test circuit provided by this invention achieves considerable technological advancement and practicality, and has broad industrial application value. It has at least the following beneficial effects:

[0009] This invention sets up a first reset control circuit and a second reset control circuit to simultaneously control the reset signals of multiple sets of asynchronous reset state controllable trigger circuits. This allows each asynchronous reset state controllable trigger circuit to be controlled by a first functional reset signal and a second functional reset signal in functional mode, and by a first test reset signal and a second test reset signal in test mode. This invention simplifies the test circuit structure for asynchronous reset state controllable trigger circuits, enables control of the asynchronous reset state of the triggers according to application requirements, and allows for testing of asynchronous reset state controllable trigger circuit structures. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A schematic diagram of an asynchronous reset state controllable trigger circuit with test circuit provided in an embodiment of the present invention;

[0012] Figure 2 A provided in an embodiment of the present invention m A schematic diagram of the circuit structure;

[0013] Figure 3 A provided in Embodiment 1 of the present invention m A schematic diagram of the circuit structure;

[0014] Figure 4 A provided in Embodiment 2 of the present invention m A schematic diagram of the circuit structure;

[0015] Figure 5 A provided in Embodiment 3 of the present invention m A schematic diagram of the circuit structure;

[0016] Figure 6 A provided in Embodiment 4 of the present invention m The circuit structure diagram is shown. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] This invention provides a trigger circuit structure with an asynchronous reset state controllable, such as... Figure 1 As shown, it includes a first reset control circuit (U1), a second reset control circuit (U2), and M sets of asynchronous reset state controllable trigger circuits {A1,A2,...,A... m ,...,A M},A m Let m be the m-th asynchronous reset-state controllable trigger circuit, where m ranges from 1 to M, and M is the total number of asynchronous reset-state controllable trigger circuits. An asynchronous reset-state controllable trigger circuit refers to a circuit that can control the value stored in the reset trigger according to application requirements.

[0019] The first reset control circuit is used to reset each A in test mode. m Provides a first test reset signal, for each A in functional mode. m Provides a first function reset signal; the second reset control circuit is used to provide a reset signal for each A in test mode. m Provide a second test reset signal, for each A in functional mode. m A second functional reset signal is provided. Therefore, embodiments of the present invention can simultaneously control the reset signals of multiple asynchronous reset state controllable trigger circuits using a first reset control circuit and a second reset control circuit, greatly simplifying the circuit structure.

[0020] The first reset control circuit includes a first selector. The first input port (1) of the first selector is used to receive a first test reset signal, and the second input port (0) of the first selector is used to receive a first functional reset signal. The enable port of the first selector is used to receive a test enable signal. When the test enable signal is high, the first input port of the first selector is turned on; when the test enable signal is low, the second input port of the first selector is turned on. It should be noted that the first test reset signal is a signal used to control the reset in test mode, and the first functional reset signal is a signal used to control the reset in functional mode.

[0021] The second reset control circuit includes a second selector. The first input port (1) of the second selector is used to receive a second test reset signal, and the second input port (0) of the second selector is used to receive a second functional reset signal. The enable port of the second selector is used to receive a test enable signal. When the test enable signal is high, the first input port of the second selector is turned on; when the test enable signal is low, the second input port of the second selector is turned on. It should be noted that the second test reset signal is a signal used to control the reset in test mode, and the second functional reset signal is a signal used to control the reset in functional mode.

[0022] As one embodiment, both the first test reset signal and the second test reset signal are controlled by the test machine. The first test reset signal and the second test reset signal can be two independent signals or the same signal, depending on the specific requirements.

[0023] As one example, such as Figure 2 As shown, A m The system includes a first flip-flop, a second flip-flop, a reset setting module, and a set setting module. The first flip-flop includes a first reset terminal (R1), a first set terminal (S1), and a first data terminal (D1). It is understood that the first flip-flop also includes a clock port (not shown in the figure) for inputting a corresponding clock signal. The second flip-flop includes a second reset terminal (R2), a second output terminal (Q2), and a second data terminal (D2). It is understood that the second flip-flop also includes a clock port (not shown in the figure) for inputting a corresponding clock signal.

[0024] The reset setting module includes a first reset data terminal, a second reset data terminal, and a reset output terminal; the set setting module includes a first set data terminal, a second set data terminal, and a set output terminal, with the second data terminal connected to the combinational logic circuit.

[0025] Both the first reset data terminal and the first set data terminal are connected to the output terminal of the first selector to receive the reset signal output by the first selector. Both the second reset data terminal and the second set data terminal are connected to the second output terminal to receive the reset signal output by the second selector. The reset output terminal is connected to the first reset terminal, the set output terminal is connected to the first set terminal, and the second reset terminal is connected to the output terminal of the second selector. The second reset signal is used to set the initial value or reset value of the second flip-flop. When the second flip-flop is in normal operating condition, the value in the second flip-flop is determined by the clock signal and data port of the second flip-flop.

[0026] The signals output from the reset output terminal and the set output terminal are mutually exclusive. When the reset signal output from the first selector is valid, the first flip-flop is either reset to 0 by the first reset terminal or set to 1 by the first set terminal. That is, when the first reset signal is valid, only one of the signals output from the reset output terminal and the set output terminal will affect the value of the first flip-flop, thus realizing the controllable asynchronous reset state of the first flip-flop. When the reset signal output from the first selector is invalid, neither the signal output from the reset output terminal nor the signal output from the set output terminal will affect the value of the first flip-flop. When the rising edge of the clock connected to the first flip-flop arrives, the first flip-flop updates the value stored in the first flip-flop to the value input from the first data terminal.

[0027] As one embodiment, the circuit structure may further include an output control circuit, the data terminal of which is connected to the second output terminal, and the output terminal of which is connected to the second reset data terminal and the second set data terminal. The output control circuit is used to adjust the value output by the second output terminal and transmit the adjusted value to the second reset data terminal and the second set data terminal, thereby increasing the flexibility of asynchronous reset state control.

[0028] As one embodiment, in test mode, the test enable signal is high, the first input port of the first selector is turned on, and the first selector outputs a first test reset signal. Each A m The first reset data terminal and the first set data terminal are both controlled by the first test reset signal; when the first input port of the second selector is turned on, the second selector outputs the second test reset signal, and each A m The second reset terminal of the second flip-flop is controlled by the second test reset signal.

[0029] During the test vector loading phase (Scan Shift) of the scan test, the triggers are chained together to form a scan chain, and the values ​​in the second triggers are controlled by the scan chain. During the response data capture phase (Scan Capture) of the scan test, the values ​​in the second triggers remain in the last state of the scan chain or are controlled by the second test reset signal, for each A... mThe second reset data terminal and the second set data terminal are controlled by the output value of the second flip-flop.

[0030] It should be noted that, in test mode, both the first test reset signal and the second test reset signal are controlled by the test equipment, and the loading of the test vector is also controlled by the test equipment. This makes the first and second reset data terminals of the reset setting module measurable, thereby making the fan-in path of the first reset terminal of the first flip-flop measurable. It also makes the first and second set data terminals of the set setting module measurable, thereby making the fan-in path of the first set terminal of the first flip-flop measurable. Furthermore, it makes the second reset terminal of the second flip-flop measurable. The circuit structure described in this embodiment of the invention enables the testability of the asynchronous reset state controllable flip-flop circuit structure in test mode, improving test coverage.

[0031] The first reset terminal and the first set terminal can be configured as asynchronous active-low ports or asynchronous active-high ports. An asynchronous active-low port refers to a port that is asynchronous and performs a reset or set operation when a low level is received. An asynchronous active-high port refers to a port that is asynchronous and performs a reset or set operation when a high level is received. Several specific embodiments are described below.

[0032] Example 1

[0033] like Figure 3 In the example shown, both the first reset terminal and the first set terminal are asynchronous low-level active ports.

[0034] The setting module includes a third selector. The first input port of the third selector is set as the first set data terminal, the second input port of the third selector is fixedly connected to a high level, the enable port of the third selector is set as the second set data terminal, and the output terminal of the third selector is set as the set output terminal. When the enable port input of the third selector is 1, the first input port of the third selector is turned on; when the enable port input of the third selector is 0, the second input port of the third selector is turned on.

[0035] The reset setting module includes a fourth selector and an inverter. The first input port of the fourth selector is set as the first reset data terminal, and the second input port of the fourth selector is fixedly connected to a high level. The enable terminal of the fourth selector is connected to the output terminal of the inverter, the data terminal of the inverter is set as the second reset data terminal, and the output terminal of the fourth selector is set as the reset output terminal. When the enable port input of the fourth selector is 1, the first input port of the fourth selector is turned on; when the enable port input of the third selector is 0, the second input port of the third selector is turned on.

[0036] In functional mode, or during the response data capture phase in test mode, when the signal output by the first selector is low and the value output by the second output is 0, the enable port input of the third selector is 0, the second input port of the third selector is enabled, the set output is high, and no set operation is performed. After the inverter input is 0, the output is 1, the enable port input of the fourth selector is 1, the first input port of the fourth selector is enabled, the reset output is low, and the first flip-flop is reset to 0. It can be understood that, for the structure described in Embodiment 1, when both the first reset port and the first set port are asynchronous low-level active ports, in functional mode, or during the response data capture phase in test mode, if it is necessary to set the value in the first flip-flop to 0, then controlling the second flip-flop to output 0 is sufficient.

[0037] In functional mode, or during the response data capture phase in test mode, when the signal output by the first selector is low and the value output by the second output terminal is 1, the enable port input of the third selector is 1, the first input port of the third selector is turned on, the set output terminal is low, and the first flip-flop is set to 1. After the inverter input is 1, the output is 0, the enable port input of the fourth selector is 0, the second input port of the fourth selector is turned on, and the reset output terminal is high, without performing a reset operation. It can be understood that, for the structure described in Embodiment 1, when both the first reset terminal and the first set terminal are asynchronous low-level active ports, in functional mode, or during the response data capture phase in test mode, if it is necessary to set the value in the first flip-flop to 1, then controlling the second flip-flop to output 1 is sufficient.

[0038] Example 2

[0039] like Figure 4 In the example shown, both the first reset terminal and the first set terminal are asynchronous low-level active ports.

[0040] The set-position module includes a third selector and an inverter. The first input port of the third selector is set as the first reset data terminal, and the second input port of the third selector is fixedly connected to a high level. The enable port of the third selector is connected to the output terminal of the inverter. The data terminal of the inverter is set as the second set data terminal, and the output terminal of the third selector is set as the set output terminal. When the enable port input of the third selector is 1, the first input port of the third selector is turned on; when the enable port input of the third selector is 0, the second input port of the third selector is turned on.

[0041] The reset setting module includes a fourth selector. The first input port of the fourth selector is set as the first reset data terminal, the second input port of the fourth selector is set to a fixed high level, the enable terminal of the fourth selector is set as the second reset data terminal, and the output terminal of the fourth selector is set as the reset output terminal. When the enable port input of the fourth selector is 1, the first input port of the fourth selector is turned on; when the enable port input of the third selector is 0, the second input port of the third selector is turned on.

[0042] The first reset and first set terminals can be configured as asynchronous active-low ports or asynchronous active-high ports. An asynchronous active-low port is an asynchronous port that performs a reset or set operation upon receiving a low level. An asynchronous active-high port is an asynchronous port that performs a reset or set operation upon receiving a high level. The following explanations will cover different scenarios.

[0043] In functional mode, or during the response data capture phase in test mode, when the signal output by the first selector is low and the value output by the second output terminal is 0, the inverter outputs 1 after inputting 0, the enable port input of the third selector is 1, the first input port of the third selector is enabled, the set output terminal outputs low, and the first flip-flop is set to 1. The enable port input of the fourth selector is 0, the second input port of the fourth selector is enabled, the reset output terminal is high, and no reset operation is performed. It can be understood that, for the structure described in Embodiment 2, when both the first reset terminal and the first set terminal are asynchronous low-level active ports, if it is necessary to set the value in the first flip-flop to 1, then controlling the second flip-flop to output 0 is sufficient.

[0044] In functional mode, or during the response data capture phase in test mode, when the signal output by the first selector is low and the value output by the second output terminal is 1, the inverter outputs 0 after inputting 1. Therefore, the enable port input of the third selector is 0, the second input port of the third selector is turned on, and the set output terminal is high, without performing a set operation. When the enable port input of the fourth selector is 1, the first input port of the fourth selector is turned on, the reset output terminal is low, and the first flip-flop is reset to 0. It can be understood that, for the structure described in Embodiment 2, when both the first reset terminal and the first set terminal are asynchronous low-level active ports, in functional mode, or during the response data capture phase in test mode, if it is necessary to set the value in the first flip-flop to 0, then controlling the second flip-flop to output 1 is sufficient.

[0045] Example 3

[0046] like Figure 5In the example shown, both the first reset terminal and the first set terminal are asynchronous high-level active ports.

[0047] The setting module includes a third selector. The first input port of the third selector is set as the first set data terminal, the second input port of the third selector is fixed at a low level, the enable port of the third selector is set as the second set data terminal, and the output terminal of the third selector is set as the set output terminal. When the enable port input of the third selector is 1, the first input port of the third selector is turned on; when the enable port input of the third selector is 0, the second input port of the third selector is turned on.

[0048] The reset setting module includes a fourth selector and an inverter. The first input port of the fourth selector is set as the first reset data terminal, and the second input port of the fourth selector is fixedly connected to a low level. The enable terminal of the fourth selector is connected to the output terminal of the inverter, the data terminal of the inverter is set as the second reset data terminal, and the output terminal of the fourth selector is set as the reset output terminal. When the enable port input of the fourth selector is 1, the first input port of the fourth selector is turned on; when the enable port input of the third selector is 0, the second input port of the third selector is turned on.

[0049] In functional mode, or during the response data capture phase in test mode, when the signal output by the first selector is high and the value output by the second output is 0, the enable port input of the third selector is 0, the second input port of the third selector is enabled, and the set output is low, without performing a set operation. After the inverter input is 0, the output is 1, the enable port input of the fourth selector is 1, the first input port of the fourth selector is enabled, the reset output is high, and the first flip-flop is reset to 0. It can be understood that, for the structure described in Embodiment 3, when both the first reset port and the first set port are asynchronous high-level active ports, in functional mode, or during the response data capture phase in test mode, if it is necessary to set the value in the first flip-flop to 0, then controlling the second flip-flop to output 0 is sufficient.

[0050] In functional mode, or during the response data capture phase in test mode, when the signal output by the first selector is high and the value output by the second output terminal is 1, the enable port input of the third selector is 1, the first input port of the third selector is turned on, the set output terminal is high, and the first flip-flop is set to 1. After the inverter input is 1, the output is 0, the enable port input of the fourth selector is 0, the second input port of the fourth selector is turned on, and the reset output terminal is low, so no reset operation is performed. It can be understood that, for the structure described in Embodiment 3, when both the first reset terminal and the first set terminal are asynchronous high-level active ports, in functional mode, or during the response data capture phase in test mode, if it is necessary to set the value in the first flip-flop to 1, then controlling the second flip-flop to output 1 is sufficient.

[0051] Example 4

[0052] like Figure 6 In the example shown, both the first reset terminal and the first set terminal are asynchronous high-level active ports.

[0053] The set-position module includes a third selector and an inverter. The first input port of the third selector is set to the first reset data terminal, and the second input port of the third selector is fixedly connected to a low level. The enable port of the third selector is connected to the output terminal of the inverter. The data terminal of the inverter is set to the second set data terminal, and the output terminal of the third selector is set to the set output terminal. When the enable port input of the third selector is 1, the first input port of the third selector is turned on; when the enable port input of the third selector is 0, the second input port of the third selector is turned on.

[0054] The reset setting module includes a fourth selector. The first input port of the fourth selector is set to the first reset data terminal, the second input port of the fourth selector is set to a fixed low level, the enable terminal of the fourth selector is set to the second reset data terminal, and the output terminal of the fourth selector is set to the reset output terminal. When the enable port input of the fourth selector is 1, the first input port of the fourth selector is turned on; when the enable port input of the third selector is 0, the second input port of the third selector is turned on.

[0055] In functional mode, or during the response data capture phase in test mode, when the signal output by the first selector is high and the value output by the second output terminal is 0, the inverter outputs 1 after inputting 0, the enable port input of the third selector is 1, the first input port of the third selector is enabled, the set output terminal outputs high, and the first flip-flop is set to 1. When the enable port input of the fourth selector is 0, the second input port of the fourth selector is enabled, and the reset output terminal is low, without performing a reset operation. It can be understood that, for the structure described in Embodiment 4, when both the first reset terminal and the first set terminal are asynchronous high-level active ports, in functional mode, or during the response data capture phase in test mode, if it is necessary to set the value in the first flip-flop to 1, then controlling the second flip-flop to output 0 is sufficient.

[0056] In functional mode or during the response data capture phase of test mode, when the signal output by the first selector is high and the value output by the second output terminal is 1, the inverter outputs 0 after inputting 1. Therefore, the enable port input of the third selector is 0, the second input port of the third selector is turned on, and the set output terminal is low, without performing a set operation. When the enable port input of the fourth selector is 1, the first input port of the fourth selector is turned on, the reset output terminal is high, and the first flip-flop is reset to 0. It can be understood that, for the structure described in Embodiment 4, when both the first reset terminal and the first set terminal are asynchronous high-level active ports, in functional mode or during the response data capture phase of test mode, if it is necessary to set the value in the first flip-flop to 0, then controlling the second flip-flop to output 1 is sufficient.

[0057] This invention, through the provision of a first reset control circuit and a second reset control circuit, simultaneously controls the reset signals of multiple sets of asynchronous reset state controllable trigger circuits. This allows each asynchronous reset state controllable trigger circuit to be controlled by a first functional reset signal and a second functional reset signal in functional mode, and by a first test reset signal and a second test reset signal in test mode. This invention simplifies the test circuit structure for asynchronous reset state controllable trigger circuits, enabling control of the asynchronous reset state of the triggers according to application requirements, and facilitating the testing of asynchronous reset state controllable trigger circuit structures.

[0058] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A trigger circuit structure with an asynchronous reset state controllable and a test circuit, characterized in that, Includes a first reset control circuit, a second reset control circuit, and M sets of asynchronous reset state controllable trigger circuits {A1, A2, ..., A... m ,...,A M },A m Let m be the m-th asynchronous reset state controllable flip-flop circuit, where m ranges from 1 to M, and M is the total number of asynchronous reset state controllable flip-flop circuits. The first reset control circuit is used to reset each A in test mode. m Provides a first test reset signal, for each A in functional mode. m Provides a first function reset signal; the second reset control circuit is used to provide a reset signal for each A in test mode. m Provide a second test reset signal, for each A in functional mode. m Provides a second function reset signal; The first reset control circuit includes a first selector. The first input port of the first selector is used to receive a first test reset signal, the second input port of the first selector is used to receive a first function reset signal, and the enable port of the first selector is used to receive a test enable signal. When the test enable signal is high, the first input port of the first selector is turned on, and when the test enable signal is low, the second input port of the first selector is turned on. The second reset control circuit includes a second selector. The first input port of the second selector is used to receive a second test reset signal, the second input port of the second selector is used to receive a second function reset signal, and the enable port of the second selector is used to receive a test enable signal. When the test enable signal is high, the first input port of the second selector is turned on, and when the test enable signal is low, the second input port of the second selector is turned on. A m It includes a first trigger, a second trigger, a reset setting module, and a set setting module, wherein, The first trigger includes a first reset terminal, a first set terminal, and a first data terminal; The second flip-flop includes a second reset terminal and a second output terminal; The reset setting module includes a first reset data terminal, a second reset data terminal, and a reset output terminal; The setting module includes a first setting data terminal, a second setting data terminal, and a setting output terminal; The first reset data terminal and the first set data terminal are both connected to the output terminal of the first selector. The second reset data terminal and the second set data terminal are both connected to the second output terminal. The reset output terminal is connected to the first reset terminal, the set output terminal is connected to the first set terminal, and the second reset terminal is connected to the output terminal of the second selector. The signals output from the reset output terminal and the signals output from the set output terminal are mutually exclusive. When the reset signal output from the first selector is valid, the first flip-flop is reset to 0 by the first reset terminal or set to 1 by the first set terminal. When the reset signal output from the first selector is invalid, the first flip-flop updates the value stored in the first flip-flop to the value input from the first data terminal when the rising edge of the clock connected to the first flip-flop arrives.

2. The circuit structure according to claim 1, characterized in that, Both the first test reset signal and the second test reset signal are controlled by the test machine.

3. The circuit structure according to claim 1, characterized in that, In test mode, the test enable signal is high, the first input port of the first selector is turned on, and each A m The first reset data terminal and the first set data terminal are both controlled by the first test reset signal; the first input port of the second selector is turned on, and each A m The second reset terminal of the second flip-flop is controlled by the second test reset signal; During the test vector loading phase of the scan test, the value in the second trigger is controlled by the scan chain. During the response data capture phase of the scan test, the value in the second trigger remains in the last state of the scan chain or is controlled by the second test reset signal. Each A m The second reset data terminal and the second set data terminal are controlled by the output value of the second flip-flop.

4. The circuit structure according to claim 3, characterized in that, The loading of the test vector is controlled by the test machine.

5. The circuit structure according to claim 1, characterized in that, Both the first reset terminal and the first set terminal are active low-level ports.

6. The circuit structure according to claim 1, characterized in that, Both the first reset terminal and the first set terminal are active high-level ports.

7. The circuit structure according to claim 3, characterized in that, The circuit structure also includes an output control circuit, the data terminal of which is connected to the second output terminal, and the output terminal of which is connected to the second reset data terminal or the second set data terminal.

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