A device switching apparatus, heterogeneous acceleration apparatus and system

Abstract

The application discloses a device switching device, a heterogeneous acceleration device and a system, and relates to the technical field of computers. The application can switch a downlink port on an exchange device into an uplink port without adjusting any hardware architecture, so that a downlink device originally connected to the downlink port is switched into an uplink device, flexible expansion of the uplink device of the heterogeneous acceleration system is realized, and the application flexibility of the heterogeneous acceleration system is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, and in particular to a device switching apparatus, a heterogeneous acceleration apparatus and system. BACKGROUND

[0002] A heterogeneous acceleration system combines multiple computing units with different architectures and different functional characteristics, so that each computing unit focuses on the type of task it is good at, and multiple computing units work together to complete complex computing tasks.

[0003] In related technologies, a heterogeneous acceleration system usually connects an uplink device and a downlink device through an uplink and downlink based on a switching device, and the uplink device includes a central processing unit and the like. However, in actual application, if the existing uplink device cannot meet the business requirements, the heterogeneous acceleration system needs to be adjusted in hardware architecture and the added uplink device needs to be manually inserted, and the whole architecture adjustment process is relatively cumbersome, which reduces the application flexibility of the heterogeneous acceleration system. SUMMARY

[0004] The present application provides a device switching apparatus, a heterogeneous acceleration apparatus and system to at least solve the problem of reducing the application flexibility of the heterogeneous acceleration system in related technologies.

[0005] The present application provides a device switching apparatus, including a multiplexing switch, a cache bank, a switching core unit, a downlink port and a first signal control unit, wherein the switching core unit establishes a firmware transmission link with different caches in the cache bank through the multiplexing switch, the switching core unit is connected to the downlink port through a data transmission link, and the first signal control unit is connected to the downlink port through an auxiliary signal transmission link.

[0006] The multiplexing switch is configured to, when a first mode switching signal is obtained, connect a first firmware transmission link in the firmware transmission link in response to the first mode switching signal.

[0007] The switching core unit is configured to load downlink port mode switching firmware from a first cache in the cache bank based on the first firmware transmission link, and switch any downlink port to an uplink port based on the downlink port mode switching firmware, and the first cache is configured to cache the downlink port mode switching firmware.

[0008] The first signal control unit is configured to, when the first mode switching signal is obtained, screen a target auxiliary signal from the auxiliary signal, and load a first signal mode switching firmware from a first internal firmware cache to correspondingly modify the transmission direction of the target auxiliary signal in the auxiliary signal transmission link.

[0009] The application further provides a heterogeneous acceleration device, comprising: a heterogeneous acceleration unit, a golden finger interface, and a second signal control unit; wherein the heterogeneous acceleration unit is connected to the golden finger interface through a data transmission link, the second signal control unit is connected to the golden finger interface through an auxiliary signal transmission link, and the heterogeneous acceleration device is connected to the device switching device through the golden finger interface.

[0010] The heterogeneous acceleration unit is configured to, when the second mode switching signal is acquired, switch the golden finger interface to an uplink mode in response to the second mode switching signal and based on a golden finger interface mode switching firmware.

[0011] The second signal control unit is configured to, when the second mode switching signal is acquired, screen a target auxiliary signal from the auxiliary signals and load a second signal mode switching firmware from a second internal firmware buffer, so as to make a corresponding modification to a transmission direction of the target auxiliary signal in the auxiliary signal transmission link.

[0012] The application further provides a heterogeneous acceleration system, comprising: a device switching device and a heterogeneous acceleration device.

[0013] The device switching device is connected to the heterogeneous acceleration device through the golden finger interface and a downlink port in a default mode.

[0014] The application further provides a device switching method applied to a device switching device, and the method comprises the following steps.

[0015] A first mode switching signal is acquired.

[0016] A downlink port mode switching firmware is loaded from a first buffer in a buffer group in response to the first mode switching signal.

[0017] Any downlink port is switched to an uplink port based on the downlink port mode switching firmware, and the first buffer is used to buffer the downlink port mode switching firmware.

[0018] A target auxiliary signal is screened from auxiliary signals.

[0019] A first signal mode switching firmware is loaded from a first internal firmware buffer, so as to make a corresponding modification to a transmission direction of the target auxiliary signal in the auxiliary signal transmission link.

[0020] The application further provides a heterogeneous acceleration method applied to a heterogeneous acceleration device, and the method comprises the following steps.

[0021] A second mode switching signal is acquired.

[0022] A golden finger interface mode switching firmware is acquired in response to the second mode switching signal.

[0023] Switch the golden finger interface to the uplink mode based on the golden finger interface mode switching firmware;

[0024] Screen the target auxiliary signal in the auxiliary signal;

[0025] Load the second signal mode switching firmware from the second internal firmware buffer to correspondingly modify the transmission direction of the target auxiliary signal in the auxiliary signal transmission link.

[0026] The application further provides an electronic device, comprising a memory for storing a computer program and a processor for executing the computer program to implement the steps of the device switching method or the heterogeneous acceleration method.

[0027] The application further provides a computer readable storage medium, which stores a computer program, wherein the computer program is executed by a processor to implement the steps of the device switching method or the heterogeneous acceleration method.

[0028] The application further provides a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the steps of the device switching method or the heterogeneous acceleration method.

[0029] According to the application, the downlink port on the switching device can be switched to the uplink port without adjusting the hardware architecture, so that the downlink device originally connected to the downlink port is switched to the uplink device, the uplink device of the heterogeneous acceleration system is flexibly expanded, and the application flexibility of the heterogeneous acceleration system is improved. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0031] Figure 1 The structural schematic diagram of the device switching apparatus provided by the embodiments of the application;

[0032] Figure 2 The structural schematic diagram of the heterogeneous acceleration apparatus provided by the embodiments of the application;

[0033] Figure 3 The structural schematic diagram of the exemplary heterogeneous acceleration apparatus provided by the embodiments of the application;

[0034] Figure 4 The structural schematic diagram of the heterogeneous acceleration system provided by the embodiments of the application;

[0035] Figure 5 A structural schematic diagram of an exemplary heterogeneous acceleration system provided for an embodiment of the present application;

[0036] Figure 6 A default mode switching flowchart of a heterogeneous acceleration system provided for an embodiment of the present application;

[0037] Figure 7 A switching flowchart of an uplink mode of a heterogeneous acceleration system provided for an embodiment of the present application;

[0038] Figure 8 A flowchart of a device switching method provided for an embodiment of the present application;

[0039] Figure 9 A flowchart of a heterogeneous acceleration method provided for an embodiment of the present application;

[0040] Figure 10 A structural schematic diagram of an electronic device provided for an embodiment of the present application. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0042] It should be noted that, in the description of the present application, the terms “comprise”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0043] The existing heterogeneous computing is mainly a combination of central processing units (CPUs) and various acceleration units, and they are high-speed interconnected through a PCIe bus. In order to meet more PCIe high-speed interconnection channels and more expansion interfaces, a PCIe switch chip is widely used in the heterogeneous computing architecture. The CPU generally acts as an RC (Root Complex) and is the root node of the PCIe tree, and communicates with other GPU and FPGA and other PCIe Endpoint (ED) acceleration units. Therefore, the general hardware design is that the CPU supports the PCIe slot, the GPU and FPGA and other acceleration units are designed into the PCIe specification Add-in Card form to be inserted into the mainboard and connected with the CPU through the PCIe bus, and the PCIe switch chip may be connected in the middle. Therefore, the PCIe switch chip has an uplink interface supporting the CPU and a downlink interface supporting the ED device. The uplink interface is almost suitable for the interface of the CPU and can support the connection of the ED device. The uplink interface and the downlink interface cannot be compatible in the same slot, that is, in the related technology, one interface cannot be used as both an uplink interface and a downlink interface.

[0044] However, in the actual application process, the existing uplink device may not meet the business requirements. At this time, if the uplink device is increased, the hardware architecture of the heterogeneous acceleration system needs to be adjusted, and the added uplink device needs to be manually inserted. The whole architecture adjustment process is relatively cumbersome, and the application flexibility of the heterogeneous acceleration system is reduced.

[0045] To address the aforementioned technical problems, embodiments of this application provide a device switching apparatus, a heterogeneous acceleration apparatus, and a system. The device switching apparatus includes: a multiplexer, a buffer group, a switching core unit, a downlink port, and a first signal control unit. The switching core unit establishes firmware transmission links with different buffers in the buffer group via the multiplexer, and is connected to the downlink port via a data transmission link. The first signal control unit is connected to the downlink port via an auxiliary signal transmission link. The multiplexer is used to connect the first firmware transmission link in response to a first mode switching signal. The switching core unit is used to load downlink port mode switching firmware from the first buffer in the buffer group based on the first firmware transmission link, and to switch any downlink port to an uplink port based on the downlink port mode switching firmware. The first buffer is used to cache the downlink port mode switching firmware. The first signal control unit is used to filter a target auxiliary signal from the auxiliary signals when the first mode switching signal is acquired, and to load the first signal mode switching firmware from a first internal firmware buffer to modify the transmission direction of the target auxiliary signal in the auxiliary signal transmission link accordingly. The device switching device provided by the above solution can switch the downlink port on the switching device to the uplink port without any hardware architecture adjustment, so that the downlink device originally connected to the downlink port is switched to the uplink device, realizing the flexible expansion of the uplink device of the heterogeneous acceleration system, thereby improving the application flexibility of the heterogeneous acceleration system.

[0046] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0047] This application provides a device switching apparatus for flexibly switching the uplink and downlink modes of switching devices in a heterogeneous acceleration system.

[0048] like Figure 1 The diagram shown is a structural schematic of a device switching device provided in an embodiment of this application. The device switching device includes: a multiplexer, a buffer group, a switching core unit, a downlink port, and a first signal control unit. The switching core unit establishes firmware transmission links with different buffers in the buffer group through the multiplexer, the switching core unit is connected to the downlink port through the data transmission link, and the first signal control unit is connected to the downlink port through the auxiliary signal transmission link.

[0049] The multiplexing switch is configured to, when the first mode switching signal is acquired, connect the first firmware transmission link in the firmware transmission link in response to the first mode switching signal; the exchange core unit is configured to load the downlink port mode switching firmware from the first buffer in the buffer group based on the first firmware transmission link, and switch any downlink port to an uplink port based on the downlink port mode switching firmware, and the first buffer is configured to buffer the downlink port mode switching firmware; and the first signal control unit is configured to, when the first mode switching signal is acquired, screen the target auxiliary signal from the auxiliary signal, and load the first signal mode switching firmware from the first internal firmware buffer to correspondingly modify the transmission direction of the target auxiliary signal in the auxiliary signal transmission link.

[0050] It should be noted that the exchange device includes a device switching apparatus, and the exchange device can specifically be a PCIe switch, and the first signal control unit can be a complex programmable logic device (CPLD). When any downlink port needs to be switched to an uplink port, and the downlink device connected to the downlink port needs to be switched to an uplink device, because a plurality of auxiliary signals need to be transmitted between the uplink and downlink devices in the heterogeneous acceleration system, and the transmission of part of the auxiliary signals (target auxiliary signals) is distinguished according to the uplink and downlink modes of the port, the transmission direction of the target auxiliary signal needs to be modified to adapt to the switching of the uplink and downlink modes of the port, so as to ensure the compatibility of the target auxiliary signal interaction after the port mode switching.

[0051] Specifically, because in the downlink port mode, the exchange device is an uplink device for the downlink device connected to the downlink port, and the target auxiliary signal includes an auxiliary signal sent by the uplink device to the downlink device, such as a reset signal used to control the reset of the downlink device. In the case of switching the downlink port to an uplink port, the downlink device is switched to an uplink device, and for the convenience of description, the device to be switched to the uplink and downlink modes and the device that has completed the switching to the uplink and downlink modes can be collectively referred to as a target switching device, and the target switching device can be a field programmable gate array (FPGA). The exchange device is a downlink device for the target switching device, that is, the reset signal is changed to be sent from the uplink device to the exchange device, and therefore the transmission direction of the reset signal needs to be correspondingly modified.

[0052] Specifically, in order to make the switching device have the port mode switching capability, a buffer group and a multiplexing switch are arranged in the device switching apparatus, and the multiplexing switch selects a first firmware transmission link between the switching core unit and the first buffer in the buffer group in response to a first mode switching signal, i.e. in the case of determining that any downstream port needs to be switched to an upstream port, to obtain a downstream port mode switching firmware, and then performs port mode switching on the downstream port based on the downstream port mode switching firmware, i.e. switches the downstream port to an upstream port, so that the downstream device originally connected to the downstream port is switched to an upstream device.

[0053] Specifically, in an embodiment, the first signal control unit can acquire transmission characteristic information of all auxiliary signals; for any auxiliary signal, according to the transmission characteristic information of the auxiliary signal, it is judged whether the transceiver end of the auxiliary signal distinguishes the upstream and downstream modes of the port; if the transceiver end of the auxiliary signal distinguishes the upstream and downstream modes of the port, it is determined that the auxiliary signal is a target auxiliary signal.

[0054] It should be noted that the transmission characteristic information of the auxiliary signal at least includes the function, transmission purpose and signal transmission constraint condition of the auxiliary signal.

[0055] Specifically, for any auxiliary signal, according to the transmission characteristic information of the auxiliary signal, the function, transmission purpose and signal transmission constraint condition of the auxiliary signal are considered to judge whether the transceiver end of the auxiliary signal distinguishes the upstream and downstream modes of the switching device, i.e. to judge whether the transceiver end of the auxiliary signal needs to be switched after the target switching device is used as a target upstream device, such as the initiator being switched from the switching device to the target switching device.

[0056] Among them, the target auxiliary signal at least includes a reset signal and a bus signal, and the bus signal includes a bus clock signal and a bus data signal.

[0057] It should be noted that the reset signal (PERST#) is sent by the switching device (first signal control unit) to the target switching device (as an input signal) in the default mode (downstream mode) for controlling the reset of the target switching device. After the target switching device switches to the upstream device, the first signal control unit adjusts the transmission direction of the signal, and changes it to be sent by the target switching device (second signal control unit) to the switching device (as an output signal). At this time, the target switching device acts as the master device (RC device) and is responsible for triggering the reset of the switching device and peripheral devices. In the default mode, the switching device acts as the master device and sends control instructions or reads status information to the target switching device (slave device) through the bus signal (SMBCLK and SMBDAT of SMBus). After the target switching device switches to the upstream device, the first signal control unit adjusts the master-slave logic of the bus signal, so that the target switching device acts as the master device and reads the information of the switching device and other downstream devices through the bus signal.

[0058] It should be further noted that the auxiliary signals in the heterogeneous acceleration system include:

[0059] Reference clock differential signal REFCLK- / REFCLK+ (required): 100MHz low-voltage differential signal, output by the mainboard through the slot to the ED card, realizing the same source always clock, and the system mainboard must provide a standard-compliant reference clock.

[0060] Reset signal PERST#: active low, provided by the processor system (CPU or switching device), which can be used to reset the PCIe slot and its connected PCIe devices such as FPGA and graphics card, etc., to ensure that the device initializes or recovers to the initial state after an exception.

[0061] Wake-up signal WAKE#: drain open, low active signal, used to wake up the PCIe device, with ED device (slave device), also known as downstream device, which pulls down to wake up the host to provide main power supply, and this function must ensure the auxiliary power supply Vaux power supply.

[0062] Bus clock signal SMBCLK, bus data signal SMBDAT: SMBus bus interface clock signal and data signal, drain open signal. Used for out-of-band data monitoring and reading card information between the host (master device) and the device board (slave device).

[0063] Joint Test Action Group interface signal JTAG (TRST#, TCK, TDI, TDO, TMS): standard JTAG bus interface signal, generally supports IEEE standard 1149.1 pins, as an optional interface of the PCIe device, mainly used for chip internal testing.

[0064] Detection signals PRSNT1#, PRSNT2# (mandatory): low active, used to detect whether the expansion card (slave) is successfully inserted into the slot, the PRSNT1 and PRSNT2 signals are used for hot plug control of the PCIe device (slave).

[0065] Clock request signal CLKREQ#: drain open, low active signal, the expansion card drives it to low to request the host to output the reference clock available (clock active state), so that the PCI Express interface can send / receive data.

[0066] Power interruption signal PWRBRK#: drain open, low active signal, the motherboard system drives it to low to indicate the emergency power reduction mechanism.

[0067] Manufacturer test mode signal MFG: the pin function is defined by the expansion card (AIC) manufacturer, and must be disabled in a non-manufacturing environment to avoid affecting the normal operation of the device.

[0068] Specifically, in order to realize master-slave compatibility, the signals of the standard interface are redefined, and the definition of the low-speed auxiliary signal is specifically designed as follows:

[0069] REFCLK- / REFCLK+: keep the original design, continue to be output to the ED card by the motherboard through the slot, because whether the FPGA PCIE bus is an RC device or an ED device, it needs to provide an external PCIe reference clock, so continue to use the motherboard to provide the clock and does not conflict. At the same time, this design also designs a local reference clock for non-syngeneic clock link support. In addition, it is explained that in the CPU chip design, the PCIE interface of the CPU also needs to input the PCIe reference clock regardless of the master-slave design, so the clock direction is also applicable to the design of the PCIe card of the CPU.

[0070] PERST#: reset signal, as a slave device, it is an input signal for the FPGA card of this design, when it is an RC device, it will be changed to an output signal according to the power-on state of the board card to provide an output signal for the motherboard. At this time, the switch needs to be exchanged to switch the master-slave mode of the motherboard synchronously, and the signal direction and function of the reset signal need to be changed. This function is realized by a programmable device of CPLD. By default, the PCIE slot and the FPGA computing node are ED devices, when it needs to be switched to RC uplink interface, it needs to control the switch chip of the motherboard and the FPGA chip of the FPGA exchange node through the remote network.

[0071] WAKE#: the target switching device is the same as the general wake circuit design when it is an ED device, and when it is an RC device, it does not have the power control function of the exchange mainboard, and this function still needs to be controlled by the mainboard. Whether the FPGA card device uses FPGA or CPU, it is not designed as a mainboard, so this function is still designed by the PCIe card as an output wake-up mainboard to provide the main power supply to start the Add-in card. When the PCIe device needs to be woken up, the device first sets the WAKE# signal valid, and then after a period of delay, the processor system starts to provide the main power Vcc to the device, and uses the PERST# signal to reset the device. When the PCIe device is an RC device, the reset signal direction is reversed, and the RC device sends a reset signal to wake up the entire mainboard device after the power supply is stable. This does not include the low-power BMC system of the mainboard.

[0072] SMBCLK, SMBDAT: SMBus bus signals mainly pay attention to the master-slave mode of SMBus and the cooperation design on the exchange mainboard to realize the master-slave interface compatibility. When the target switching device is an ED device, the mainboard end I2C interface is the master, and the ED end I2C is the slave device. When it is an RC device, it needs to be a master device to read the information of the mainboard and the extended ED device. The application embodiment specially uses the double-sided CPLD of the mainboard and the PCIE card as a low-speed signal processing node design to realize the master-slave design of the online programming control I2C link. The design can be adjusted, and the I2C link of the PCIE slot that needs to support master-slave compatibility is connected to the CPLD separately. The CPLD programming realizes the I2C master-slave function switching and realizes the link arbitration mechanism under the multi-master mode.

[0073] PRSNT1#, PRSNT2#: expansion card presence detection pins, PRSNT1 and PRSNT2 signals in the application embodiment are the same as the standard interface design, whether the PCIE interface is in RC mode or ED mode, the essence is still the physical form of Add-in card, so the signal definition and application are the same, but it needs to be noted that the application embodiment is the same as the PCIe 5.0 design specification and does not support non-controlled hot plug.

[0074] Specifically, in an embodiment, the first signal control unit is specifically configured to switch the firmware based on the first signal mode, and configure and modify the signal transmission pin of the auxiliary signal transmission link, so that the transmission direction of the target auxiliary signal in the auxiliary signal transmission link is correspondingly modified.

[0075] Specifically, if the downlink port to be switched (connected to the target switching device) is referred to as a target downlink port, and the target downlink port after the uplink mode switching is referred to as a target uplink port, the first signal control unit loads the first signal mode switching firmware pre-configured in the first internal firmware buffer when switching the target downlink port to the target uplink port. The first signal mode switching firmware contains a logical configuration for the transmission direction of the target auxiliary signal. By executing the control logic in the firmware, the first signal control unit can dynamically modify the transmission direction of the auxiliary signal between the switching device and the target switching device, that is, the transmission direction of the target auxiliary signal in the auxiliary signal transmission link is modified accordingly to adapt to the conversion of the master-slave mode.

[0076] In an exemplary default mode, the reset signal PERST# is sent from the switching device to the target switching device (input), and the switching device sends the clock and data as the master device in the bus signal; after switching, the first signal control unit changes the transmission direction of PERST# to be sent from the target switching device to the switching device (output) based on the first signal mode switching firmware, and adjusts the master-slave logic of the bus signal so that the target switching device initiates signal transmission as the master device, thereby realizing signal compatibility of the same port in the master-slave mode.

[0077] Specifically, the first signal control unit re-maps the physical pin functions connected between the switching device and the target switching device through the logic defined in the first signal mode switching firmware, for example, the pin originally used for the switching device to output PERST# is configured as an input pin to receive the target switching device to output PERST#; the pin originally used for the switching device to send SMBCLK or SMBDAT is configured as an input pin to receive the target switching device to send SMBCLK / SMBDAT. Through the dynamic adjustment of the pin function, the transmission direction of the target auxiliary signal is reversed, and the signal interaction between the master and slave devices after the target downlink port is switched to the target uplink port meets the new mode requirements.

[0078] Specifically, in an embodiment, the device switching apparatus further comprises a first DIP switch, a signal output port of the first DIP switch is connected to the multiplexing switch and the first signal control unit respectively, the first buffer is connected to the firmware transmission port of the switching core unit through the multiplexing switch, and the firmware transmission port of the switching core unit includes an SPI port.

[0079] The first DIP switch is configured to send a first mode switching signal to the multiplexing switch and the first signal control unit in a case where the original uplink device connected to the uplink port of the switching core unit meets a preset uplink device addition condition.

[0080] Specifically, when the original uplink device (CPU) cannot meet the service demand due to insufficient computing power or CPU failure, it is determined that the original uplink device meets the preset uplink device addition condition. At this time, the user end or the control end of the heterogeneous acceleration system can adjust the state of the first dial switch to send a first mode switching signal to the multiplexing switch and the first signal control unit, such as a high-level effective first mode switching signal, to trigger the uplink and downlink mode switching logic inside the multiplexing switch and the first signal control unit.

[0081] Correspondingly, in an embodiment, the multiplexing switch is also used for:

[0082] Under the acquisition of the second mode switching signal, the second firmware transmission link in the firmware transmission link is connected, so that the exchange core unit loads the uplink port mode switching firmware from the second buffer in the buffer group based on the second firmware transmission link, and switches the uplink port to the downlink port based on the uplink port mode switching firmware. The second buffer is used to buffer the uplink port mode switching firmware.

[0083] It should be noted that the device switching device provided by the embodiments of the application can not only switch the downlink device connected to the downlink port to the uplink device, but also switch the uplink device connected to the uplink port to the downlink device.

[0084] Specifically, in the default mode, or in the case of needing to switch the uplink device connected to the uplink port to the downlink device (acquiring the second mode switching signal), the multiplexing switch connects the second firmware transmission link between the exchange core unit and the second buffer. The second buffer is used to store the default firmware (uplink port mode switching firmware). After the exchange core unit loads the firmware through the second firmware transmission link connected by the multiplexing switch, the uplink port is defined as a downlink port according to the configuration logic in the firmware, so that it has the function of connecting a downlink device.

[0085] Among them, by storing the default firmware (uplink port mode switching firmware) based on the second buffer and the mode switching firmware (downlink port mode switching firmware) based on the first buffer in the exchange device, the multiplexing switch realizes the flexible switching of the port mode of the exchange core unit by switching the connection relationship with the two buffers, thereby supporting the master-slave mode compatibility of the same port.

[0086] Specifically, in an embodiment, the device switching device further comprises an original signal control unit, and the original signal control unit is connected to the power supply, temperature sensor and cooling fan of the device switching device.

[0087] Among them, the original signal control unit is used to acquire the power supply information and the board temperature information of the device switching device, and according to the power supply information and the board temperature information of the device switching device, to send corresponding speed control signals to the cooling fan to adjust the speed of the cooling fan.

[0088] Specifically, the power supply information of the switching device includes power input voltage, current and power consumption, etc., and the board card temperature information can be obtained through a temperature sensor. The original signal control unit can generate corresponding speed control signals according to the power supply information and the board card temperature information of the switching device according to the preset control logic and send them to the cooling fan.

[0089] Correspondingly, in an embodiment, the original signal control unit is configured to perform system power-off processing on the device switching apparatus when the user modifies the state of the first dial switch, and perform system power-on on the device switching apparatus when the first dial switch completes the state modification, so that the first dial switch after power-on triggers the first mode switching signal.

[0090] Specifically, when the original upstream device connected to the upstream port of the switching device meets the preset upstream device addition condition, the original signal control unit will first perform system power-off processing to avoid modifying the hardware configuration in the device live state, causing configuration errors and ensuring the safety of the hardware.

[0091] Specifically, the control end modifies the state of the first dial switch after the system power-off to trigger the subsequent mode switching. After completing the state modification of the first dial switch, the original signal control unit controls the system to power on again. After power-on again, the first dial switch with modified state will send the first mode switching signal to the multiplexer and the first signal control unit, triggering the switching process of the target downstream port of the switching device to the target upstream port.

[0092] Specifically, in an embodiment, the device switching apparatus further comprises a clock generator, and a clock signal output end of the clock generator is connected to a clock signal input end of the first signal control unit.

[0093] The clock generator is configured to generate a clock signal and send the clock signal to the first signal control unit, so that the first signal control unit transmits the clock signal to a plurality of peripheral devices of the device switching apparatus through an auxiliary signal transmission link.

[0094] It should be noted that the clock signal generated by the clock generator is a 100MHz reference clock required by the PCIe standard, and the clock generator sends the signal to the first signal control unit of the switching device. The first signal control unit, as a signal distribution hub, will further transmit the clock signal to all peripheral devices connected to the switching device. The upstream devices include the original upstream device and the target switching device switched to the upstream mode, and the downstream devices include the target switching device in the default mode and other acceleration units.

[0095] All peripheral devices use a unified clock signal provided by the switching device clock generator, which can avoid timing deviation of data transmission caused by clock source difference, and ensure normal operation of the communication protocol of the PCIe bus and other high-speed interfaces. Moreover, when the target switching device switches from the downstream mode to the upstream mode, the unified clock is used to keep timing synchronization between the switching device and other peripheral devices, thereby ensuring system compatibility after mode switching.

[0096] The device switching apparatus provided by the embodiment of the present application comprises a multiplexing switch, a buffer group, a switching core unit, a downstream port and a first signal control unit. The switching core unit establishes firmware transmission links with different buffers in the buffer group through the multiplexing switch. The switching core unit is connected to the downstream port through a data transmission link. The first signal control unit is connected to the downstream port through an auxiliary signal transmission link. The multiplexing switch is configured to, when a first mode switching signal is acquired, connect a first firmware transmission link in the firmware transmission links in response to the first mode switching signal. The switching core unit is configured to load downstream port mode switching firmware from a first buffer in the buffer group based on the first firmware transmission link, and switch any downstream port to an upstream port based on the downstream port mode switching firmware. The first buffer is configured to buffer the downstream port mode switching firmware. The first signal control unit is configured to, when the first mode switching signal is acquired, screen a target auxiliary signal from the auxiliary signal, and load a first signal mode switching firmware from a first internal firmware buffer to correspondingly modify a transmission direction of the target auxiliary signal in the auxiliary signal transmission link. The device switching apparatus provided by the above scheme can switch the downstream port on the switching device to the upstream port without any adjustment of the hardware architecture, so that the downstream device originally connected to the downstream port is switched to the upstream device, thereby realizing flexible expansion of the upstream device of the heterogeneous acceleration system, and improving the application flexibility of the heterogeneous acceleration system.

[0097] The embodiment of the present application provides a heterogeneous acceleration apparatus for flexible switching of the upstream and downstream modes of devices in a heterogeneous acceleration system.

[0098] As shown in Figure 2 FIG. 1 is a structural schematic diagram of a heterogeneous acceleration apparatus provided by the embodiment of the present application. The heterogeneous acceleration apparatus comprises a heterogeneous acceleration unit, a golden finger interface and a second signal control unit. The heterogeneous acceleration unit is connected to the golden finger interface through a data transmission link. The second signal control unit is connected to the golden finger interface through an auxiliary signal transmission link. The heterogeneous acceleration apparatus is connected to the device switching apparatus provided by the above embodiment through the golden finger interface.

[0099] The heterogeneous acceleration unit is configured to, when the second mode switching signal is acquired, acquire a golden finger interface mode switching firmware in response to the second mode switching signal, and switch the golden finger interface to an uplink mode based on the golden finger interface mode switching firmware; and the second signal control unit is configured to, when the second mode switching signal is acquired, screen a target auxiliary signal from the auxiliary signals, and load the second signal mode switching firmware from the second internal firmware buffer, so as to modify the transmission direction of the target auxiliary signal in the auxiliary signal transmission link.

[0100] It should be noted that the target switching device in the above embodiment includes a heterogeneous acceleration device, and a golden finger interface of the heterogeneous acceleration device is a physical interface connected with a switching device slot (an uplink port or a downlink port). In a default mode (a downlink mode), the golden finger interface receives a target auxiliary signal and the like sent by a first signal control unit in the switching device as a downlink interface. The target auxiliary signal is transmitted to the golden finger interface in the default mode by the first signal control unit through a target downlink interface, or is transmitted to a target uplink port by the second signal control through the golden finger interface in the uplink mode.

[0101] Specifically, when the system triggers mode switching, that is, when the target downlink port of the switching device is switched to the target uplink port, the heterogeneous acceleration unit reconfigures the golden finger interface in response to the state change, for example, by modifying the signal direction mapping, electrical parameter setting and protocol logic in the interface, and switches the golden finger interface from the default mode to the uplink mode. After switching, the golden finger interface is redefined as the uplink mode, so that the target switching device can send the target auxiliary signal and the like to the switching device as an uplink device, to adapt to the connection requirement of the target uplink port of the switching device.

[0102] Specifically, the target switching device (FPGA) is connected with the switching device as a downlink device through a target downlink port of the switching device. At this time, the FPGA mainly undertakes the heterogeneous acceleration task of receiving and executing the forwarding of the switching device. The switching device switches the target downlink port originally connected with the FPGA to the target uplink port, so as to have the function of connecting the uplink device. The heterogeneous acceleration unit switches the target switching device from the default downlink device mode to the uplink device mode by loading a specific mode switching firmware (the golden finger interface mode switching firmware), so as to connect with the switching device through the target uplink port after switching as a new uplink device, and undertake the task scheduling function of the uplink device. The same PCIe slot (the target downlink port) of the switching device is compatible with the uplink device and the downlink device, which improves the flexibility of the heterogeneous acceleration system, and the heterogeneous acceleration system including the heterogeneous acceleration device provided in the embodiment is especially suitable for edge computing and the like which is sensitive to the cost of hardware deployment.

[0103] For example, the heterogeneous acceleration device includes a golden finger interface, a first signal control unit, a second signal control unit, a heterogeneous acceleration unit, and a second internal firmware buffer. Figure 3As shown, the structural schematic diagram of the exemplary heterogeneous acceleration device provided by the embodiment of the application includes an FPGA chip (heterogeneous acceleration unit), a flash memory FLASH, a memory module (DDR4 SODIMM), a four-channel small package pluggable 28G module (QSFP28 interface), a USB interface, a PCIe Gen5.0 x16 interface, a PCIe Gen5.0 x16 endpoint device (gold finger interface), a MCIO PCIe x8 interface, a 12V power input (P12V IN), a clock generator (Clock Generator), a PCIe 5.0 reference clock (PCIe 5.0 Ref), a second signal control unit (CPLD), and a second DIP switch, etc. Among them, the Intel agilex-I series SOC FPGA chip is used as the main processing core of the heterogeneous acceleration unit, two PCIe Gen5.0 x16 interfaces are respectively an ED endpoint slave mode device interface in the gold finger mode and a PCIe Gen5.0 x16 interface connected through an external MCIO high-speed connector mode. The gold finger interface can be used as an ED device and also supports being used as an RC device to access a switch mainboard (switch device), that is, the gold finger interface can realize master-slave mode switching and compatibility.

[0104] Specifically, in an embodiment, the second signal control unit is further configured to: acquire transmission characteristic information of all auxiliary signals; and for any auxiliary signal, determine whether a transceiving end of the auxiliary signal distinguishes port uplink mode and downlink mode according to the transmission characteristic information of the auxiliary signal; and if the transceiving end of the auxiliary signal distinguishes port uplink mode and downlink mode, determine that the auxiliary signal is a target auxiliary signal.

[0105] The filtering manner of the second signal control unit for the target auxiliary signal is the same as the filtering manner of the first signal control unit for the target auxiliary signal, which will not be described herein again.

[0106] Specifically, in an embodiment, the heterogeneous acceleration device further includes: a second DIP switch, a signal output port of the second DIP switch being connected to the heterogeneous acceleration unit and the second signal control unit respectively; and the second DIP switch is configured to send a second mode switching signal to the heterogeneous acceleration unit and the second signal control unit in a case where the original uplink device connected to the uplink port of the external device switching device meets the preset uplink device addition condition.

[0107] The state of the first DIP switch and the second DIP switch is modified through internal control logic. Remote control of mode switching is realized through the control end or the user end, so that the heterogeneous acceleration system is especially suitable for scenes where manual operation is inconvenient. The trigger logic of the second DIP switch is the same as that of the first DIP switch, which will not be described herein again.

[0108] Specifically, in an embodiment, the heterogeneous acceleration unit is configured to perform heterogeneous acceleration task scheduling on a plurality of downlink devices connected to the device switching apparatus in the uplink mode of the gold finger interface.

[0109] It should be noted that the heterogeneous acceleration unit has the function of the uplink device in the uplink mode (in the uplink mode of the gold finger interface), and can replace the original uplink device to perform heterogeneous acceleration task scheduling and the like.

[0110] For example, the heterogeneous acceleration unit can assign image processing and data encryption and other heterogeneous acceleration tasks to a plurality of downlink devices such as other FPGAs, GPUs and ASICs connected to the switching device according to the overall demand of the system, such as the demand of task priority and device load. During the heterogeneous acceleration task scheduling process, the heterogeneous acceleration unit can also monitor the task execution status of each downlink device, and adjust the task allocation strategy according to the task execution status of each downlink device to improve the overall acceleration efficiency of the heterogeneous acceleration system.

[0111] Among them, when the original uplink device is insufficient or fails in the heterogeneous acceleration system, the target switching device can replace the original uplink device to play a scheduling function when it is available, without the need to adjust the hardware architecture of the heterogeneous acceleration system, thereby improving the application flexibility of the heterogeneous acceleration system and reducing the hardware cost.

[0112] Correspondingly, in an embodiment, the heterogeneous acceleration unit is also configured to receive the heterogeneous acceleration task forwarded by the device switching apparatus in the downlink mode of the gold finger interface, and execute the heterogeneous acceleration task to obtain an acceleration task execution result; and feed back the acceleration task execution result to the device switching apparatus to forward the acceleration task execution result to the original uplink device through the device switching apparatus.

[0113] Specifically, the heterogeneous acceleration unit receives the heterogeneous acceleration task forwarded by the switching device through the target downlink port connected to the switching device. The heterogeneous acceleration task can be issued by the original uplink device, and the heterogeneous acceleration task includes data processing tasks and algorithm acceleration tasks and the like. The heterogeneous acceleration unit executes the received heterogeneous acceleration task by using its hardware acceleration capability such as the parallel computing function of FPGA. After the task execution is completed, the heterogeneous acceleration unit generates an acceleration task execution result and feeds it back to the switching device (switching core unit) for forwarding to the original uplink device by the switching device.

[0114] The heterogeneous acceleration device provided by the embodiment of the application comprises a heterogeneous acceleration unit, a golden finger interface and a second signal control unit; wherein the heterogeneous acceleration unit is connected with the golden finger interface through a data transmission link, the second signal control unit is connected with the golden finger interface through an auxiliary signal transmission link, and the heterogeneous acceleration device is connected with a device switching device through the golden finger interface; the heterogeneous acceleration unit is configured to, when a second mode switching signal is acquired, acquire a golden finger interface mode switching firmware in response to the second mode switching signal, and switch the golden finger interface to an uplink mode based on the golden finger interface mode switching firmware; and the second signal control unit is configured to, when the second mode switching signal is acquired, screen a target auxiliary signal from the auxiliary signal, and load a second signal mode switching firmware from a second internal firmware buffer, so as to make a corresponding modification to a transmission direction of the target auxiliary signal in the auxiliary signal transmission link. The heterogeneous acceleration device provided by the above scheme can switch the uplink and downlink modes without any hardware architecture adjustment, so as to switch a downlink device originally connected to a downlink port of a switching device to an uplink device, and realize flexible expansion of the uplink device of the heterogeneous acceleration system, thereby improving the application flexibility of the heterogeneous acceleration system.

[0115] The embodiment of the application provides a heterogeneous acceleration system for flexibly switching the uplink and downlink modes of the heterogeneous acceleration system.

[0116] As shown in Figure 4 , it is a structural schematic diagram of the heterogeneous acceleration system provided by the embodiment of the application, which comprises a device switching device and a heterogeneous acceleration device.

[0117] The device switching device is connected with the heterogeneous acceleration device through a golden finger interface and a downlink port in a default mode.

[0118] For example, Figure 5As shown, the structure schematic diagram of the exemplary heterogeneous acceleration system provided by the embodiment of the application, the switching device includes device switching apparatus, the target switching device includes heterogeneous acceleration apparatus, the switching core unit of the switching device adopts XC50256 switching chip to realize the design of 6 uplink PCIE slots (PE0~PE5) and 8 PCIE downlink ports (6 PCIe slots of PE8~PE13 and 2 MCIO interfaces of PE6~PE7), the MCIO interface is used to connect the MCIO connector of the hard disk backboard, the hard disk backboard includes a hard disk, and is used to expand hard disk storage resources for the heterogeneous acceleration system, a special first dial switch is designed in the board, and the state of the three slots PE3, PE4 and PE5 can be the uplink interface of RC or the downlink interface connected with the ED device, that is, PE3, PE4 and PE5 are target downlink ports or target uplink ports. Two CPLD units in the board, CPLD0 is used as an original signal control unit for monitoring power supply, board temperature, fan speed and LED indicator light and other basic board management, and CPLD1 is used as a second signal control unit for low-speed signal (auxiliary signal) and logic signal management of all board slots. The CPLD0 management module is not easy to tamper with the firmware information device, the CPLD1 realizes the PMBus arbitration function of the uplink port, and receives the control management of the host end (control end) to the board card. The clock signals of the whole board are provided by the PCIE clock generator, so that the clock of all devices is kept homologous, and the clock of the CPU of the original uplink device is also provided by the clock generator.

[0119] Specifically, when the target switching device is inserted into the switching backboard (switching device) slot (PE3, PE4 or PE5) as an ED device, the target switching device receives the PCIE reference clock provided by the backboard, receives the control reset signal of the backboard to determine whether the FPGA card (heterogeneous acceleration unit) starts or resets, and supports the hardware signal design of other PCIE low-power consumption functions. At this time, the target switching device can be used as a general FPGA acceleration card, loads different function programs to realize variable function acceleration, such as 200G intelligent network card, key data storage acceleration (4-way NVME hard disk can be expanded at the tail MCIO interface), data encryption, etc.

[0120] Specifically, the slot state is switched from the ED state to the RC device interface state (the dial switch is changed to the ON state), the mainboard PE3, PE4 and PE5 are changed to the interface (target uplink port) supporting the RC device, the switching chip of the switching backplane supports the design that the slot can be defined as an uplink interface or a downlink interface, the switching is realized by loading the two firmware of flash0 (the second buffer) and flash1 (the first buffer), the default loading of flash0 is the ED mode, and the multiplexing switch (MUX) is switched to flash1, which is the RC mode. For the target switching device, the FPGA firmware can also be updated through the JTAG debugging interface of the CPU node connected to the FPGA, so as to realize the change of the golden finger PCIE interface mode of the FPGA node from the ED mode to the RC mode. Among them, the mode needs to be changed after the whole device is powered off, the dial switch state is changed and then powered on. The switching chip is restarted after the firmware is changed, so that the PE3, 4, 5 interface is an uplink RC mode interface, and the dial switch also controls the CPLD1 chip to change the signal definition of the low-speed limit number of the interface at the same time, so as to realize the switching of the ED and RC modes of the backplane.

[0121] Specifically, as shown in Figure 6 the default mode switching process diagram of the heterogeneous acceleration system provided by the embodiment of the application, the dial switch of the switching device and the dial switch (the first dial switch and the second dial switch) of the FPGA are in the default mode (off), the control signal (selection control signal) of the first dial switch is low, that is, the first mode switching signal is low, and the control signal (CONFIG_SEL) of the second dial switch is also low, that is, the second mode switching signal is low. The first signal control unit CPLD1 in the switching device loads the default image 0 (default signal firmware), and configures PE3, PE4 and PE5 as target downlink ports connected to a downlink device, the multiplexing switch switches the switching chip (switching core unit) to connect the second buffer, and loads the default firmware (downlink port mode switching firmware) of the three uplink ports (RC interface) and 11 downlink ports (ED interface). The second signal control unit CPLD in the target switching device loads the default image 0 (default signal firmware) to define the auxiliary signal (low-speed signal) of the golden finger interface of the target switching device as a downlink mode, and the target switching device loads the default firmware to define the golden finger interface as a downlink mode. After the above mode switching is completed, the whole machine of the heterogeneous acceleration system is restarted or restarted after power off, so that the target switching device is connected to the switching device as a downlink device through the target downlink port.

[0122] Correspondingly, as shown in Figure 7As shown in the figure, the switching process diagram of the uplink mode of the heterogeneous acceleration system provided by the embodiment of the application, the dial switch of the switching device and the dial switch (the first dial switch and the second dial switch) of the FPGA are in the uplink mode switching mode (ON). After the system is powered on, the control signal of the first dial switch is high level, and the control signal of the second dial switch is also high level. The first signal control unit CPLD1 in the switching device loads image 1 (the first signal mode switching firmware), and configures PE3, PE4 and PE5 as target uplink ports to connect the uplink device, the multiplexing switch switches the switching chip to connect the first buffer, and loads the downlink port mode switching firmware of 6 uplink ports and 8 downlink ports. The second signal control unit CPLD in the target switching device loads image 1 (the second signal mode switching firmware) to define the auxiliary signal (low-speed signal) of the golden finger interface of the target switching device as the uplink mode, and the target switching device loads the golden finger interface mode switching firmware to define the golden finger interface as the uplink mode. After the above mode switching is completed, the whole machine of the heterogeneous acceleration system is restarted or restarted after power off, so that the target switching device connects the switching device through the target uplink port as the uplink device.

[0123] The heterogeneous acceleration system provided by the embodiment of the application comprises a device switching apparatus and a heterogeneous acceleration apparatus. In the default mode, the device switching apparatus is connected to the heterogeneous acceleration apparatus through a golden finger interface and a downlink port. The system provided by the above scheme can switch the target switching device originally connected to the target downlink port of the switching device as a downlink device to an uplink device without any hardware architecture adjustment, realizes flexible expansion of the uplink device of the heterogeneous acceleration system, and thus improves the application flexibility of the heterogeneous acceleration system. Moreover, the application flexibility of the FPGA heterogeneous computing device is greatly improved by using the reconfigurable feature of the FPGA, and the hardware architecture deployment cost is reduced. A new CPU-free heterogeneous computing architecture, such as FPGA+GPU, FPGA+FPGA and FPGA+ASIC, is realized. The different types of computing units can be combined and applied to some specific edge computing scenarios, which helps to reduce cost and power consumption, and has high technical innovation and advancement.

[0124] The embodiment of the application provides a device switching method, which is applied to the device switching apparatus provided by the above embodiment. The execution subject of the embodiment of the application is an electronic device, such as a server, a desktop computer, a notebook computer, a tablet computer and other electronic devices that can be used to realize device switching.

[0125] As Figure 8 shown, the flowchart of the device switching method provided by the embodiment of the application, the method comprises:

[0126] Step 801, a first mode switching signal is acquired;

[0127] Step 802: In response to the first mode switching signal, load the downlink port mode switching firmware from the first buffer in the buffer group;

[0128] Step 803: Based on the downlink port mode switching firmware, switch any downlink port to an uplink port. The first buffer is used to cache the downlink port mode switching firmware.

[0129] Step 804: Filter the target auxiliary signal from the auxiliary signals;

[0130] Step 805: Load the first signal mode switching firmware from the first internal firmware cache to modify the transmission direction of the target auxiliary signal in the auxiliary signal transmission link accordingly.

[0131] For a description of the features in the embodiments corresponding to the device switching method, please refer to the relevant descriptions of the embodiments corresponding to the device switching device, which will not be repeated here.

[0132] This application provides a heterogeneous acceleration method, applied to the heterogeneous acceleration device provided in the above embodiments. The executing entity in this application is an electronic device, such as a server, desktop computer, laptop computer, tablet computer, and other electronic devices that can be used to implement heterogeneous acceleration.

[0133] like Figure 9 The diagram shown is a flowchart of a heterogeneous acceleration method provided in an embodiment of this application. The method includes:

[0134] Step 901: Obtain the second mode switching signal;

[0135] Step 902: In response to the second mode switching signal, obtain the gold finger interface mode switching firmware;

[0136] Step 903: Based on the firmware for switching the gold finger interface mode, switch the gold finger interface to uplink mode;

[0137] Step 904: Filter the target auxiliary signal from the auxiliary signals;

[0138] Step 905: Load the second signal mode switching firmware from the second internal firmware cache to modify the transmission direction of the target auxiliary signal in the auxiliary signal transmission link accordingly.

[0139] For a description of the features in the embodiments corresponding to the heterogeneous acceleration method, please refer to the relevant descriptions of the embodiments corresponding to the heterogeneous acceleration device, which will not be repeated here.

[0140] Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software on a necessary general hardware platform, and of course can also be realized by hardware, but in many cases the former is a better embodiment.

[0141] The embodiments of the present application also provide an electronic device, as shown in Figure 10 The electronic device provided by the embodiments of the present application has the structure as shown in the figure, which includes a processor 10 and a memory 20, the memory 20 stores a computer program, and the processor 10 is configured to run the computer program to execute the steps in any of the device switching method or heterogeneous acceleration method embodiments.

[0142] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program, wherein the computer program is configured to execute the steps in any of the heterogeneous acceleration method embodiments when running.

[0143] In an exemplary embodiment, the computer readable storage medium described above can include but is not limited to a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0144] The embodiments of the present application also provide a computer program product, which includes a computer program, and the computer program is executed by a processor to implement the steps in any of the device switching method or heterogeneous acceleration method embodiments.

[0145] The embodiments of the present application also provide another computer program product, which includes a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps in any of the device switching method or heterogeneous acceleration method embodiments.

[0146] The skilled person can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized by electronic hardware, computer software or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in the above description in general terms. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0147] The above describes in detail the device switching apparatus, heterogeneous acceleration apparatus and system provided by the present application. The principles and implementation manners of the present application are described by using specific examples, and the above description of the embodiments is only used to help understand the method of the present application and the core idea thereof. It should be noted that, for those skilled in the art, some improvements and modifications can be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A device switching apparatus, characterized in that, include: The system includes a multiplexer, a buffer group, a switching core unit, a downlink port, and a first signal control unit. The switching core unit establishes firmware transmission links with different buffers in the buffer group through the multiplexer. The switching core unit is connected to the downlink port through a data transmission link. The first signal control unit is connected to the downlink port through an auxiliary signal transmission link. The multiplexer is used to connect the first firmware transmission link in the firmware transmission link in response to the first mode switching signal when the first mode switching signal is received. The switching core unit is used to load downlink port mode switching firmware from the first buffer in the buffer group based on the first firmware transmission link, and to switch any of the downlink ports to uplink ports based on the downlink port mode switching firmware. The first buffer is used to cache the downlink port mode switching firmware. The first signal control unit is configured to, upon receiving a first mode switching signal, filter a target auxiliary signal from the auxiliary signals; and load a first signal mode switching firmware from a first internal firmware cache to modify the transmission direction of the target auxiliary signal in the auxiliary signal transmission link accordingly. The first signal control unit is further configured to: Obtain the transmission characteristic information of all the auxiliary signals; For any of the auxiliary signals, based on the transmission characteristic information of the auxiliary signal, it is determined whether the transmitting and receiving ends of the auxiliary signal distinguish between port uplink and downlink modes; If the transmitting and receiving ends of the auxiliary signal can distinguish between the uplink and downlink modes of the port, then the auxiliary signal is determined to be the target auxiliary signal.

2. The equipment switching device according to claim 1, characterized in that, The first signal control unit is specifically used for: Based on the first signal mode switching firmware, the configuration of the signal transmission pins of the auxiliary signal transmission link is modified so that the transmission direction of the target auxiliary signal in the auxiliary signal transmission link is modified accordingly.

3. The equipment switching device according to claim 1, characterized in that, The target auxiliary signal includes at least a reset signal and a bus signal; The bus signals include bus clock signals and bus data signals.

4. The equipment switching device according to claim 1, characterized in that, The device switching device further includes: a first DIP switch, the signal output port of the first DIP switch being connected to the multiplex switch and the first signal control unit respectively; The first DIP switch is used to send the first mode switching signal to the multiplex switch and the first signal control unit when the original uplink device connected to the uplink port of the switching core unit meets the preset uplink device addition conditions.

5. The equipment switching device according to claim 4, characterized in that, The multiplexing switch is also used for: Upon receiving the second mode switching signal, the second firmware transmission link in the firmware transmission link is connected, so that the switching core unit loads the uplink port mode switching firmware from the second buffer in the buffer group based on the second firmware transmission link, and switches the uplink port to the downlink port based on the uplink port mode switching firmware. The second buffer is used to cache the uplink port mode switching firmware.

6. The equipment switching device according to claim 4, characterized in that, The device switching device further includes: an original signal control unit, which is connected to the power supply, temperature sensor and cooling fan of the device switching device; The original signal control unit is used to acquire the power information and board temperature information of the device switching device, and send a corresponding speed control signal to the cooling fan according to the power information and board temperature information of the device switching device, so as to adjust the speed of the cooling fan.

7. The equipment switching device according to claim 6, characterized in that, The original signal control unit is used for: When the user terminal modifies the state of the first DIP switch, the device switching device is powered off. When the first DIP switch completes the state modification, the device switching device is powered on again so that the first DIP switch after power-on triggers the first mode switching signal.

8. The equipment switching device according to claim 1, characterized in that, The device switching device further includes: a clock generator, wherein the clock signal output terminal of the clock generator is connected to the clock signal input terminal of the first signal control unit; The clock generator is used to generate a clock signal and send the clock signal to a first signal control unit, so that the clock signal can be transmitted to multiple peripheral devices of the device switching device through the auxiliary signal transmission link based on the first signal control unit; The peripheral equipment includes uplink and downlink devices.

9. A heterogeneous acceleration device, characterized in that, include: A heterogeneous acceleration unit, a gold finger interface, and a second signal control unit; wherein the heterogeneous acceleration unit is connected to the gold finger interface via a data transmission link, the second signal control unit is connected to the gold finger interface via an auxiliary signal transmission link, and the heterogeneous acceleration device is connected to the device switching device as described in any one of claims 1 to 8 via the gold finger interface. The heterogeneous acceleration unit is used to, upon receiving the second mode switching signal, in response to the second mode switching signal, acquire the gold finger interface mode switching firmware, and based on the gold finger interface mode switching firmware, switch the gold finger interface to uplink mode. The second signal control unit is used to filter the target auxiliary signal from the auxiliary signals when the second mode switching signal is acquired, and load the second signal mode switching firmware from the second internal firmware cache to modify the transmission direction of the target auxiliary signal in the auxiliary signal transmission link accordingly.

10. The heterogeneous acceleration device according to claim 9, characterized in that, The second signal control unit is also used for: Obtain the transmission characteristic information of all the auxiliary signals; For any of the auxiliary signals, based on the transmission characteristic information of the auxiliary signal, it is determined whether the transmitting and receiving ends of the auxiliary signal distinguish between port uplink and downlink modes; If the transmitting and receiving ends of the auxiliary signal can distinguish between the uplink and downlink modes of the port, then the auxiliary signal is determined to be the target auxiliary signal.

11. The heterogeneous acceleration device according to claim 9, characterized in that, The heterogeneous acceleration device further includes: a second DIP switch, the signal output port of which is connected to the heterogeneous acceleration unit and the second signal control unit respectively; The second DIP switch is used to send the second mode switching signal to the heterogeneous acceleration unit and the second signal control unit when the original uplink device connected to the uplink port in the external device switching device meets the preset uplink device addition conditions.

12. The heterogeneous acceleration device according to claim 9, characterized in that, The heterogeneous acceleration unit is used for: When the gold finger interface is in uplink mode, it replaces the original uplink device and performs heterogeneous acceleration task scheduling on multiple downlink devices connected to the device switching device.

13. The heterogeneous acceleration device according to claim 12, characterized in that, The heterogeneous acceleration unit is also used for: When the gold finger interface is in downlink mode, it receives the heterogeneous acceleration task forwarded by the device switching device, executes the heterogeneous acceleration task, and obtains the acceleration task execution result. The result of the acceleration task execution is fed back to the device switching device, so that the device switching device can forward the result of the acceleration task execution to the original uplink device.

14. A heterogeneous acceleration system, characterized in that, include: The device switching apparatus as described in any one of claims 1 to 8 and the heterogeneous acceleration apparatus as described in any one of claims 9 to 13; In the default mode, the device switching device connects to the heterogeneous acceleration device via a gold finger interface and a downlink port.

15. A device switching method, applied to the device switching apparatus as described in any one of claims 1 to 8, characterized in that, The method includes: Obtain the first mode switching signal; In response to the first mode switching signal, the downlink port mode switching firmware is loaded from the first buffer in the buffer group; Based on the downlink port mode switching firmware, any downlink port is switched to an uplink port, and the first buffer is used to cache the downlink port mode switching firmware. Filter the target auxiliary signal from the auxiliary signals; Load the first signal mode switching firmware from the first internal firmware buffer to modify the transmission direction of the target auxiliary signal in the auxiliary signal transmission link accordingly; The process of filtering the target auxiliary signal from the auxiliary signal includes: Obtain the transmission characteristic information of all the auxiliary signals; For any of the auxiliary signals, based on the transmission characteristic information of the auxiliary signal, it is determined whether the transmitting and receiving ends of the auxiliary signal distinguish between port uplink and downlink modes; If the transmitting and receiving ends of the auxiliary signal can distinguish between the uplink and downlink modes of the port, then the auxiliary signal is determined to be the target auxiliary signal.

16. A heterogeneous acceleration method, applied to the heterogeneous acceleration device as described in any one of claims 9 to 13, characterized in that, The method includes: Obtain the second mode switching signal; In response to the second mode switching signal, obtain the gold finger interface mode switching firmware; Based on the aforementioned gold finger interface mode switching firmware, the gold finger interface is switched to uplink mode; Filter the target auxiliary signal from the auxiliary signals; The second signal mode switching firmware is loaded from the second internal firmware cache to modify the transmission direction of the target auxiliary signal in the auxiliary signal transmission link accordingly.

17. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the device switching method as described in claim 15 or the steps of the heterogeneous acceleration method as described in claim 16 when executing the computer program.

18. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the device switching method as described in claim 15 or the steps of the heterogeneous acceleration method as described in claim 16.

19. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the device switching method as described in claim 15 or the steps of the heterogeneous acceleration method as described in claim 16.

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