Memory chiplet bond pad configuration

Abstract

In one embodiment, an apparatus includes a memory die having a 3D memory structure that includes non-volatile memory cells in an array region. The non-volatile memory cells are connected through word lines and bit lines. The word line is connected to a vertical word line via in a stair region adjacent to the array region. The vertical word line vias include a first plurality of vertical word line vias connected to a first word line bonding pad in the stair region and a second plurality of vertical word line vias connected to a second word line bonding pad in the array region.

Description

BACKGROUND

[0001] Semiconductor memory is widely used in various electronic devices such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices, and other devices. Semiconductor memory can include non-volatile memory or volatile memory. Non-volatile memory allows storage and retention of information even when not connected to a power source (e.g., a battery).

[0002] One type of non-volatile memory has strings of non-volatile memory cells with select transistors at each end of the string. Generally, such strings are referred to as NAND strings and a non-volatile memory chip or die in which such NAND strings are formed can be referred to as a NAND chip or die.

[0003] In some examples, a silicon wafer including a plurality of non-volatile memory dies (e.g., NAND dies) can be bonded to another silicon wafer including an equal number of dies including logic circuitry (e.g., control dies, logic dies, or application specific integrated circuits (ASICs)). The bonded wafers are then scribed (singulated) into individual assemblies (integrated memory assemblies) each including a memory die and a control die. Bonding pads are disposed on opposing surfaces to enable connection of the logic circuitry to components of the memory dies (e.g., word lines and bit lines). BRIEF DESCRIPTION OF DRAWINGS

[0004] Like-numbered elements refer to common parts throughout the several views.

[0005] FIG. 1 FIG. 1 is a functional block diagram of a memory device.

[0006] FIGS. 2A-2B is a block diagram depicting an embodiment of a memory system.

[0007] FIG. 3 is a perspective view of a portion of one embodiment of a monolithic three-dimensional memory structure.

[0008] FIGS. 4A-4C An example of a non-volatile memory structure is shown.

[0009] FIG. 5 An example of wafer-to-wafer bonding is shown.

[0010] FIGS. 6A-6B An example of a die-to-wafer bond for forming an integrated memory assembly is illustrated.

[0011] FIGS. 7A-7B ​Another example of a die-to-wafer bond for forming an integrated memory assembly is illustrated.

[0012] FIGS. 8A-8B Another example of a die-to-wafer bond for forming an integrated memory assembly is illustrated.

[0013] FIGS. 9A-9B Another example of a die-to-wafer bond for forming an integrated memory assembly is illustrated.

[0014] FIGS. 10A-10B Another example of a die-to-wafer bond for forming an integrated memory assembly is illustrated.

[0015] FIGS. 11A-11B Examples of a bond pad on a control die and a corresponding bond pad on a memory die are illustrated.

[0016] FIG. 12 Examples of an integrated memory assembly are illustrated.

[0017] FIG. 13 Examples of an array region and a staircase region of a memory die are illustrated.

[0018] FIG. 14 Examples of an array region and a staircase region of a memory die bonded to a control die in an integrated memory assembly are illustrated.

[0019] FIGS. 15A-15B Examples of routing of electrical connections in an integrated memory assembly are illustrated.

[0020] FIGS. 16A-16B Examples of routing of electrical connections in an integrated memory assembly including word line bond pads in an array region are illustrated.

[0021] FIGS. 17A-17C Examples of routing of traces for connecting word line bond pads in an array region are illustrated.

[0022] FIGS. 18A-18B Examples of a pattern of bond pads are illustrated.

[0023] FIG. 19 Examples of a method including forming word line bond pads in an array region are illustrated.

[0024] FIG. 20 Examples of a method including forming traces connecting word line bond pads and extending over bit lines are illustrated. DETAILED DESCRIPTION

[0025] Techniques are provided for fabricating integrated memory assemblies that include individually bonding memory dies or chiplets to a memory control circuit wafer in what can be referred to as die-to-wafer bonding. Die-to-wafer bonding allows selection of the number of memory dies and the characteristics of the individual memory dies (e.g., only defect-free memory dies with the appropriate capacity) as compared to wafer-to-wafer bonding in which the entire wafer of opposing dies are aligned and bonded. The control die can have a plurality of slots, each configured to interface with a memory chiplet. Some or all of the slots can be occupied by memory chiplets, which can be the same or can have different characteristics to impart a high degree of configurability.

[0026] When the memory dies are a different size than the corresponding control die to which they are bonded (e.g., the memory chiplets are smaller than the control die), bond pad placement can be limited and the control circuit can not be aligned with the corresponding memory structure components (e.g., word line driver circuits in the control die can not be aligned with word line vias in the corresponding memory dies). Some control circuitry can be located in overhang regions of the control die (regions that extend beyond the connected memory dies). In some cases, die-to-wafer alignment can not be as accurate as wafer-to-wafer alignment (more alignment noise), such that bond pads can need to be configured in a manner that tolerates misalignment (e.g., implementing larger bond pads and / or bond pad spacing).

[0027] Aspects of the technology relate to the technical problem of efficiently connecting control circuitry in the control die with corresponding memory die components (e.g., where there is a size mismatch between the dies and / or misalignment of the control circuitry with corresponding features, which makes direct connections challenging and / or requires bond pad arrangements that are less sensitive to misalignment). Solutions to these problems can include distributing word line bond pads over a wide area. For example, some word line bond pads can be located in the array region, over the bit lines and memory cells, and can be connected to corresponding word line vias through traces that extend into the memory array region (bit line bond pads can also be located in the array region). Other word line bond pads can be located over corresponding word line vias, with these differently connected vias interleaved (e.g., alternating between vias that are directly connected to overlying word line bond pads and vias that are connected to bond pads in the array region through traces). The traces can extend on either side of the via rows. For space efficiency, the bond pads can be arranged in a repeating hexagonal (honeycomb) arrangement.

[0028] FIG. 1 is a functional block diagram of an example memory system 100. FIG. 1The components depicted are electronic circuitry. The memory system 100 includes one or more memory dies 108. The one or more memory dies 108 can be complete memory dies or partial memory dies. In one embodiment, each memory die 108 includes a memory structure 126, a control circuit 110, and a read / write circuit 128. The memory structure 126 is addressable by a word line via a row decoder 124 and by a bit line via a column decoder 132. The read / write / erase circuit 128 includes a plurality of sense blocks 150 including SB1, SB2,..., SBp (sense circuitry) and allows a page of memory cells to be read or programmed in parallel. In addition, many strings of memory cells can be erased in parallel.

[0029] In some systems, the controller 122 is included in the same package (e.g., removable memory card) as the one or more memory dies 108. However, in other systems, the controller can be separate from the memory dies 108. In some embodiments, the controller will be on a different die than the memory dies 108. In some embodiments, one controller 122 will communicate with multiple memory dies 108. In other embodiments, each memory die 108 has its own controller. Commands and data are transferred between the host 140 and the controller 122 via a data bus 120 and between the controller 122 and the one or more memory dies 108 via lines 118. In one embodiment, the memory dies 108 include a set of input and / or output (I / O) pins connected to the lines 118.

[0030] The control circuit 110 cooperates with the read / write circuits 128 to perform memory operations on the memory structure 126 (e.g., write, read, erase, etc.) and includes a state machine 112, an on-chip address decoder 114, and a power control circuit 116. In one embodiment, the control circuit 110 includes a buffer such as a register, a ROM fuses, and other storage devices for storing default values such as base voltages and other parameters.

[0031] The on-chip address decoder 114 provides an address interface between the addresses used by the host 140 or controller 122 to the hardware addresses used by the decoders 124 and 132. The power control circuit 116 controls the power and voltages provided to the word lines, bit lines, and select lines during memory operations. In one embodiment, the power control circuit 116 includes voltage circuitry. The power control circuit 116 includes a charge pump 117 for generating voltages. The sense blocks include bit line drivers. In one embodiment, the power control circuit 116 is executed under the control of the state machine 112.

[0032] The state machine 112 and / or controller 122 (or equivalent functional circuitry) communicates with the memory structure 126 via the read / write circuits 128 and the on-chip address decoder 114. The state machine 112 and / or controller 122 (or equivalent functional circuitry) also communicates with the host 140 via the data bus 120 and with an external memory interface 130 via the lines 118. FIG. 1The combination of all or a subset of the other circuits depicted can be considered to be a control circuit that performs the various functions described herein. A control circuit can include hardware only, or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is one example of a control circuit. A control circuit can include a processor, a PGA (programmable gate array), an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), an integrated circuit, or other type of circuit.

[0033] The (on-chip or off-chip) controller 122 (circuit in one embodiment) can include one or more processors 122c, ROM 122a, RAM 122b, a memory interface (MI) 122d, and a host interface (HI) 122e, all interconnected. The storage devices (ROM 122a, RAM 122b) store code (software) such as instruction sets (including firmware), and the one or more processors 122c are operable to execute the instruction sets to provide the functions described herein. Alternatively or additionally, the one or more processors 122c can access code from storage devices in the memory structure, such as a reserved area of memory cells connected to one or more word lines. The RAM 122b can be used to store data for the controller 122, including cached program data (discussed below). The memory interface 122d in communication with the ROM 122a, RAM 122b, and the processor(s) 122c is circuitry that provides an electrical interface between the controller 122 and the one or more memory dies 108. For example, the memory interface 122d can change the format or timing of signals, provide a buffer, isolate from surges, latch I / O, etc. The one or more processors 122c can issue commands to the control circuit 110 (or another component of the memory die 108) via the memory interface 122d. The host interface 122e provides an electrical interface with the host 140 data bus 120 to receive commands, addresses, and / or data from the host 140 to provide data and / or status to the host 140.

[0034] In one embodiment, the memory structure 126 includes a three-dimensional memory array of non-volatile memory cells, with multiple levels of memory formed over a single substrate such as a wafer. The memory structure can include any type of non-volatile memory formed monolithically in one or more physical layers of memory cells, with active regions disposed over a silicon (or other type) substrate. In one example, the non-volatile memory cells include vertical NAND strings with charge-trapping material.

[0035] In another implementation, the memory structure 126 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells that utilize a floating gate. Other types of memory cells (e.g., NOR type flash memory) can also be used. The exact type of memory array architecture or memory cell included in the memory structure 126 is not limited to the examples described above.

[0036] FIG. 2A is a block diagram of an example memory system 100 depicting more details of one implementation of the controller 122. FIG. 2A The controller in is a flash memory controller, but it should be noted that the non-volatile memory die 108 is not limited to flash. Thus, the controller 122 is not limited to the example of a flash memory controller. As used herein, a flash memory controller is a device that manages data stored on a flash memory and communicates with a host such as a computer or electronic device. In addition to the specific functionality described herein, a flash memory controller can have various functionality. For example, a flash memory controller can format the flash memory to ensure proper operation of the memory, map out bad flash memory cells, and allocate spare memory cells to replace future failed cells. Some of the spare cells can be used to hold firmware to operate the flash memory controller and implement other features. In operation, when a host needs to read data from or write data to the flash memory, it will communicate with the flash memory controller. If the host provides a logical address to read / write data, the flash memory controller can convert the logical address received from the host to a physical address in the flash memory. (Alternatively, the host can provide a physical address). The flash memory controller can also perform various memory management functions such as, but not limited to, wear leveling (spreading writes to avoid wearing out particular memory blocks that would otherwise be repeatedly written to) and garbage collection (after a block is full, only valid data pages are moved to a new block so the full block can be erased and reused).

[0037] The interface between the controller 122 and the non-volatile memory die 108 can be any suitable flash interface such as the switch mode 200, 400, or 800. In one implementation, the memory system 100 can be a card-based system such as a secure digital (SD) or micro-secure digital (micro-SD) card. In alternative implementations, the memory system 100 can be part of an embedded memory system. For example, the flash memory can be embedded within a host. In other examples, the memory system 100 can be in the form of a solid state drive (SSD).

[0038] In some implementations, the memory system 100 includes a single channel between the controller 122 and the non-volatile memory die 108, the subject matter described herein is not limited to having a single memory channel. For example, in some memory system architectures, there are 2, 4, 8, or more channels between the controller and the memory die, depending on the capabilities of the controller. In any of the implementations described herein, even though a single channel is shown in the figures, there can be more than one single channel between the controller and the memory die.

[0039] As FIG. 2A The controller 122 includes a front end module 208 that interfaces with the host, a back end module 210 that interfaces with one or more non-volatile memory dies 108, and various other modules that perform functions that will now be described in detail.

[0040] FIG. 2A The components of the controller 122 depicted in FIG. 2 can take the form of, for example, a packaged functional hardware unit (e.g., an electrical circuit) designed for use with other components, a portion of a program code (e.g., software or firmware) executable by a specific function of a (micro)processor or processing circuitry that typically performs the relevant functions, or a self-contained hardware or software component that interfaces with a larger system. For example, each module can include an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a circuit, a digital logic circuit, an analog circuit, a discrete circuit, a gate, or any other type of hardware component, or a combination of any of these. Alternatively or additionally, each module can include software stored in a processor readable device (e.g., a memory) to program a processor to carry out the functions described herein. FIG. 2A The architecture depicted in FIG. 2 is one that can or can not use FIG. 1 One example implementation of the components of the controller 122 (i.e., RAM, ROM, processor, interfaces) depicted in FIG. 2.

[0041] Referring again to the modules of the controller 122, the buffer manager / bus controller 214 manages buffers in random access memory (RAM) 216 and controls internal bus arbitration of the controller 122. Read only memory (ROM) 218 stores system boot code. While FIG. 2A While illustrated as being located separately from the controller 122, in other implementations, one or both of the RAM 216 and the ROM 218 can be located within the controller. In yet other implementations, portions of the RAM and the ROM can be located both within the controller 122 and external to the controller. Further, in some implementations, the controller 122, the RAM 216, and the ROM 218 can be located on separate semiconductor dies.

[0042] The front-end module 208 includes a host interface 220 and a physical layer interface (PHY) 222 that provides an electrical interface to a host or next level storage controller. The type of host interface 220 can be selected depending on the type of memory used. Examples of host interfaces 220 include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface 220 generally facilitates the transfer of data, control signals, and timing signals.

[0043] The back-end module 210 includes an error correction code (ECC) engine 224 that encodes data bytes received from a host and decodes and error corrects data bytes read from the non-volatile memory. A command sequencer 226 generates command sequences, such as program command sequences and erase command sequences, for transmission to the non-volatile memory die 108. A RAID (redundant array of independent dies) module 228 manages the generation of RAID parity and the recovery of failed data. The RAID parity can be used as an additional level of integrity protection for data written into the memory device 100. In some cases, the RAID module 228 can be part of the ECC engine 224. It should be noted that the RAID parity can be added as an extra die or dies as the common name implies, but can also be added within the existing dies, for example, as an extra plane, or extra blocks, or extra WLs within the blocks. A memory interface 230 provides command sequences to the non-volatile memory die 108 and receives status information from the non-volatile memory die 108. In one embodiment, the memory interface 230 can be a double data rate (DDR) interface, such as a Toggle Mode 200, 400, or 800 interface. A flash control layer 232 controls the overall operation of the back-end module 210.

[0044] FIG. 2A Additional components of the illustrated memory system 100 include a media management layer 238 that performs wear leveling of the memory cells of the non-volatile memory die 108. The memory system 100 also includes other discrete components 240, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that can interface with the controller 122. In alternative embodiments, one or more of the physical layer interface 222, the RAID module 228, the media management layer 238, and the buffer management / bus controller 214 are optional components that are not needed in the controller 122.

[0045] A flash translation layer (FTL) or media management layer (MML) 238 can be integrated as part of the flash management that can handle flash errors and interface with the host. In particular, the MML can be a module in flash management and can be responsible for the internals of NAND management. In particular, the MML 238 can include an algorithm in the memory device firmware that translates writes from the host to writes to the memory structure 126 of the memory die 108. The MML 238 can be needed because: 1) the memory can have limited endurance; 2) the memory structure 126 can only be written to in multiples of pages; and / or 3) the memory structure 126 can not be written to unless it is erased as a block (or in some embodiments, as a tier within a block). The MML 238 understands these potential limitations of the memory structure 126, which can not be visible to the host. Thus, the MML 238 attempts to translate writes from the host to writes into the memory structure 126.

[0046] The controller 122 can interface with one or more memory dies 108. In one embodiment, the controller 122 and the plurality of memory dies (together comprising the memory system 100) implement a solid state drive (SSD), which can emulate, replace, or be used in place of a hard disk drive within a host such as a NAS device, in a laptop, in a tablet, in a server, etc. Additionally, the SSD need not function as a hard disk drive.

[0047] Some embodiments of the non-volatile storage system will include one memory die 108 connected to one controller 122. However, other embodiments can include a plurality of memory dies 108 in communication with one or more controllers 122. In one example, the plurality of memory dies can be grouped as a set of memory packages. Each memory package includes one or more memory dies in communication with the controller 122. In one embodiment, the memory package includes a printed circuit board (or similar structure) on which the one or more memory dies are mounted. In some embodiments, the memory package can include a molding material to encapsulate the memory dies of the memory package. In some embodiments, the controller 122 is physically separate from any of the memory packages.

[0048] In one embodiment, control circuitry (e.g., control circuitry 110) is formed on a first die, referred to as a control die, and a memory array (e.g., memory structure 126) is formed on a second die, referred to as a memory die. For example, some or all of the control circuitry associated with the memory (e.g., control circuitry 110, row decoder 124, column decoder 132, and read / write circuitry 128) may be formed on the same control die. The control die may be bonded to one or more corresponding memory dies to form an integrated memory component. The control die and the memory die may have bonding pads arranged for electrical connection to each other. The bonding pads of the control die and the memory die may be aligned and bonded together using any of a variety of bonding techniques, depending in part on the bonding pad size and bonding pad spacing (i.e., bonding pad pitch). In some embodiments, the bonding pads are bonded directly to each other without solder or other additional materials in a so-called Cu-Cu bonding process. In some examples, the dies are bonded in a one-to-one arrangement (e.g., one control die to one memory die). In some examples, there may be more than one control die and / or more than one memory die in an integrated memory assembly. In some embodiments, the integrated memory assembly includes a stack of multiple control dies and / or multiple memory dies. In some embodiments, the control die is connected to or otherwise communicates with a memory controller. For example, the memory controller may receive data to be programmed into the memory array. The memory controller forwards the data to the control die so that the control die can program the data into the memory array on the memory die.

[0049] FIG. 2B Shown FIG. 2A An alternative arrangement to the arrangement of , which may be achieved using wafer-to-wafer bonding to provide bonded die pairs. FIG. 2B 1. A functional block diagram of one embodiment of an integrated memory component 307 is depicted. One or more integrated memory components 307 can be used in a memory package in the memory system 100. The integrated memory component 307 includes two types of semiconductor dies (or more simply, "dies"). Memory die 301 includes memory structure 126.

[0050] Control die 311 includes column control circuitry 364, row control circuitry 320, and system control logic 360 (including state machine 312, power control module 316 (including charge pump 117), storage device 366, and memory interface 368). In some embodiments, control die 311 is configured to connect to memory structure 126 in memory die 301. FIG. 2BAn example of a peripheral circuit is shown that includes control circuitry formed in the peripheral circuit or control die 311 that is coupled to the memory array 126 formed in the memory die 301. The system control logic 360, row control circuitry 320, and column control circuitry 364 are located in the control die 311. In some embodiments, all or a portion of the column control circuitry 364 and all or a portion of the row control circuitry 320 are located on the memory die 301. In some embodiments, some of the circuitry in the system control logic 360 is located on the memory die 301.

[0051] The system control logic 360, row control circuitry 320, and column control circuitry 364 can be formed from conventional processes (e.g., CMOS processes) such that adding elements and functionality more commonly found on the memory controller 102, such as ECC, can require few or no additional process steps (i.e., the same process steps used to manufacture the memory controller 102 can also be used to manufacture the system control logic 360, row control circuitry 320, and column control circuitry 364). Thus, while removing such circuitry from a die, such as the memory die 301, can reduce the number of steps required to manufacture such a die, adding such circuitry to a die, such as the control die 311, can not require many additional process steps.

[0052] FIG. 2B Column control circuitry 364 including the sense block 350 on the control die 311 is shown coupled to the memory array 126 on the memory die 301 by electrical paths 370. For example, the electrical paths 370 can provide electrical connections between the column decoders 332, driver circuitry 372 (bit line driver circuitry), block selectors 373, and the bit lines of the memory array (or memory structure) 126. The electrical paths can extend from the column control circuitry 364 in the control die 311 through pads on the control die 311 that are bonded to corresponding pads of the memory die 301 that are connected to the bit lines of the memory structure 126. Each bit line of the memory structure 126 can have a corresponding electrical path in the electrical paths 370 connected to the column control circuitry 364, including a pair of bonded pads. Similarly, the row control circuitry 320 (including the row decoders 324, array drivers 374 (word line driver circuitry), and block selectors 376) is coupled to the memory array 126 by electrical paths 308. Each of the electrical paths 308 can correspond to a word line, dummy word line, or select gate line. Additional electrical paths can also be provided between the control die 311 and the memory die 301.

[0053] In some embodiments, there is more than one control die 311 and / or more than one memory die 301 in the integrated memory component 307. In some embodiments, the integrated memory component 307 includes a stack of multiple control dies 311 and multiple memory dies 301. In some embodiments, each control die 311 is attached (e.g., bonded) to at least one of the memory dies 301.

[0054] FIG. 3 is a perspective view of part of one example embodiment of a monolithic three-dimensional memory array including a memory structure 126 including a plurality of non-volatile memory cells. For example, FIG. 3 A portion of one memory block is shown. The depicted structure includes a set of bit lines BL located above a stack of alternating layers of dielectric material and conductive material on a substrate. For example, one of the dielectric layers is labeled D and one of the conductive layers (also referred to as word line layers) is labeled W. The number of alternating dielectric and conductive layers can vary based on particular implementation requirements. One set of embodiments includes between 108 and 300 alternating dielectric and conductive layers. One example embodiment includes 96 data word line layers, 8 select layers, 6 dummy word line layers, and 110 dielectric layers. More or fewer than 108 to 300 layers can also be used. The data word line layers have data memory cells. The dummy word line layers have dummy memory cells. As will be explained below, the alternating dielectric and conductive layers are divided into “fingers” in zones separated by local interconnects LI. FIG. 3 Two zones are shown, each with a respective NAND string and two local interconnects LI. Under the alternating dielectric and word line layers are source line layers SL. Memory holes are formed in the stack of alternating dielectric and conductive layers. For example, one of the memory holes is labeled MH. Note that in FIG. 3 In, the dielectric layers are depicted as a perspective view so that the reader can see the memory holes located in the stack of alternating dielectric and conductive layers. In one embodiment, the NAND strings are formed by filling the memory holes with material including a charge trapping material to form a vertical column of memory cells. Each memory cell can store one or more bits of data.

[0055] FIG. 4Ais a block diagram illustrating one example organization of memory structure 126, which is divided into two planes 302 and 304. Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, different numbers of blocks and planes can be used. In one implementation, for two-plane memory, the block IDs are generally such that even blocks belong to one plane and odd blocks belong to the other plane; thus, plane 302 includes blocks 0, 2, 4, 6,..., and plane 304 includes blocks 1, 3, 5, 7,.... In one implementation, a block of memory cells is an erase unit. That is, all memory cells of one block are erased together. In other implementations, memory cells can be grouped into blocks for other reasons, such as to organize memory structure 126 to enable signaling and selection circuitry.

[0056] FIGS. 4B-4C An example 3D NAND structure is depicted. FIG. 4B is a block diagram depicting a top view of a portion of one block from memory structure 126. FIG. 4B The portion of the block depicted in FIG. 4A portion 306 in block 2 of. In one implementation, the memory array will have 60 layers. Other implementations have fewer or more than 60 layers (e.g.,. However, FIG. 4B Only the top layer is shown.

[0057] FIG. 4B A plurality of circles representing vertical columns is depicted. Each of the vertical columns includes a plurality of select transistors and a plurality of memory cells. In one implementation, each vertical column implements one NAND string. For example, FIG. 4B Vertical columns 422, 432, 442, and 452 are depicted. Vertical column 422 implements NAND string 482. Vertical column 432 implements NAND string 484. Vertical column 442 implements NAND string 486. Vertical column 452 implements NAND string 488. More details of this vertical column are provided below. A block can include more than FIG. 4B More vertical columns than depicted in

[0058] FIG. 4B A set of bit lines 425, including bit lines 411, 412, 413, 414,..., 419, is also depicted. FIG. 4B Twenty-four bit lines are shown because only a portion of the block is depicted. It is contemplated that more than twenty-four bit lines are connected to the vertical columns of the block. Each of the circles representing vertical columns has an "x" to indicate that it is connected to one bit line. For example, bit line 414 is connected to vertical columns 422, 432, 442, and 452.

[0059] FIG. 4BThe depicted block includes a set of local interconnects 402, 404, 406, 408, and 410 that connect the various tiers to the source lines below the vertical columns. The local interconnects 402, 404, 406, 408, and 410 also serve to divide each tier of the block into four zones; for example, FIG. 4B The top tier depicted is divided into zones 420, 430, 440, and 450, which are referred to as fingers. In a tier of a block that implements memory cells, the four zones are referred to as word line fingers that are separated by local interconnects. In one embodiment, the word line fingers on a common level of a block are connected together at the ends of the block to form a single word line. In another embodiment, the word line fingers on a common level are not connected together. In one example implementation, a bit line is connected to only one vertical column in each of the zones 420, 430, 440, and 450. In that implementation, each block has sixteen rows of active columns, and each bit line is connected to four rows in each block. In one embodiment, all of the four rows connected to a common bit line are connected to the same word line (via different word line fingers on a common level that are connected together); thus, the system uses source side select lines and drain side select lines to select one of the four (or another subset) to perform a memory operation (program, verify, read, and / or erase).

[0060] Although FIG. 4B The depiction shows that each zone in a block has four rows of vertical columns, and that the four zones have sixteen rows of vertical columns, but those exact numbers are example implementations. Other embodiments can include more or fewer zones per block, more or fewer rows of vertical columns per zone, and more or fewer rows of vertical columns per block.

[0061] FIG. 4C The depiction also shows that the vertical columns are staggered. In other embodiments, different staggering patterns can be used. In some embodiments, the vertical columns are not staggered.

[0062] FIG. 4B A portion of an embodiment of the three-dimensional memory structure 126 is depicted, showing a cross-sectional view along the line AA of FIG. 4B The cross-sectional view cuts through the vertical columns 432 and 434 and the zone 430 (see FIG. 4C ). FIG. 4BThe structure includes four drain side select layers SGD0, SGD1, SGD2, and SGD3; four source side select layers SGS0, SGS1, SGS2, and SGS3; four dummy word line layers DD0, DD1, DS0, and DS1; and forty-eight data word line layers WLL0 through WLL47 for connection to data memory cells. Other implementations can implement more or fewer than four drain side select layers, more or fewer than four source side select layers, more or fewer than four dummy word line layers, and more or fewer than forty-eight word line layers (e.g., 96 word line layers or more than 100 word line layers). Vertical columns 432 and 434 are depicted as protruding through the drain side select layers, source side select layers, dummy word line layers, and word line layers. In one implementation, each vertical column includes a NAND string. For example, vertical column 432 includes NAND string 484. Below the vertical columns and the layers listed below are substrate 101, insulating film 454 on the substrate, and source line SL. The NAND string of vertical column 432 has a source end at the bottom of the stack and a drain end at the top of the stack. Consistent with FIG. 4C FIG. 4C Vertical column 432 is shown connected to bit line 414 via connector 415. Local interconnects 404 and 406 are also depicted.

[0063] Bit line 414 is connected to pad 416 by bit line via 417. Additional bit lines coupled to additional vertical columns are similarly connected. Multiple bit lines can extend over such a memory structure and can be connected to multiple blocks by block select circuitry. Such bit lines are connected to pads that can be exposed along the top surface (major surface) of the workpiece, so that they can be used to form electrical connections. Similarly, word lines (e.g., WLL0 through WLL47), dummy word lines (e.g., DD0-1, DS0-1), and select lines (e.g., SGD0 through SGD3) can be coupled to pads on the major surface of the workpiece (e.g., pads that are coplanar with pad 416) by word line vias (not shown in FIG. 4A). For example, word line layers can be arranged in a stepped “staircase” arrangement in an outer region (outside the region where memory cells are formed), so that each word line layer is exposed and can be contacted by a via. FIG. 5

[0064] ​​Non-volatile memory cells are formed along vertical columns that extend through alternating conductive and dielectric layers in a stack. In one embodiment, the memory cells are arranged in NAND strings. Word line layers WLL0 through WLL47 are connected to memory cells, also referred to as data memory cells. Dummy word line layers DD0, DD1, DS0, and DS1 are connected to dummy memory cells. The dummy memory cells do not store user data, while the data memory cells are eligible to store user data. Drain side select layers SGD0, SGD1, SGD2, and SGD3 are used to electrically connect and disconnect the NAND strings with bit lines. Source side select layers SGS0, SGS1, SGS2, and SGS3 are used to electrically connect and disconnect the NAND strings with source lines SL.

[0065] The exact type of memory array architecture or memory cell included in the memory structure 126 is not limited to the examples described above. Many different types of memory array architecture or memory cell technology can be used to form the memory structure 126. Implementing the claimed new embodiments presented herein does not require a particular non-volatile memory technology. Other examples of technologies suitable for the memory cells of the memory structure 126 include ReRAM memory, magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), phase change memory (e.g., PCM), etc. Examples of suitable technologies for the architecture of the memory structure 126 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc. One of ordinary skill in the art will recognize that the technology described herein is not limited to a single particular memory structure, but encompasses many related memory structures within the spirit and scope of the technology described herein and as understood by one of ordinary skill in the art.

[0066] One example of ReRAM memory includes a reversible resistance switching element arranged in a cross-point array accessed by X and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells can include a conductive bridge memory element. The conductive bridge memory element can also be referred to as a programmable metallization cell. The conductive bridge memory element can function as a state change element based on physical repositioning of ions within a solid electrolyte. In some cases, the conductive bridge memory element can include two solid metal electrodes, one of which is relatively inert (e.g., tungsten) and the other of which is electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases, which results in a lower programming threshold for the conductive bridge memory cell. Thus, the conductive bridge memory element can have a wide range of programming thresholds across a range of temperatures.

[0067] Magnetoresistive memory (MRAM) stores data by magnetic storage elements. The elements are formed from two ferromagnetic plates, each of which can hold a magnetization, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a particular polarity; the magnetization of the other plate can be changed to match the magnetization of an external magnetic field to store memory. This configuration is called a spin valve, and is the simplest structure for an MRAM bit. Memory devices are constructed from a grid of such memory cells. In one embodiment for programming a non-volatile storage system, each memory cell is located between a pair of write lines, which are arranged at right angles to each other, parallel to the cell, one above the cell and one below the cell. When current is passed through them, an induced magnetic field is created.

[0068] Phase change memory (PCRAM) takes advantage of the unique properties of chalcogenide glasses. One embodiment uses a GeTe-Sb2Te3superlattice to achieve non-thermal phase changes by changing the coordination state of germanium atoms using only a laser pulse (or a light pulse from another source). Thus, the dose of programming is the laser pulse. A memory cell can be inhibited by preventing it from receiving light. It should be noted that the use of "pulse" in this document does not require a rectangular pulse, but includes a (continuous or non-continuous) vibration or burst of sound, current, voltage light or other wave.

[0069] FIG. 3 The process of wafer-to-wafer bonding of wafer 500 and wafer 600 is illustrated. Substrate 501 is processed to fabricate a memory die including a non-volatile memory array (e.g., memory structure 126), interconnect structures, and pads for bonding, as discussed above with reference to FIGS. 4A-4C and FIG. 2B Substrate 601 is processed to fabricate a control die including memory control circuitry (e.g., logic circuitry formed as CMOS circuitry), interconnect structures, and pads for bonding, as discussed above with reference to FIG. 5The discussed, thereby forming wafer 600. Wafer 500 is then flipped (either wafer can be flipped) in this example, so that major surface 506 of wafer 500 is opposite major surface 606 of wafer 600. Wafers 500 and 600 are aligned so that corresponding dies are aligned in pairs (in a one-to-one arrangement of memory dies and control dies), and pads on such pairs of dies are aligned for bonding. Subsequently, with wafers 500, 600 aligned, pressure and / or heat or other conditions are applied to wafers 500, 600 to bond the respective pads together, thereby forming electrical connections between the memory arrays of wafer 500 and the control circuitry of wafer 600 (i.e., bonding along the interface between major surfaces 506, 606). Bonded wafers 500 and 600 form a combined wafer 700 that includes pairs of dies, where each pair includes a memory die and a control die that form a memory system. Combined wafer 700 can be scribed (diced) into pairs of dies 702 for packaging. Combined wafer 700 or a portion of such a wafer can be referred to as a CMOS bonded array (CbA), and an individual pair of dies 702 (a memory die and a control die) can be referred to as an integrated memory component.

[0070] One feature of wafer-to-wafer bonding as described with reference to FIG. 5 One feature of wafer-to-wafer bonding as described with reference to

[0071] FIG. 5Another feature of the one-to-one relationship between memory dies and control dies of an integrated memory component is that the failure rate of the integrated memory component can be relatively high and multiple“good” dies (memory dies and control dies that meet specifications and are free of defects) can be wasted. Good memory dies can be joined to bad control dies, and good control dies can be joined to bad memory dies, resulting in bad integrated memory components. For example, where 5% of the memory dies are bad (defective) and 5% of the control dies are bad (defective), the resulting yield loss can be about 10% (e.g., about 10% of the resulting integrated memory components are defective because of a defective memory die or a defective control die). Even if bad dies are identified prior to joining, wafer-to-wafer joining can not allow for any rearrangement of die pairings (e.g., a given die is paired with a counterpart die based on its physical location in the wafer, which can not be able to be changed prior to wafer-to-wafer joining).

[0072] According to aspects of the present technology, an integrated memory component can not be limited to FIGS. 6A-6Bone-to-one arrangement, free from die size matching constraints and can allow integration of high-density memory structures in an efficient manner with lower failure rates than wafer-to-wafer bonding (e.g., less defective integrated memory assemblies for a given die failure rate). According to examples presented below, two or more memory small dies or chips (e.g., memory dies such as memory die 301 having a memory structure 126 that can form one or more planes or sub-planes and is not limited by die size matching) can be combined with a control die having slots (e.g., bond pad arrangements connected to corresponding control circuitry) to accommodate multiple memory small chips (e.g., bonded directly to the control die). Each memory small chip can be composed of an appropriate unit of memory structure (e.g., one, two or more planes or sub-planes of NAND memory). The memory small chips in such an arrangement can be the same or different. For example, the small chips can have different capacities (e.g., number of planes or blocks), different structures (e.g., different number of layers), different configurations (e.g., configured to store different number of bits per cell), and / or otherwise be different. Such an arrangement can be able to accommodate different needs (e.g., by using small chips of different capacities and / or different number of small chips, the capacity can be configurable), and can combine high performance and low cost (e.g., some high performance small chips for demanding applications and some low cost small chips for less demanding applications). Testing of the small chips and / or control die prior to assembly can reduce the number of defective integrated memory assemblies (e.g., compared to wafer-to-wafer bonding). For example, defective control dies in a wafer can be identified, marked as defective and can not be bonded to any small chips, while defective small chips can be identified and discarded without being bonded to any control die. Such die screening prior to bonding can have significant benefits. For example, in a case where 5% of the memory small chips and 5% of the control dies are defective, discarding the defective memory small chips and bonding the remaining good memory small chips (95%) to good control dies (without being bonded to the defective 5% of the control dies), such that the yield loss is limited to 5% (e.g., about half of the yield loss of a wafer-to-wafer bonding of similar dies).

[0073] FIG. 6A An example of a die-to-wafer bonding is shown in which four memory small chips (memory dies) 610a-610d are bonded to a control die 612 in a silicon wafer 600. For example, the silicon wafer 600 can include a large number of control dies including FIG. 6A control dies 612 and 614 are shown. In some cases, one or more defective control dies can be identified prior to assembly of the integrated memory assemblies (e.g., as in a wafer-to-wafer bonding of similar dies) and can not be bonded to any small chips. In some cases, one or more defective small chips can be identified prior to assembly of the integrated memory assemblies (e.g., as in a wafer-to-wafer bonding of similar dies) and can not be bonded to any control dies. FIG. 5The defective control die 614 is detected. In the example shown, the control die 614 is detected as a defective control die, and thus no memory die is bonded to the control die 614. As with the wafer-to-wafer bonding example of FIGS. 6A-6D, the defective control die 614 can be omitted from the integrated memory component 600, as shown in FIG. 6E. In some examples, the defective control die 614 can be replaced with a replacement control die, as shown in FIG. 6F. FIG. 6B Unlike the wafer-to-wafer bonding example of FIGS. 6A-6D, the bonding can be selective on a die-by-die basis, such that defective dies can be omitted from the bonding, thereby saving resources.

[0074] FIGS. 7A-7B A top view of the control die 612 is shown, which shows an upper (first) surface 616 that includes four slots 616a-616d corresponding to the four memory dies 610a-610d. Each slot 616a-616d can include a bonding pad for bonding to a corresponding bonding pad of a memory die 610a-610d, and each slot can have dimensions that accommodate a memory die (e.g., dimensions equal to or greater than the dimensions of the opposing (second) surface of the memory die or die). Each memory die can be individually aligned and bonded. For example, the memory die 610a can be aligned with and bonded to the corresponding slot 616a of the corresponding control die 612, and subsequently, the memory die 610b can be aligned with and bonded to the corresponding slot 616b of the corresponding control die 612, and so on, until the desired number of memory dies are bonded to the control die 612. Subsequently, the memory dies can be aligned and bonded to additional control dies of the wafer 600 (omitting defective control dies such as the control die 614). In some examples, the order of such bonding can be different from the example described above.

[0075] FIG. 7A Another example of a die-to-wafer bonding is shown in which eight memory dies (memory dies) 620a-620h are bonded to a control die 622 in a silicon wafer 600. For example, the silicon wafer 600 can include a large number of control dies, including the control dies 622 and 624 shown. Defective control dies can be detected prior to assembly of the integrated memory component (e.g., prior to bonding the memory dies to the control dies as shown in FIG. 6G) and omitted from the integrated memory component. FIG. 7A The defective control die 624 is detected. In the example shown, the control die 624 is detected as a defective control die, and thus no memory die is bonded to the control die 624. FIG. 7B

[0076] FIGS. 6A-7B ​A top view of control die 622 is shown, which shows an upper (first) surface 626 that includes eight slots 626a-626h corresponding to the eight memory dies 620a-620h. Each slot 626a-626h can include a bond pad for bonding to a corresponding bond pad of a memory die 620a-620h, and each slot can have dimensions that accommodate a memory die (e.g., dimensions equal to or greater than the dimensions of the opposing (second) surface of a memory chiplet or die).

[0077] Although FIGS. 8A-8B Examples of control dies 612 and 622 are shown with four and eight slots, respectively, but the number of slots and the arrangement of the slots is not limited to any particular number or arrangement. The example described here is illustrative for purposes of explanation and is not intended to provide an exhaustive list of all possible implementations. Moreover, control dies in a given silicon wafer can not be identical. For example, a single silicon wafer can include control dies with four slots (e.g., control die 612) and control dies with eight slots (e.g., control die 622) or otherwise different dies.

[0078] In addition to providing flexibility regarding whether to bond a die (e.g., to bond only good dies), aspects of the present technology can also provide flexibility regarding how many memory chiplets and what types of memory chiplets to bond to a given control die. It is not generally required that every slot on a control die be occupied by a memory chiplet in order to form a functionally integrated memory assembly.

[0079] For example, FIGS. 9A-9B A case is shown in which control die 612 has four slots 616a-616d, two of which have been used (occupied) slots 616a and 616c and two of which are unused (empty) slots 616b and 616d. Memory chiplets 610a and 610c are bonded in corresponding slots 616a and 616c, while no memory chiplets are bonded in slots 616b and 616d, which remain empty. The assembly composed of control die 612 and memory chiplets 610a and 610c can be considered a completed integrated memory assembly.

[0080] FIGS. 10A-10B Another example is shown in which control die 622 has eight slots 626a-626h, six of which have been used slots 626a and 626c-626g and two of which are unused slots 626b and 626h. Memory chiplets 620a and 620c-620g are bonded in corresponding slots 626a and 626c-626g, while no memory chiplets are bonded in slots 626b and 626h, which remain empty. The assembly composed of control die 622 and memory chiplets 620a and 620c-620g can be considered a completed integrated memory assembly.

[0081] According to aspects of the technology, an integrated memory component can be formed using two or more different memory dies (e.g., memory dies having different structures, capacities, configurations, and / or otherwise different memory dies). For example, a first type of memory die and a second type of additional memory die.

[0082] FIGS. 10A-10B An example is shown in which different memory dies are bonded to a control die 622 to form an integrated memory component. Memory dies 630a and 630c-630g are not the same. For example, memory die 630a is physically larger than memory dies 630c-630g and occupies two slots 626a and 626e. Memory die 630a can be designed to interface with the bonding pads of two slots so that it can be bonded as shown (e.g., the slots can define a minimum memory die footprint and bonding pad arrangement without limiting the die size to a single slot). Memory die 630c is smaller than memory die 630a (e.g., about half the size) and can accordingly have a smaller capacity (e.g., half the capacity with similar structure and configuration). Memory die 630d has a greater number of layers than memory die 630c (e.g., more word line layers and more memory cells providing more data storage capacity). Memory die 630f has a different configuration than memory die 630c (e.g., although memory die 630c can be configured to store four bits per cell (QLC), memory die 630f can be configured to store three bits per cell (TLC) or one bit per cell (SLC)). Memory die 630g can have a different structure than memory die 630c. For example, although memory die 630c can have a 3D NAND flash memory structure, memory die 630g can have a different structure (e.g., ReRAM, MRAM, PCM, or other structure). Although FIG. 10B The different memory dies shown are provided as examples, but the range of memory dies that can be bonded to a single control die is not limited to the examples described.

[0083] Forming integrated memory components from memory dies having different characteristics allows customization of integrated memory components for particular uses in a cost-saving manner (e.g., combining high-performance memory dies with cheaper, lower-performance memory dies). Memory dies manufactured using older technology can be integrated with memory dies using newer technology in order to obtain the benefits of the newer technology at a lower overall cost. The data storage capacity of such integrated memory components can be configured by selecting the number and capacity of the memory dies used. Common control die designs can be used to provide integrated memory components having different capacity ranges. Integrated memory components having different capacities (and / or other different characteristics) can be formed in the same manufacturing facility and can be formed from the same silicon wafer (e.g., silicon wafer 600 can include a control die bonded to a different set of memory dies than those bonded to control die 622).

[0084] The bond pads of any of the slots (e.g., FIG. 11A The bond pads of any of the slots 626a-626h on the upper surface 626 of the slot 626c can be arranged to align with corresponding bond pads on the (second) surface of the memory die. FIG. 11B An example of the bond pads of slot 626c is shown, including a bit line bond pad 1150 located in the middle of the slot 626c, and word line bond pads 1152a, 1152b located on either side of the bit line bond pad 1150. The bit line bond pad 1150 can be connected to a bit line driver circuit (e.g., driver circuit 372 of column control circuit 364) in the control die 622. The word line bond pads 1152a-1152b can be connected to a word line driver circuit (e.g., array driver 374 of row control circuit 320) in the control die 622. Additional bond pads 1154 are provided in the slot 626c, and can include bond pads providing one or more voltages, e.g., ground or 0 volts, a supply voltage such as 3 volts, 5 volts, or other non-zero voltage, one or more clock signals, and / or voltages or signals that can be used by the memory die.

[0085] FIG. 10B A corresponding bond pad on the surface 632c (second surface) of the memory die 630c is shown, corresponding to (and in FIG. 11A bonded to) the bond pads of the slot 626c shown. FIG. 11B The corresponding bond pad on the surface 632c (second surface) of the memory die 630c is shown, corresponding to (and in FIG. 4C bonded to) the bond pads of the slot 626c shown. FIG. 4CThe bit line engagement pads 1150 can be connected to bit lines in the memory chiplet 630c (e.g., bit lines BL0 to BL15). The word line engagement pads 1162a-1162b can be connected to word lines (e.g., word lines WLL0 to WLL47) in the memory chiplet 630c. Additional engagement pads 1164 are disposed on the surface 632c and can correspond to the additional engagement pads 1154 (e.g., pads for one or more voltages, clock signals, and / or other signals). FIG. 12 The bit line engagement pads 1150 can be connected to bit lines in the memory chiplet 630c (e.g., bit lines BL0 to BL15). The word line engagement pads 1162a-1162b can be connected to word lines (e.g., word lines WLL0 to WLL47) in the memory chiplet 630c. Additional engagement pads 1164 are disposed on the surface 632c and can correspond to the additional engagement pads 1154 (e.g., pads for one or more voltages, clock signals, and / or other signals).

[0086] During fabrication of the integrated memory assembly, the memory chiplets can be aligned such that the engagement pads of the memory chiplets are aligned with corresponding engagement pads of the slots on the surface of the control die. For example, the memory chiplet 630c is aligned with the slot 626c such that the bit line engagement pads 1150 of the slot 626c (first bit line engagement pads) are aligned with the bit line engagement pads 1160 on the surface 632c (second bit line engagement pads), the first word line engagement pads 1152a-1152b are aligned with the second word line engagement pads 1162a-1162b, and the first additional engagement pads 1154 are aligned with the second additional engagement pads 1164. Bonding of the engagement pads can then be performed such that the first bit line engagement pads 1150 are bonded to the second bit line engagement pads 1160, the first word line engagement pads 1152a-1152b are bonded to the second word line engagement pads 1162a-1162b, and the first additional engagement pads 1154 are bonded to the second additional engagement pads 1164, resulting in connection of the control circuitry in the control die 622 with corresponding components of the memory chiplet 630c (e.g., bit line drivers connected to bit lines and word line drivers connected to word lines).

[0087] FIG. 2B An example of an integrated memory assembly 1270 formed by bonding two memory chiplets 1272a and 1272c to the control die 622 is illustrated. Certain components of the control die 622 were previously described with respect to the control die 311 of the integrated memory assembly 307 FIG. 13 ) and are not further described here.

[0088] In contrast to integrated memory component 307, integrated memory component 1270 includes two memory die 1272a and 1272c connected to corresponding slots 616a and 616c of control die 622. Memory die 1272a and 1272c each include word lines 1274 and bit lines 1276 and are aligned and bonded such that pads of memory die 1272a and 1272c are bonded to corresponding pads of slots 616a and 616c to connect WL 1274 to row control circuitry 320 and BL 1276 to column control circuitry 364. Slots 616b and 616d are not used in integrated memory component 1270. System control logic 360 can include circuitry to detect the presence / absence of a memory die at each of slots 616a-616d and to configure operations accordingly. For example, memory interface circuitry 1278 can be configured to detect the presence / absence of a memory die at each slot 616a-616d (and can perform additional detection of, e.g., the capacity and / or configuration of each memory die). The physical configuration (number and type of memory die) can be used to determine the available space for data storage (e.g., to initiate a logical to physical mapping). Memory access operations (e.g., write operations, read operations, and erase operations) can be directed according to the configuration detected by memory interface circuitry 1278 (e.g., by accessing memory die 1272a and 1272c through corresponding slots 616a and 616c, without attempting to access through slots 616b and 616d).

[0089] In some memory dies including a 3D memory structure (e.g., memory structure 126), one or more stair regions can be provided to facilitate connection of word lines in different word line layers. For example, a stair region can be provided on either side of the memory array region to facilitate connection of word lines from both sides of the memory structure.

[0090] FIG. 13 An example of a stair structure including stepped word line (control gate) layers is shown, along with an example of connections to bond pads, where each word line layer is connected to a separate bond pad. In this example, the word line layers (along with the select gate layers) form a step or stair at one side of the block (a similar stair can be formed on the opposite side of the structure). A vertical word line via is formed on the exposed top portion of each word line layer, such that each word line is electrically connected to a corresponding vertical word line via. Each vertical word line via can extend to a metallization layer above the stack, where a bond pad is formed on the via. The vertical word line via can include a metal or other conductive material. The bond pads can be metal and can be connected to a row decoder to receive voltages for application to the word line layers. Each bond pad can be connected to one or more vias.

[0091] An array region 1300 is shown that includes memory cells formed at intersections of vertical columns (e.g., columns 432) or local bit lines and word lines (e.g., any of WLL0-WLL9). This structure can be similar to that of memory structure 126 as previously described.

[0092] In addition to array region 1300, FIG. 14 A staircase region 1302 is also shown that includes a staircase structure in which the steps correspond to word line layers (additional steps are provided for select gate layers). Bond pads AO-N are at the top of vertical word line vias to enable electrical connections. For example, bond pad N is connected to via 1226, which in turn is connected to a SGS layer. Bond pads M are connected to vertical word line vias 1224 and 1225, which in turn are connected to a WLDS1 layer and a WLDS0 layer (dummy word line layers), respectively. Bond pads C-L are connected to vertical word line vias 1214-1223, which in turn are connected to WLL9-WLL0 layers, respectively. Bond pads B are connected to vertical word line vias 1212 and 1213, which in turn are connected to a WLD0 layer and a WLD1 layer, respectively. Bond pads AO are connected to vias 1210 and 1211, which in turn are connected to a SGD0(0) layer and a SGD1(0) layer, respectively. The SGD0(0) layer and the SGD1(0) layer are used in SB0.

[0093] FIG. 13 An example of a portion of an integrated memory component 1420 is illustrated that includes a memory die 1422 bonded to a control die 1424 that includes an arrangement of bond pads that couple word lines and bit lines in the memory die 1422 to corresponding circuitry in the control die 1424. The memory die 1422 includes a staircase region 1302 and an array region 1300 as described with reference to FIG. 14 The conductive paths 1425 (e.g., vertical word line vias 1210-1226) in the staircase region 1302 of the memory die 1422 are connected to word line bond pads 1426 at a face of the memory die. The word line bond pads 1426 are in turn connected to word line bond pads 1428 on the control die 1424. The word line bond pads 1428 can be connected to circuitry 1430 (e.g., row control circuitry 320 or word line switches / switch circuitry) through conductive paths 1432. Spaces between the dies can be filled with epoxy or other resin or polymer.

[0094] NAND strings including memory cells are connected by bit lines 1434. For example, NAND strings formed by vertical columns 432 are connected to bit lines 1434. Bit lines 1434 are in turn connected to bit line bond pads 1436 by conductive paths 1438. Bit line bond pads 1436 are bonded to corresponding bit line bond pads 1440 of control die 1424, which are connected to control circuitry 1444 (e.g., column control circuitry 364 or bit line control circuitry, including sense amplifiers and / or data latches, or “SADL”) by conductive paths 1442.

[0095] Although FIGS. 15A-15B Vertical connections from word lines in staircase region 1302 through vertical word line vias 1425, bond pads 1426 and 1428, and conductive paths 1432 to circuitry 1430, and from bit lines 1434 through conductive paths 1438, bond pads 1436 and 1440, and conductive paths 1442 to control circuitry 1444 are shown, in some examples, the connections can be made differently.

[0096] FIG. 15A An example is shown in which circuitry in control die 1524 is not directly aligned with corresponding components in memory die 1522. FIG. 15B The arrangement of control circuitry including word line switches WLSW 1530a and 1530b (e.g., row control circuitry) of control die 1524 and SADL 1544 (e.g., column control circuitry) is shown in plan view. FIG. 15B A cross-sectional view of control die 1524 and memory die 1522 is shown in cross-sectional view. Row control circuitry such as word line switches WLSW 1530a and 1530b of control die 1524 can be larger than corresponding staircase regions 1302a and 1302b of memory die 1522, as shown. FIGS. 15A-15B In memory die 1522, some bit line bond pads are not directly above corresponding bit lines (e.g., bit line bond pad 1536 occupies only a central portion of array region 1300 with traces that fan out from bond pad 1536 to connect to a bit line). In control die 1524, word line bond pads 1528a and 1528b are connected to corresponding circuitry, WLSW 1530a and 1530b, by traces that also fan out.

[0097] In contrast to FIGS. 16A-16B FIG. 16A ​An example is shown in which the control die 1624 is bonded with a memory die 1622 having different dimensions (the memory die or small chip is smaller than the control die). This results in a portion of the control die 1624 extending beyond the memory die 1622 to form overhangs 1624a and 1624b. Such dimensional differences can be achieved, for example, using die-to-wafer bonding (or die-to-die bonding) to bond one or more memory small chips into a control circuit wafer (or separately from such a wafer) to corresponding slots of the control die. Although aspects of the technology are described with respect to die-to-wafer bonding, the technology is not limited to such examples.

[0098] FIG. 16B An arrangement of control circuitry including word line switches WLSW 1530a and 1530b (e.g., row control circuitry) of the control die 1524 and SADL 1544 (e.g., column control circuitry) is shown in plan view. The overhangs 1624a and 1624b extend beyond the memory die 1622 in the x-direction and include portions of the WLSW 1530a and 1530b. FIG. 15A A cross-sectional view of the control die 1624 and the memory die 1622 is shown. Row control circuitry such as the word line switches WLSW 1530a and 1530b of the control die 1624 are not aligned with the stair regions 1302a and 1302b of the memory die 1622. In contrast, the SADL 1544 is aligned with the stair regions 1302a and 1302b of the memory die 1622. FIG. 16B Different, FIG. 16B In the memory die 1522, some word line bond pads are located in the array region 1300 and connected to vertical word line vias by horizontal traces that extend from the stair regions 1302a and 1302b to the array region 1300. For example, although the word line bond pad 1662a is directly above and electrically connected to the via 1660a, and the word line bond pad 1662c is directly above and electrically connected to the via 1660c, the vertical word line vias 1660b and 1660d are not connected to the word line bond pads directly above them. The vertical word line via 1660b is connected to the word line bond pad 1662b in the array region 1300 by the trace 1666b, and the via 1660d is connected to the word line bond pad 1662d in the array region 1300 by the trace 1666d. The traces 1666b and 1666d extend from the stair region 1302a into the array region 1300, where they extend over and at right angles to the bit lines.

[0099] In this example, the bit line bond pads of the memory die 1622 are located in the array region 1300. For example, FIGS. 17A-17CBit line bond pads 1664a-1664b are shown. Bit line bond pad 1664a is located between word line bond pad 1662b and word line bond pad 1662d in the array region 1300 in an alternating WL / BL arrangement between bit line bond pads 1664a and 1664b.

[0100] In control die 1624, word line bond pads 1672a and 1672c (bonded to corresponding word line bond pads 1662a and 1662c in the staircase region 1302a) are connected to WLSW 1530a by vertical connections, while word line bond pads 1672b and 1672d (bonded to corresponding word line bond pads 1662b and 1662d in the array region 1300) are connected to WLSW 1530a by traces 1676b and 1676d, respectively. Word line bond pads 1672b and 1672d and bit line bond pads 1674a and 1674b in the array region are in an alternating arrangement corresponding to word line bond pads 1662b, 1662d, bit line bond pads 1664a, and 1664b of memory die 1622. Although bond pads of a single memory die 1622 with corresponding slots of control die 1624 are shown, additional memory dies can be similarly bonded to control die 1624.

[0101] Positioning at least some word line bond pads in the array region can facilitate use of memory dies or small chips that are smaller than the control die (e.g., to facilitate overhang and misalignment of the staircase region with corresponding control circuitry such as WLSW 1530a-1530b). Such an arrangement can also facilitate use of larger bond pads (e.g., not all word line bond pads need to be located in the staircase region) and can be suitable for die-to-wafer bonding (e.g., to provide a larger margin for die-to-wafer misalignment). Traces connecting vertical word line vias in the staircase region with word line bond pads in the array region can be arranged in any suitable pattern. Word line bond pads and bit line bond pads in the array region can be arranged in any suitable pattern.

[0102] FIG. 17A Examples of routing of traces in a control die (e.g., control die 1624) and a corresponding memory die (e.g., memory die 1622) are shown, respectively. FIG. 17BWiring of traces 1676 (e.g., 1676d) in control die 1624 is shown. A row of word line bond pads 1672 (e.g., word line bond pads 1672a-1672d) extends across staircase region 1302a and into array region 1300. Word line bond pads 1672 are connected by traces 1676 to a row of WLSW connections 1673 (locations of WLSW connections 1673 can correspond to locations of WLSW circuitry in control die 1624) located in staircase region 1302a and overhang 1624a. Traces 1676 enable connection of WLSW circuitry (including in overhang 1624a) through bond pads located in staircase region 1302a and array region 1300.

[0103] FIG. 17B Another example of wiring of traces 1666 (e.g., traces 1666a and 1666d) in memory die 1622 is shown. A row of vertical word line vias 1660 (e.g., vias 1660a-1660d) is located in staircase region 1302a, as FIG. 17C Another row of word line bond pads 1762 is also shown in outline. Row 1762 can extend above row 1660 and / or traces 1666 (e.g., word line bond pads can be displaced in the y-direction from the vias to which they are connected).

[0104] FIG. 16B Another example of wiring of traces 1666 (e.g., traces 1666a and 1666d) in memory die 1622 is shown. A row of vertical word line vias 1660 (e.g., vias 1660a-1660d) is located in staircase region 1302a, as FIG. 17CThe first vertical word line vias are directly connected to corresponding bond pads (first bond pads) that are directly above the corresponding vias in the staircase region 1302a. For example, via 1660a is directly connected to word line bond pad 1662a, and via 1660c is directly connected to word line bond pad 1662c. The second vertical word line vias are connected to word line bond pads (second word line bond pads) that are laterally displaced from the corresponding vias in the x-direction and are located in the array region 1300 (e.g., the traces extend across the staircase region 1302a and into the array region 1300). For example, vertical word line via 1660b is connected to word line bond pad 1662b through trace 1666b, and vertical word line via 1660d is connected to word line bond pad 1662d through trace 1666d. The dimensions of the row of word line bond pads 1662 (pad dimensions and spacing) are greater than the dimensions of the vias of row 1660, which can facilitate alignment with the word line bond pads 1672 (e.g., facilitate die to wafer alignment). The traces such as traces 1666b and 1666d can extend over and at right angles to the bit lines (not shown in FIG. 13) in the array region 1300. FIG. 17C The traces such as traces 1666b and 1666d can extend over and at right angles to the bit lines (not shown in FIG. 13) in the array region 1300.

[0105] In this example, the first vias are directly connected to first bond pads in the staircase region, and the second vias are connected to second bond pads in the array region through traces (in other examples, different patterns can be applied). In this example, the first and second vias are interleaved in the staircase region 1302a such that, for example, odd vias are directly connected and even vias are connected through traces (in other examples, different patterns can be used). Although the first word line bond pads 1662 and the second word line bond pads 1662 are aligned to form a row that extends through the staircase region 1302a into the array region 1300, other arrangements can be used. The illustrated trace pattern includes traces on either side of the row 1660 in an alternating arrangement. For example, trace 1666b extends from via 1660b over the row 1660 in the positive y-direction, and trace 1666d extends from via 1660d under the row 1660 in the negative y-direction. FIG. 17C FIG. 17C The arrangement of FIG. 13B can be considered more efficient than the arrangement of FIG. 13A because some vias do not require traces, thereby reducing the number of traces required, and the traces extend on either side of a row of vias to more efficiently use available space. The traces such as traces 1666b and 1666d can be considered examples of means for electrically connecting a second plurality of vertical word line vias to second word line bond pads that are located outside of the staircase region. FIG. 17B The arrangement of FIG. 13B can be considered more efficient than the arrangement of FIG. 13A because some vias do not require traces, thereby reducing the number of traces required, and the traces extend on either side of a row of vias to more efficiently use available space. The traces such as traces 1666b and 1666d can be considered examples of means for electrically connecting a second plurality of vertical word line vias to second word line bond pads that are located outside of the staircase region. FIG. 18A

[0106] ​​Bonding pads (e.g., word line bonding pads and / or bit line bonding pads in any of the previous examples) can be arranged in any suitable pattern. For a given number of bonding pads, the distance between bonding pads (“bonding pitch”) can depend on the arrangement of the bonding pads (e.g., some patterns can achieve a larger spacing for a given number of bonding pads in regions such as staircase regions and / or array regions).

[0107] FIG. 18B A first example of an arrangement of pads 1880a-1880d is shown. In this arrangement, the bonding pads 1880a-1880d are located at the corners of a square such that each bonding pad is displaced from its neighbors in the x-direction and y-direction by the bonding pitch (the square pattern can repeat such that the bonding pads are in a grid arrangement).

[0108] FIG. 16B A second example of an arrangement of bonding pads 1880a-1880g is shown. In this arrangement, the bonding pads 1880a-1880g are arranged in a hexagonal pattern with a bonding pad in the center of the hexagon and one at each corner of the hexagon. Each side of the hexagon is one bonding pitch in length, with the center bonding pad 1800g equidistant from each of the bonding pads 1880a-1880f by one bonding pitch. This pattern, which repeats in a honeycomb arrangement, achieves a more efficient use of available space (e.g., either more bonding pads per unit area for a given bonding pitch, or a larger bonding pitch for a given number of bonding pads per unit area). Word line bonding pads in a staircase region (e.g., word line bonding pads 1662a, 1662c in staircase region 1302a) can be arranged in a hexagonal pattern as shown to enable a larger number of bonding pads to be located in the staircase region and / or to achieve a larger bonding pitch. Word line bonding pads and bit line bonding pads in an array region (e.g., word line bonding pads 1662b, 1662d and bit line bonding pads 1664a, 1664b in array region 1300 of FIG. 18B may be arranged in a repeating hexagonal pattern (e.g., a repeating FIG. 19 arrangement across the x-y plane) to enable a larger number of bonding pads to be located in the array region and / or to achieve a larger bonding pitch.

[0109] FIG. 13 An example of a method in accordance with aspects of the present technology is shown. The method includes: forming a 3D non-volatile memory structure having a memory array region and a staircase region in a memory die, the memory array region including a plurality of non-volatile memory cells connected by word lines and bit lines, the staircase region including a plurality of steps contacted by vertical word line via contacts, each step corresponding to a word line layer 1990 connected to a corresponding via (e.g., forming a structure such as FIG. 20The method also includes forming a plurality of bond pads on a surface of the memory die, the plurality of bond pads including word line bond pads electrically connected to the plurality of word lines and bit line bond pads electrically connected to the plurality of bit lines, the plurality of bond pads being formed such that a first plurality of the word line bond pads are located in the staircase region and a second plurality of the word line bond pads are located in the memory array region 1992 (e.g., word line bond pads 1662b and 1662d located in array region 1300).

[0110] FIG. 19 Examples of additional optional steps that can be combined with the method of FIG. 20 FIG. 1 1 1 1. FIG. 17C includes positioning the first plurality of the word line bond pads directly above corresponding first vertical word line vias to form direct electrical connections between the first plurality of word line bond pads and the first vertical word line vias 2010 (e.g., word line bond pads 1662a and 1662c positioned directly above corresponding vias 1660a and 1660c, respectively); forming a plurality of metal traces electrically connecting the second word line bond pad and a corresponding second vertical word line via, the traces extending above the bit line 2012 (e.g., traces 1666); and positioning the first word line bond pad and the second word line bond pad in a row that extends through the staircase region and the memory array region 2014 (e.g., a row of bond pads 1662 extending through staircase region 1302a and array region 1300). The method optionally includes staggering the first word line vias and the second word line vias in the staircase region, and positioning the traces on either side of the row 2016 (e.g., as shown in FIG. 1 1 1 1). ​

[0111] Examples of apparatus include a memory die having a 3D memory structure including non-volatile memory cells in an array region. The non-volatile memory cells are connected by word lines and bit lines. The word lines are connected to vertical word line vias in a staircase region adjacent to the array region. The vertical word line vias include a first plurality of vertical word line vias connected to first word line bond pads in the staircase region and a second plurality of vertical word line vias connected to second word line bond pads in the array region.

[0112] ​The device can include a plurality of metal traces connecting the second plurality of vertical word line vias to the second word line bond pads, the plurality of metal traces extending over the bit lines in the array region. The device can include a plurality of bit line bond pads located in the array region, each bit line bond pad electrically connected to a corresponding bit line. The first word line bond pads can be disposed in a honeycomb arrangement. The device can include a control die bonded to the memory die such that each bit line bond pad, first word line bond pad, and second word line bond pad is bonded to a corresponding control die bond pad. The control die can be larger than the memory die. The control die can be bonded to at least one additional memory die. Each of the first word line bond pads can be directly above a corresponding via of the first plurality of vertical word line vias in the staircase region, and the second word line bond pads can be laterally shifted from the second plurality of vertical word line vias and connected to the second plurality of vertical word line vias by traces that extend into the array region over the bit lines and at a right angle to the bit lines. The first word line bond pads and the second word line bond pads can be aligned to form a row that extends through the staircase region and the memory array region. The first vertical word line vias and the second vertical word line vias can be interleaved in the staircase region, and the traces extend from the second vertical word line vias on either side of the row.

[0113] Examples of methods include forming a 3D non-volatile memory structure having a memory array region and a staircase region in a memory die, the memory array region including a plurality of non-volatile memory cells connected by a plurality of word lines and a plurality of bit lines, the staircase region including a plurality of steps contacted by vertical word line vias, each step corresponding to a word line layer connected to a corresponding vertical word line via; and forming bond pads on a surface of the memory die, the bond pads including word line bond pads electrically connected to the plurality of word lines and bit line bond pads electrically connected to the plurality of bit lines, the bond pads formed such that a first plurality of word line bond pads are located in the staircase region and a second plurality of the word line bond pads are located in the memory array region.

[0114] The method can further include positioning the first plurality of word line bond pads directly above corresponding first vertical word line vias to form a direct electrical connection between the first plurality of word line bond pads and the first vertical word line vias, and forming a plurality of metal traces electrically connecting the second word line bond pad and a corresponding second vertical word line via, the traces extending above the bit lines. The method can further include positioning the first word line bond pad and the second word line bond pad in a row extending through the staircase region and the memory array region. The method can further include staggering the first vertical word line vias and the second vertical word line vias in the staircase region, and positioning the plurality of metal traces on either side of the row. The method can further include aligning a control die with the memory die such that the word line bond pads and the bit line bond pads are aligned with corresponding control die bond pads on a surface of the control die, and bonding the word line bond pads and the bit line bond pads of the memory die with the corresponding control die bond pads on the surface of the control die. The method can further include subsequently aligning and bonding at least one additional memory die with the control die. Forming the plurality of bond pads can include positioning the plurality of bond pads in a honeycomb arrangement.

[0115] Examples of a memory system include a control circuit die having a plurality of slots for bonding of memory dies, and a plurality of memory dies bonded to corresponding slots of the control circuit die, each memory die having a 3D memory structure including non-volatile memory cells in an array region connected by word lines and bit lines, the word lines connected to vertical word line vias in a staircase region adjacent to the array region, a first plurality of the vertical word line vias connected to a first word line bond pad in the staircase region, each memory die further including means for electrically connecting a second plurality of vertical word line vias to a second word line bond pad located outside of the staircase region.

[0116] The second word line bond pad can be located in the array region with a plurality of bit line bond pads, the second word line bond pad and the plurality of bit line bond pads arranged in a repeating hexagonal pattern. The first word line bond pad and the second word line bond pad can be aligned in a row.

[0117] For the purposes of this document, reference to an “implementation,” “one implementation,” “some implementations,” or “another implementation” can be used to describe different implementations or the same implementation.

[0118] For the purposes of this document, a connection can be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element can be directly connected to the other element or connected to the other element via an intervening element. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. If two devices are directly or indirectly connected, the two devices are “in communication,” such that they can communicate electronic signals between them.

[0119] For the purposes of this document, the term “based on” can be understood as “based at least in part on.”

[0120] For the purposes of this document, the use of the term “about” in conjunction with a numerical value or a range of values can be understood as “substantially around” or “substantially approximately.”

[0121] For the purposes of this document, the term “group” of objects can refer to a “group” of one or more of the objects.

[0122] The detailed description has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments were chosen in order to best illustrate the principles of the technology and its practical application to thereby enable others skilled in the art to best utilize it in various embodiments and with various modifications as are suited to the particular use contemplated. The scope of the disclosure is intended to be defined by the claims appended hereto.

Claims

1. A device, comprising: A memory die having a 3D memory structure, the 3D memory structure including nonvolatile memory cells in an array region, the nonvolatile memory cells connected by word lines and bit lines, the word lines connected to vertical word line vias in a staircase region adjacent to the array region, the vertical word line vias including a first plurality of vertical word line vias connected to first word line bond pads in the staircase region and a second plurality of vertical word line vias connected to second word line bond pads in the array region. 2 . The apparatus of claim 1 , further comprising a plurality of metal traces connecting the second plurality of vertical wordline vias to the second wordline bond pads, the plurality of metal traces extending over the bitlines in the array region. 3 . The apparatus of claim 2 , further comprising a plurality of bit line bond pads located in the array region, each bit line bond pad being electrically connected to a corresponding bit line. The device of claim 3 , wherein the first wordline bond pads are disposed in a honeycomb arrangement. 5 . The apparatus of claim 3 , further comprising a control die bonded to the memory die such that each bitline bond pad, first wordline bond pad, and second wordline bond pad is bonded to a corresponding control die bond pad. The apparatus of claim 5 , wherein the control die is larger than the memory die.

7. The apparatus of claim 6, wherein the control die is bonded to at least one additional memory die.

8. The apparatus of claim 1 , wherein each of the first word line bond pads is located directly above a corresponding one of the first plurality of vertical word line vias in the staircase region, and the second word line bond pad is laterally displaced from the second plurality of vertical word line vias and connected to the second plurality of vertical word line vias by a trace that extends over the bit lines into the array region and at right angles to the bit lines.

9. The apparatus of claim 8, wherein the first wordline bond pad and the second wordline bond pad are aligned to form a row extending through the staircase region and the memory array region.

10. The device of claim 9, wherein first and second vertical wordline vias are staggered in the staircase region, and the traces extend from the second vertical wordline vias on either side of the row.

11. A method comprising: forming a 3D nonvolatile memory structure in a memory die having a memory array region including a plurality of nonvolatile memory cells connected by a plurality of word lines and a plurality of bit lines, and a staircase region including a plurality of steps contacted by vertical word line vias, each step corresponding to a word line layer connected to a corresponding vertical word line via; as well as Bonding pads are formed on a surface of the memory die, the bonding pads including word line bonding pads electrically connected to the plurality of word lines and bit line bonding pads electrically connected to the plurality of bit lines, the bonding pads being formed such that a first plurality of word line bonding pads are located in the staircase region and a second plurality of the word line bonding pads are located in the memory array region.

12. The method according to claim 11, further comprising: positioning the first plurality of wordline bond pads directly above corresponding first vertical wordline vias to form direct electrical connections between the first plurality of wordline bond pads and the first vertical wordline vias; as well as A plurality of metal traces are formed electrically connecting the second wordline bond pads with corresponding second vertical wordline vias, the traces extending over the bitlines.

13. The method according to claim 12, further comprising: The first wordline bond pad and the second wordline bond pad are positioned in a row extending through the staircase region and the memory array region.

14. The method according to claim 13, further comprising: The first and second vertical wordline vias are staggered in the staircase region, and the plurality of metal traces are positioned on either side of the row.

15. The method according to claim 11, further comprising: aligning a control die with the memory die such that the wordline bond pads and the bitline bond pads are aligned with corresponding control die bond pads on a surface of the control die; as well as The wordline bond pads and the bitline bond pads of the memory die are bonded to the corresponding control die bond pads on the surface of the control die.

16. The method according to claim 15, further comprising: At least one additional memory die is then aligned and bonded to the control die.

17. The method of claim 11, wherein forming the plurality of bonding pads comprises: The plurality of bond pads are positioned in a honeycomb arrangement.

18. A memory system, comprising: a control circuit die having a plurality of slots for bonding the memory die; and A plurality of memory dies are bonded to corresponding trenches of the control circuit die, each memory die having a 3D memory structure, the 3D memory structure including non-volatile memory cells in an array region, the non-volatile memory cells being connected by word lines and bit lines, the word lines being connected to vertical word line vias in a staircase region adjacent to the array region, a first plurality of the vertical word line vias being connected to first word line bonding pads in the staircase region, and each memory die further comprising means for electrically connecting a second plurality of vertical word line vias to a second word line bonding pad located outside the staircase region.

19. The memory system of claim 18, wherein the second wordline bond pad is located in the array region having a plurality of bitline bond pads, the second wordline bond pad and the plurality of bitline bond pads being arranged in a repeating hexagonal pattern.

20. The memory system of claim 18, wherein the first wordline bond pad and the second wordline bond pad are aligned in a row.

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