Preparation method of shield gate groove type power device

Abstract

The invention discloses a preparation method of a shield gate groove type power device, a preparation method of a semiconductor device, a semiconductor structure for the shield gate groove type power device and the semiconductor device.The method comprises the steps that a semiconductor substrate is provided, and a groove is formed in the semiconductor substrate; forming a first oxide layer on the surface of the groove; forming an isolation layer on the surface of the first oxide layer in the groove; removing a part of the first oxide layer on the side wall of the groove to a set depth; the isolation layer is removed; forming a second oxide layer on the surface of the groove and the surface of the first oxide layer; and filling polycrystalline silicon on the second oxide layer in the groove. Therefore, according to the preparation method of the shield gate trench type power device provided by the embodiment of the invention, the field intensity distribution and the overall performance of the SGT MOSFET device can be improved while the process complexity and the manufacturing cost are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a preparation method of a shielded gate trench power device, a preparation method of a semiconductor device, a semiconductor structure for a shielded gate trench power device and a semiconductor device. BACKGROUND

[0002] The SGT MOSFET (Shielded Gate Trench Metal-Oxide-Semiconductor Field-Effect Transistor) is a kind of high-performance power semiconductor device, which introduces a lateral electric field in the body region to assist the drift region depletion, thereby improving the withstand voltage capability of the device. However, the traditional SGT MOSFET has a low field strength in the middle and a high field strength at the bottom in the trench depth direction, which does not fully utilize the withstand voltage potential of the device.

[0003] In the related art, in order to fully utilize the withstand voltage potential of the device, the following method is usually adopted: first, after forming the field oxide (a composite film layer is used to thicken the bottom field oxide), the polysilicon is deposited for the first time and grinded; then, etching to the designed depth, the upper field oxide is partially etched to the target thickness; then, the polysilicon is deposited for the second time and etched to the final depth. Although this method can optimize the field strength distribution, it needs to deposit polysilicon twice, which increases the process complexity and manufacturing cost, and during the first polysilicon deposition, the polysilicon may have gaps due to the top closure problem, which will have an adverse effect on the morphology in the subsequent etching process; in addition, there may be a natural oxide layer between the two deposited polysilicon, which causes high interface contact resistance and affects the dynamic performance of the device.

[0004] Therefore, how to reduce the process complexity and manufacturing cost while improving the field strength distribution and overall performance of the SGT MOSFET device has become a technical problem to be solved. SUMMARY

[0005] The present application provides a preparation method of a shielded gate trench power device, a preparation method of a semiconductor device, a semiconductor structure for a shielded gate trench power device and a semiconductor device, which can reduce the process complexity and manufacturing cost while improving the field strength distribution and overall performance of the SGT MOSFET device. The specific scheme is as follows: In a first aspect, the embodiments of the present application provide a preparation method of a shielded gate trench power device, comprising: providing a semiconductor substrate, wherein a trench is formed in the semiconductor substrate; forming a first oxide layer on a surface of the trench; forming an isolation layer on a surface of the first oxide layer in the trench; removing part of the first oxide layer on a sidewall of the trench to a set depth; removing the isolation layer; forming a second oxide layer on the surface of the trench and the surface of the first oxide layer; and filling polycrystalline silicon on the second oxide layer in the trench.

[0006] Optionally, the forming of the first oxide layer on the surface of the trench comprises: performing thermal oxidation or chemical vapor deposition to form the first oxide layer on the surface of the trench and the surface of the substrate.

[0007] Optionally, the forming of the isolation layer on the surface of the first oxide layer in the trench comprises: forming the isolation layer on the surface of the first oxide layer in the trench and the surface of the substrate; and grinding the isolation layer formed on the surface of the first oxide layer of the substrate to expose the first oxide layer on the surface of the substrate.

[0008] Optionally, the removing of the part of the first oxide layer on the sidewall of the trench to the set depth specifically comprises: wet etching the first oxide layer to the set depth.

[0009] Optionally, after the removing of the isolation layer, the method further comprises: wet etching the upper surface of the first oxide layer or the sidewall of the trench, so that an included angle between the upper surface of the first oxide layer and the sidewall of the trench is greater than 90 degrees.

[0010] Optionally, the forming of the second oxide layer on the surface of the trench and the surface of the first oxide layer comprises: performing thermal oxidation or chemical vapor deposition to form the second oxide layer on the surface of the trench, the surface of the first oxide layer and the surface of the substrate.

[0011] Optionally, the filling of the polycrystalline silicon on the second oxide layer in the trench comprises: depositing the polycrystalline silicon on the second oxide layer in the trench and on the second oxide layer on the surface of the substrate.

[0012] Optionally, in the case that the second oxide layer is formed by chemical vapor deposition, the thickness of the first oxide layer is a difference between a preset target thickness and a first thickness, the first thickness being a sum of a thickness of the first oxide layer removed when the first oxide layer is wet etched and a thickness of the second oxide layer formed.

[0013] Optionally, in the case that the first oxide layer and the second oxide layer are both formed by thermal oxidation, the thickness of the first oxide layer is a difference between an oxidation thickness of the second thermal oxidation and an oxidation thickness of the first thermal oxidation.

[0014] Optionally, the set depth is a sum of a preset target depth, a height of the first oxide layer removed when the first oxide layer is etched by wet etching, and a thickness of the second oxide layer formed.

[0015] Optionally, the polysilicon filled in the trench includes a first polysilicon part and a second polysilicon part, the first polysilicon part is isolated from the substrate by the second oxide layer, and the second polysilicon part is isolated from the substrate by the first oxide layer and the second oxide layer; after the polysilicon is filled on the second oxide layer in the trench, the method further includes: removing the polysilicon in the first polysilicon part to a first depth, and removing the second oxide layer on the trench sidewall and the substrate surface above the first depth; forming a third oxide layer on the polysilicon in the trench, the trench sidewall and the substrate surface above the first depth, the thickness of the third oxide layer is less than the thickness of the second oxide layer; and filling the polysilicon on the third oxide layer in the trench.

[0016] Optionally, the isolation layer is one of a nitride layer including SIN, SION, SIHN, or other non-oxide layer.

[0017] In a second aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, including: providing a semiconductor substrate, the semiconductor substrate having a trench formed therein; forming a first oxide layer on a surface of the trench; forming an isolation layer on a surface of the first oxide layer in the trench; removing part of the first oxide layer on a sidewall of the trench to a set depth; removing the isolation layer; forming a second oxide layer on a surface of the trench and a surface of the first oxide layer; and filling polysilicon on the second oxide layer in the trench.

[0018] In a third aspect, an embodiment of the present application provides a semiconductor structure for a shielded gate trench type power device, including: a semiconductor substrate, the semiconductor substrate having a trench formed therein; an oxide layer formed on a bottom region and a lower region of a sidewall of the trench; and an isolation layer formed on the oxide layer, the isolation layer extending to a position of an opening of the trench along the sidewall oxide layer in a direction of the opening of the trench, the isolation layer being used to protect a sidewall surface and a bottom surface of the oxide layer from being etched when the oxide layer is formed.

[0019] In a fourth aspect, the present application further provides a semiconductor device manufactured by the method of the first aspect or the second aspect.

[0020] Compared with the prior art, the present application has the following advantages: The preparation method of the shielded gate trench power device provided in an embodiment of the present application includes: providing a semiconductor substrate with a trench formed therein; forming a first oxide layer on the surface of the trench; forming an isolation layer on the surface of the first oxide layer in the trench, so that when the first oxide layer is removed, it is possible to avoid affecting the left and right side wall surfaces of the first oxide layer; removing part of the first oxide layer from the sidewalls of the trench to a set depth, so that a U-shaped structure can be formed inside the trench; removing the isolation layer; forming a second oxide layer on the surface of the trench and the surface of the first oxide layer, so that a stepped field oxygen can be formed inside the trench; filling polysilicon on the second oxide layer in the trench, thereby forming T-shaped polysilicon in the trench. On the one hand, since the bottom width of polysilicon is small and the top width is large, it is possible to optimize the electric field distribution of the device, increase its breakdown voltage, enhance the depletion effect of the drift region, thereby increasing the central field strength and improving the performance of the device; on the other hand, compared with the solution of depositing polysilicon twice, polysilicon can be formed by one deposition in this solution, which can avoid the problem of high contact resistance between the two caused by the oxide layer between the two deposited polysilicon while reducing the process steps, thereby improving the uniformity of the formed polysilicon. In addition, in this solution, the upper field oxygen is prepared by a single process, which reduces the thickness fluctuation introduced by the wet etching process, so that the thickness of the upper field oxygen formed will be more uniform. Therefore, the preparation method of the shielded gate trench power device provided in the embodiment of the present application can improve the field strength distribution and overall performance of the SGTMOSFET device while reducing process complexity and manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a flow chart of a method for preparing a shielded gate trench power device provided in this application.

[0022] Figure 2 It is a schematic diagram of a semiconductor substrate provided in the method for preparing a shielded gate trench power device provided in an embodiment of the present application.

[0023] Figure 3 It is a schematic diagram of forming a first oxide layer on the substrate surface and the trench surface in the method for preparing a shielded gate trench power device provided in this application.

[0024] Figure 4 It is a schematic diagram of forming an isolation layer in the method for preparing a shielded gate trench power device provided in an embodiment of the present application.

[0025] Figure 5 This is a schematic diagram of the process after grinding the isolation layer formed by the first oxide layer on the surface of the substrate in the method for preparing the shielded gate trench power device provided in an embodiment of the present application.

[0026] Figure 6FIG. 6 is a schematic view of removing part of the first oxide layer of the trench sidewall in the preparation method of the shielded gate trench power device provided by the embodiment of the present application.

[0027] Figure 7 FIG. 7 is a schematic view of removing the isolation layer in the preparation method of the shielded gate trench power device provided by the embodiment of the present application.

[0028] Figure 8 FIG. 8 is a schematic view of etching the first oxide layer again in the preparation method of the shielded gate trench power device provided by the embodiment of the present application.

[0029] Figure 9 FIG. 9 is a schematic view of etching the trench sidewall in the preparation method of the shielded gate trench power device provided by the embodiment of the present application.

[0030] Figure 10 FIG. 10 is a schematic view of forming the second oxide layer in the preparation method of the shielded gate trench power device provided by the embodiment of the present application.

[0031] Figure 11 FIG. 11 is a schematic view of filling the polycrystalline silicon on the second oxide layer in the trench in the preparation method of the shielded gate trench power device provided by the embodiment of the present application.

[0032] Figure 12 FIG. 12 is a schematic view of removing part of the polycrystalline silicon in the trench in the preparation method of the shielded gate trench power device provided by the embodiment of the present application.

[0033] Figure 13 FIG. 13 is a schematic view of forming the third oxide layer in the preparation method of the shielded gate trench power device provided by the embodiment of the present application.

[0034] Figure 14 FIG. 14 is a schematic view of filling the polycrystalline silicon above the third oxide layer in the preparation method of the shielded gate trench power device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0035] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without the specific details set forth in this description. In other instances, well-known methods have not been described in detail in order not to unnecessarily obscure aspects of the present application.

[0036] It should be noted that the terms "first", "second", "third", etc. in the claims, specification and drawings of the present application are used to distinguish like elements and are not necessarily used to describe a particular sequential or chronological order. As such, the use of these terms in the description is not meant to limit the application to the exact sequence and / or order presented, but is used for the sake of description. Furthermore, the terms "comprising", "having", "containing", and "including", or variations thereof, are intended to cover non-exclusive inclusions, such that processes, methods, systems, products, or devices that comprise, have, contain, or include a list of steps or elements are not necessarily limited to those steps or elements, but can include additional steps or elements not expressly listed or inherent to such processes, methods, products, or devices.

[0037] It should be understood that in the embodiments of the present application, "at least one" means one or more, and "multiple" means two or more. "And / or" is only a description of the relationship between the associated objects, which means that there can be three relationships, for example, A and / or B can represent the existence of A alone, the existence of A and B together, and the existence of B alone. The character " / " generally represents an "or" relationship between the associated objects. "Including A, B and / or C" means including any one or any two or three of A, B and C.

[0038] It should be understood that in the embodiments of the present application, "B corresponding to A", "B corresponding to A", "A corresponding to B" or "B corresponding to A" means that B is associated with A, and B can be determined according to A. Determining B according to A does not mean that B is determined only according to A, but also can be determined according to A and / or other information.

[0039] In the related art, for SGT MOSFET, in order to fully exert the potential of the withstand voltage of the device, in addition to the method mentioned in the background art, the following method is also used: first, after forming the field oxide, the photoresist is filled and etched to the target depth; then, the upper field oxide is partially etched to the target thickness; finally, the photoresist is removed, and the polysilicon is filled again.

[0040] However, in the above method, there is often a problem of not firm enough adhesion between the photoresist and the sidewall of the oxide layer, so that when etching the photoresist, the chemical solution may penetrate through the gap between the photoresist and the oxide layer to places that should not be etched, resulting in abnormal and unstable topography, affecting the performance of the device.

[0041] To solve the above problems, and to improve the field intensity distribution and overall performance of the SGT MOSFET device while reducing the process complexity and manufacturing cost, the first embodiment of the present application provides a preparation method of a shield gate trench power device.

[0042] The technical solutions of the present application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described in detail in some embodiments.

[0043] The following will be described in detail with reference to the specific embodiments of the present application. Figures 1-14 The preparation method of the shield gate trench power device provided by the embodiments of the present application will be described below.

[0044] As shown in Figure 1 is a flow chart of the preparation method of the shield gate trench power device provided by the present application, which includes the following steps S101-S107.

[0045] Step S101: providing a semiconductor substrate, wherein a trench is formed in the semiconductor substrate.

[0046] In semiconductor manufacturing, a semiconductor substrate refers to the basic material used to prepare a semiconductor device. The semiconductor substrate can include, but is not limited to, pure single crystal silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc. The material of the semiconductor substrate can be selected according to actual needs in the preparation process.

[0047] As shown in Figure 2 is a schematic diagram of the semiconductor substrate provided in the preparation method of the shield gate trench power device provided by the embodiments of the present application. The semiconductor substrate can include an epitaxial layer 02 and a substrate layer 01, wherein a trench 03 is formed in the epitaxial layer 02.

[0048] In a specific implementation, the trench can be formed in the to-be-processed semiconductor substrate without the trench through the following steps: etching the epitaxial layer 02 of the to-be-processed semiconductor substrate to form the trench 03.

[0049] Epitaxy, or simply Epi, is a process of growing a new layer of material with specific doping concentration and crystal structure on a original semiconductor substrate. This process can control the composition, thickness, and doping type and concentration of the new layer to achieve specific electrical properties. The epitaxial layer can match the substrate at the atomic level, forming a continuous crystal structure. The epitaxial layer can be the same material as the substrate (homoepitaxy) or a different material (heteroepitaxy); specifically, the epitaxial layer can be silicon-based or silicon carbide.

[0050] It should be noted that the epitaxial layer is used to support the current transmission of the device, and generally has higher purity and fewer defects than the original substrate. By epitaxial growth, the type and concentration of dopants in the epitaxial layer can be precisely controlled to customize the required electrical properties. For example, in a power MOSFET, the breakdown voltage and on-resistance can be optimized by adjusting the doping of the epitaxial layer; and during the epitaxial process, materials with different doping concentrations or types can be grown layer by layer as needed to form complex multilayer structures. This capability is essential for the manufacture of high-performance integrated circuits (ICs), power devices, etc. In other embodiments, the trench can also not be formed in the epitaxial layer.

[0051] Step S102: Forming a first oxide layer on the surface of the trench.

[0052] In the embodiments of the present application, the first oxide layer can be a single film layer or a composite film layer. When the first oxide layer is a composite film layer, the first oxide layer can include at least a first sub-oxide layer and a second sub-oxide layer. The first sub-oxide layer can be a film layer with low etching rate (i.e., corrosion-resistant), and the second sub-oxide layer can be a film layer with high etching rate (i.e., easily etched).

[0053] Specifically, thermal oxidation and / or chemical vapor deposition can be performed to form the first oxide layer on the surface of the trench and the surface of the substrate. That is, in the embodiments of the present application, only thermal oxidation can be performed to form the first oxide layer on the surface of the trench and the surface of the substrate; only chemical vapor deposition can be performed to form the first oxide layer on the surface of the trench and the surface of the substrate; or first thermal oxidation can be performed to form a first sub-oxide layer on the surface of the trench and the surface of the substrate, and then chemical vapor deposition can be performed to form a second sub-oxide layer on the first sub-oxide layer, the first oxide layer including the first sub-oxide layer and the second sub-oxide layer.

[0054] The first sub-oxide layer formed by thermal oxidation is a dense and uniform oxide layer with low etching rate, and the second sub-oxide layer formed by chemical vapor deposition is a loose oxide layer with high etching rate. In this way, by forming the first oxide layer including the first sub-oxide layer and the second sub-oxide layer, the first sub-oxide layer with low etching rate is close to the inner side of the trench sidewall, and the second sub-oxide layer with high etching rate is on the outer side. Therefore, when the partial first oxide layer of the trench sidewall is removed to a certain depth in the subsequent step S104, the etching amount of the second sub-oxide layer on the outer side will be greater than that of the first sub-oxide layer on the inner side, so that the included angle between the upper surface of the first oxide layer and the trench sidewall is greater than 90 degrees. Thus, the surface of the remaining first oxide layer abutting the trench sidewall forms a downwardly inclined slope, which is more conducive to the uniform attachment of the oxidant, thereby forming a second oxide layer with more uniform thickness in the subsequent step.

[0055] As shown in Figure 3 FIG. 1 is a schematic diagram of a substrate surface and a trench surface forming a first oxide layer in a method for manufacturing a shield gate trench power device provided by the present application. The surface of the epitaxial layer 02 and the surface of the trench 03 form a first oxide layer 04.

[0056] The oxide layer refers to a layer of insulating material (usually silicon dioxide ) grown or deposited on the surface of the epitaxial layer and the surface of the trench after etching the trench on the semiconductor substrate.

[0057] It should be noted that the oxide layer, as a dielectric, provides the necessary electrical isolation between the gate and the channel, preventing direct current flow from the gate to the source or drain of the subsequently formed device, which helps to control and manage the current through the channel, ensuring that current will only flow under appropriate voltage conditions. This oxide layer is generally referred to as field oxide, or simply field oxide. Furthermore, the formation of an oxide layer inside the trench can help optimize the electric field distribution in the channel region. In particular, in high-voltage applications, good electric field management can improve the breakdown voltage and enhance the reliability and performance of the device. Typically, the breakdown voltage, the optimization of the electric field distribution, and the reliability of the device are improved by adjusting the thickness of the oxide layer.

[0058] The oxide layer can be formed on the trench sidewall and the upper surface of the epitaxial layer by thermal oxidation or chemical vapor deposition (CVD), etc. Among them, thermal oxidation is a method of growing silicon dioxide (SiO2) by exposing the substrate to oxygen or water vapor in a high-temperature environment. ) process, thermal oxidation includes dry oxygen oxidation and wet oxygen oxidation. Dry oxygen oxidation refers to the use of pure oxygen as an oxidant to generate a high-quality, dense oxide layer. Wet oxygen oxidation refers to the use of water vapor to react with silicon to generate an oxide layer. The growth rate of wet oxygen oxidation is faster than that of dry oxygen oxidation, but the density of the oxide layer is lower than that of dry oxygen oxidation. Chemical vapor deposition is a technology that uses chemical reactions to deposit thin films on the surface of a substrate.

[0059] It should be noted that if dry oxygen oxidation is selected as the thermal oxidation method in the present application, the oxidation temperature is generally between 900°C and 1100°C, and the oxidation time depends on the thickness of the oxide layer to be generated. For example, it may take about 2 hours to grow a 100-nanometer-thick oxide layer by dry oxygen oxidation at 1000°C. If wet oxygen oxidation is selected as the thermal oxidation method in the present application, the oxidation temperature is generally between 700°C and 1000°C, and the oxidation time also depends on the thickness of the oxide layer to be generated. However, the speed of wet oxygen oxidation is greater than that of dry oxygen oxidation. For example, it may take about 10 to 15 minutes to grow a 100-nanometer-thick oxide layer by wet oxygen oxidation at 1000°C. It should be noted that the oxidation temperature and oxidation time herein are merely examples and are not intended to limit the present application.

[0060] Step S103: forming an isolation layer on the surface of the first oxide layer in the trench.

[0061] This step is used to form an isolation layer on the surface of the first oxide layer, thereby protecting the surface of the first oxide layer when a portion of the first oxide layer on the trench sidewall is subsequently removed, and the first oxide layer is only corroded from above the trench sidewall.

[0062] In a specific implementation, step S103 can be implemented by following steps S201 and S202.

[0063] Step S201: forming an isolation layer on the surface of the first oxide layer in the trench and the first oxide layer on the surface of the substrate.

[0064] like Figure 4 , which is a schematic diagram of forming an isolation layer in the method for preparing a shielded gate trench power device according to an embodiment of the present invention. After forming a first oxide layer 04 on the surface of the epitaxial layer 02 and the surface of the trench 03, an isolation layer 05 can be deposited on the surface of the epitaxial layer 02 and the surface of the trench 03.

[0065] The isolation layer 05 is a film layer made of a different material than the first oxide layer 04. For example, the isolation layer 05 may be a nitride film, including but not limited to SiN (silicon nitride), SiON (silicon oxynitride), or SiHN (silicon hydrogen nitride). It should be noted that the isolation layer may also be a non-oxidizing layer, such as silicon carbide (SiC).

[0066] Step S202: grinding the isolation layer formed on the first oxide layer of the substrate surface until the first oxide layer of the substrate surface is exposed.

[0067] This step is used to remove the isolation layer on the substrate surface, so that the first oxide layer is exposed, so that the first oxide layer of the trench sidewall is removed in the subsequent step.

[0068] As shown in FIG. 2B, after the isolation layer 05 is formed on the surface of the epitaxial layer 02 and the surface of the trench 03, the isolation layer 05 formed on the first oxide layer 04 of the epitaxial layer 02 is chemically and mechanically polished, and the polishing is stopped until the first oxide layer 04 of the epitaxial layer 02 is exposed. In this way, only the isolation layer 05 on the inner wall of the trench is retained, and an opening is formed on the top of the first oxide layer 04 of the trench sidewall, thereby providing a basis for the removal of the first oxide layer 04 of the trench sidewall in the subsequent step. Figure 5

[0069] Step S104: removing part of the first oxide layer of the trench sidewall to a set depth.

[0070] This step is used to remove part of the first oxide layer on the upper half of the trench sidewall, thereby forming a U-shaped oxide layer structure at the bottom of the trench.

[0071] As shown in FIG. 3B, after the isolation layer 05 formed on the first oxide layer 04 of the epitaxial layer 02 is chemically and mechanically polished, the first oxide layer 04 on the surface of the epitaxial layer 02 (i.e., the surface of the substrate) can be removed by wet etching, and the first oxide layer 04 on the sidewall of the trench 03 can be removed to a set depth by wet etching, thereby forming a U-shaped oxide layer at the bottom of the trench 03. Figure 6 Wet etching of the oxide layer refers to a process of selectively removing the oxide layer by a chemical solution without damaging the substrate or other materials. In general, hydrofluoric acid (HF) can be used as a solution for wet etching, which can effectively react with and dissolve the oxide layer. In this process, the hydrofluoric acid can convert the silicon dioxide into soluble fluorosilicic acid (

[0072]

[0073] ​​​It should be noted that if the isolation layer is not formed on the surface of the first oxide layer in the trench, the exposed sidewall of the first oxide layer will be corroded by the chemical solution when the first oxide layer is wet etched, resulting in uneven thickness of the first oxide layer in some areas, and even complete removal of the first oxide layer. On the one hand, it will cause local electric field concentration, increasing the risk of breakdown in this area. Especially for devices in high-voltage applications, this will seriously affect the breakdown voltage and reliability of the device; on the other hand, it will increase the leakage current of the device, causing electrical problems. In the embodiments of the present application, by forming an isolation layer on the surface of the first oxide layer in the trench, since the isolation layer has high corrosion resistance, it can protect the exposed sidewall of the first oxide layer in the trench, effectively prevent the exposed sidewall of the first oxide layer from being corroded by the chemical solution, avoid the uneven thickness of the first oxide layer, make the field oxide in the lower part of the formed semiconductor structure more uniform, thereby avoiding the breakdown of the device and electrical problems.

[0074] Step S105: removing the isolation layer.

[0075] This step is used to remove the isolation layer after forming the U-shaped oxide layer at the bottom of the trench, facilitating the formation of the second oxide layer subsequently.

[0076] As shown in Figure 7 , it is a schematic diagram of removing the isolation layer in the preparation method of the shield gate trench type power device provided by the embodiments of the present application. After removing the first oxide layer 04 on the sidewall of the trench 03 to a certain depth, the isolation layer 05 can be removed by wet etching or dry etching.

[0077] It should be noted that in semiconductor technology, wet etching or dry etching can be used to remove the isolation layer (nitride layer).

[0078] Among them, wet etching mainly uses liquid chemical reagents to remove the isolation layer, and the chemical reagents used are different for different materials of the isolation layer. Specifically, if the material of the isolation layer is silicon nitride (SiN), the commonly used wet etching solution is hot phosphoric acid ( ), which has good selectivity to silicon nitride at high temperature (about 160°C to 180°C), and can effectively remove silicon nitride and have little effect on the oxide layer; if the material of the isolation layer is silicon oxynitride (SiON), hot phosphoric acid can also be used for etching. However, since the composition of silicon oxynitride is slightly different from that of silicon nitride, the etching rate may change, so the temperature and concentration need to be adjusted according to the actual situation; if the material of the isolation layer is silicon hydronitride (SiHN), the efficiency can be improved by adding nitric acid ( ) or sulfuric acid ( ) and other chemicals in the hot phosphoric acid solution.

[0079] The dry etching method for removing the isolation layer mainly includes reactive ion etching (RIE) and inductively coupled plasma etching (ICP). The reactive ion etching is a technology for realizing etching by bombarding the material surface with active ions in plasma. For silicon nitride, a gas mixture containing fluorine groups (such as 、 ) is often used as the etching gas, which can provide a high etching rate while maintaining good selectivity. The inductively coupled plasma etching generates plasma by using a high-frequency electromagnetic field to excite the gas, and uses these active particles to etch the material surface, which can provide a higher etching rate.

[0080] In an optional embodiment, in the case that the first oxide layer is a single layer, in order to make the subsequent second oxide layer fill the upper surface of the first oxide layer in the trench more closely and without gaps, after removing the isolation layer, the step S203 of wet etching the upper surface of the first oxide layer or the sidewall of the trench is performed to make the included angle between the upper surface of the first oxide layer and the sidewall of the trench greater than 90 degrees.

[0081] In a specific implementation, the object of wet etching is the upper surface of the first oxide layer, so that the included angle between the upper surface of the first oxide layer and the sidewall of the trench is greater than 90 degrees. Specifically, as shown in Figure 8 , it is a schematic diagram of etching the first oxide layer again in the preparation method of the shield gate trench power device provided by the present application. After removing the isolation layer 05, the top surface of the remaining first oxide layer 04 in the trench 03 is etched by chemical solution wet etching, so that the included angle between the upper surface of the remaining first oxide layer 04 and the sidewall of the trench 03 is greater than 90 degrees. In this way, the surface of the remaining first oxide layer 04 bordering with the sidewall of the trench 03 forms a downward inclined slope. It should be noted that if the included angle between the first oxide layer and the sidewall of the trench is a right angle, the oxidant may not be able to uniformly contact the included angle, resulting in incomplete oxidation at the included angle, and the thickness of the second oxide layer formed is not uniform. In comparison, in the present embodiment, the included angle between the first oxide layer and the sidewall of the trench is obtuse, so that the included angle is more conducive to the uniform adhesion of the oxidant, thereby forming a second oxide layer with more uniform thickness in the subsequent process. In addition, by etching the first oxide layer, the corner between the upper surface of the first oxide layer and the sidewall exposed by the first oxide layer can be arc-shaped, which will make the surface transition smoother, facilitating the adhesion of the second oxide layer at the corner in the subsequent process. In addition, the corner arc can disperse the electric field distribution, avoid local high electric field, thereby improving the device withstand voltage capability and stability, and improving the electrical properties of the device.

[0082] In the case that the wet etching is used to make the included angle between the upper surface of the first oxide layer and the trench sidewall greater than 90 degrees in step S203, the depth of the first oxide layer removed in step S104 needs to be reserved. Specifically, in the case that the wet etching is used to make the included angle between the upper surface of the first oxide layer and the trench sidewall greater than 90 degrees in step S203, the set depth of the first oxide layer removed in step S104 is the sum of the preset target depth of the upper half of the T-shaped structure, the height of the first oxide layer removed in the wet etching of the first oxide layer, and the thickness of the second oxide layer formed. Thus, the T-shaped structure upper half formed finally reaches the preset target depth through the mutual cooperation of the processes.

[0083] In another specific implementation, the object of the wet etching is the trench sidewall, so that the included angle between the upper surface of the first oxide layer and the trench sidewall is greater than 90 degrees. Specifically, as shown in FIG. 4, after the isolation layer 05 is removed, the remaining first oxide layer 04 is etched by a chemical solution to make the included angle between the upper surface of the remaining first oxide layer 04 and the trench 03 sidewall greater than 90 degrees. Thus, the surface of the remaining first oxide layer 04 bordering with the trench 03 sidewall forms a downwardly inclined slope. Figure 9 It is to be noted that, compared with the right angle between the first oxide layer 04 and the trench 03 sidewall in FIG. 2, the obtuse angle between the first oxide layer 04 and the trench 03 sidewall in FIG. 4 makes the oxidant more uniformly distributed at the included angle when the second oxide layer is formed subsequently, so that the second oxide layer formed is more uniform and compact. In addition, when the trench sidewall is etched by the wet etching (the way shown in FIG. 4), the opening of the trench can also be increased, which facilitates the subsequent deposition of the polysilicon.

[0084] It is to be noted that, compared with the right angle between the first oxide layer 04 and the trench 03 sidewall in FIG. 2, the obtuse angle between the first oxide layer 04 and the trench 03 sidewall in FIG. 4 makes the oxidant more uniformly distributed at the included angle when the second oxide layer is formed subsequently, so that the second oxide layer formed is more uniform and compact. In addition, when the trench sidewall is etched by the wet etching (the way shown in FIG. 4), the opening of the trench can also be increased, which facilitates the subsequent deposition of the polysilicon. Figure 7 Figure 8 It is to be noted that, compared with the right angle between the first oxide layer 04 and the trench 03 sidewall in FIG. 2, the obtuse angle between the first oxide layer 04 and the trench 03 sidewall in FIG. 4 makes the oxidant more uniformly distributed at the included angle when the second oxide layer is formed subsequently, so that the second oxide layer formed is more uniform and compact. In addition, when the trench sidewall is etched by the wet etching (the way shown in FIG. 4), the opening of the trench can also be increased, which facilitates the subsequent deposition of the polysilicon. Figure 9 Figure 9 It is to be noted that, compared with the right angle between the first oxide layer 04 and the trench 03 sidewall in FIG. 2, the obtuse angle between the first oxide layer 04 and the trench 03 sidewall in FIG. 4 makes the oxidant more uniformly distributed at the included angle when the second oxide layer is formed subsequently, so that the second oxide layer formed is more uniform and compact. In addition, when the trench sidewall is etched by the wet etching (the way shown in FIG. 4), the opening of the trench can also be increased, which facilitates the subsequent deposition of the polysilicon.

[0085] Step S106: Forming a second oxide layer on the trench surface and the first oxide layer surface.

[0086] This step is used to form a second oxide layer on the first oxide layer surface and the trench sidewall, so as to form a stepped field oxide in the trench.

[0087] As shown in FIG. 6, after the isolation layer 05 is removed, the remaining first oxide layer 04 is etched by a chemical solution to make the included angle between the upper surface of the remaining first oxide layer 04 and the trench 03 sidewall greater than 90 degrees. Thus, the surface of the remaining first oxide layer 04 bordering with the trench 03 sidewall forms a downwardly inclined slope. Figure 10 ​​As shown, it is a schematic diagram of forming the second oxide layer in the method for manufacturing the shielded gate trench power device provided by the embodiment of the present application. After the U-shaped first oxide layer 04 is formed inside the trench 03, the thermal oxidation and / or chemical vapor deposition can be performed to form the second oxide layer 06 on the sidewall of the trench 03, the surface of the first oxide layer 04 and the surface of the epitaxial layer 02 (i.e. the surface of the substrate). That is, the second oxide layer 06 can be a thermal oxide layer formed by only using the thermal oxidation method, can be a deposited oxide layer formed by only using the chemical vapor deposition method, or can be a composite oxide layer obtained by first growing a thermal oxide layer by using the thermal oxidation method and then forming a deposited oxide layer on the formed thermal oxide layer by using the chemical vapor deposition method.

[0088] In this way, the stepped field oxide (the oxide layer of the upper half of the sidewall of the trench is the second oxide layer, and the oxide layer of the lower half of the sidewall of the trench is the first oxide layer and the second oxide layer) can be formed in the trench 03.

[0089] In the embodiment of the present application, in the case where the second oxide layer is formed by using the chemical vapor deposition, the calculation method of the thickness of the first oxide layer is as follows: in the case where the wet etching of the first oxide layer is used in step S203 to make the included angle between the upper surface of the first oxide layer and the sidewall of the trench greater than 90 degrees, the upper surface of the first oxide layer 04 is etched into an inclined downward slope, and at the same time, the thickness of the first oxide layer can also be thinned. In this case, the thickness of the first oxide layer is the preset target thickness of the oxide layer of the lower half of the sidewall of the trench minus the thickness of the formed second oxide layer, plus the thickness of the first oxide layer removed in step S203 when the wet etching of the first oxide layer is performed; in the case where the wet etching of the sidewall of the trench is used in step S203 to make the included angle between the upper surface of the first oxide layer and the sidewall of the trench greater than 90 degrees, the thickness of the first oxide layer is the preset target thickness of the oxide layer of the lower half of the sidewall of the trench minus the thickness of the formed second oxide layer. Since the oxide layer finally formed on the lower half of the sidewall of the trench is the first oxide layer and the second oxide layer, by the mutual cooperation of the processes, the oxide layer finally formed on the lower half of the sidewall of the trench can reach the preset target thickness.

[0090] In the case where the first oxide layer and the second oxide layer are both formed by using the thermal oxidation, the thickness of the first oxide layer is the difference between the total thickness of the oxide layers formed by the first thermal oxidation and the second thermal oxidation and the thickness of the formed second oxide layer.

[0091] In step S203, when the trench sidewalls are wet-etched so that the angle between the upper surface of the first oxide layer and the trench sidewalls is greater than 90 degrees, or when step S203 is not performed, the set depth to which the first oxide layer is removed in step S104 is the sum of the preset target depth of the upper half of the T-shaped structure and the thickness of the second oxide layer formed. In this embodiment, since the set depth to which the first oxide layer is removed is the sum of the preset target depth of the upper half of the T-shaped structure and the thickness of the second oxide layer formed, and the depth of the upper half of the T-shaped structure finally formed is the difference between the depth of the removed first oxide layer and the thickness of the subsequently formed second oxide layer, through mutual cooperation in the processes, the depth of the upper half of the T-shaped structure finally formed reaches the preset target depth, and the expected T-shaped structure is finally formed.

[0092] Step S107: filling polysilicon on the second oxide layer in the trench.

[0093] This step is used to deposit polysilicon.

[0094] like Figure 11 Figure 2 is a schematic diagram of the method for fabricating a shielded gate trench power device according to an embodiment of the present invention, wherein polysilicon is filled onto the second oxide layer in the trench. After forming a second oxide layer 06 on the sidewalls of trench 03, the surface of first oxide layer 04, and the surface of epitaxial layer 02 (i.e., the substrate surface), polysilicon 07 is deposited on second oxide layer 06 in trench 03 and on the surface of epitaxial layer 02. The polysilicon formed in the trench thus forms a T-shape, with a narrow bottom width and a wide top width. This structure optimizes the device's electric field distribution, increases its breakdown voltage, and enhances the depletion effect in the drift region, thereby increasing the central field strength and improving device performance.

[0095] It can be seen that the preparation method of the shield gate trench power device provided in the embodiment of the present application comprises the following steps: providing a semiconductor substrate, a trench is formed in the semiconductor substrate; forming a first oxide layer on the surface of the trench; forming an isolation layer on the surface of the first oxide layer in the trench, so that the influence on the left and right sidewall surfaces of the first oxide layer can be avoided when the first oxide layer is removed; removing part of the first oxide layer on the sidewall of the trench to a set depth, so that a U-shaped structure can be formed in the trench; removing the isolation layer; forming a second oxide layer on the surface of the trench and the surface of the first oxide layer, so that a stepped field oxide can be formed in the trench; and filling polycrystalline silicon on the second oxide layer in the trench to form a T-shaped polycrystalline silicon in the trench. On the one hand, because the bottom width of the polycrystalline silicon 07 is small and the top width is large, the electric field distribution of the device can be optimized, the breakdown voltage thereof can be improved, and the depletion effect of the drift region can be enhanced, so that the high middle field strength can be pulled and the performance of the device can be improved. On the other hand, compared with the scheme of depositing polycrystalline silicon twice, the polycrystalline silicon 07 can be formed by depositing once in the present scheme, which can reduce the process steps and avoid the problem of high contact resistance caused by the oxidation layer between the two deposited polycrystalline silicon, and improve the uniformity of the formed polycrystalline silicon. In addition, in the present scheme, the upper field oxide is prepared by a single process, which reduces the thickness fluctuation introduced by the wet etching process, so that the thickness of the formed upper field oxide is more uniform. Moreover, compared with the related art in which the photoresist is filled after the formation of the field oxide, the photoresist is etched to a target depth, and the upper field oxide is partially etched to form a T-shaped polycrystalline silicon, the drug solution may penetrate into the place that should not be etched along the gap between the photoresist and the oxide layer, resulting in abnormal and unstable morphology. In the embodiment of the present application, the isolation layer is formed on the surface of the first oxide layer, the isolation layer and the first oxide layer have good adhesion and closer interface contact, when the first oxide layer is removed, the drug solution will not flow down the sidewall, so that the sidewall of the first oxide layer will not be etched, and the thickness of the lower field oxide in the trench is also more uniform, thereby improving the performance of the device. Therefore, the preparation method of the shield gate trench power device provided in the embodiment of the present application can improve the field strength distribution and overall performance of the SGT MOSFET device while reducing the process complexity and manufacturing cost.

[0096] In an optional embodiment, the T-shaped polycrystalline silicon formed in step S107 is the gate polycrystalline silicon. In this embodiment, the T-shaped polycrystalline silicon formed is a polycrystalline silicon layer used as a gate electrode in a semiconductor device.

[0097] In another alternative embodiment, the T-shaped polysilicon formed in step S107 can be further etched to form a shield gate, and further polysilicon is deposited above the shield gate to form a gate polysilicon. Alternatively, the polysilicon filled in the trench includes a first polysilicon portion and a second polysilicon portion, the first polysilicon portion is isolated from the substrate by the second oxide layer, and the second polysilicon portion is isolated from the substrate by the first oxide layer and the second oxide layer. After the polysilicon is filled in the trench on the second oxide layer, the following steps S108-S110 can be performed.

[0098] Step S108: removing the polysilicon in the first polysilicon portion to a first depth, and removing the second oxide layer on the trench sidewall and the substrate surface above the first depth.

[0099] This step is used to remove part of the polysilicon in the trench, and remove the second oxide layer exposed in the trench and the second oxide layer on the substrate surface.

[0100] It should be noted that through the above steps S101-S107, a plurality of trenches filled with polysilicon can be formed on the substrate (as shown in Figure 11 three trenches filled with polysilicon are formed), and the trenches that do not need to be etched can be protected from being etched by coating photoresist on the surface thereof. In this way, for the trenches that need to be etched, part of the polysilicon therein can be removed by etching to form a shield gate.

[0101] As shown in Figure 12 , it is a schematic diagram for removing part of the polysilicon in the trench in the preparation method of the shield gate trench type power device provided by the embodiment of the present application. After the polysilicon 07 is deposited on the second oxide layer 06 in the trench 03 and on the second oxide layer 06 on the surface of the epitaxial layer 02, the polysilicon 07 deposited on the second oxide layer 06 on the surface of the epitaxial layer 02 and the second oxide layer 06 on the surface of the epitaxial layer 02 can be ground first to expose the epitaxial layer 02 (i.e. the substrate), and then the trench that does not need to be etched is covered by a photolithography process, for example, photoresist is coated on the surface of the left trench region in Figure 12 to protect the polysilicon 07 filled in the left trench in Figure 12 from being etched, and part of the polysilicon 07 in the first polysilicon portion in the trenches that need to be etched (the two trenches on the right side in Figure 12 ) is removed to a first depth by etching, so that Figure 12 T-shaped polysilicon structures 07-1 are formed in the two trenches on the right side, and the second oxide layer on the sidewall of the trench 03 above the first depth is removed by wet etching or other methods.

[0102] After that, the photoresist coated on the substrate can be removed.

[0103] Step S109: forming a third oxide layer above the polysilicon in the trench, on the trench sidewalls and on the substrate surface above the first depth, wherein the thickness of the third oxide layer is less than the thickness of the second oxide layer.

[0104] This step is used to form a third oxide layer on the polysilicon, the trench sidewalls and the substrate surface.

[0105] like Figure 13 As shown, it is a schematic diagram of forming a third oxide layer in the preparation method of the shielded gate trench power device provided in an embodiment of the present application. After removing part of the polysilicon 07 in the trench 03, thermal oxidation or chemical vapor deposition is performed to form a third oxide layer 08 on the sidewall of the trench 03 and the surface of the epitaxial layer 02 (substrate surface) above the T-shaped polysilicon structure 07-1 in the trench 03 and above the first depth, and the thickness of the third oxide layer 08 is less than the thickness of the second oxide layer 06.

[0106] Step S110: filling polysilicon on the third oxide layer in the trench.

[0107] This step is used to fill polysilicon above the shielding gate.

[0108] like Figure 14 FIG. 1 is a schematic diagram of filling polysilicon above the third oxide layer in the method for preparing a shielded gate trench power device according to an embodiment of the present invention. After forming the third oxide layer 08, the trench having the third oxide layer is formed ( Figure 14 Polysilicon 09 is filled onto the third oxide layer 08 in the two trenches on the right side of the transistor (as shown), thereby forming gate polysilicon. Subsequent steps proceed normally, including implantation of source and body regions, deposition of an interlayer dielectric layer, and etching of contact holes in the semiconductor substrate to form the source, gate, and drain electrodes. Specifically, the source and body regions of the semiconductor substrate are implanted, and impurity atoms are introduced into specific areas through ion implantation to change the conductivity type (N-type or P-type) of these areas, thereby defining the functional areas of the transistor. An interlayer dielectric layer is then deposited. After the source and body regions are implanted, a layer of insulating material is deposited to isolate the different conductive layers and provide a foundation for subsequent contact hole etching. Contact holes are then etched to allow subsequent metal interconnect layers to establish electrical connections with the electrodes through the contact holes.

[0109] The second embodiment of the present application provides a method for fabricating a semiconductor device, which includes steps S101 to S107 of the method for fabricating a shielded gate trench power device provided in the first embodiment of the present application. The method for fabricating a semiconductor device provided in the second embodiment of the present application differs from the method for fabricating a shielded gate trench power device provided in the first embodiment of the present application in that the method for fabricating a semiconductor device provided in the second embodiment of the present application can be used to fabricate a non-shielded gate trench semiconductor device with deep trench isolation (DTI). For details regarding the method for fabricating the semiconductor device provided in the second embodiment of the present application, please refer to the detailed description of the method for fabricating a shielded gate trench power device provided in the first embodiment of the present application, and will not be elaborated upon here.

[0110] The third embodiment of the present application provides a semiconductor structure for a shielded gate trench power device, comprising: a semiconductor substrate having a trench formed therein; an oxide layer formed in the bottom region of the trench and the lower region of the sidewall; an isolation layer formed above the oxide layer, and the isolation layer extends along the trench sidewall oxide layer toward the trench opening to the position of the trench opening, the isolation layer being used to protect the sidewall surface and bottom surface of the oxide layer from being corroded when the oxide layer is formed.

[0111] The semiconductor structure for shielded gate trench power device provided in the third embodiment of the present application can be referred to in the attached Figure 6 In this embodiment, the oxide layer formed in the bottom area of ​​the trench and the lower area of ​​the sidewall is the attached Figure 6 The U-shaped first oxide layer 04 shown in FIG. 1 is formed on the isolation layer 04. Figure 6 The isolation layer 05 shown, the isolation layer 05 extends along the U-shaped first oxide layer 04 of the trench sidewall toward the trench opening to the position of the trench opening. It should be noted that by forming an isolation layer with a height higher than the height of the U-shaped oxide layer in the trench, in this way, when the original first oxide layer of the trench sidewall is corroded to form the U-shaped first oxide layer 04, the side wall surface and the bottom surface of the first oxide layer can be protected from corrosion, so that the bottom area of ​​the trench sidewall forms a U-shaped first oxide layer 04 with uniform thickness. In this way, when another oxide layer (the second oxide layer in the first embodiment of the present application) is further formed on the surface of the trench sidewall and the surface of the U-shaped first oxide layer, a stepped field oxygen can be formed in the trench. For details, please refer to the attached Figure 14 The semiconductor structure shown on the left side of the figure is a staircase field oxide in this embodiment. Figure 14 The second oxide layer 06 and the first oxide layer 04 on the sidewall of the trench 03 in the semiconductor structure shown on the left. In this way, polysilicon can be further filled in the trench to form T-shaped polysilicon. The formed T-shaped polysilicon is the attached Figure 14 Polysilicon 07 filled in the trench in the semiconductor structure shown on the left.

[0112] It should be noted that, when the semiconductor structure shown in the left side of the middle is formed, at least one semiconductor structure can be further etched, thermally oxidized or chemically vapor deposited to form a third oxide layer, and the third oxide layer is filled with polysilicon, so that at least one semiconductor structure is formed on the substrate. Figure 14 The semiconductor structure shown in the right side of the middle can be formed on the substrate. Figure 14 The semiconductor structure shown in the left side of the middle and the semiconductor structure shown in the right side of the middle can be simultaneously formed on a substrate. Figure 14 The semiconductor structure shown in the left side of the middle and the semiconductor structure shown in the right side of the middle can be simultaneously formed on a substrate. Figure 14 The semiconductor structure shown in the left side of the middle and the semiconductor structure shown in the right side of the middle can be simultaneously formed on a substrate.

[0113] The semiconductor structure for the shielded gate trench power device in the third embodiment of the present application can be prepared by the preparation method of the shielded gate trench power device provided in the first embodiment of the present application or the preparation method of the semiconductor device provided in the second embodiment of the present application. For details, reference can be made to the detailed description of the preparation method of the shielded gate trench power device provided in the first embodiment of the present application and the preparation method of the semiconductor device provided in the second embodiment of the present application, which will not be repeated here.

[0114] It can be seen that the semiconductor structure for the shielded gate trench power device provided in the third embodiment of the present application comprises: a semiconductor substrate, wherein a trench is formed in the semiconductor substrate; an oxide layer is formed in the bottom region and the lower region of the side wall of the trench; an isolation layer is formed above the oxide layer, and the isolation layer extends to the position of the opening of the trench along the trench side wall oxide layer in the direction of the opening of the trench, and the isolation layer is used to protect the side wall surface and the bottom surface of the oxide layer from being corroded when the oxide layer is formed. In this way, the side wall surface and the bottom surface of the oxide layer are not corroded in the process of forming the U-shaped oxide layer in the bottom region and the lower region of the side wall, so as to ensure the uniformity of the thickness of the U-shaped oxide layer formed in the bottom region and the lower region of the side wall. Moreover, since the U-shaped oxide layer is formed in the bottom region and the lower region of the side wall, a stepped field oxide can be further formed in the trench. Since the stepped field oxide is formed, a T-shaped polysilicon can be further deposited, so as to optimize the electric field distribution of the device, improve the breakdown voltage, enhance the depletion effect of the drift region, pull the high central field strength, and improve the performance of the device. Moreover, since the stepped field oxide is formed before the polysilicon is deposited, the T-shaped polysilicon can be formed by one-time deposition, which can reduce the process steps and avoid the problem of high contact resistance between the polysilicon formed by multiple times of deposition and the oxide layer, so as to improve the uniformity of the formed polysilicon.

[0115] The fourth embodiment of the present application provides a semiconductor device, which can be a shielded gate trench type power device or a non-shielded gate trench type power device with shallow trench isolation. It can be prepared by the preparation method of the shielded gate trench type power device provided in the first embodiment of the present application or the preparation method of the semiconductor device provided in the second embodiment of the present application. For details, please refer to the detailed introduction of the preparation method of the shielded gate trench type power device provided in the first embodiment of the present application and the preparation method of the semiconductor device provided in the second embodiment of the present application, which will not be repeated here.

[0116] Although the present application is disclosed as above with the preferred embodiments, it is not intended to limit the present application. Any person skilled in the art may make possible changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims of the present application.

Claims

1. A method for preparing a shielded gate trench power device, characterized in that: include: providing a semiconductor substrate having a trench formed therein; forming a first oxide layer on the surface of the groove; forming an isolation layer on the surface of the first oxide layer in the trench; removing a portion of the first oxide layer on the sidewall of the trench to a set depth; removing the isolation layer; forming a second oxide layer on the surface of the groove and the surface of the first oxide layer; The second oxide layer in the trench is filled with polysilicon.

2. The method according to claim 1, characterized in that The forming of a first oxide layer on the surface of the groove comprises: Thermal oxidation or chemical vapor deposition is performed to form a first oxide layer on the surface of the trench and the surface of the substrate.

3. The method according to claim 2, characterized in that The step of forming an isolation layer on the surface of the first oxide layer in the trench comprises: forming an isolation layer on the surface of the first oxide layer in the trench and the first oxide layer on the surface of the substrate; The isolation layer formed by the first oxide layer on the surface of the substrate is ground until the first oxide layer on the surface of the substrate is exposed.

4. The method according to claim 1 or 2, characterized in that Part of the first oxide layer on the sidewall of the trench is removed to a set depth: The first oxide layer is etched to a set depth using a wet method.

5. The method according to claim 1, wherein After removing the isolation layer, the method further includes: The upper surface of the first oxide layer or the sidewall of the trench is wet-etched so that the angle between the upper surface of the first oxide layer and the sidewall of the trench is greater than 90 degrees.

6. The method according to claim 1, characterized in that The forming of the second oxide layer on the surface of the groove and the surface of the first oxide layer comprises: Thermal oxidation or chemical vapor deposition is performed to form a second oxide layer on the surface of the trench, the surface of the first oxide layer, and the surface of the substrate.

7. The method according to claim 6, characterized in that Filling polysilicon on the second oxide layer in the trench comprises: Polysilicon is deposited on the second oxide layer in the trench and on the second oxide layer on the surface of the substrate.

8. The method according to claim 5, characterized in that When the second oxide layer is formed by chemical vapor deposition, the thickness of the first oxide layer is the difference between the preset target thickness and the first thickness, and the first thickness is the sum of the thickness of the first oxide layer removed when the first oxide layer is wet-etched and the thickness of the second oxide layer formed.

9. The method according to claim 5, characterized in that In the case where both the first oxide layer and the second oxide layer are formed by thermal oxidation, the thickness of the first oxide layer is the difference between the oxidation thickness of the second thermal oxidation and the oxidation thickness of the first thermal oxidation.

10. The method according to claim 5, characterized in that The set depth is the sum of a preset target depth, a height of the first oxide layer removed when the first oxide layer is wet-etched, and a thickness of the formed second oxide layer.

11. The method according to claim 1, wherein The polysilicon filled in the trench includes a first polysilicon portion and a second polysilicon portion, the first polysilicon portion and the substrate are isolated from each other by a second oxide layer, and the second polysilicon portion and the substrate are isolated from each other by the first oxide layer and the second oxide layer; After filling polysilicon on the second oxide layer in the trench, the method further comprises: removing polysilicon in the first polysilicon portion to a first depth, and removing the second oxide layer on the trench sidewall and the substrate surface above the first depth; forming a third oxide layer above the polysilicon in the trench, above the first depth, on the trench sidewalls and on the substrate surface, wherein the thickness of the third oxide layer is less than the thickness of the second oxide layer; Filling polysilicon on the third oxide layer in the trench.

12. The method according to claim 1, characterized in that The isolation layer is a nitride layer including any one of SIN, SION, and SIHN, or other non-oxidation layers.

13. A method for preparing a semiconductor device, characterized in that: include: providing a semiconductor substrate having a trench formed therein; forming a first oxide layer on the surface of the groove; forming an isolation layer on the surface of the first oxide layer in the trench; removing a portion of the first oxide layer on the sidewall of the trench to a set depth; removing the isolation layer; forming a second oxide layer on the surface of the groove and the surface of the first oxide layer; The second oxide layer in the trench is filled with polysilicon.

14. A semiconductor structure for a shielded gate trench power device, characterized in that: include: a semiconductor substrate having a trench formed therein; An oxide layer is formed in the bottom area of ​​the trench and the lower area of ​​the sidewall; An isolation layer is formed above the oxide layer, and the isolation layer extends along the trench sidewall oxide layer toward the trench opening to the position of the trench opening, and the isolation layer is used to protect the sidewall surface and bottom surface of the oxide layer from being corroded when the oxide layer is formed.

15. A semiconductor device, characterized in that: It is prepared by the method according to any one of claims 1 to 13.

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