Semiconductor chip with high metal filling coverage rate and preparation method thereof

Abstract

The invention discloses a semiconductor chip with a high metal filling coverage rate and a preparation method thereof, and belongs to the technical field of semiconductors. The semiconductor chip comprises a substrate and a semiconductor layer. The semiconductor layer is located on one face of the substrate, a hole groove is formed in the face, back to the substrate, of the semiconductor layer and comprises a groove body part and a groove opening part, the included angle between the inner side wall of the groove body part and the plane where the substrate is located ranges from 85 degrees to 90 degrees, the groove opening part is located at the end, away from the substrate, of the groove body part, and the groove opening part is located at the end, away from the substrate, of the groove body part. The included angle between the inner side wall of the notch part and the plane where the substrate is located ranges from 50 degrees to 70 degrees. The embodiment of the invention can improve the metal filling coverage rate.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular to a semiconductor chip with high metal filling coverage and a preparation method thereof. BACKGROUND

[0002] HEMT (High Electron Mobility Transistor) is a kind of heterojunction field effect transistor, which is widely used in aerospace, communication technology, automotive electronics and switching power supply fields, and is particularly widely concerned in high-power and high-frequency application fields. The HEMT chip, as a kind of semiconductor chip, is an important component of HEMT.

[0003] In the related art, the HEMT chip mainly includes a substrate, a semiconductor layer grown on the substrate, and a metal layer deposited on the semiconductor layer.

[0004] However, since the semiconductor layer is composed of multiple thin film layers, the layer-by-layer stacking of each thin film layer and the metal layer will cause height differences at different positions, resulting in low metal filling coverage and voids. SUMMARY

[0005] The present disclosure provides a semiconductor chip with high metal filling coverage, which can improve the metal filling coverage. The technical solution is as follows:

[0006] In one aspect, the present disclosure provides a semiconductor chip with high metal filling coverage, which includes a substrate and a semiconductor layer.

[0007] The semiconductor layer is located on one side of the substrate, and the side of the semiconductor layer away from the substrate has a hole slot, the hole slot includes a slot body part and a slot opening part, the included angle between the inner side wall of the slot body part and the plane where the substrate is located is 85°-90°, the slot opening part is located at one end of the slot body part away from the substrate, and the included angle between the inner side wall of the slot opening part and the plane where the substrate is located is 50°-70°.

[0008] In one implementation manner of the present disclosure, the semiconductor layer includes a Ti layer, an AlSi layer, a TiN layer and a dielectric layer.

[0009] The Ti layer, the AlSi layer, the TiN layer and the dielectric layer are sequentially stacked on one side of the substrate.

[0010] The slot body part penetrates the dielectric layer, and one end of the slot body part close to the substrate is located in the TiN layer, and the slot opening part is located in the dielectric layer.

[0011] In an implementation form of the disclosure, an included angle between an inner side wall of the groove body part and a plane where the substrate is located is 90°.

[0012] An included angle between an inner side wall of the notch part and a plane where the substrate is located is 60°.

[0013] In another aspect, the disclosure provides a preparation method of a semiconductor chip, which is used for preparing the semiconductor chip as described in the above aspect, and the preparation method comprises:

[0014] providing a substrate;

[0015] preparing a semiconductor layer on one side of the substrate, the semiconductor layer comprising a Ti layer, an AlSi layer, a TiN layer and a dielectric layer which are sequentially stacked;

[0016] preparing a photoresist layer on a side of the semiconductor layer away from the substrate;

[0017] performing first etching based on the photoresist layer to obtain an intermediate groove on the semiconductor layer;

[0018] performing second etching based on the photoresist layer to obtain a hole groove on the basis of the intermediate groove, and in a cross section along an epitaxial growth direction, the hole groove comprises a groove body part and a notch part, an included angle between an inner side wall of the groove body part and a plane where the substrate is located is 85°-90°, and an included angle between an inner side wall of the notch part and the plane where the substrate is located is 50°-70°.

[0019] In an implementation form of the disclosure, the photoresist layer prepared on the side of the semiconductor layer away from the substrate comprises:

[0020] coating photoresist on the side of the semiconductor layer away from the substrate;

[0021] patterning the photoresist to obtain the photoresist layer, the photoresist layer having an etching hole, and an included angle between an inner side wall of the etching hole and a plane where the substrate is located is 70°-75°.

[0022] In an implementation form of the disclosure, the first etching based on the photoresist layer comprises:

[0023] setting an etching pressure to 200-300 mTorr, setting an etching power to 500-700 W, setting an etching time to 70-90 s, and setting an etching gas to CHF3, AR and CF4.

[0024] In an implementation form of the disclosure, the first etching based on the photoresist layer further comprises:

[0025] The flow rate of CHF3 is set to 40-60 sccm, the flow rate of AR is set to 130-170 sccm, and the flow rate of CF4 is set to 50-70 sccm.

[0026] In an implementation manner of the present disclosure, the second etching based on the photoresist layer comprises:

[0027] The etching pressure is set to 200-300 mTorr, the etching power is set to 400-600 W, the etching time is set to 220-250 s, and the etching gas is set to CF4 and O2.

[0028] In an implementation manner of the present disclosure, the second etching based on the photoresist layer further comprises:

[0029] The flow rate of CF4 is set to 90-110 sccm, and the flow rate of O2 is set to 15-25 sccm.

[0030] In an implementation manner of the present disclosure, the preparation method further comprises:

[0031] During the first etching based on the photoresist layer, the selectivity ratio of the dielectric layer to the photoresist layer is greater than 2;

[0032] During the second etching based on the photoresist layer, the selectivity ratio of the dielectric layer to the photoresist layer is less than 1.

[0033] The technical scheme provided by the embodiments of the present disclosure has at least the following beneficial effects:

[0034] The semiconductor chip provided by the embodiments of the present disclosure has a substrate and a semiconductor layer, and one side of the semiconductor layer has a hole groove composed of a groove body part and a groove opening part. The groove opening part is located at one end of the groove body part away from the substrate. Since the included angle between the inner side wall of the groove body part and the plane in which the substrate is located is 85°-90°, and the included angle between the inner side wall of the groove opening part and the plane in which the substrate is located is 50°-70°, the included angle between the inner side wall of the groove body part and the plane in which the substrate is located is greater than the included angle between the inner side wall of the groove opening part and the plane in which the substrate is located, so that the groove opening part is inclined outward relative to the groove body part. Such a design is beneficial for depositing metal in the hole groove and effectively improves the metal filling coverage, thereby avoiding the occurrence of voids.

[0035] That is, the semiconductor chip provided by the embodiments of the present disclosure has a hole groove on one side of the semiconductor layer, and the groove opening part of the hole groove is inclined outward relative to the groove body part, thereby being beneficial for depositing metal in the hole groove and effectively improving the metal filling coverage, thereby avoiding the occurrence of voids. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0037] Figure 1 is a structural schematic diagram of a semiconductor chip provided by an embodiment of the present disclosure;

[0038] Figure 2 is a structural schematic diagram of a semiconductor layer provided by an embodiment of the present disclosure;

[0039] Figure 3 is a flowchart of a preparation method of a semiconductor chip provided by an embodiment of the present disclosure;

[0040] Figure 4 is a flowchart of another preparation method of a semiconductor chip provided by an embodiment of the present disclosure;

[0041] Figure 5 is a preparation process schematic diagram provided by an embodiment of the present disclosure;

[0042] Figure 6 is a preparation process schematic diagram provided by an embodiment of the present disclosure;

[0043] Figure 7 is a preparation process schematic diagram provided by an embodiment of the present disclosure;

[0044] Figure 8 is a preparation process schematic diagram provided by an embodiment of the present disclosure.

[0045] Reference signs:

[0046] 10, substrate;

[0047] 20, semiconductor layer;

[0048] 210, Ti layer; 220, AlSi layer; 230, TiN layer; 240, dielectric layer;

[0049] 30, hole groove;

[0050] 310, groove body part; 320, groove opening part;

[0051] 40, photoresist layer;

[0052] 410, etching hole;

[0053] 50, intermediate groove. DETAILED DESCRIPTION

[0054] In order to make the purposes, technical solutions and advantages of the present disclosure clearer, the following will further describe the embodiments of the present disclosure in detail with reference to the drawings.

[0055] The HEMT (High Electron Mobility Transistor) is a kind of heterojunction field effect transistor, which is widely used in aerospace, communication technology, automobile electronics and switching power supply fields, and is especially widely concerned in high-power and high-frequency application fields. The HEMT chip is an important component of the HEMT.

[0056] In the related art, the HEMT chip mainly includes a substrate, a semiconductor layer grown on the substrate, and a metal layer deposited on the semiconductor layer.

[0057] However, since the semiconductor layer is composed of multiple thin film layers, the layer-by-layer stacking of the thin film layers and the metal layer will cause height differences at different positions, resulting in low metal filling coverage and voids.

[0058] In order to solve the above technical problems, the present disclosure provides a semiconductor chip, Figure 1 The structure of the semiconductor chip is shown in the figure, and the structure of the semiconductor chip is described in detail as follows. Figure 1 In the present embodiment, the semiconductor chip includes a substrate 10 and a semiconductor layer 20.

[0059] The semiconductor layer 20 is located on one side of the substrate 10, and the side of the semiconductor layer 20 away from the substrate 10 has a hole slot 30, the hole slot 30 includes a slot body part 310 and a slot opening part 320, the included angle a between the inner side wall of the slot body part 310 and the plane where the substrate 10 is located is 85°-90°, the slot opening part 320 is located at one end of the slot body part 310 away from the substrate 10, and the included angle b between the inner side wall of the slot opening part 320 and the plane where the substrate 10 is located is 50°-70°.

[0060] The semiconductor chip provided by the embodiment of the present disclosure has a substrate 10 and a semiconductor layer 20, and one side of the semiconductor layer 20 has a hole groove 30, which is composed of a groove body part 310 and a groove opening part 320. The groove opening part 320 is located at the end of the groove body part 310 away from the substrate 10. Since the included angle between the inner side wall of the groove body part 310 and the plane where the substrate 10 is located is 85°-90°, and the included angle between the inner side wall of the groove opening part 320 and the plane where the substrate 10 is located is 50°-70°, the included angle between the inner side wall of the groove body part 310 and the plane where the substrate 10 is located is greater than the included angle between the inner side wall of the groove opening part 320 and the plane where the substrate 10 is located, so that the groove opening part 320 is outwardly tilted relative to the groove body part 310. In this way, the opening area of the groove opening part 320 is increased, thereby allowing more metal atoms to be deposited into the hole groove 30, that is, facilitating the deposition of metal in the hole groove 30, and effectively improving the metal filling coverage, thereby avoiding the occurrence of voids.

[0061] That is, the semiconductor chip provided by the embodiment of the present disclosure has the hole groove 30 on one side of the semiconductor layer 20, and the groove opening part 320 of the hole groove 30 is outwardly tilted relative to the groove body part 310, thereby facilitating the deposition of metal in the hole groove 30, and effectively improving the metal filling coverage, thereby avoiding the occurrence of voids.

[0062] In the embodiment, the semiconductor chip can be a normally-off GaN HEMT chip or a normally-on GaN HEMT chip, and the present disclosure does not limit this.

[0063] Figure 2 The semiconductor layer 20 is a structural schematic diagram, which is combined with Figure 2 In the embodiment, the semiconductor layer 20 includes a Ti layer 210, an AlSi layer 220, a TiN layer 230, and a dielectric layer 240.

[0064] The Ti layer 210, the AlSi layer 220, the TiN layer 230, and the dielectric layer 240 are sequentially stacked on one side of the substrate 10. The groove body part 310 penetrates the dielectric layer 240, and the end of the groove body part 310 close to the substrate 10 is located in the TiN layer 230. The groove opening part 320 is located in the dielectric layer 240.

[0065] In the above implementation manner, the top of the groove body part 310 is located in the dielectric layer 240, the bottom of the groove body part 310 penetrates the dielectric layer 240 and is located in the TiN layer 230, and the groove opening part 320 is located in the dielectric layer 240 together with the top of the groove body part 310.

[0066] The combination of the Ti layer 210, the AlSi layer 220, and the TiN layer 230 belongs to a metal layer and is mainly used for conducting electricity. The Ti layer 210 plays a role of adhesion and can be well adhered to a substrate or a medium layer in a previous process. The TiN layer 230 plays a role of adhesion and passivation, preventing the AlSi layer 220 from being oxidized. The AlSi layer 220 mainly plays a role of conducting electronic charges.

[0067] Exemplarily, the specification parameters are as follows: the thickness of the Ti layer 210 is about 80-120 nm; the thickness of the AlSi layer 220 is about 2-4 um; and the thickness of the TiN layer 230 is about 80-120 nm.

[0068] In this embodiment, the thickness of the Ti layer 210 is 100 nm; the thickness of the AlSi layer 220 is 3 um; and the thickness of the TiN layer 230 is 100 nm.

[0069] Exemplarily, the medium layer 240 is a SiN layer, a SiO layer, or a composite medium layer 240, and the present disclosure does not limit this.

[0070] In this embodiment, the medium layer 240 is a SiO layer.

[0071] Since the opening area of the notch part 320 is increased, more metal atoms are allowed to be deposited into the hole groove 30, the medium layer 240 and the metal layer in the hole groove 30 are more easily attached, thereby facilitating the deposition of metal in the hole groove 30 and effectively improving the metal filling coverage.

[0072] In this embodiment, the included angle a between the inner side wall of the groove body part 310 and the plane where the substrate 10 is located is 90°. The included angle b between the inner side wall of the notch part 320 and the plane where the substrate 10 is located is 60°.

[0073] In the above implementation manner, the extension direction of the groove body part 310 is perpendicular to the substrate 10, that is, the groove body part 310 is vertically etched downward until the TiN layer 230. Such a design is conducive to accommodating the deposition of metal. The notch part 320 is designed to have the above angles, which can be conducive to the deposition of metal in the groove body part 310, improve the metal filling coverage, and effectively reduce the generation of voids.

[0074] Of course, in other embodiments, the values of the included angle a and the included angle b can also be adjusted within the above angle range according to actual needs, and the present disclosure does not limit this.

[0075] Figure 3 A flowchart of a preparation method of a semiconductor chip provided by the present disclosure is provided. The preparation method is used for preparing a semiconductor chip as shown in Figure 1 , and in combination with Figure 3 , the preparation method comprises the following steps:

[0076] Step 301: providing a substrate 10.

[0077] Step 302: preparing a semiconductor layer 20 on one side of the substrate 10.

[0078] Step 303: preparing a photoresist layer 40 on the side of the semiconductor layer 20 away from the substrate 10.

[0079] Step 304: performing a first etching based on the photoresist layer 40 to obtain an intermediate groove 50 on the semiconductor layer 20.

[0080] Step 305: performing a second etching based on the photoresist layer 40 to obtain a hole groove 30 on the basis of the intermediate groove 50.

[0081] In a cross section along the epitaxial growth direction, the hole groove 30 comprises a groove body part 310 and a groove opening part 320, an included angle between an inner side wall of the groove body part 310 and a plane where the substrate 10 is located is 85°-90°, and the groove opening part 320 is located at an end of the groove body part 310 away from the substrate 10, and an included angle between an inner side wall of the groove opening part 320 and the plane where the substrate 10 is located is 50°-70°.

[0082] The preparation method provided by the embodiment of the present disclosure forms the hole groove 30 on the semiconductor layer 20 through the first etching and the second etching, and the hole groove 30 is composed of the groove body part 310 and the groove opening part 320. The groove opening part 320 is located at an end of the groove body part 310 away from the substrate 10. Since the included angle between the inner side wall of the groove body part 310 and the plane where the substrate 10 is located is 85°-90°, and the included angle between the inner side wall of the groove opening part 320 and the plane where the substrate 10 is located is 50°-70°, the included angle between the inner side wall of the groove body part 310 and the plane where the substrate 10 is located is greater than the included angle between the inner side wall of the groove opening part 320 and the plane where the substrate 10 is located, so that the groove opening part 320 is inclined outward relative to the groove body part 310. Such a design is conducive to depositing metal in the hole groove 30 and effectively improves the metal filling coverage, thereby avoiding the occurrence of voids.

[0083] That is, the semiconductor chip prepared by the preparation method provided by the embodiment of the present disclosure is provided with the hole groove 30 on one side of the semiconductor layer 20, and the groove opening part 320 of the hole groove 30 is inclined outward relative to the groove body part 310, thereby being conducive to depositing metal in the hole groove 30 and effectively improving the metal filling coverage, thereby avoiding the occurrence of voids.

[0084] Figure 4 Another flowchart of a preparation method of a semiconductor chip provided by the embodiment of the present disclosure is provided in combination with Figure 4 In the embodiment, the preparation method comprises:

[0085] Step 401: providing a substrate 10.

[0086] Exemplarily, the substrate 10 is one of a sapphire substrate 10, a SiC substrate 10, a Si substrate 10, and a GaN substrate 10.

[0087] In this embodiment, the substrate 10 is a Si substrate 10.

[0088] Step 402: preparing a semiconductor layer 20 on one side of the substrate 10.

[0089] In this embodiment, step 402 includes the following steps.

[0090] Step 4021: sequentially preparing a Ti layer 210, an AlSi layer 220, and a TiN layer 230 on one side of the substrate 10 by physical vapor deposition (PVD), so that the Ti layer 210, the AlSi layer 220, and the TiN layer 230 are sequentially stacked.

[0091] Step 4022: preparing a dielectric layer 240 on the side of the TiN layer 230 away from the substrate 10 by plasma enhanced chemical vapor deposition (PECVD).

[0092] Exemplarily, the dielectric layer 240 is a SiN layer, a SiO layer, or a composite dielectric layer 240, and the present disclosure does not limit the dielectric layer 240.

[0093] In this embodiment, the dielectric layer 240 is a SiO layer.

[0094] Step 403: preparing a photoresist layer 40 on the side of the semiconductor layer 20 away from the substrate 10 (see FIG. 1). Figure 5 ).

[0095] In this embodiment, step 403 includes the following steps.

[0096] Step 4031: coating the photoresist on the side of the semiconductor layer 20 away from the substrate 10.

[0097] Exemplarily, the thickness of the photoresist is 3 μm.

[0098] In the above implementation, the thickness of the photoresist is set to the above value, which can ensure the functionality of the photoresist and the coating efficiency.

[0099] Step 4032: patterning the photoresist to obtain the photoresist layer 40.

[0100] Exemplarily, the photoresist is patterned, i.e., the photoresist is converted into a photoresist layer 40 with patterns by solidification, exposure, development and the like, to prepare for subsequent etching.

[0101] In this embodiment, the photoresist layer 40 has etching holes 410, and the included angle c between the inner side wall of the etching holes 410 and the plane where the substrate 10 is located is 70°-75°.

[0102] In the above implementation, since the inner side wall of the etching holes 410 has a certain angle, in the subsequent etching step, a groove with a certain angle can be etched.

[0103] Step 404: First etching based on the photoresist layer 40 to obtain an intermediate groove 50 on the semiconductor layer 20 (see Figure 6 ).

[0104] Exemplarily, in step 404, the etching parameters of the first etching are designed as follows:

[0105] The etching pressure is set to 200-300 mTorr, the etching power is set to 500-700 W, the etching time is set to 70-90 s, and the etching gas is set to CHF3, AR and CF4.

[0106] Exemplarily, the flow rate of CHF3 is set to 40-60 sccm, the flow rate of AR is set to 130-170 sccm, and the flow rate of CF4 is set to 50-70 sccm.

[0107] In this embodiment, the etching pressure is set to 250 mTorr, the etching power is set to 600 W, the etching time is set to 79 s, the flow rate of CHF3 is set to 50 sccm, the flow rate of AR is set to 150 sccm, and the flow rate of CF4 is set to 60 sccm.

[0108] Through the above etching parameters, the intermediate groove 50 with a depth of 500 nm can be etched on the dielectric layer 240.

[0109] It is worth noting that the included angle d between the inner wall of the intermediate groove 50 and the plane where the substrate 10 is located is consistent with the included angle c between the inner side wall of the etching holes 410 and the plane where the substrate 10 is located, which is 70°-75°.

[0110] Step 405: Second etching based on the photoresist layer 40 to obtain a hole groove 30 on the basis of the intermediate groove 50 (see Figure 7 ).

[0111] Exemplarily, in step 405, the etching parameters of the second etching are designed as follows:

[0112] The etching pressure is set to 200-300 mTorr, the etching power is set to 400-600 W, the etching time is set to 220-250 s, and the etching gas is set to CF4 and O2.

[0113] For example, the flow rate of CF4 is set to 90-110 sccm, and the flow rate of O2 is set to 15-25 sccm.

[0114] In this embodiment, the etching pressure is set to 250 mTorr, the etching power is set to 500 W, the etching time is set to 235 s, the flow rate of CF4 is set to 100 sccm, and the flow rate of O2 is set to 20 sccm.

[0115] In the second etching process, since the etching gas is switched from CHF3, AR and CF4 to CF4 and O2, the content of O2 is increased, so that the included angle c between the inner sidewall of the etching hole 410 and the plane where the substrate 10 is located is continuously reduced (from 70°-75° to 60°), that is, the inclination angle of the etching hole 410 gradually becomes gentle. At the same time, the change in the inclination angle of the etching hole 410 will also transmit the change in its morphology to the dielectric layer 240, so that the inclination angle of the dielectric layer 240 is also reduced (from 70°-75° to 60°), that is, it gradually becomes gentle, thereby forming the notch portion 320. At the same time, since O2 can remove the by-products, the combination of CF4 and O2 causes the chemical etching to be relatively strong, so that the etching forms a groove that extends vertically, thereby forming the groove body portion 310.

[0116] It is worth noting that the time of the second etching is obtained by dividing the thickness of the remaining photoresist layer 40 after the first etching by the stripping rate. The etching time needs to be long enough to ensure that the included angle c can extend to the dielectric layer 240.

[0117] In this embodiment, in the cross section along the epitaxial growth direction, the hole groove 30 includes the groove body portion 310 and the notch portion 320, the included angle between the inner sidewall of the groove body portion 310 and the plane where the substrate 10 is located is 85°-90°, and the notch portion 320 is located at the end of the groove body portion 310 away from the substrate 10, and the included angle between the inner sidewall of the notch portion 320 and the plane where the substrate 10 is located is 50°-70°.

[0118] In this embodiment, in the first etching process based on the photoresist layer 40, the selectivity ratio of the dielectric layer 240 to the photoresist layer 40 is greater than 2. In the second etching process based on the photoresist layer 40, the selectivity ratio of the dielectric layer 240 to the photoresist layer 40 is less than 1.

[0119] That is, in the process of the first etching based on the photoresist layer 40, the selectivity ratio of the dielectric layer 240 and the photoresist layer 40 is greater than the selectivity ratio of the dielectric layer 240 and the photoresist layer 40 in the process of the second etching based on the photoresist layer 40.

[0120] In this way, the photoresist layer 40 can be prevented from being consumed too quickly in the process of the second etching, thereby avoiding insufficient etching depth.

[0121] The preparation method provided by the embodiments of the present disclosure can be applied not only to dry etching of shallow holes (aspect ratio not greater than 5), but also to dry etching of deep holes (aspect ratio greater than 5).

[0122] Step 406: removing the excess photoresist layer 40 (see Figure 8 ).

[0123] The preparation method provided by the embodiments of the present disclosure forms the hole groove 30 on the semiconductor layer 20 through the first etching and the second etching, and the hole groove 30 is composed of the groove body part 310 and the groove opening part 320. The groove opening part 320 is located at one end of the groove body part 310 away from the substrate 10. Since the included angle between the inner side wall of the groove body part 310 and the plane where the substrate 10 is located is 85°-90°, and the included angle between the inner side wall of the groove opening part 320 and the plane where the substrate 10 is located is 50°-70°, the included angle between the inner side wall of the groove body part 310 and the plane where the substrate 10 is located is greater than the included angle between the inner side wall of the groove opening part 320 and the plane where the substrate 10 is located, so that the groove opening part 320 is outwardly tilted relative to the groove body part 310. Such a design is conducive to depositing metal in the hole groove 30 and effectively improves the metal filling coverage, thereby avoiding the occurrence of voids.

[0124] That is, the semiconductor chip prepared by the preparation method provided by the embodiments of the present disclosure is provided with the hole groove 30 on one side of the semiconductor layer 20, and the groove opening part 320 of the hole groove 30 is outwardly tilted relative to the groove body part 310, thereby being conducive to depositing metal in the hole groove 30 and effectively improving the metal filling coverage, thereby avoiding the occurrence of voids.

[0125] Unless otherwise defined, technical terms or scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", "third" and similar terms used herein do not denote any order, quantity, or importance, but are used to distinguish one element from another. Also, the terms "a" or "an" do not denote a limitation of quantity, but denote the presence of at least one. The terms "include" or "comprise" and similar terms do not exclude the presence of other elements or items. The terms "connected" or "coupled" and similar terms do not exclude the presence of intermediate elements or intervening components between two elements that are connected or coupled together. The terms "above", "below", "top", "bottom", "up", "down", and the like are used for ease of description to describe one element's relationship to another element as the absolute position of the elements changes. Thus, if a relative position is changed, then such absolute positions can also change.

[0126] The above is not intended to limit the present disclosure in any form, although the present disclosure has been disclosed as above through embodiments, however, not intended to limit the present disclosure, any skilled person in the art, within the scope of the technical solution of the present disclosure, can make some changes or modifications to the equivalent embodiments of the above disclosed technical content, but as long as it does not deviate from the content of the technical solution of the present disclosure, any simple modification, equivalent change and modification of the above embodiments according to the technical essence of the present disclosure, still belongs to the scope of the technical solution of the present disclosure.

Claims

1. A semiconductor chip with high metal filling coverage, characterized in that: It comprises a substrate (10) and a semiconductor layer (20); The semiconductor layer (20) is located on one side of the substrate (10); the side of the semiconductor layer (20) facing away from the substrate (10) has a hole groove (30); the hole groove (30) includes a groove body portion (310) and a groove opening portion (320); the angle between the inner side wall of the groove body portion (310) and the plane where the substrate (10) is located is 85° to 90°; the groove opening portion (320) is located at one end of the groove body portion (310) away from the substrate (10); the angle between the inner side wall of the groove opening portion (320) and the plane where the substrate (10) is located is 50° to 70°.

2. The semiconductor chip according to claim 1, wherein The semiconductor layer (20) comprises a Ti layer (210), an AlSi layer (220), a TiN layer (230) and a dielectric layer (240); The Ti layer (210), the AlSi layer (220), the TiN layer (230) and the dielectric layer (240) are sequentially stacked on one side of the substrate (10); The groove body portion (310) penetrates the dielectric layer (240), and one end of the groove body portion (310) close to the substrate (10) is located in the TiN layer (230), and the notch portion (320) is located in the dielectric layer (240).

3. The semiconductor chip according to claim 1, wherein The angle between the inner side wall of the groove portion (310) and the plane where the substrate (10) is located is 90°; The angle between the inner side wall of the notch portion (320) and the plane where the substrate (10) is located is 60°.

4. A method for preparing a semiconductor chip, characterized in that: The preparation method is used to prepare the semiconductor chip according to claim 1, and the preparation method comprises: Providing a substrate (10); A semiconductor layer (20) is prepared on one side of the substrate (10), wherein the semiconductor layer (20) comprises a Ti layer (210), an AlSi layer (220), a TiN layer (230), and a dielectric layer (240) stacked in sequence; preparing a photoresist layer (40) on a side of the semiconductor layer (20) facing away from the substrate (10); Performing a first etching based on the photoresist layer (40) to obtain a middle groove (50) on the semiconductor layer (20); A second etching is performed based on the photoresist layer (40) to obtain a hole groove (30) on the basis of the intermediate groove (50); in a cross section along the epitaxial growth direction, the hole groove (30) comprises a groove body portion (310) and a groove opening portion (320); the angle between the inner side wall of the groove body portion (310) and the plane where the substrate (10) is located is 85° to 90°; the groove opening portion (320) is located at one end of the groove body portion (310) away from the substrate (10); the angle between the inner side wall of the groove opening portion (320) and the plane where the substrate (10) is located is 50° to 70°.

5. The preparation method according to claim 4, characterized in that Preparing a photoresist layer (40) on a side of the semiconductor layer (20) facing away from the substrate (10), comprising: coating a photoresist on a side of the semiconductor layer (20) facing away from the substrate (10); The photoresist is patterned to obtain the photoresist layer (40), wherein the photoresist layer (40) has an etching hole (410), and the angle between the inner side wall of the etching hole (410) and the plane where the substrate (10) is located is 70° to 75°.

6. The preparation method according to claim 4, characterized in that Performing a first etching based on the photoresist layer (40), comprising: The etching pressure is set to 200-300 mTorr, the etching power is set to 500-700 W, the etching time is set to 70-90 s, and the etching gas is set to CHF3, AR, and CF4.

7. The preparation method according to claim 6, characterized in that Performing a first etching based on the photoresist layer (40), further comprising: The flow rate of CHF3 is set to 40-60 sccm, the flow rate of AR is set to 130-170 sccm, and the flow rate of CF4 is set to 50-70 sccm.

8. The preparation method according to claim 4, characterized in that Performing a second etching based on the photoresist layer (40), comprising: The etching pressure is set to 200-300 mTorr, the etching power is set to 400-600 W, the etching time is set to 220-250 s, and the etching gas is set to CF4 and O2.

9. The preparation method according to claim 8, characterized in that Performing a second etching based on the photoresist layer (40), further comprising: The flow rate of CF4 is set to 90-110 sccm, and the flow rate of O2 is set to 15-25 sccm.

10. The preparation method according to claim 4, characterized in that The preparation method further comprises: During the first etching process based on the photoresist layer (40), the selectivity ratio between the dielectric layer (240) and the photoresist layer (40) is greater than 2; During the second etching process based on the photoresist layer (40), the selectivity ratio between the dielectric layer (240) and the photoresist layer (40) is less than 1.

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