Voltage-resistant MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with embedded oxide buried layer and preparation method thereof

Abstract

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a voltage-resistant MOSFET (metal oxide semiconductor field effect transistor) device with an embedded oxide buried layer and a preparation method thereof, the voltage-resistant MOSFET device comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P well layer and a P + layer, an upper oxidation buried layer is arranged between every two adjacent P well layers and located under the corresponding grid electrode, and each upper oxidation buried layer is composed of a plurality of oxidation particles which are not in contact with each other. The vertical electric field distribution is optimized while the transverse electric field peak value is blocked through the upper and lower discrete oxide buried layer structure, namely the particle swarms of the upper oxide buried layer and the rectangular particles of the lower oxide buried layer, so that the stray capacitance problem caused by a continuous dielectric layer is effectively avoided; the breakdown voltage performance of the device is obviously improved; and the energy loss in the switching process is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of MOS semiconductor technology, and in particular to a voltage-resistant MOSFET device with embedded oxide buried layer and a preparation method thereof. BACKGROUND

[0002] In current high-voltage MOSFET devices, the traditional continuous medium buried layer structure is prone to introduce parasitic capacitance, leading to increased switching loss and limiting the increase of breakdown voltage; and the voltage-resistant technology such as super-junction often relies on complex epitaxy or multiple implantation processes, facing problems such as high manufacturing cost and uneven electric field distribution. Especially in the key area below the gate, a single dielectric layer is difficult to optimize the lateral and vertical electric fields at the same time, restricting the application performance of the device in high-frequency and high-power scenarios. The existing solutions have significant bottlenecks in balancing the on-resistance, voltage resistance and process feasibility.

[0003] An existing patent discloses a semi-super junction MOSFET with auxiliary oxide buried layer (publication number CN107425070B). The bottom auxiliary layer electric field of the semi-super junction MOSFET in the existing patent is in a triangular / gradient distribution, which limits its contribution to the overall voltage resistance. Moreover, the avalanche breakdown point of the existing patent is located at the edge of the P-body region, and the breakdown current flowing through the parasitic BJT base region resistance is prone to cause device failure. SUMMARY

[0004] The present application provides a voltage-resistant MOSFET device with embedded oxide buried layer and a preparation method thereof to solve the existing technical problems, solving the problem of parasitic capacitance caused by continuous dielectric layer.

[0005] To solve the above technical problems, according to one aspect of the present application, more specifically, a voltage-resistant MOSFET device with embedded oxide buried layer, comprising a plurality of parallel MOS cells, a single MOS cell comprising a drain, a semiconductor epitaxial layer, a source and a gate, the semiconductor epitaxial layer comprising an N substrate layer, an N drift layer, an N well layer, a P well layer and a P+ layer, an upper oxide buried layer is provided between two adjacent P well layers and directly below the gate, the upper oxide buried layer is composed of a plurality of non-contact oxide particles; A lower oxide buried layer is provided inside the N substrate layer and directly below the gate, the lower oxide buried layer is composed of three non-contact oxide rectangular particles, wherein the bottom end of the oxide rectangular particle is in direct contact with the drain.

[0006] Further, the material of the upper oxide buried layer and the lower oxide buried layer is one of silicon dioxide and a silicon nitride composite material.

[0007] Further, the cross-sectional profile of the N substrate layer near the lower oxide buried layer is in a convex shape.

[0008] Further, the inside of the N drift layer and directly below the P+ layer is formed with a side P- layer by ion implantation, the top end of the side P- layer directly contacts the P+ layer, and the bottom end of the side P- layer directly contacts the N substrate layer.

[0009] Further, the inside of the N drift layer and above the raised area of the N substrate layer is provided with a covering N- layer.

[0010] Further, the cross-sectional profile of the covering N- layer is arc-shaped, and the covering N- layer only covers the raised area of the N substrate layer.

[0011] Further, the covering N- layer further includes a full-covering N- layer covering the entire N substrate layer.

[0012] Further, the inside of the N substrate layer and between two adjacent rectangular oxide particles is formed with a doped P- layer by ion implantation, the height of the cross-sectional profile of the doped P- layer is lower than the height of the cross-sectional profile of the rectangular oxide particles.

[0013] A preparation method of a buried oxide layer embedded voltage-resistant MOSFET device, specifically comprising: S1, forming a raised area on the surface of an N substrate layer by photolithography and selective etching process, and predefining the pattern position of the lower buried oxide layer in the raised area; S2, performing local oxidation or dielectric deposition on the raised area of the N substrate layer to form a lower buried oxide layer composed of three mutually non-contacting rectangular oxide particles, ensuring that the bottom end of the rectangular oxide particles directly contacts the drain formed subsequently, and that a semiconductor groove is reserved between the particles; S3, performing boron ion implantation in the groove between the rectangular oxide particles of the lower buried oxide layer by mask control to form a doped P- layer with a height lower than that of the oxide particles; S4, epitaxially growing an N drift layer on the N substrate layer, and synchronously controlling the epitaxial parameters to make the raised topography of the N substrate layer extend upward; S5, etching a groove between adjacent P well regions, depositing silicon dioxide or composite dielectric and performing back etching to form a discrete particle-shaped upper buried oxide layer; sequentially forming an N well layer, a P well layer and a P+ layer by multiple photolithography and ion implantation; S6, depositing polysilicon and patterning to form a gate electrode covering directly above the upper buried oxide layer; S7, depositing a metal layer on the front surface of the device and performing photolithography to form a source electrode and a gate electrode contact, and preparing a drain metal layer after thinning the back surface of the substrate.

[0014] The application provides a voltage-resistant MOSFET device with a buried oxide layer embedded and a preparation method thereof, and compared with the prior art, the method has the following effects: 1. The upper and lower double-layer discrete oxide buried layer structure, i.e. the particle group of the upper oxide buried layer and the rectangular particle of the lower oxide buried layer, optimizes the vertical electric field distribution while blocking the transverse electric field peak, effectively avoids the parasitic capacitance problem caused by the continuous medium layer, significantly improves the breakdown voltage performance of the device and reduces the energy loss in the switching process.

[0015] 2. The local super-junction charge compensation mechanism is formed in the drift region by the longitudinal deep implantation design of the side P-layer, which suppresses the abnormal increase of the on-resistance under high voltage, thereby improving the dynamic resistance characteristics and enhancing the resistance of the device under avalanche breakdown conditions.

[0016] 3. The arc-shaped N-layer covering the substrate protruding area is designed to offset the electric field concentration effect through concentration gradient modulation, which significantly improves the breakdown voltage while maintaining low on-resistance, and is particularly suitable for high-frequency application scenarios that require both efficiency and withstand voltage.

[0017] 4. The introduction of the full-coverage N-layer simplifies the complex process required by the traditional withstand voltage layer structure, reduces the number of photolithography and implantation through global uniform doping, significantly improves the production yield while maintaining the core withstand voltage capability, and reduces the manufacturing cost.

[0018] 5. The injection of the low-position doped P-layer between the particles of the lower oxide buried layer widens the depletion region range, effectively suppresses the electric field peak at the edge of the oxide medium, significantly reduces the leakage current under high temperature environment and improves the stability of the breakdown voltage. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a schematic diagram of example one in the present application; Figure 2 is a schematic diagram of example two in the present application; Figure 3 is a schematic diagram of example three in the present application; Figure 4 is a schematic diagram of example four in the present application; Figure 5 is a schematic diagram of example five in the present application.

[0020] In the figure: 1, drain; 2, source; 3, gate; 4, N substrate layer; 5, N drift layer; 6, N well layer; 7, P well layer; 8, P+ layer; 9, upper oxide buried layer; 10, lower oxide buried layer; 11, side P-layer; 12, covering N-layer; 13, doped P-layer; 1201, full-coverage N-layer. DETAILED DESCRIPTION

[0021] In order to make the technical scheme of the present application clearer, the following will further explain the present application in combination with the drawings and specific embodiments.

[0022] As Figure 5 shown, a preparation method of a buried oxide voltage-resistant MOSFET device with embedded oxide, specifically comprising: Step one, forming a convex region on the surface of the N substrate layer 4 through photolithography and selective etching process, and predefining the pattern position of the lower oxide buried layer 10 in the convex region; through photolithography and selective etching, the substrate convex region and the position of the lower oxide buried layer are precisely defined to ensure that the subsequent structure is strictly aligned with the gate projection area, providing a geometric basis for electric field optimization, and at the same time avoiding additional mask layer to simplify the process.

[0023] Step two, local oxidation or dielectric deposition is performed on the convex region of the N substrate layer 4 to form a lower oxide buried layer 10 composed of three mutually non-contacting rectangular oxide particles, ensuring that the bottom end of the rectangular oxide particles is in direct contact with the subsequently formed drain 1, and that the semiconductor grooves between the particles are reserved; local oxidation or dielectric deposition forms a discrete rectangular particle structure, realizes the vertical electric field modulation of the lower oxide buried layer and the drain, significantly reduces the on-resistance, and the semiconductor grooves reserved between the particles create space for P-type implantation.

[0024] Step three, in the groove between the rectangular oxide particles of the lower oxide buried layer 10, boron ion implantation is performed through mask control to form a doped P-layer 13 with a height lower than the oxide particles; low-position boron implantation is performed in the oxide particle groove to form a doped P-layer, effectively widening the depletion region and suppressing the electric field concentration at the edge of the dielectric, improving high-temperature stability while avoiding affecting the substrate carrier mobility.

[0025] Step four, epitaxially growing an N drift layer 5 on the N substrate layer 4, and synchronously controlling the epitaxial parameters to make the convex topography of the N substrate layer 4 extend upward; epitaxial growth synchronously replicates the substrate convex topography to the drift layer, maintaining the continuity of the longitudinal electric field distribution, providing a forming basis for the arc-shaped N-layer, and ensuring the coordinated optimization of breakdown voltage and on-resistance.

[0026] Step five, etching a groove between adjacent P-well regions 7, depositing silicon dioxide or composite dielectric and etching back to form a discrete particle-shaped upper oxide buried layer 9; sequentially forming N-well layer 6, P-well layer 7 and P+ layer 8 through multiple photolithography and ion implantation; the groove etching back process realizes the discrete particle structure of the upper oxide buried layer, blocking the lateral peak electric field between P-wells; the composite dielectric is selected to enhance the voltage resistance reliability, and the synchronous well region implantation ensures the super-junction charge compensation effect.

[0027] Step six, depositing polysilicon and patterning to form a gate 3, covering directly above the upper oxide buried layer 9; the gate polysilicon directly covers the discrete upper oxide buried layer, utilizing the dielectric segmentation effect to reduce the gate-source capacitance and gate-drain capacitance, significantly improving the switching speed and reducing the driving loss.

[0028] Step 7: Deposit a metal layer on the front of the device and photolithographically form the source 2 and gate 3 contacts. Thin the back of the substrate to form the drain 1 metal layer. This integrated process of front-side metallization and back-side thinning optimizes the current path and reduces the source-drain series resistance. Simultaneously, substrate thinning enhances heat dissipation and ensures device reliability at high power densities.

[0029] Example 1 like Figure 1 As shown, according to one aspect of the present invention, a voltage-resistant MOSFET device with an embedded buried oxide layer is provided, comprising several mutually parallel MOS cells. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 2, and a gate 3. The semiconductor epitaxial layer includes an N substrate layer 4, an N drift layer 5, an N well layer 6, a P well layer 7, and a P+ layer 8. An upper buried oxide layer 9 is provided between two adjacent P well layers 7 and directly below the gate 3. The upper buried oxide layer 9 is composed of several non-contacting oxide particles. A lower buried oxide layer 10 is provided within the N substrate layer 4 and directly below the gate 3. The lower buried oxide layer 10 is composed of three non-contacting oxide rectangular particles, wherein the bottom ends of the oxide rectangular particles are in direct contact with the drain 1. The material of the upper buried oxide layer 9 and the lower buried oxide layer 10 are both selected from silicon dioxide or a composite material of silicon dioxide and silicon nitride. The cross-sectional profile of the N substrate layer 4 near the lower buried oxide layer 10 is convex.

[0030] Upper buried oxide layer 9 forms discrete particles between adjacent P-wells 7, blocking lateral electric field peaks. The bottoms of the rectangular particles in lower buried oxide layer 10 connect to drain 1, optimizing vertical electric field distribution. Furthermore, the discrete structure avoids parasitic capacitance associated with continuous dielectric layers. Dual electric field modulation significantly improves breakdown voltage while reducing switching losses.

[0031] Example 2 like Figure 2 As shown, a side P- layer 11 is formed inside the N drift layer 5 and directly below the P+ layer 8 by ion implantation. The top of the side P- layer 11 is in direct contact with the P+ layer 8, and the bottom of the side P- layer 11 is in direct contact with the N substrate layer 4.

[0032] The deep-implanted P- layer 11, extending from the P+ layer 8 to the N substrate layer 4, forms a local superjunction with the N drift layer 5, enabling longitudinal charge compensation during depletion. This also suppresses the increase in on-resistance in the drift region with voltage, thereby reducing dynamic resistance and improving avalanche withstand.

[0033] Example 3 like Figure 3 As shown, a covering N-layer 12 is provided inside the N drift layer 5 and above the raised area of ​​the N substrate layer 4. The cross-sectional profile of the covering N-layer 12 is arc-shaped, and the covering N-layer 12 only covers the raised area of ​​the N substrate layer 4.

[0034] The arc-shaped N-layer 12 is implanted only above the raised area of ​​the N substrate 4, offsetting the electric field concentration effect at the raised area through the concentration gradient. The breakdown voltage is significantly improved compared to traditional structures, while maintaining low on-resistance, making it suitable for high-frequency applications.

[0035] Example 4 like Figure 4 As shown, a covering N-layer 12 is provided inside the N drift layer 5 and above the raised area of ​​the N substrate layer 4. The covering N-layer 12 further includes a full covering N-layer 1201, which covers the entire N substrate layer 4.

[0036] The full coverage N-layer 1201 evenly covers the entire N substrate 4, reducing process complexity through global doping. While maintaining 90% withstand voltage capability, the number of photolithography steps is reduced, significantly improving mass production yield and reducing costs.

[0037] Example 5 like Figure 5 As shown, a doped P- layer 13 is formed inside the N substrate layer 4 and between two adjacent oxidized rectangular particles by ion implantation. The height of the cross-sectional profile of the doped P- layer 13 is lower than that of the cross-sectional profile of the oxidized rectangular particles.

[0038] By implanting a low-lying P-layer 13 between the particles in the lower buried oxide layer 10, the depletion region of the PN junction widens the electric field distribution and suppresses the electric field spikes at the edges of the oxide particles. This reduces leakage current by an order of magnitude and significantly improves breakdown voltage stability at high temperatures (175°C).

[0039] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A voltage-resistant MOSFET device with an embedded buried oxide layer, comprising a plurality of mutually parallel MOS cells, wherein each of the MOS cells comprises a drain (1), a semiconductor epitaxial layer, a source (2) and a gate (3), wherein the semiconductor epitaxial layer comprises an N substrate layer (4), an N drift layer (5), an N well layer (6), a P well layer (7) and a P+ layer (8), and is characterized in that: An upper buried oxide layer (9) is provided between two adjacent P-well layers (7) and directly below the gate (3), and the upper buried oxide layer (9) is composed of a plurality of oxide particles that are not in contact with each other; A lower buried oxide layer (10) is provided inside the N substrate layer (4) and directly below the gate (3). The lower buried oxide layer (10) is composed of three mutually non-contacting rectangular oxide particles, wherein the bottom ends of the rectangular oxide particles are in direct contact with the drain (1).

2. The voltage-withstand MOSFET device with an embedded buried oxide layer according to claim 1, wherein: The material of the upper buried oxide layer (9) and the lower buried oxide layer (10) is one of silicon dioxide and a composite material of silicon dioxide and silicon nitride.

3. The withstand voltage MOSFET device with an embedded buried oxide layer according to claim 1, wherein: The cross-sectional profile of the N substrate layer (4) close to the lower buried oxide layer (10) is in a convex shape.

4. The voltage-withstand MOSFET device with an embedded buried oxide layer according to claim 1, wherein: A side P-layer (11) is formed inside the N drift layer (5) and directly below the P+ layer (8) by ion implantation. The top of the side P-layer (11) is in direct contact with the P+ layer (8), and the bottom of the side P-layer (11) is in direct contact with the N substrate layer (4).

5. The withstand voltage MOSFET device with an embedded buried oxide layer according to claim 1, wherein: A covering N-layer (12) is provided inside the N drift layer (5) and above the raised area of ​​the N substrate layer (4).

6. The voltage-withstand MOSFET device with an embedded buried oxide layer according to claim 5, characterized in that: The cross-sectional profile of the covering N-layer (12) is arc-shaped, and the covering N-layer (12) only covers the raised area of ​​the N substrate layer (4).

7. The voltage-withstand MOSFET device with an embedded buried oxide layer according to claim 5, characterized in that: The covering N-layer (12) further includes a full covering N-layer (1201), and the full covering N-layer (1201) covers the entire N substrate layer (4).

8. The voltage-withstand MOSFET device with an embedded buried oxide layer according to claim 1, wherein: A doped P-layer (13) is formed inside the N substrate layer (4) and between two adjacent oxidized rectangular particles by ion implantation, and the height of the cross-sectional profile of the doped P-layer (13) is lower than that of the cross-sectional profile of the oxidized rectangular particles.

9. A method for preparing a MOSFET device with an embedded buried oxide layer, characterized in that: The withstand voltage MOSFET device with an embedded buried oxide layer as claimed in claim 8, wherein the method for preparing the withstand voltage MOSFET device with an embedded buried oxide layer specifically comprises: S1, forming a raised area on the surface of the N substrate layer (4) by photolithography and selective etching processes, and predefining the graphic position of the lower oxide buried layer (10) in the raised area; S2. Local oxidation or dielectric deposition is performed on the raised area of ​​the N substrate layer (4) to form three mutually non-contacting rectangular oxide particles to form a lower buried oxide layer (10), ensuring that the bottom ends of the rectangular oxide particles are in direct contact with the subsequently formed drain (1), and that semiconductor trenches are retained between the particles; S3, in the rectangular grooves between the oxide particles of the lower buried oxide layer (10), boron ions are implanted by mask control to form a doped P-layer (13) with a height lower than the oxide particles; S4, epitaxially growing an N drift layer (5) on the N substrate layer (4), and synchronously controlling epitaxial parameters so that the convex morphology of the N substrate layer (4) extends upward; S5, etching trenches between adjacent P-well regions (7), depositing silicon dioxide or a composite dielectric and etching back to form a discrete granular upper oxide buried layer (9); sequentially forming an N-well layer (6), a P-well layer (7) and a P+ layer (8) through multiple photolithography and ion implantation; S6, depositing polysilicon and patterning to form a gate (3), covering the upper buried oxide layer (9); S7. Deposit a metal layer on the front of the device and photolithographically form source (2) and gate (3) contacts, and thin the back of the substrate to prepare a drain (1) metal layer.

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