Enhanced MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) performance structure with strained silicon channel and manufacturing process thereof

Abstract

The invention discloses an enhanced MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) performance structure with a strained silicon channel and a manufacturing process of the enhanced MOSFET performance structure, and belongs to the technical field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; through the rectangular side symmetric P-layers with V-shaped notches on the two sides of the N drift layer, the contact area with the N substrate layer is enlarged, transverse electric field constraint is constructed, the short-channel effect is remarkably inhibited, scattering of carriers on the edge of a channel is reduced, and electric field concentration between a drain electrode and the channel can be relieved through a longitudinal doping gradient formed by the lightly doped N layer and the trapezoidal heavily doped N layer; and the electric field breakdown risk under the short channel is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to an enhanced MOSFET performance structure with a strained silicon channel and a manufacturing process thereof. BACKGROUND

[0002] With the rapid development of integrated circuit technology, chip manufacturing is constantly moving towards nanometer scale. In this process, it is increasingly difficult to rely solely on reducing device feature size to continue Moore's law. Short channel effects and parasitic effects are becoming increasingly prominent, which seriously restricts the further improvement of device performance. Short channel effects include speed saturation, surface scattering, drain-induced barrier lowering, drain-induced barrier punch-through, impact ionization, and hot carriers, etc. At low feature size, the parasitic effects of devices are also increasingly significant. These all have a negative impact on device performance.

[0003] The prior art (publication number: CN104576378B) discloses a MOSFET structure and a manufacturing method thereof. The method comprises: a. providing a substrate; b. forming a silicon germanium channel layer, a pseudo gate stack and a sacrificial side wall on the substrate; c. removing the silicon germanium channel layer and part of the substrate which are not covered by the pseudo gate stack and are located below both sides of the pseudo gate stack, to form a void; d. selectively epitaxially growing a first semiconductor layer on the semiconductor structure to fill the bottom and sidewall area of the void; e. removing the sacrificial side wall and filling a second semiconductor layer in the void which is not filled by the first semiconductor layer. The semiconductor structure prepared by the method can improve the carrier mobility in the channel, effectively suppress the adverse effects of short channel effects, and improve the device performance.

[0004] However, the structure of the MOSFET structure in the above-mentioned technology is relatively simple, and does not fully consider how to more effectively optimize the performance of the strained silicon channel under short channel conditions. When facing a series of problems caused by short channel effects, the structure cannot provide sufficient coping strategies, resulting in limited improvement of device performance in the short channel scenario. At the same time, the manufacturing process in the above-mentioned technology is relatively conventional. In the process of forming the strained silicon layer and the subsequent processing, there is a lack of innovative methods to reduce defect density and improve the quality of the strained silicon film. Therefore, it is difficult to ensure the formation of a strained silicon film with low defect density in the actual manufacturing process. A higher defect density often leads to an increase in leakage current during the "off" stage of the device, which seriously affects the overall performance of the device and cannot fully utilize the potential advantages of strained silicon technology. SUMMARY

[0005] Invention purposes: The purpose of the present application is to solve the problem that the structure of the prior art MOSFET structure design is relatively simple, and the performance of the strained silicon channel under the short channel condition is not fully considered; the present application also aims to solve the problem that the prior art lacks innovative methods for reducing defect density and improving the quality of the strained silicon film during the formation of the strained silicon layer and subsequent processing, which seriously affects the overall performance of the device.

[0006] Technical scheme: An enhanced MOSFET performance structure with a strained silicon channel, comprising a plurality of parallel MOS cells, each MOS cell comprising a drain, a semiconductor epitaxial layer, a source and a gate; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P+ layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; The left and right sides of the N drift layer in each MOS cell are provided with a symmetric P- layer, and the cross-sectional profile of the two symmetric P- layers is a rectangular shape with a V-shaped notch, and the bottom end of the two symmetric P- layers is in contact with the upper surface of the N substrate layer.

[0007] Furthermore, the bottom end of the lightly doped N layer is formed by ion implantation to form a heavily doped N layer, and the cross-sectional profile of the heavily doped N layer is a trapezoidal shape, and the bottom end of the heavily doped N layer is in contact with the upper surface of the N substrate layer.

[0008] Furthermore, the inside of the lightly doped N layer is formed by ion implantation to form a T-shaped P- layer, and the bottom end of the T-shaped P- layer is in contact with the upper surface of the heavily doped N layer.

[0009] Furthermore, the inside of the heavily doped N layer is formed by ion implantation to form a rectangular lightly doped N layer, and the top end of the rectangular lightly doped N layer is in contact with the bottom end of the T-shaped P- layer.

[0010] Furthermore, the inside of the heavily doped N layer and on both sides of the T-shaped P- layer are formed by ion implantation to form a heavily doped N-type half layer, and the cross-sectional profile of the heavily doped N-type half layer is a trapezoidal shape, and the opposite sides of the heavily doped N-type half layer are in contact with the N drift layer.

[0011] Furthermore, the inside left and inside right of the lightly doped N layer are formed by ion implantation to form a semi-elliptical heavily doped N-type half layer, and the opposite sides of the two semi-elliptical heavily doped N-type half layers are in contact with the N drift layer.

[0012] Furthermore, the inside of the lightly doped N layer is formed by ion implantation to form a round head columnar P- layer, and the bottom end of the round head columnar P- layer is in contact with the upper surface of the N substrate layer.

[0013] Further, the inside of the lightly doped N layer and on both sides of the round head cylinder P layer are formed with rectangular heavily doped N type half layers by ion implantation, and the bottom ends of the two rectangular heavily doped N type half layers are in contact with the upper surface of the N substrate layer.

[0014] A manufacturing process of an enhanced MOSFET performance structure with a strained silicon channel, comprising: S1, selecting high-purity single crystal silicon to prepare the N substrate layer as a device base support, and epitaxially growing the N drift layer on the N substrate layer by a chemical vapor deposition process; S2, using a photolithography technology to coat photoresist on the left and right regions of the N drift layer and expose and develop, to define a rectangular pattern region with a V-shaped notch, and using an ion implantation device to implant boron ions into the rectangular pattern region with a V-shaped notch to form the side-symmetrical P layer, and performing annealing treatment after implantation to activate impurities and repair lattice damage; S3, forming a rectangular mask pattern of the lightly doped N layer by photoresist coating, exposure and development in the middle region of the N drift layer by a photolithography technology, implanting nitrogen ions into the rectangular mask pattern region by an ion implantation process to form the lightly doped N layer, removing the photoresist after the completion of the implantation of the lightly doped N layer, and forming a trapezoidal mask pattern one at the bottom end region of the lightly doped N layer again by a photolithography technology, implanting nitrogen ions into the trapezoidal mask pattern one region to form the heavily doped N layer, and placing it into an annealing furnace after the completion of the implantation to repair lattice damage; S4, forming a T-shaped mask pattern of the T-shaped P layer by photolithography definition in the inside of the lightly doped N layer, and implanting boron ions by an ion implantation process to form the T-shaped P layer, and performing annealing treatment after implantation; S5, forming a trapezoidal mask pattern two of the heavily doped N type half layer on both sides of the T-shaped P layer by a photolithography technology, implanting nitrogen ions into the trapezoidal mask pattern two region to form the heavily doped N type half layer, and placing it into an annealing furnace after the completion of the implantation to repair lattice damage; S6, defining the regions of the P+ layer, the N well layer and the P well layer respectively by a photolithography technology, implanting boron ions for the P+ layer, implanting nitrogen ions for the N well layer, and implanting boron ions for the P well layer, and performing annealing treatment after the completion of the implantation to activate impurities and repair lattice damage; S7, finally depositing and patterning metal layers in sequence by a photolithography or sputtering process to form ohmic contact and Schottky contact of the drain, the source and the gate.

[0015] Beneficial effects: the application expands the contact area with the N substrate layer by the side-symmetrical P-layer with V-shaped notches in the shape of a rectangle on both sides of the N drift layer, constructs a lateral electric field constraint, significantly suppresses the short channel effect, reduces the scattering of carriers at the edge of the channel, the longitudinal doping gradient formed by the lightly doped N layer and the trapezoidal heavily doped N layer can alleviate the electric field concentration between the drain and the channel, avoid the risk of electric field breakdown under the short channel, through the structure of the T-shaped P-layer "lateral extension + longitudinal depth", the carrier movement range of the short channel region can be accurately limited, and the carrier mobility is further improved by cooperating with the strained silicon channel design, even under the condition of the short channel, the switching speed and current driving capability of the device can be guaranteed; The doping layers of the application are formed by ion implantation process combined with annealing treatment, the smooth profile of the semi-elliptical heavily doped N-type half layer has no obvious corners, which can avoid stress concentration and defect accumulation at the interface, reduce the defect density of the strained silicon thin film, and the rectangular lightly doped N layer buffers the doping mutation of the heavily doped N layer and the T-shaped P-layer, and the rectangular heavily doped N-type half layer is symmetrically distributed to stabilize the current conduction path, so that the interface state density can be reduced, the recombination loss of carriers at defects can be avoided, the quality of the strained silicon thin film can be significantly improved, and the stability of the device in long-term work can be guaranteed. The application does not need to introduce complex special equipment, can effectively control the production cost while improving the performance, the side-symmetrical P-layer and the heavily doped N layer are accurately defined by photolithography technology, the ion implantation parameters are easy to match with the existing production line, the process covers the conventional processes such as substrate preparation, doping and metallization, the annealing treatment and photolithography sputtering processes are mature technologies, which can be directly integrated into the existing production link, so that the high cost of equipment modification and process iteration can be avoided, and the application has stronger industrialization advantage; The overall structure of the application is synergistically optimized, which promotes the comprehensive improvement of MOSFET in key indicators such as conduction loss, withstand voltage, switching frequency, etc., the side-symmetrical P-layer and the semi-elliptical heavily doped N-type half layer are synergistically optimized to reduce the leakage current, the heavily doped N layer and the rectangular heavily doped N-type half layer reduce the contact resistance and reduce the conduction loss, the T-shaped P-layer and the round head column-shaped P-layer accurately control the threshold voltage and improve the switching stability, so that the device can realize a synergistic breakthrough in low conduction loss, high withstand voltage, high switching frequency and high reliability by cooperating with the strained silicon channel design, which far exceeds the performance level of the existing simple structure MOSFET, and can better meet the stringent application requirements in the fields of high-performance integrated circuits and power electronics. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a structure schematic diagram of embodiment 1 of the application.

[0017] Figure 2 is a structure schematic diagram of embodiment 2 of the application.

[0018] Figure 3is a structural schematic diagram of embodiment 3 of the present application.

[0019] Figure 4 is a structural schematic diagram of embodiment 4 of the present application.

[0020] Figure 5 is a structural schematic diagram of embodiment 5 of the present application.

[0021] Figure 6 is a structural schematic diagram of embodiment 6 of the present application.

[0022] Figure 7 is a structural schematic diagram of embodiment 7 of the present application.

[0023] Figure 8 is a structural schematic diagram of embodiment 8 of the present application.

[0024] In the figure: 1, drain; 2, source; 3, gate; 4, N substrate layer; 5, N drift layer; 6, P+ layer; 7, N well layer; 8, P well layer; 9, lightly doped N layer; 10, side-symmetrical P- layer; 11, heavily doped N layer; 12, T-shaped P- layer; 13, rectangular lightly doped N layer; 14, heavily doped N-type half layer; 15, semi-elliptical heavily doped N-type half layer; 16, round-head columnar P- layer; 17, rectangular heavily doped N-type half layer. DETAILED DESCRIPTION

[0025] In order to make the technical scheme of the present application clearer, the present application will be further described in detail below in combination with the drawings and specific embodiments.

[0026] As Figures 1-8 shown, according to one aspect of the present application, there is provided a manufacturing process of an enhanced MOSFET performance structure with a strained silicon channel, comprising: Step one: select high-purity single crystal silicon to prepare an N substrate layer 4 as a device base support, and grow an N drift layer 5 on the N substrate layer 4 by a chemical vapor deposition process; a device longitudinal basic structure can be constructed, the high-purity single crystal silicon N substrate layer 4 guarantees a low-defect, high-stability support base, and the epitaxially grown N drift layer 5 builds a framework for subsequent doping structures and lays a foundation for the electrical properties of the device such as voltage resistance and conduction.

[0027] Step two: using photolithography technology, the photoresist is coated on the left and right areas of the N drift layer 5, and exposed and developed to define a rectangular pattern area with V-shaped notches. Through ion implantation equipment, boron ions are implanted into the rectangular pattern area with V-shaped notches to form a side-symmetrical P-layer 10. After implantation, annealing treatment is performed to activate impurities and repair lattice damage; the preparation of the side-symmetrical P-layer 10 optimizes the lateral electric field distribution of the device. The rectangular structure with V-shaped notches cooperates with boron ion doping to suppress the short channel effect, and the annealing treatment ensures the impurity activation and lattice repair of the side-symmetrical P-layer 10, guarantees its electrical activity and crystal quality, and provides conditions for subsequent channel performance regulation.

[0028] Step three: through photolithography technology, photoresist is coated, exposed and developed in the middle area of the N drift layer 5 to form a rectangular mask pattern of the lightly doped N layer 9. Using ion implantation process, nitrogen ions are implanted into the rectangular mask pattern area to form a lightly doped N layer 9. After the completion of the implantation of the lightly doped N layer 9, the photoresist is removed, and again using photolithography technology, a trapezoidal mask pattern one is formed at the bottom end area of the lightly doped N layer 9. Nitrogen ions are implanted into the trapezoidal mask pattern one area to form a heavily doped N layer 11. After the implantation is completed, it is put into an annealing furnace to repair lattice damage; the doping gradient of the drain-channel transition region can be constructed, the lightly doped N layer can moderate the electric field concentration, the trapezoidal heavily doped N layer can reduce the drain contact resistance and optimize the longitudinal electric field, improve the device withstand voltage and switching speed, and the annealing treatment can repair the lattice damage caused by ion implantation to ensure the stable performance of the two N-type doped regions; the doping gradient of the channel transition region can be constructed, the lightly doped N layer 9 can moderate the electric field concentration, the trapezoidal heavily doped N layer 11 can reduce the drain contact resistance and optimize the longitudinal electric field, improve the device withstand voltage and switching speed, and the annealing treatment can repair the lattice damage caused by ion implantation to ensure the stable performance of the lightly doped N layer 9.

[0029] Step four: through photolithography technology, a T-shaped mask pattern of the T-shaped P-layer 12 is formed inside the lightly doped N layer 9, boron ions are implanted by ion implantation process to form a T-shaped P-layer 12, and annealing treatment is performed after implantation; the carrier environment of the channel center area is precisely regulated, the T-shaped P-layer 12 penetrates into the lightly doped N layer 9, cooperates with boron ion doping to optimize the carrier mobility of the strained silicon channel, and the annealing activates impurities and repairs the lattice to guarantee the regulation effect of the T-shaped P-layer 12 on the channel performance.

[0030] Step five: through photolithography technology, a trapezoidal mask pattern two of the heavily doped N-type half layer 14 is formed on both sides of the T-shaped P-layer 12, nitrogen ions are implanted into the trapezoidal mask pattern two area to form a heavily doped N-type half layer 14, and after the implantation is completed, it is put into an annealing furnace to repair lattice damage; the electrical properties of both sides of the T-shaped P-layer 12 can be balanced, the trapezoidal heavily doped N-type half layer 14 fills the space on both sides to avoid electric field abrupt change, suppress edge effect, ensure uniform carrier movement in the channel, and the annealing treatment guarantees the doping activity and crystal integrity.

[0031] Step six: define the area of P+ layer 6, N well layer 7 and P well layer 8 by photolithography technology, for P+ layer 6, boron ion implantation is adopted, for N well layer 7, nitrogen ion implantation is adopted, and for P well layer 8, boron ion implantation is adopted, after implantation, annealing treatment is carried out to activate impurities and repair lattice damage; the core functional area of the device can be divided, P+ layer 6 provides low resistance contact to optimize the conductivity of source 2, N well layer 7 and P well layer 8 define the active area through different types of doping, and the gate 3 controls the channel formation, the annealing treatment activates the impurities of each layer, and ensures that the electrical performance of the functional area meets the standard.

[0032] Step seven: finally, through photolithography or sputtering process, metal layer is deposited and patterned in sequence to form ohmic contact and Schottky contact of drain 1, source 2 and gate 3; realize the electrical connection of the device and the external circuit, the metal layer is patterned to build drain 1, source 2 and gate 3, ohmic contact ensures low resistance conduction, and Schottky contact ensures the effective control of gate 3 to the channel, completes the functional closure of the device, so that it can normally play the role of switch. Example 1

[0033] As shown in Figure 1 , an enhanced MOSFET performance structure with strained silicon channel is provided, which is composed of a plurality of parallel MOS cells, and a single MOS cell includes drain 1, semiconductor epitaxial layer, source 2 and gate 3; the semiconductor epitaxial layer includes N substrate layer 4, N drift layer 5, P+ layer 6, N well layer 7 and P well layer 8, and a lightly doped N layer 9 is arranged in the middle of the N drift layer 5 of a single MOS cell; a side-symmetrical P- layer 10 is arranged inside the single MOS cell and located on the left and right sides of the N drift layer 5, the cross-sectional profile of the two side-symmetrical P- layers 10 is rectangular with V-shaped notches, and the bottom ends of the two side-symmetrical P- layers 10 are in contact with the upper surface of the N substrate layer 4; The overall structure composed of a plurality of mutually juxtaposed MOS cells can improve the overall current carrying capacity of the device by cell parallel connection, meet the demand of high power application scenarios, in a single MOS cell, the lightly doped N layer 9 arranged in the middle of the N drift layer 5 can effectively alleviate the electric field concentration between the drain 1 and the channel, reduce the on-resistance of the device while improving the withstand voltage performance, avoid the risk of electric field breakdown under high voltage, the side-symmetrical P-layer 10 arranged on the left and right sides of the N drift layer 5 has a V-shaped notch rectangular cross-sectional profile, which not only increases the contact area with the N substrate layer 4, ensures the stability of current conduction between the N substrate layer 4 and the side-symmetrical P-layer 10, but also forms an electric field constraint with the surrounding N-type region through P-type doping, significantly suppresses the short channel effect, reduces the scattering of carriers at the edge of the channel, further improves the carrier mobility with the strained silicon channel design, speeds up the switching speed of the device, and the bottom ends of the two side-symmetrical P-layers 10 are in contact with the upper surface of the N substrate layer 4, which builds a more reasonable longitudinal doping gradient, optimizes the potential distribution in the device, reduces the leakage current, and improves the reliability of the device in the "off" state. Meanwhile, the P+ layer 6 in the semiconductor epitaxial layer can form a low-resistance ohmic contact with the source 2, reducing the contact loss of the source 2, and the N well layer 7 and the P well layer 8 can accurately define the channel region, ensuring that the enhancement mode MOSFET stably forms a conductive channel under the voltage control of the gate 3, realizing effective regulation of the current, without the need to introduce complex special equipment, reducing production costs, and ultimately achieving synergistic improvement in low on-resistance, high switching frequency, high withstand voltage and high reliability of the MOSFET, which is suitable for high-performance integrated circuits, power electronics and other fields with strict requirements on device performance. Embodiment 2

[0034] As shown in Figure 2 the bottom end of the lightly doped N layer 9 is formed with a heavily doped N layer 11 by ion implantation, the cross-sectional profile of the heavily doped N layer 11 is trapezoidal, and the bottom end of the heavily doped N layer 11 is in contact with the upper surface of the N substrate layer 4; The high-doping characteristic of the heavily doped N layer 11 can significantly reduce the contact resistance between the lightly doped N layer 9 and the N substrate layer 4, reduce the loss of current during longitudinal conduction, and improve the overall on-state efficiency of the device, while the trapezoidal cross-sectional shape can increase the contact area of the heavily doped N layer 11 with the lightly doped N layer 9 and the N substrate layer 4, further optimize the current conduction path, and avoid the problem of overheating caused by excessive local current density. Secondly, the longitudinal doping gradient formed by the heavily doped N layer 11 and the lightly doped N layer 9 can cooperatively alleviate the electric field concentration phenomenon between the drain 1 and the channel, further improve the withstand voltage performance of the device in cooperation with the electric field regulation effect of the N drift layer 5, effectively prevent the risk of electric field breakdown under high voltage conditions, and the trapezoidal structure can guide the electric field to be more uniformly distributed inside the device, reducing the probability of leakage current generation. Embodiment 3

[0035] As shown in Figure 3 the inner part of the lightly doped N layer 9 is formed with a T-shaped P-layer 12 by ion implantation, the bottom end of the T-shaped P-layer 12 is in contact with the upper surface of the heavily doped N layer 11; The profile of the T-shaped P-layer 12 forms a "lateral extension + longitudinal depth" distribution inside the lightly doped N layer 9, the lateral part can expand the action range with the surrounding area, more accurately constrain the carrier movement in the channel region, reduce the carrier scattering at the edge of the channel, further improve the carrier mobility with the strained silicon channel design, speed up the device switching speed, the longitudinal part bottom end is in contact with the upper surface of the heavily doped N layer 11, which can build a stable potential anchor point, avoid the electric field distortion at the interface between the lightly doped N layer 9 and the heavily doped N layer 11 due to the sudden change of doping concentration, optimize the potential distribution in the device body, at the same time, the P-type doping of the T-shaped P-layer 12 and the N-type doping of the lightly doped N layer 9 form a PN junction effect, which can effectively suppress the short channel effect and reduce the punch-through current between the drain 1 and the source 2. In addition, the T-shaped P-layer 12 is formed by ion implantation process, which is tightly combined with the interface of the lightly doped N layer 9 and the heavily doped N layer 11 without additional gap defects, which can reduce the interface state density, reduce the carrier recombination loss at the interface, improve the current driving capability of the device, and at the same time, its structure is compatible with the existing photolithography and ion implantation process without the need to introduce special manufacturing equipment, which can optimize the performance while controlling the production cost, and finally help the MOSFET to realize the synergistic improvement in low leakage current, high switching frequency and high reliability, which is more suitable for high-performance integrated circuits, power electronics and other application scenarios with high requirements for device precision and stability. Embodiment 4

[0036] As shown in Figure 4 the inner part of the heavily doped N layer 11 is formed with a rectangular lightly doped N layer 13 by ion implantation, the top end of the rectangular lightly doped N layer 13 is in contact with the bottom end of the T-shaped P-layer 12; The rectangular lightly doped N layer 13 is located inside the heavily doped N layer 11 and in contact with the bottom end of the T-shaped P-layer 12, forming a longitudinal doping gradient structure of the heavily doped N layer 11-rectangular lightly doped N layer 13-T-shaped P-layer 12. Through gradient design, the sudden change of doping concentration between the heavily doped N layer 11 and the T-shaped P-layer 12 can be buffered, the electric field concentration at the interface can be effectively alleviated, the carrier scattering caused by the sudden change of electric field can be reduced, and the carrier migration efficiency in the channel region can be improved, which further enhances the current driving capability of the device in cooperation with the strained silicon channel design. Embodiment 5

[0037] As shown in Figure 5As shown, heavily doped N-type half layers 14 are formed inside the heavily doped N layer 11 and on both sides of the T-shaped P-layer 12 by ion implantation. The cross-sectional profiles of the heavily doped N-type half layers 14 are all trapezoidal, and the opposite sides of the heavily doped N-type half layers 14 are in contact with the N drift layer 5. The trapezoidal cross-sectional profile enables the heavily doped N-type half-layer 14 to form a "gradual" doping transition on both sides of the T-shaped P-layer 12. This not only avoids electric field distortion caused by sudden changes in doping type or concentration between the T-shaped P-layer 12 and the heavily doped N-layer 11 and N-drift layer 5, but also guides the electric field uniformly through the trapezoidal slope, effectively alleviating the electric field concentration between the drain 1 and the channel, further improving the device's withstand voltage performance and reducing the risk of breakdown under high voltage. At the same time, the heavily doped N-type half-layer 14 is located on both sides of the T-shaped P-layer 12 and contacts the N-drift layer 5 on its opposite sides, forming a "conductive bridge" between the T-shaped P-layer 12 and the N-drift layer 5. This optimizes the current conduction path between the heavily doped N-layer 11 and the N-drift layer 5, reduces local impedance during current conduction, and reduces device conduction losses. At the same time, its heavily doped nature enhances carrier transport efficiency and, combined with the strained silicon channel design, further improves the device's current driving capability. Example 6

[0038] like Figure 6 As shown, a semi-elliptical heavily doped N-type half layer 15 is formed on both the inner left side and the inner right side of the lightly doped N-type layer 9 by ion implantation, and the opposite sides of the two semi-elliptical heavily doped N-type half layers 15 are in contact with the N-drift layer 5; The semi-elliptical cross-sectional profile creates a "smooth transition" doping region between the lightly doped N layer 9 and the N-drift layer 5, effectively mitigating the sudden doping concentration gradient between the lightly doped N layer 9, the semi-elliptical heavily doped N-type half layer 15, and the N-drift layer 5. This avoids electric field concentration at the interface and reduces carrier scattering caused by electric field distortion. Combined with the strained silicon channel design, this further improves carrier mobility and accelerates device switching response. Furthermore, the semi-elliptical heavily doped N-type half layers 15 are located on both sides of the lightly doped N layer 9, with their opposite sides contacting the N-drift layer 5, creating a "low-resistance conduction path" between the lightly doped N layer 9 and the N-drift layer 5. The high doping characteristics of the semi-elliptical structure significantly reduce the contact resistance and path impedance of current conduction between the two layers, thereby reducing conduction losses. Furthermore, the curved edges of the semi-elliptical structure expand the contact area with the lightly doped N layer 9 and the N-drift layer 5, optimizing current distribution, avoiding local overheating of the device caused by excessive local current density, and improving long-term operational stability. Example 7

[0039] like Figure 7 As shown, a round-headed cylindrical P-layer 16 is formed inside the lightly doped N-layer 9 by ion implantation, and the bottom end of the round-headed cylindrical P-layer 16 contacts the upper surface of the N substrate layer 4; The round-headed cylindrical profile makes the top of the P-layer 16 free of sharp corners, which can avoid the electric field concentration caused by structural mutations in the lightly doped N layer 9, reduce the scattering of carriers in this area, and further improve the carrier mobility in conjunction with the strained silicon channel design. At the same time, the cylindrical part can penetrate deep into the lightly doped N layer 9, expand the range of action with the surrounding N-type region, more accurately constrain the movement of channel carriers, enhance the ability to regulate the device threshold voltage, and ensure that the enhancement MOSFET can achieve stable conduction and shutdown under the control of the gate 3. At the same time, the bottom end of the round-headed cylindrical P-layer 16 contacts the upper surface of the N substrate layer 4, constructing a vertical P-type doping path from the N substrate layer 4 to the lightly doped N layer 9. It can effectively suppress the short channel effect and the punch-through current between the drain 1 and the source 2 through the PN junction effect formed with the surrounding N-type region, reduce the leakage current in the off state of the device, and improve reliability. Example 8

[0040] like Figure 8 As shown, rectangular heavily doped N-type half layers 17 are formed inside the lightly doped N layer 9 and on both sides of the round-headed cylindrical P-layer 16 by ion implantation. The bottom ends of the two rectangular heavily doped N-type half layers 17 are in contact with the upper surface of the N substrate layer 4. Through the high doping characteristics and symmetrical distribution of the rectangular heavily doped N-type half layer 17, a low-resistance longitudinal conduction path can be constructed on both sides of the cylindrical P-layer 16. The bottom end of the rectangular heavily doped N-type half layer 17 contacts the upper surface of the N substrate layer 4, which can enhance the longitudinal conduction efficiency of the current between the lightly doped N layer 9 and the N substrate layer 4, and reduce the conduction loss. At the same time, the regular boundary of the rectangular structure can accurately limit the current conduction range, avoid the disordered diffusion of carriers in the two side areas, and further improve the carrier mobility with the strained silicon channel design, speeding up the switching speed of the device. At the same time, the rectangular heavily doped N-type half layer 17 forms a coordinated doping gradient with the cylindrical P-layer 16 and the lightly doped N layer 9, which can alleviate the cylindrical The electric field is concentrated at the interface between the bulk P-layer 16 and the lightly doped N-layer 9, avoiding electric field distortion caused by a sudden change in doping type and reducing leakage current. At the same time, the symmetrical structure can make the potential distribution in the device more uniform, effectively suppress the short channel effect, and improve the switching stability of the enhancement MOSFET under the control of the gate 3. At the same time, the rectangular heavily doped N-type half layer 17 is formed by an ion implantation process. The rectangular outline can be easily controlled precisely through a photolithography mask. It is tightly bonded to the interface of the lightly doped N-layer 9, the round-headed cylindrical P-layer 16, and the N substrate layer 4 without additional gap defects, which can reduce the interface state density, reduce the carrier recombination loss at the interface, and ensure the current driving capability.

[0041] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, several modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. An enhancement-mode MOSFET performance structure with a strained silicon channel, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain (1), a semiconductor epitaxial layer, a source (2) and a gate (3); the semiconductor epitaxial layer comprises an N substrate layer (4), an N drift layer (5), a P+ layer (6), an N well layer (7) and a P well layer (8), characterized in that: A lightly doped N layer (9) is provided in the middle of the N drift layer (5) of a single MOS cell; A lateral symmetrical P-layer (10) is provided inside a single MOS cell and on the left and right sides of the N drift layer (5); the cross-sectional profiles of the two lateral symmetrical P-layers (10) are both rectangular with a V-shaped notch; and the bottom ends of the two lateral symmetrical P-layers (10) are in contact with the upper surface of the N substrate layer (4).

2. The enhancement mode MOSFET performance structure with strained silicon channel according to claim 1, characterized in that: The bottom end of the lightly doped N layer (9) is formed with a heavily doped N layer (11) by ion implantation, the cross-sectional profile of the heavily doped N layer (11) is a trapezoidal shape, and the bottom end of the heavily doped N layer (11) is in contact with the upper surface of the N substrate layer (4).

3. The enhancement mode MOSFET performance structure with strained silicon channel according to claim 2, characterized in that: A T-shaped P-layer (12) is formed inside the lightly doped N layer (9) by ion implantation, and the bottom end of the T-shaped P-layer (12) contacts the upper surface of the heavily doped N layer (11).

4. The enhancement mode MOSFET structure with strained silicon channel according to claim 3, characterized in that: A rectangular lightly doped N layer (13) is formed inside the heavily doped N layer (11) by ion implantation, and the top of the rectangular lightly doped N layer (13) is in contact with the bottom of the T-shaped P-layer (12).

5. The enhancement mode MOSFET performance structure with strained silicon channel according to claim 3, characterized in that: A heavily doped N-type half layer (14) is formed inside the heavily doped N layer (11) and on both sides of the T-shaped P-layer (12) by ion implantation. The cross-sectional profile of the heavily doped N-type half layer (14) is a trapezoidal shape, and the opposite sides of the heavily doped N-type half layer (14) are in contact with the N drift layer (5).

6. The enhancement mode MOSFET performance structure with strained silicon channel according to claim 1, characterized in that: A semi-elliptical heavily doped N-type half layer (15) is formed on the inner left side and the inner right side of the lightly doped N layer (9) by ion implantation, and the opposite sides of the two semi-elliptical heavily doped N-type half layers (15) are in contact with the N drift layer (5).

7. The enhancement mode MOSFET performance structure with strained silicon channel according to claim 1, characterized in that: A round-headed cylindrical P-layer (16) is formed inside the lightly doped N layer (9) by ion implantation, and the bottom end of the round-headed cylindrical P-layer (16) is in contact with the upper surface of the N substrate layer (4).

8. The enhancement mode MOSFET performance structure with strained silicon channel according to claim 7, characterized in that: A rectangular heavily doped N-type half layer (17) is formed inside the lightly doped N layer (9) and on both sides of the round-headed cylindrical P-layer (16) by ion implantation, and the bottom ends of the two rectangular heavily doped N-type half layers (17) are in contact with the upper surface of the N substrate layer (4).

9. A process for manufacturing an enhancement mode MOSFET performance structure with a strained silicon channel, characterized in that: An enhancement mode MOSFET performance structure having a strained silicon channel according to any one of claims 1 to 5, comprising the following steps: S1, selecting high-purity single crystal silicon to prepare the N substrate layer (4) as a basic support for the device, and epitaxially growing the N drift layer (5) on the N substrate layer (4) through a chemical vapor deposition process; S2. Using photolithography technology, coating photoresist on the left and right areas of the N drift layer (5), exposing and developing, defining a rectangular pattern area with a V-shaped notch, and injecting boron ions into the rectangular pattern area with the V-shaped notch through ion implantation equipment to form the side-symmetrical P-layer (10), and performing annealing after the implantation to activate impurities and repair lattice damage; S3, coating, exposing and developing a photoresist in the middle area of ​​the N drift layer (5) by photolithography technology to form a rectangular mask pattern of the lightly doped N layer (9), and using an ion implantation process to implant nitrogen ions into the rectangular mask pattern area to form the lightly doped N layer (9). After the implantation of the lightly doped N layer (9), the photoresist is removed, and photolithography technology is used again to form a trapezoidal mask pattern 1 in the bottom area of ​​the lightly doped N layer (9). Nitrogen ions are implanted into the trapezoidal mask pattern 1 area to form the heavily doped N layer (11). After the implantation is completed, the heavily doped N layer (11) is placed in an annealing furnace to repair lattice damage. S4, using a photolithography technique to define a T-shaped mask pattern for forming the T-shaped P-layer (12) inside the lightly doped N-layer (9), implanting boron ions using an ion implantation process to form the T-shaped P-layer (12), and performing an annealing treatment after the implantation; S5, forming a second trapezoidal mask pattern of the heavily doped N-type half layer (14) on both sides of the T-shaped P-layer (12) by photolithography technology, implanting nitrogen ions into the second trapezoidal mask pattern region to form the heavily doped N-type half layer (14), and placing the layer in an annealing furnace after the implantation is completed to repair lattice damage; S6. Using photolithography technology, the regions of the P+ layer (6), the N-well layer (7), and the P-well layer (8) are respectively defined. For the P+ layer (6), boron ion implantation is performed. For the N-well layer (7), nitrogen ion implantation is performed. For the P-well layer (8), boron ion implantation is performed. After the implantation is completed, annealing treatment is performed to activate impurities and repair lattice damage. S7. Finally, by photolithography or sputtering process, metal layers are sequentially deposited and patterned to form ohmic contacts and Schottky contacts of the drain (1), the source (2) and the gate (3).

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