An enhancement-mode MOSFET structure with strained silicon channel and its fabrication process

Abstract

This invention discloses an enhancement-mode MOSFET structure with strained silicon channel and its manufacturing process, belonging to the field of semiconductor technology. It comprises several parallel MOSFET cells, each including a drain, a semiconductor epitaxial layer, a source, and a gate. The semiconductor epitaxial layer includes an N-substrate layer, an N-drift layer, a P+ layer, an N-well layer, and a P-well layer. A lightly doped N-layer is disposed in the middle of the N-drift layer of each MOSFET cell. This invention expands the contact area with the N-substrate layer by using rectangular, side-symmetric P-layers with V-shaped notches on both sides of the N-drift layer, thus constructing a lateral electric field constraint, significantly suppressing the short-channel effect, reducing carrier scattering at the channel edge, and mitigating the electric field concentration between the drain and the channel by the vertical doping gradient formed by the lightly doped N-layer and the trapezoidal heavily doped N-layer, avoiding the risk of electric field breakdown under short-channel conditions.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an enhancement MOSFET structure with strained silicon channel and its manufacturing process. Background Technology

[0002] With the rapid development of integrated circuit technology, chip manufacturing processes are constantly moving towards the nanoscale. In this process, it is becoming increasingly difficult to continue Moore's Law by simply shrinking the feature size of devices. Problems such as short-channel effect and parasitic effect are becoming increasingly prominent, which seriously restricts the further improvement of device performance. The short-channel effect encompasses a variety of phenomena such as velocity saturation, surface scattering, drain-induced barrier reduction, drain-induced barrier punching, impact ionization, and hot carriers. At low feature sizes, the parasitic effect of devices is also becoming more and more significant, all of which have a negative impact on device performance.

[0003] A prior art MOSFET structure and its manufacturing method are disclosed in the present invention (publication number: CN104576378B). The method includes: a. providing a substrate; b. forming a silicon-germanium channel layer, a dummy gate stack, and sacrificial sidewalls on the substrate; c. removing the silicon-germanium channel layer and part of the substrate not covered by the dummy gate stack and located below both sides of the dummy gate stack to form vacancies; d. selectively epitaxially growing a first semiconductor layer on the semiconductor structure to fill the bottom and sidewall regions of the vacancies; e. removing the sacrificial sidewalls and filling the vacancies not filled by the first semiconductor layer with a second semiconductor layer. The semiconductor structure prepared by this invention can improve the carrier mobility in the channel, effectively suppress the adverse effects of the short-channel effect, and improve device performance.

[0004] However, the MOSFET structure design in the above technologies is relatively simple and fails to fully consider how to more effectively optimize the performance of strained silicon channels under short-channel conditions. When faced with a series of problems caused by the short-channel effect, its structure cannot provide sufficient coping strategies, resulting in limited improvement in device performance in short-channel scenarios. At the same time, the manufacturing process in the above technologies is relatively conventional. In the process of forming the strained silicon layer and subsequent processing, there is a lack of innovative methods to reduce defect density and improve the quality of strained silicon films. As a result, it is difficult to ensure the formation of strained silicon films with low defect density in actual manufacturing. Higher defect density often leads to increased leakage current in the "turn-off" stage of the device, which seriously affects the overall performance of the device and fails to fully realize the potential advantages of strained silicon technology. Summary of the Invention

[0005] Purpose of the Invention: The purpose of this invention is to provide a solution to the problem that the existing MOSFET structure design is relatively simple and fails to fully consider how to more effectively optimize the performance of strained silicon channels under short-channel conditions. Another purpose of this invention is to provide a solution to the problem that the existing technology lacks innovative methods for reducing defect density and improving the quality of strained silicon films during the formation of strained silicon layers and subsequent processing, which seriously affects the overall performance of the device.

[0006] Technical solution: An enhancement MOSFET structure with strained silicon channel, comprising a plurality of parallel MOS cells, each MOS cell including a drain, a semiconductor epitaxial layer, a source, and a gate; the semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a P+ layer, an N well layer, and a P well layer, wherein a lightly doped N layer is provided in the middle of the N drift layer of each MOS cell;

[0007] A laterally symmetrical P-layer is disposed inside a single MOS cell and on the left and right sides of the N drift layer. The cross-sectional profile of the two laterally symmetrical P-layers is rectangular with a V-shaped notch, and the bottom ends of the two laterally symmetrical P-layers are in contact with the upper surface of the N substrate layer.

[0008] Furthermore, a heavily doped N layer is formed at the bottom of the lightly doped N layer by ion implantation. The cross-sectional profile of the heavily doped N layer is trapezoidal, and the bottom of the heavily doped N layer is in contact with the upper surface of the N substrate.

[0009] Furthermore, a T-shaped P-layer is formed inside the lightly doped N-layer by ion implantation, and the bottom end of the T-shaped P-layer is in contact with the upper surface of the heavily doped N-layer.

[0010] Furthermore, a rectangular lightly doped N layer is formed inside the heavily doped N layer by ion implantation, and the top end of the rectangular lightly doped N layer contacts the bottom end of the T-shaped P-layer.

[0011] Furthermore, within the lightly doped N-layer and on both sides of the T-shaped P-layer, a heavily doped N-type half-layer is formed by ion implantation. The cross-sectional profile of the heavily doped N-type half-layer is trapezoidal, and the opposite side of the heavily doped N-type half-layer is in contact with the N-drift layer.

[0012] Furthermore, the inner left and inner right sides of the lightly doped N layer are both formed with semi-elliptical heavily doped N-type half-layers by ion implantation, and the opposite sides of the two semi-elliptical heavily doped N-type half-layers are in contact with the N drift layer.

[0013] Furthermore, a cylindrical P-layer is formed inside the lightly doped N-layer by ion implantation, and the bottom end of the cylindrical P-layer is in contact with the upper surface of the N-substrate layer.

[0014] Furthermore, rectangular heavily doped N-type half-layers are formed inside the lightly doped N-layer and on both sides of the cylindrical P-layer by ion implantation, and the bottom ends of the two rectangular heavily doped N-type half-layers are in contact with the upper surface of the N substrate layer.

[0015] A fabrication process for an enhancement-mode MOSFET structure with a strained silicon channel includes:

[0016] S1. Select high-purity single-crystal silicon to prepare the N substrate layer as the basic support for the device, and epitaxially grow the N drift layer on the N substrate layer by chemical vapor deposition process;

[0017] S2. Using photolithography, photoresist is coated on the left and right sides of the N-drift layer and exposed and developed to define a rectangular patterned area with a V-shaped notch. Boron ions are implanted into the rectangular patterned area with the V-shaped notch using an ion implantation device to form the side-symmetric P-layer. After implantation, annealing is performed to activate impurities and repair lattice damage.

[0018] S3. Photoresist is coated, exposed, and developed in the middle region of the N drift layer using photolithography to form a rectangular mask pattern of the lightly doped N layer. Nitrogen ions are implanted into the rectangular mask pattern region using ion implantation to form the lightly doped N layer. After the lightly doped N layer implantation is completed, the photoresist is removed, and a trapezoidal mask pattern is formed again in the bottom region of the lightly doped N layer using photolithography. Nitrogen ions are implanted into the trapezoidal mask pattern region to form the heavily doped N layer. After implantation, the layer is placed in an annealing furnace to repair lattice damage.

[0019] S4. A T-shaped mask pattern of the T-shaped P-layer is defined and formed inside the lightly doped N-layer by photolithography. Boron ions are implanted by ion implantation process to form the T-shaped P-layer. Annealing is performed after implantation.

[0020] S5. A trapezoidal mask pattern two of the heavily doped N-type half-layer is formed on both sides of the T-shaped P-layer using photolithography. Nitrogen ions are implanted into the area of ​​the trapezoidal mask pattern two to form the heavily doped N-type half-layer. After implantation, the layer is placed in an annealing furnace to repair lattice damage.

[0021] S6. Define the regions of the P+ layer, the N-well layer and the P-well layer respectively using photolithography. For the P+ layer, boron ion implantation is used; for the N-well layer, nitrogen ion implantation is used; and for the P-well layer, boron ion implantation is used. After implantation, perform annealing to activate impurities and repair lattice damage.

[0022] S7. Finally, metal layers are deposited and patterned sequentially using photolithography or sputtering processes to form ohmic and Schottky contacts for the drain, source, and gate.

[0023] Beneficial effects: This invention expands the contact area with the N substrate by using rectangular laterally symmetrical P-layers with V-shaped notches on both sides of the N drift layer, thereby constructing a lateral electric field constraint, significantly suppressing the short-channel effect, reducing carrier scattering at the channel edge, and mitigating the electric field concentration between the drain and the channel by the vertical doping gradient formed by the lightly doped N layer and the trapezoidal heavily doped N layer, thus avoiding the risk of electric field breakdown under short channels. The "lateral extension + vertical penetration" structure of the T-shaped P-layer can precisely limit the carrier movement range in the short channel region. Combined with the strained silicon channel design, it further improves the carrier mobility, ensuring the device switching speed and current drive capability even under short-channel conditions.

[0024] In this invention, each doped layer is formed by ion implantation combined with annealing. The smooth contour of the semi-elliptical heavily doped N-type half-layer has no obvious sharp corners, which can avoid stress concentration and defect accumulation at the interface and reduce the defect density of the strained silicon film. At the same time, the rectangular lightly doped N-layer buffers the doping abrupt change between the heavily doped N-layer and the T-shaped P-layer. The symmetrical distribution of the rectangular heavily doped N-type half-layer stabilizes the current conduction path, thereby reducing the interface state density, avoiding recombination loss of charge carriers at defects, significantly improving the quality of the strained silicon film, and thus ensuring the stability of the device in long-term operation.

[0025] This invention does not require the introduction of complex and special equipment, and effectively controls mass production costs while improving performance. The patterns are precisely defined by photolithography through side-symmetric P-layers and heavily doped N-layers. The ion implantation parameters are easy to match with existing production lines. The process covers conventional processes such as substrate preparation, doping, and metallization. The annealing and photolithography sputtering processes are mature technologies that can be directly integrated into existing mass production processes, thus avoiding the high costs of equipment modification and process iteration, and having stronger advantages for industrial application.

[0026] The synergistic optimization of the various structures in this invention comprehensively improves the key performance indicators of MOSFETs, such as conduction loss, breakdown voltage, and switching frequency. The laterally symmetrical P-layer and the semi-elliptical heavily doped N-type half-layer synergistically optimize the electric field distribution, reducing leakage current. The heavily doped N-layer and the rectangular heavily doped N-type half-layer reduce contact resistance, thus lowering conduction loss. The T-shaped P-layer and the rounded cylindrical P-layer precisely control the threshold voltage, improving switching stability. Combined with the strained silicon channel design, this ultimately enables the device to achieve a synergistic breakthrough in low conduction loss, high breakdown voltage, high switching frequency, and high reliability, far exceeding the performance level of existing simple structure MOSFETs. It can better meet the stringent application requirements of high-performance integrated circuits, power electronics, and other fields. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of Embodiment 1 of the present invention;

[0028] Figure 2 This is a schematic diagram of the structure of Embodiment 2 of the present invention;

[0029] Figure 3 This is a schematic diagram of the structure of Embodiment 3 of the present invention;

[0030] Figure 4 This is a schematic diagram of the structure of Embodiment 4 of the present invention;

[0031] Figure 5 This is a structural schematic diagram of Embodiment 5 of the present invention;

[0032] Figure 6 This is a schematic diagram of the structure of Embodiment 6 of the present invention;

[0033] Figure 7 This is a schematic diagram of the structure of Embodiment 7 of the present invention;

[0034] Figure 8 This is a schematic diagram of the structure of Embodiment 8 of the present invention.

[0035] In the figure: 1. Drain; 2. Source; 3. Gate; 4. N-substrate layer; 5. N-drift layer; 6. P+ layer; 7. N-well layer; 8. P-well layer; 9. Lightly doped N-layer; 10. Laterally symmetric P-layer; 11. Heavily doped N-layer; 12. T-shaped P-layer; 13. Rectangular lightly doped N-layer; 14. Heavily doped N-type half-layer; 15. Semi-elliptical heavily doped N-type half-layer; 16. Round-headed cylindrical P-layer; 17. Rectangular heavily doped N-type half-layer. Detailed Implementation

[0036] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] like Figure 1-8 As shown, according to one aspect of the present invention, a manufacturing process for an enhancement-mode MOSFET structure with a strained silicon channel is provided, comprising:

[0038] Step 1: Select high-purity single-crystal silicon to prepare N substrate layer 4 as the basic support for the device. Through chemical vapor deposition, an N drift layer 5 is epitaxially grown on the N substrate layer 4. This can construct the vertical basic structure of the device. The high-purity single-crystal silicon N substrate layer 4 ensures a low-defect, high-stability support substrate, while the epitaxially grown N drift layer 5 provides a framework for subsequent doping structures, laying the foundation for the device's electrical performance such as voltage withstand and conduction.

[0039] Step 2: Using photolithography, photoresist is coated on the left and right sides of the N-drift layer 5, and then exposed and developed to define a rectangular patterned region with a V-shaped notch. Boron ions are implanted into the rectangular patterned region with the V-shaped notch using an ion implantation device to form a side-symmetric P-layer 10. After implantation, annealing is performed to activate impurities and repair lattice damage. The fabrication of the side-symmetric P-layer 10 optimizes the lateral electric field distribution of the device. The rectangular structure with the V-shaped notch and boron ion doping work together to suppress the short-channel effect. At the same time, the annealing process ensures the activation of impurities and lattice repair in the side-symmetric P-layer 10, guaranteeing its electrical activity and crystal quality, and providing conditions for subsequent channel performance regulation.

[0040] Step 3: Photoresist is coated, exposed, and developed in the middle region of the N-drift layer 5 using photolithography to form a rectangular mask pattern of a lightly doped N-layer 9. Nitrogen ions are then implanted into the rectangular mask pattern area using ion implantation to form the lightly doped N-layer 9. After implantation of the lightly doped N-layer 9, the photoresist is removed, and a trapezoidal mask pattern is formed again at the bottom region of the lightly doped N-layer 9 using photolithography. Nitrogen ions are then implanted into the trapezoidal mask pattern area to form the heavily doped N-layer 11. After implantation, the layer is placed in an annealing furnace to repair lattice damage; this process can construct a drain-channel structure. The doping gradient in the channel transition region is achieved by using a lightly doped N-layer to mitigate electric field concentration, and a trapezoidal heavily doped N-layer to reduce drain contact resistance and optimize the longitudinal electric field, thereby improving device breakdown voltage and switching speed. Annealing treatment repairs lattice damage caused by ion implantation, ensuring the performance stability of the two N-type doped regions.

[0041] Step 4: A T-shaped mask pattern of a T-shaped P-layer 12 is defined inside the lightly doped N-layer 9 using photolithography. Boron ions are implanted using an ion implantation process to form the T-shaped P-layer 12. After implantation, annealing is performed. The carrier environment in the central region of the channel is precisely controlled. The T-shaped P-layer 12 penetrates deep into the lightly doped N-layer 9. The carrier mobility of the strained silicon channel is optimized by boron ion doping. Annealing activates impurities and repairs the lattice, ensuring the regulatory effect of the T-shaped P-layer 12 on the channel performance.

[0042] Step 5: Using photolithography, a trapezoidal mask pattern 2 of heavily doped N-type half-layer 14 is formed on both sides of the T-shaped P-layer 12. Nitrogen ions are implanted into the area of ​​the trapezoidal mask pattern 2 to form the heavily doped N-type half-layer 14. After implantation, the layer is placed in an annealing furnace to repair lattice damage. This process balances the electrical characteristics on both sides of the T-shaped P-layer 12. The trapezoidal heavily doped N-type half-layer 14 fills the space on both sides, avoiding abrupt changes in the electric field, suppressing edge effects, and ensuring uniform carrier movement in the channel. Annealing ensures its doping activity and crystal integrity.

[0043] Step Six: Define the regions of P+ layer 6, N-well layer 7, and P-well layer 8 using photolithography. Boron ion implantation is used for P+ layer 6, nitrogen ion implantation for N-well layer 7, and boron ion implantation for P-well layer 8. After implantation, annealing is performed to activate impurities and repair lattice damage. The core functional area of ​​the device can be divided. P+ layer 6 provides low-resistance contacts to optimize the conductivity of source 2. N-well layer 7 and P-well layer 8 define active regions through different types of doping, which work together with gate 3 to control channel formation. Annealing activates impurities in each layer to ensure that the electrical performance of the functional areas meets the standards.

[0044] Step 7: Finally, through photolithography or sputtering, metal layers are deposited and patterned sequentially to form ohmic and Schottky contacts for drain 1, source 2, and gate 3; this achieves the electrical connection between the device and external circuits. The metal layer patterning constructs drain 1, source 2, and gate 3, the ohmic contacts ensure low-resistance conduction, and the Schottky contacts ensure effective control of the channel by gate 3, thus completing the device's functional closure and enabling it to function as a switch.

[0045] Example 1

[0046] like Figure 1 As shown, an enhancement-mode MOSFET structure with strained silicon channel is provided, comprising a plurality of parallel MOS cells. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 2, and a gate 3. The semiconductor epitaxial layer includes an N substrate layer 4, an N drift layer 5, a P+ layer 6, an N well layer 7, and a P well layer 8. A lightly doped N layer 9 is provided in the middle of the N drift layer 5 of each MOS cell. Laterally symmetrical P-layers 10 are provided inside each MOS cell and on the left and right sides of the N drift layer 5. The cross-sectional profile of the two laterally symmetrical P-layers 10 is rectangular with a V-shaped notch, and the bottom ends of the two laterally symmetrical P-layers 10 are in contact with the upper surface of the N substrate layer 4.

[0047] The overall structure, composed of several parallel MOS cells, can enhance the overall current carrying capacity of the device through cell parallelization, meeting the requirements of high-power applications. In a single MOS cell, the lightly doped N-layer 9, located in the middle of the N-drift layer 5, effectively mitigates the electric field concentration between the drain 1 and the channel, reducing the device's on-resistance while improving its breakdown voltage performance and avoiding the risk of electric field breakdown under high voltage. The laterally symmetrical P-layers 10 located on the left and right sides of the N-drift layer 5 have rectangular cross-sectional profiles with V-shaped notches, which not only increase the contact area with the N-substrate layer 4, but also... It ensures the stability of current conduction between the N substrate layer 4 and the side-symmetric P-layer 10, and can also form an electric field confinement with the surrounding N-type region through P-type doping, which significantly suppresses the short-channel effect and reduces carrier scattering at the channel edge. Combined with the strained silicon channel design, it further improves carrier mobility and speeds up device switching. Moreover, the bottom ends of the two side-symmetric P-layers 10 are in contact with the upper surface of the N substrate layer 4, which creates a more reasonable vertical doping gradient, optimizes the potential distribution in the device, reduces leakage current, and improves the reliability of the device in the "off" state.

[0048] Meanwhile, the P+ layer 6 in the semiconductor epitaxial layer can form a low-resistance ohmic contact with the source 2, reducing the contact loss of the source 2. The N-well layer 7 and P-well layer 8 can precisely define the channel region, ensuring that the enhancement-mode MOSFET can stably form a conductive channel under the voltage control of the gate 3, achieving effective current regulation. There is no need to introduce complex special equipment, reducing mass production costs. Ultimately, the MOSFET achieves synergistic improvement in low conduction loss, high switching frequency, high withstand voltage and high reliability, making it suitable for high-performance integrated circuits, power electronics and other fields with stringent device performance requirements.

[0049] Example 2

[0050] like Figure 2 As shown, a heavily doped N layer 11 is formed at the bottom of the lightly doped N layer 9 by ion implantation. The cross-sectional profile of the heavily doped N layer 11 is trapezoidal, and the bottom of the heavily doped N layer 11 is in contact with the upper surface of the N substrate layer 4.

[0051] The high doping characteristics of the heavily doped N-layer 11 can significantly reduce the contact resistance between the lightly doped N-layer 9 and the N-substrate layer 4, reduce current loss during longitudinal conduction, and improve the overall conduction efficiency of the device. Compared with the traditional rectangular structure, the trapezoidal cross-section can increase the contact area between the heavily doped N-layer 11 and the lightly doped N-layer 9 and N-substrate layer 4, further optimizing the current conduction path and avoiding the heating problem caused by excessive local current density. Secondly, the longitudinal doping gradient formed by the heavily doped N-layer 11 and the lightly doped N-layer 9 can synergistically mitigate the electric field concentration phenomenon between the drain 1 and the channel. Combined with the electric field modulation effect of the N-drift layer 5, it can further improve the breakdown voltage performance of the device and effectively prevent the risk of electric field breakdown under high voltage conditions. At the same time, the trapezoidal structure can guide the electric field to be more evenly distributed inside the device, reduce the electric field abrupt change region, and reduce the probability of leakage current generation.

[0052] Example 3

[0053] like Figure 3 As shown, a T-shaped P-layer 12 is formed inside the lightly doped N-layer 9 by ion implantation, and the bottom end of the T-shaped P-layer 12 is in contact with the upper surface of the heavily doped N-layer 11.

[0054] The T-shaped P-layer 12 is designed to form a "lateral extension + vertical penetration" distribution within the lightly doped N-layer 9. The lateral portion expands the interaction range with the surrounding area, more precisely constraining carrier movement in the channel region and reducing carrier scattering at the channel edges. Combined with the strained silicon channel design, this further enhances carrier mobility and accelerates device switching speed. The bottom of the vertical portion contacts the upper surface of the heavily doped N-layer 11, creating a stable potential anchor point and preventing electric field distortion caused by abrupt changes in doping concentration at the interface between the lightly doped N-layer 9 and the heavily doped N-layer 11. This optimizes the potential distribution within the device. Simultaneously, the P-type doping of the T-shaped P-layer 12 and the N-type doping of the lightly doped N-layer 9 form a PN junction effect, which can... It effectively suppresses the short-channel effect and reduces the punch-through current between drain 1 and source 2. In addition, the T-shaped P-layer 12 is formed by ion implantation and has a tight interface with the lightly doped N-layer 9 and the heavily doped N-layer 11 without additional gap defects. This reduces the interface state density, reduces the recombination loss of charge carriers at the interface, and improves the current drive capability of the device. At the same time, its structure is highly compatible with existing photolithography and ion implantation processes, and does not require the introduction of special manufacturing equipment. It optimizes performance while controlling mass production costs. Ultimately, it helps the MOSFET achieve synergistic improvement in low leakage current, high switching frequency and high reliability, and is more suitable for high-performance integrated circuits, power electronics and other application scenarios with strict requirements for device precision and stability.

[0055] Example 4

[0056] like Figure 4As shown, a rectangular lightly doped N layer 13 is formed inside the heavily doped N layer 11 by ion implantation, and the top of the rectangular lightly doped N layer 13 is in contact with the bottom of the T-shaped P-layer 12.

[0057] The rectangular lightly doped N-layer 13 is located inside the heavily doped N-layer 11 and contacts the bottom of the T-shaped P-layer 12, forming a vertical doping gradient structure of heavily doped N-layer 11-rectangular lightly doped N-layer 13-T-shaped P-layer 12. The gradient design can buffer the abrupt change in doping concentration between the heavily doped N-layer 11 and the T-shaped P-layer 12, effectively mitigate the electric field concentration at the interface, reduce carrier scattering caused by the abrupt change in electric field, and improve the carrier migration efficiency in the channel region. Combined with the strained silicon channel design, it further enhances the current driving capability of the device.

[0058] Example 5

[0059] like Figure 5 As shown, a heavily doped N-type half-layer 14 is formed inside the lightly doped N-layer 9 and on both sides of the T-shaped P-layer 12 by ion implantation. The cross-sectional profile of the heavily doped N-type half-layer 14 is trapezoidal, and the opposite side of the heavily doped N-type half-layer 14 is in contact with the N drift layer 5.

[0060] The trapezoidal cross-sectional profile allows the heavily doped N-type half-layer 14 to form a "gradual" doping transition on both sides of the T-shaped P-layer 12. This avoids electric field distortion caused by abrupt changes in doping type or concentration between the T-shaped P-layer 12 and the lightly doped N-layer 9 and N-drift layer 5. The trapezoidal slope also guides the uniform distribution of the electric field, effectively mitigating the electric field concentration between the drain 1 and the channel, further improving the device's breakdown voltage performance and reducing the risk of breakdown under high voltage. At the same time, the heavily doped N-type half-layer 14 is located on both sides of the T-shaped P-layer 12 and contacts the N-drift layer 5 on the opposite side, constructing a "conductive bridge" between the T-shaped P-layer 12 and the N-drift layer 5. This optimizes the current conduction path between the lightly doped N-layer 9 and the N-drift layer 5, reduces local impedance during current conduction, and lowers device conduction losses. Furthermore, its heavy doping characteristics enhance carrier transport efficiency, which, combined with the strained silicon channel design, further improves the device's current drive capability.

[0061] Example 6

[0062] like Figure 6 As shown, semi-elliptical heavily doped N-type half-layers 15 are formed on the inner left and inner right sides of the lightly doped N-layer 9 by ion implantation, and the opposite sides of the two semi-elliptical heavily doped N-type half-layers 15 are in contact with the N drift layer 5.

[0063] The semi-elliptical cross-sectional profile creates a smooth transition doped region between the lightly doped N-layer 9 and the N-drift layer 5, effectively mitigating abrupt changes in doping concentration gradients among the three layers. This avoids electric field concentration at the interface, reduces carrier scattering caused by electric field distortion, and, combined with the strained silicon channel design, further enhances carrier mobility and accelerates device switching response. Simultaneously, the semi-elliptical heavily doped N-type half-layer 15, located on both sides of the lightly doped N-layer 9 and contacting the N-drift layer 5 on its opposite side, constructs a low-resistance conduction path between the lightly doped N-layer 9 and the N-drift layer 5. Its high doping characteristics significantly reduce the contact resistance and path impedance of current conduction between the two layers, reducing conduction losses. Furthermore, the arc-shaped boundary of the semi-elliptical structure expands the contact area with the lightly doped N-layer 9 and the N-drift layer 5, optimizing current distribution, preventing localized overheating due to excessively high local current density, and improving long-term operational stability.

[0064] Example 7

[0065] like Figure 7 As shown, a cylindrical P-layer 16 is formed inside the lightly doped N-layer 9 by ion implantation, and the bottom end of the cylindrical P-layer 16 is in contact with the upper surface of the N-substrate layer 4.

[0066] The rounded cylindrical shape of the P-layer 16 eliminates sharp edges at the top, preventing electric field concentration caused by structural abrupt changes within the lightly doped N-layer 9 and reducing carrier scattering in this region. This, combined with the strained silicon channel design, further enhances carrier mobility. Simultaneously, the cylindrical portion extends deep into the lightly doped N-layer 9, expanding its interaction range with the surrounding N-type region and more precisely constraining channel carrier movement. This enhances the ability to regulate the device's threshold voltage, ensuring stable turn-on and turn-off of the enhancement-mode MOSFET under gate 3 control. Furthermore, the bottom of the rounded cylindrical P-layer 16 contacts the upper surface of the N-substrate layer 4, creating a vertical P-type doped path from the N-substrate layer 4 to the lightly doped N-layer 9. Through the PN junction effect formed with the surrounding N-type region, this effectively suppresses short-channel effects and punch-through current between drain 1 and source 2, reducing leakage current in the device's off-state and improving reliability.

[0067] Example 8

[0068] like Figure 8 As shown, rectangular heavily doped N-type half-layers 17 are formed by ion implantation inside the lightly doped N-layer 9 and on both sides of the rounded cylindrical P-layer 16. The bottom ends of the two rectangular heavily doped N-type half-layers 17 are in contact with the upper surface of the N substrate layer 4.

[0069] By leveraging the high doping characteristics and symmetrical distribution of the rectangular heavily doped N-type half-layer 17, a low-resistance longitudinal conduction path can be constructed on both sides of the rounded cylindrical P-layer 16. Its bottom end contacts the upper surface of the N-substrate layer 4, enhancing the longitudinal conduction efficiency of current between the lightly doped N-layer 9 and the N-substrate layer 4, reducing conduction losses. Simultaneously, the regular boundary of the rectangular structure precisely defines the current conduction range, preventing disordered carrier diffusion in the lateral regions. Combined with the strained silicon channel design, this further improves carrier mobility and accelerates device switching speed. Furthermore, the rectangular heavily doped N-type half-layer 17, together with the rounded cylindrical P-layer 16 and the lightly doped N-layer 9, forms a synergistic doping gradient, mitigating the negative effects of the rounded cylindrical structure. The electric field is concentrated at the interface between the bulk P-layer 16 and the lightly doped N-layer 9, avoiding electric field distortion caused by abrupt changes in doping type and reducing leakage current. At the same time, the symmetrical structure makes the potential distribution within the device more uniform, effectively suppressing the short-channel effect and improving the switching stability of the enhancement-mode MOSFET under the control of the gate 3. Meanwhile, the rectangular heavily doped N-type half-layer 17 is formed by ion implantation, and the rectangular outline is easily and precisely controlled by photolithography mask. It is tightly bonded to the interface of the lightly doped N-layer 9, the rounded cylindrical P-layer 16, and the N-substrate layer 4, without additional gap defects, which can reduce the interface state density, reduce the recombination loss of charge carriers at the interface, and ensure the current driving capability.

[0070] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. An enhancement-mode MOSFET structure with a strained silicon channel, comprising a plurality of parallel MOS cells, each MOS cell including a drain (1), a semiconductor epitaxial layer, a source (2), and a gate (3); the semiconductor epitaxial layer including an N-substrate layer (4), an N-drift layer (5), a P+ layer (6), an N-well layer (7), and a P-well layer (8), characterized in that: A lightly doped N layer (9) is provided in the middle of the N drift layer (5) of a single MOS cell; A laterally symmetrical P-layer (10) is provided inside a single MOS cell and on the left and right sides of the N drift layer (5). The cross-sectional profile of the two laterally symmetrical P-layers (10) is a rectangle with a V-shaped notch. The bottom ends of the two laterally symmetrical P-layers (10) are in contact with the upper surface of the N substrate layer (4). The bottom end of the lightly doped N layer (9) is formed by ion implantation to form a heavily doped N layer (11). The cross-sectional profile of the heavily doped N layer (11) is trapezoidal. The bottom end of the heavily doped N layer (11) is in contact with the upper surface of the N substrate layer (4). A T-shaped P-layer (12) is formed inside the lightly doped N-layer (9) by ion implantation, and the bottom end of the T-shaped P-layer (12) is in contact with the upper surface of the heavily doped N-layer (11). A rectangular lightly doped N-layer (13) is formed inside the heavily doped N-layer (11) by ion implantation, and the top end of the rectangular lightly doped N-layer (13) is in contact with the bottom end of the T-shaped P-layer (12). Inside the lightly doped N layer (9) and on both sides of the T-shaped P-layer (12), a heavily doped N-type half-layer (14) is formed by ion implantation. The cross-sectional profile of the heavily doped N-type half-layer (14) is trapezoidal, and the opposite side of the heavily doped N-type half-layer (14) is in contact with the N drift layer (5).

2. A manufacturing process for an enhancement-mode MOSFET structure with a strained silicon channel, characterized in that, The enhancement-mode MOSFET structure with strained silicon channel as described in claim 1 includes the following steps: S1. Select high-purity single-crystal silicon to prepare the N substrate layer (4) as the device base support, and epitaxially grow the N drift layer (5) on the N substrate layer (4) through chemical vapor deposition process. S2. Using photolithography, photoresist is coated on the left and right sides of the N drift layer (5) and exposed and developed to define a rectangular patterned area with a V-shaped notch. Boron ions are implanted into the rectangular patterned area with a V-shaped notch using an ion implantation device to form the side-symmetric P-layer (10). After implantation, annealing is performed to activate impurities and repair lattice damage. S3. Photoresist is coated, exposed and developed in the middle region of the N drift layer (5) by photolithography to form a rectangular mask pattern of the lightly doped N layer (9). Nitrogen ions are implanted into the rectangular mask pattern area by ion implantation to form the lightly doped N layer (9). After the implantation of the lightly doped N layer (9) is completed, the photoresist is removed and a trapezoidal mask pattern is formed in the bottom region of the lightly doped N layer (9) by photolithography again. Nitrogen ions are implanted into the trapezoidal mask pattern area to form the heavily doped N layer (11). After the implantation is completed, the layer is placed in an annealing furnace to repair the lattice damage. S4. The T-shaped mask pattern of the T-shaped P-layer (12) is defined by photolithography inside the lightly doped N-layer (9). Boron ions are implanted by ion implantation process to form the T-shaped P-layer (12). After implantation, annealing is performed. S5. A trapezoidal mask pattern two of the heavily doped N-type half-layer (14) is formed on both sides of the T-shaped P-layer (12) by photolithography. Nitrogen ions are implanted into the area of ​​the trapezoidal mask pattern two to form the heavily doped N-type half-layer (14). After implantation, the layer is placed in an annealing furnace to repair lattice damage. S6. Define the regions of the P+ layer (6), the N-well layer (7) and the P-well layer (8) respectively by photolithography. For the P+ layer (6), boron ion implantation is used. For the N-well layer (7), nitrogen ion implantation is used. For the P-well layer (8), boron ion implantation is used. After implantation, annealing is performed to activate impurities and repair lattice damage. S7. Finally, through photolithography or sputtering processes, metal layers are deposited and patterned sequentially to form ohmic and Schottky contacts for the drain (1), source (2) and gate (3).

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