An image sensor and a method of manufacturing the same

Abstract

The application provides an image sensor and a preparation method thereof, and comprises the following steps: providing a substrate, sequentially forming a sacrificial layer and an epitaxial layer on the substrate; forming support columns of the epitaxial layer and the sacrificial layer, and the support columns are also arranged in extension in a first direction, and the first direction is perpendicular to the thickness direction of the substrate; etching the epitaxial layer to form at least one release groove exposing part of the sacrificial layer; etching and removing the sacrificial layer to form a cavity between the epitaxial layer and the substrate by taking the release groove as a release channel; forming a capacitor structure in the cavity, wherein the capacitor structure comprises a first electrode layer, a second electrode layer and a dielectric layer arranged between the first electrode layer and the second electrode layer; forming a pixel array comprising a plurality of pixel units in the epitaxial layer, and each pixel unit comprises at least one photodiode region, at least one floating diffusion region and at least one transistor, the photodiode region and the floating diffusion region are arranged in interval, and the side of the photodiode region away from the capacitor structure is a light-in side.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to an image sensor and a method for fabricating the same. Background Technology

[0002] Complementary Metal Oxide Semiconductor (CMOS) image sensor (CIS) technology has been widely used in applications such as still digital cameras, digital camcorders, medical imaging devices, and automotive imaging devices. CMOS image sensors are mainly divided into two structures: front-side illumination CMOS image sensors (FSI) and back-side illumination CMOS image sensors (BSI). With the development of microelectronics technology, in order to improve the overall performance of image sensors to achieve faster processing speeds, larger data storage capacity, and more functions, the capacitance requirements in the devices are becoming increasingly stringent.

[0003] Metal-Insulator-Metal Capacitor (MIM) capacitors have high capacitance values ​​and are widely used as charge storage, coupling, and filtering devices. An MIM capacitor structure consists of an upper electrode plate, a lower electrode plate, and a dielectric layer sandwiched between the upper and lower electrode plates. The capacitance value of an MIM capacitor is proportional to the area of ​​the electrode plates.

[0004] In related technologies, front-illuminated CMOS image sensors place the MIM capacitor structure in the metal layer of the back-end-of-line (BEOL) process. However, light needs to pass through the metal layer to reach the photodiode (PD) area. This causes the MIM capacitor structure to block some light from entering the photodiode (PD) area, reducing the photosensitive efficiency of the photodiode (PD), affecting the sensitivity of the image sensor, and thus reducing the image quality. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To address the existing problems, this application provides a method for fabricating an image sensor, comprising: providing a substrate, and sequentially forming a sacrificial layer and an epitaxial layer on the substrate; forming a support pillar penetrating the epitaxial layer and the sacrificial layer, wherein the support pillar extends along a first direction perpendicular to the thickness direction of the substrate; etching the epitaxial layer to form at least one release trench exposing a portion of the sacrificial layer; using the release trench as a release channel, etching away the sacrificial layer to form a cavity between the epitaxial layer and the substrate; forming a capacitor structure in the cavity, wherein the capacitor structure includes a first electrode layer, a second electrode layer, and a dielectric layer disposed between the first electrode layer and the second electrode layer; forming a pixel array comprising a plurality of pixel units in the epitaxial layer, each pixel unit comprising: at least one photodiode region, at least one floating diffusion region, and at least one transistor, wherein the photodiode region and the floating diffusion region are spaced apart, and the side of the photodiode region away from the capacitor structure is the light incident side.

[0007] For example, forming a capacitor structure in the cavity includes: forming an electrode material layer in the cavity, wherein the electrode material layer disposed on the side of the epitaxial layer facing the substrate is the first electrode layer, and the electrode material layer disposed on the side of the substrate facing the epitaxial layer is the second electrode layer, and there is a spatial gap between the first electrode layer and the second electrode layer; and forming a dielectric layer to fill the spatial gap.

[0008] Exemplarily, before forming the capacitor structure, the method further includes: forming an isolation layer covering the surface of the substrate facing the epitaxial layer, the surface of the epitaxial layer, the sidewalls of the release trench, and a portion of the sidewalls of the support pillar, wherein the first electrode layer covers the isolation layer on the side of the epitaxial layer facing the substrate, and the second electrode layer covers the isolation layer on the side of the substrate facing the epitaxial layer; the electrode material layer disposed in the release trench serves as a first electrode conductor, the first electrode conductor and the first electrode layer are electrically connected, and the dielectric layer further fills the release trench.

[0009] Exemplarily, the electrode material layer further covers the isolation layer exposed in the cavity on the sidewall of the support column. The method further includes: after forming the dielectric layer, removing the support column and a portion of the isolation layer, a portion of the electrode material layer, a portion of the dielectric layer, and a portion of the epitaxial layer located outside the sidewall of the support column to form an isolation trench and electrically isolate the first electrode layer and the second electrode layer; filling the isolation trench with an insulating material to form an insulating isolation structure.

[0010] For example, after forming the capacitor structure and before forming the pixel array, the method further includes: forming at least one second electrode wire through the epitaxial layer, the first electrode layer and the dielectric layer, the second electrode wire being electrically connected to the second electrode layer.

[0011] For example, the step of forming at least one second electrode wire penetrating the epitaxial layer, the first electrode layer, and the dielectric layer includes: etching the epitaxial layer, the first electrode layer, and the dielectric layer to form at least one contact hole, wherein the bottom of the contact hole is located in the second electrode layer; forming an insulating layer on the sidewall of the contact hole; filling the contact hole with a conductive material to form a second electrode wire, the second electrode wire further extending along the first direction, wherein at least one second electrode wire is located between two adjacent pixel units in the second direction; each of the release trenches is disposed between two adjacent pixel units in the first direction, and the release trenches further extend along the second direction, a first electrode wire is formed on the sidewall of the release trench, the first electrode wire being electrically connected to the first electrode layer; wherein the first direction and the second direction are perpendicular to each other, the first electrode wire and the second electrode wire are electrically isolated from each other, and the two intersect.

[0012] For example, the transistor includes a gate structure formed on the epitaxial layer. After forming the pixel array, the transistor further includes: forming an interlayer dielectric layer covering the epitaxial layer and the gate structure, and forming a metal interconnect layer in the interlayer dielectric layer; forming a passivation layer on the interlayer dielectric layer, and forming a plurality of grid structures on the passivation layer, wherein a grid structure is disposed between adjacent pixel units, and a grid opening is formed between adjacent grid structures, the grid opening exposing the surface of the passivation layer; embedding a color filter layer in the grid opening; and forming a plurality of microlenses on the color filter layer, the plurality of microlenses corresponding to the plurality of pixel units.

[0013] This application also provides an image sensor, comprising: a substrate; a capacitor structure disposed on the surface of the substrate, wherein the capacitor structure includes a first electrode layer, a second electrode layer, and a dielectric layer disposed between the first electrode layer and the second electrode layer; an epitaxial layer disposed on the capacitor structure; and a pixel array comprising a plurality of pixel units formed in the epitaxial layer, each pixel unit comprising: at least one photodiode region, at least one floating diffusion region, and at least one transistor, wherein the photodiode region and the floating diffusion region are spaced apart, and the side of the photodiode region away from the capacitor structure is the light incident side.

[0014] Exemplarily, it further includes: an isolation layer disposed between the first electrode layer and the epitaxial layer, and between the second electrode layer and the substrate; at least one first electrode wire, the first electrode wire penetrating the epitaxial layer and electrically connected to the first electrode layer; at least one second electrode wire, the second electrode wire penetrating the epitaxial layer, the first electrode layer and the dielectric layer, and electrically connected to the second electrode layer, wherein the first electrode wire and the second electrode wire are electrically isolated from each other; wherein the first electrode wire is disposed between two adjacent pixel units spaced apart in a first direction and extends along a second direction, the second electrode wire is disposed between two adjacent pixel units spaced apart in the second direction and extends along the first direction, and the first direction and the second direction are perpendicular to each other.

[0015] Exemplarily, the transistor includes a gate structure disposed on the epitaxial layer, and the image sensor further includes: an interlayer dielectric layer covering the epitaxial layer and the gate structure, wherein a metal interconnect layer is formed in the interlayer dielectric layer; a passivation layer located on the interlayer dielectric layer; a plurality of grid structures located on the passivation layer, wherein a grid structure is disposed between adjacent pixel units, and a grid opening is formed between adjacent grid structures, the grid opening exposing the surface of the passivation layer; a color filter layer embedded in the grid opening; and a plurality of microlenses located on the color filter layer, the plurality of microlenses corresponding to the plurality of pixel units.

[0016] The image sensor and its fabrication method provided in this application form a cavity between the substrate and the epitaxial layer, and form a capacitor structure in the cavity. Subsequently, a photodiode region is formed in the epitaxial layer. Since the capacitor structure is away from the light-incident side (i.e., the non-light-incident side) of the photodiode region, the situation where the capacitor structure blocks the incident light from entering the photodiode region can be effectively avoided, thereby reducing light loss, improving the photosensitivity of the photodiode, thereby improving the sensitivity of the image sensor, and thus improving the image quality. Attached Figure Description

[0017] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0018] In the attached image:

[0019] Figure 1 A flowchart illustrating an image sensor fabrication method according to a specific embodiment of this application is shown;

[0020] Figures 2 to 23The diagram illustrates a schematic representation of the device obtained by sequentially implementing a method for fabricating an image sensor according to a specific embodiment of this application. Detailed Implementation

[0021] The invention will now be described more fully with reference to the accompanying drawings, which illustrate embodiments of the invention. However, the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0022] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0023] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0025] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0026] In related technologies, CMOS front-illuminated image sensors place the MIM capacitor structure within a metal layer of the back-end-of-line (BEOL) process, with the photodiode (PD) region located below the metal layer. Therefore, incident light must pass through the metal layer to reach the underlying photodiode (PD) region. Consequently, the MIM capacitor structure in the metal layer obstructs some of the incident light from reaching the photodiode (PD), reducing its photosensitivity, affecting the image sensor's sensitivity, and ultimately degrading image quality.

[0027] Therefore, in view of the aforementioned technical problems, this application proposes a method for fabricating an image sensor, such as... Figure 1 As shown, it mainly includes the following steps:

[0028] Step S1: Provide a substrate, and sequentially form a sacrificial layer and an epitaxial layer on the substrate;

[0029] Step S2, forming a support pillar penetrating the epitaxial layer and the sacrificial layer, and the support pillar is further extended along a first direction, which is perpendicular to the thickness direction of the substrate;

[0030] Step S3: Etch the epitaxial layer to form at least one release trench exposing a portion of the sacrificial layer;

[0031] Step S4: Using the release trench as a release channel, the sacrificial layer is etched away to form a cavity between the epitaxial layer and the substrate;

[0032] Step S5: A capacitor structure is formed in the cavity, wherein the capacitor structure includes a first electrode layer, a second electrode layer, and a dielectric layer disposed between the first electrode layer and the second electrode layer.

[0033] Step S6: A pixel array comprising multiple pixel units is formed in the epitaxial layer. Each pixel unit includes at least one photodiode region, at least one floating diffusion region, and at least one transistor. The photodiode region and the floating diffusion region are spaced apart, and the side of the photodiode region away from the capacitor structure is the light-incident side.

[0034] The image sensor fabrication method of this application embodiment forms a cavity between the substrate and the epitaxial layer, and forms a capacitor structure in the cavity. Subsequently, a photodiode region is formed in the epitaxial layer. Since the capacitor structure is away from the light-incident side (i.e., the non-light-incident side) of the photodiode region, the situation where the capacitor structure blocks the incident light from entering the photodiode region can be effectively avoided, thereby reducing light loss, improving the photosensitivity of the photodiode, thereby improving the sensitivity of the image sensor, and thus improving the image quality.

[0035] Example 1

[0036] Below, for reference Figure 1 as well as Figures 2 to 23 The method for fabricating the image sensor of this application is described in detail, wherein, Figure 1 A flowchart illustrating a method for fabricating an image sensor according to a specific embodiment of this application is shown. Figures 2 to 23 The diagram illustrates a method for fabricating an image sensor according to a specific embodiment of this application, showing the resulting device obtained by sequential implementation of the method. Figures 4 to 16 In each of the figures, (a) shows a top view of the device obtained by sequentially implementing the image sensor fabrication method of a specific embodiment of the present application, and (b) shows a cross-sectional view of the device obtained by sequentially implementing the image sensor fabrication method of a specific embodiment of the present application.

[0037] For example, the method for fabricating the image sensor of this application includes the following steps:

[0038] First, step S1 is performed, a substrate is provided, and a sacrificial layer and an epitaxial layer are sequentially formed on the substrate.

[0039] In one example, such as Figure 2As shown, a substrate 201 is provided. The material of the substrate 201 includes, but is not limited to, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire, or other III / V compound semiconductors; or silicon on dielectric (SOI), silicon on dielectric (SSOI), silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI), and germanium on dielectric (GeOI); or it may be a double-sided polished wafer (DSP), a ceramic substrate such as alumina, a quartz, or a glass substrate, etc. Although several examples of materials that can form a substrate have been described herein, any material that can serve as a substrate falls within the spirit and scope of the invention. In this embodiment, the substrate 201 is a silicon substrate.

[0040] In one example, such as Figure 3 As shown, a sacrificial layer 202 is formed on substrate 201. Exemplarily, the material of the sacrificial layer 202 includes, but is not limited to, amorphous silicon, polycrystalline silicon, silicon-germanium (SiGe), or other suitable materials. The process method for forming the sacrificial layer 202 can be selected as needed, for example, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or other suitable epitaxial techniques, and is not specifically limited thereto. In this embodiment, the material of the sacrificial layer 202 is silicon-germanium. The sacrificial layer facilitates the subsequent formation of a cavity between the substrate 201 and the epitaxial layer, thereby enabling the formation of a capacitor structure within the cavity.

[0041] In one example, such as Figure 3 As shown, an epitaxial layer 203 is then formed on the sacrificial layer 202. Exemplarily, the material of the epitaxial layer 203 includes, but is not limited to, silicon, silicon germanium, silicon carbide, or other suitable epitaxial materials. The process method for forming the epitaxial layer 203 can be selected as needed, for example, metal-organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), molecular beam epitaxy (MBE), or other suitable techniques, and is not specifically limited thereto. In this embodiment, the material of the epitaxial layer 203 is silicon, the same as the material of the substrate 201. Therefore, the silicon formed by epitaxial growth can have the same crystal structure and orientation as the substrate, which helps to maintain high-quality electronic properties.

[0042] Next, step S2 is performed to form a support pillar that penetrates the epitaxial layer and the sacrificial layer, and the support pillar is also extended along a first direction, which is perpendicular to the thickness direction of the substrate.

[0043] In one example, such as Figure 4 and Figure 5As shown, the steps for forming the support pillar 205 penetrating the epitaxial layer 203 and the sacrificial layer 202 include:

[0044] First, the sacrificial layer 202 and the epitaxial layer 203 are etched to form a support trench 204 that penetrates the sacrificial layer 202 and the epitaxial layer 203, and the support trench 204 extends along a first direction. Specifically, a patterned photoresist layer is formed on the surface of the epitaxial layer 203, exposing the area and position corresponding to the support trench 204. Using the photoresist layer as a mask, the epitaxial layer 203 and the sacrificial layer 202 are etched to form the support trench 204, which penetrates the sacrificial layer 202 and the epitaxial layer 203 and exposes part of the surface of the substrate 201. Then, the photoresist layer is removed. The etching of the sacrificial layer 202 and the epitaxial layer 203 can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching.

[0045] Next, support pillars 205 are formed in the support trench 204. Specifically, support material is filled into the support trench 204, wherein the support material includes, but is not limited to, silicon oxide, silicon nitride, polysilicon, or other suitable materials. The process methods for forming the support pillars 205 include, but are not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDP-CVD), or physical vapor deposition (PVD), etc., and are not specifically limited thereto. The formed support pillars 205 extend along a first direction and are located in the epitaxial layer 203 and the sacrificial layer 202, the first direction being perpendicular to the thickness direction of the substrate. After forming the support pillars 205, the support material can also be planarized, for example, by using chemical mechanical polishing (CMP) to remove excess support material on the epitaxial layer 203, so that the epitaxial layer 203 has a flat surface. The number of support pillars can be reasonably set according to actual needs, such as one, two, three, or more. Preferably, the support pillars are formed in the edge region of the epitaxial layer to avoid the support pillars occupying too much of the device area in the middle region. In a specific example, the number of support pillars is two, and the two support pillars are spaced apart in the second direction. For example, support pillars are provided between any two pixel units.

[0046] Continue, perform step S3 to etch the epitaxial layer to form at least one release trench 240 that exposes a portion of the sacrificial layer.

[0047] In one example, such as Figure 6As shown, the epitaxial layer 203 is etched to form at least one release trench 240 exposing a portion of the sacrificial layer 202. The release trench 240 also extends along a second direction. Specifically, a patterned photoresist layer is formed on the surface of the epitaxial layer 203, exposing the area and position corresponding to the release trench 240 formed by the epitaxial layer. The epitaxial layer 203 is etched using the photoresist layer as a mask to form at least one release trench 240 extending along the second direction, exposing a portion of the surface of the sacrificial layer 202. The photoresist layer is then removed. The etching of the epitaxial layer 203 can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching, without specific limitations. The release trench 240 is also disposed between two adjacent pixel units formed subsequently in the first direction. The first direction is perpendicular to the thickness direction of the substrate 201, and the second direction is perpendicular to both the first and the thickness direction of the substrate 201.

[0048] Next, step S4 is performed to etch away the sacrificial layer using the release trench as a release channel to form a cavity between the epitaxial layer and the substrate.

[0049] In one example, such as Figure 7 As shown, the release trench 240 serves as the release channel, and the sacrificial layer 202 is etched away to form a cavity 206 between the epitaxial layer 203 and the substrate 201. Specifically, conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, plasma etching, and wet etching can be used to remove the sacrificial layer 202 between the epitaxial layer 203 and the substrate 201. For example, a gaseous hydrofluoric acid (VHF) etching process can be used to release the sacrificial layer 202, that is, gaseous hydrofluoric acid is introduced into the release trench, and the sacrificial layer 202 is removed by etching through the release trench 240, thereby forming a cavity 206 between the epitaxial layer 203 and the substrate 201.

[0050] Then, step S5 is performed to form a capacitor structure in the cavity, wherein the capacitor structure includes a first electrode layer, a second electrode layer, and a dielectric layer disposed between the first electrode layer and the second electrode layer.

[0051] In one example, such as Figure 8As shown, before forming the capacitor structure, the method further includes forming an isolation layer 207 covering the surface of the substrate 201 facing the epitaxial layer 203, the surface of the epitaxial layer 203, the sidewalls of the release trench 240, and a portion of the sidewalls of the support pillar 205. Exemplarily, the material of the isolation layer 207 includes, but is not limited to, oxides, such as silicon oxide, etc., and is not specifically limited thereto. The process methods for forming the isolation layer 207 include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD), etc., and are not specifically limited thereto. The isolation layer can provide a physical barrier to prevent damage caused by subsequent processing, thereby improving the reliability and stability of the device, and it can also serve an insulating function.

[0052] In one example, such as Figure 9 As shown, an electrode material layer 208 is formed in the cavity 206. The electrode material layer 208 disposed on the side of the epitaxial layer 203 facing the substrate 201 is a first electrode layer 2081, and the electrode material layer 208 disposed on the side of the substrate 201 facing the epitaxial layer 203 is a second electrode layer 2082. A spatial gap exists between the first electrode layer 2081 and the second electrode layer 2082. Exemplarily, the material of the electrode material layer 208 includes, but is not limited to, titanium nitride, tungsten, copper, aluminum, or other suitable electrode materials. The process methods for forming the electrode material layer 208 include, but are not limited to, physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD), and are not specifically limited thereto.

[0053] Electrode material layer 208 covers the isolation layer 207 of epitaxial layer 203 facing substrate 201 through release trench 240 to form a first electrode layer 2081. Electrode material layer 208 covers the isolation layer 207 of substrate 201 facing epitaxial layer 203 through release trench 240 to form a second electrode layer 2082. Electrode material layer 208 also covers the isolation layer 207 exposed on the sidewall of support pillar 205 in cavity 206 through release trench 240, and also covers the isolation layer 207 on the side of epitaxial layer 203 away from substrate 201.

[0054] In one example, such as Figure 10As shown, the dielectric layer 209 is formed to fill the space gap. Specifically, the dielectric layer 209 is formed in the space gap. Exemplarily, the material of the dielectric layer 209 includes, but is not limited to, alumina, hafnium oxide (HfO), zirconium trioxide (Zr2O3), silicon oxide, barium strontium titanate, or other suitable dielectric materials. The process methods for forming the dielectric layer 209 include, but are not limited to, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), or thermal oxidation, etc., and are not specifically limited thereto. Specifically, the formed dielectric layer 209 covers the surface of the electrode material layer 208, fills the space gap through the release trench 240, and is also located between the first electrode layer 2081 and the second electrode layer 2082.

[0055] In one example, such as Figures 11 to 13 As shown, after forming the dielectric layer 209, the step of removing the support pillar 205 and a portion of the isolation layer 207, a portion of the electrode material layer 208, a portion of the dielectric layer 209, and a portion of the epitaxial layer 203 located outside the sidewall of the support pillar 205 to form the isolation trench 210 includes:

[0056] First, such as Figure 11 As shown, a portion of the isolation layer 207, a portion of the electrode material layer 208, and a portion of the dielectric layer 209 on the outer sidewall of the support pillar 205 and on the epitaxial layer 203 are removed. Specifically, chemical mechanical polishing (CMP) can be used to remove the portion of the isolation layer 207, the portion of the electrode material layer 208, and the portion of the dielectric layer 209 on the outer sidewall of the support pillar 205 and on the epitaxial layer 203. Then, wet cleaning can be performed to remove any residual material from the CMP process to avoid affecting the device performance.

[0057] Then, as Figure 12 and Figure 13As shown, the support pillar 205 is removed and the electrode material layer 208 and dielectric layer 209 are etched to form an isolation trench 210. First, conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, plasma etching, and wet etching can be used to remove the support pillar 205. Next, a patterned photoresist layer is formed on the epitaxial layer 203, exposing the area and position corresponding to the isolation trench 210. Using the photoresist layer as a mask, the epitaxial layer 203, isolation layer 207, electrode material layer 208, and dielectric layer 209 are etched to form the isolation trench 210. The isolation trench 210 penetrates the epitaxial layer 203, isolation layer 207, electrode material layer 208, and dielectric layer 209 to expose part of the surface of the substrate 201. Then, the photoresist layer is removed. The etching of the epitaxial layer 203, isolation layer 207, electrode material layer 208, and dielectric layer 209 can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching. No specific limitation is made in this regard. The formed isolation trench 210 electrically isolates the first electrode layer 2081 and the second electrode layer 2082, and the first electrode layer 2081, the dielectric layer 209, and the second electrode layer 2082 constitute a capacitor structure 230. Forming the capacitor structure 230 in the cavity 206 can prevent the capacitor structure from blocking incident light from entering the photodiode area, thereby improving the sensitivity of the image sensor and thus improving the image quality.

[0058] In one example, such as Figure 14 As shown, after forming the isolation trench 210, the method further includes filling the isolation trench 210 with insulating material to form an insulating isolation structure 211. Exemplarily, the material of the insulating isolation structure 211 includes, but is not limited to, oxides, such as silicon oxide, etc., and is not specifically limited thereto. The process methods for forming the insulating isolation structure 211 include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD), etc., and are not specifically limited thereto. After forming the insulating isolation structure 211, the epitaxial layer 203 can be planarized, for example, by using chemical mechanical polishing (CMP) to remove excess insulating material on the epitaxial layer 203, so that the epitaxial layer 203 has a flat surface, improving the reliability of the device.

[0059] In one example, such as Figure 15 and Figure 16 As shown, after forming the capacitor structure 230 and before forming the pixel array, the step of forming at least one second electrode wire 2101 penetrating the epitaxial layer 203, the first electrode layer 2081, and the dielectric layer 209 includes:

[0060] First, such as Figure 15As shown, the epitaxial layer 203, the first electrode layer 2081 and the dielectric layer 209 are etched to form at least one contact hole 212, wherein the bottom of the contact hole 212 is located in the second electrode layer 2082 (including the surface that contacts the second electrode layer 2082 or is located below the surface). Specifically, a patterned photoresist layer is formed on the epitaxial layer 203, exposing the area and position corresponding to the contact hole 212. Using the photoresist layer as a mask, the epitaxial layer 203, the isolation layer 207, the first electrode layer 2081, and the dielectric layer 209 are etched to form at least one contact hole 212. The bottom of the contact hole 212 is located in the second electrode layer 2082. Each contact hole 212 extends along a first direction, and the formed contact holes 212 are also located between two adjacent pixel units formed subsequently in the second direction. The photoresist layer is then removed. The etching of the epitaxial layer 203, the isolation layer 207, the first electrode layer 2081, and the dielectric layer 209 can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching; no specific limitation is made. The first direction is perpendicular to the thickness direction of the substrate 201, and the first and second directions are perpendicular to each other. The formed contact hole 212 is used for the subsequent formation of the second electrode wire 2101 to form an electrical connection with the second electrode layer 2082. Optionally, the top view shape of the contact hole 212 is elongated, square, circular, or other suitable shape.

[0061] Then, as Figure 16 As shown, before forming the second electrode wire 2101, the method of this application further includes filling the contact hole 212 with an insulating material. The insulating material covers the sidewalls of the contact hole 212 to form an insulating isolation layer 213. The insulating material includes, but is not limited to, oxides, such as silicon oxide, etc., and is not specifically limited thereto. The process methods for forming the insulating isolation layer 213 include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). The insulating isolation layer 213 can be used to electrically isolate the second electrode wire 2101 from its outer epitaxial layer, and to electrically isolate it from the first electrode wire.

[0062] Next, as Figure 16As shown, a conductive material is filled into the contact hole 212 to form a second electrode wire 2101. Exemplarily, the conductive material includes, but is not limited to, titanium nitride, tungsten, copper, aluminum, or other suitable conductive materials. The process methods for forming the second electrode wire 2101 include, but are not limited to, physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD), and are not specifically limited thereto. The conductive material fills the contact hole 212 to form at least one second electrode wire 2101, thus the formed second electrode wire 2101 extends along a first direction, and at least one second electrode wire 2101 is located between two adjacent pixel units subsequently formed in a second direction, wherein the bottom of the second electrode wire 2101 is located in the second electrode layer 2082. After forming the second electrode wire 2101, a planarization process can also be performed to remove excess insulating and conductive material from the epitaxial layer 203, for example, using chemical mechanical polishing (CMP) to remove excess insulating and conductive material from the epitaxial layer 203, so that the epitaxial layer 203 has a flat surface, improving the reliability of the device.

[0063] In one example, at least one first electrode wire 2100 (i.e., an electrode material layer 208 covering the insulating layer 207 on the sidewall of the release trench 240) is formed on the sidewall of the release trench 240. The first electrode wire 2100 and the first electrode layer 2081 are electrically connected, and the dielectric layer 209 also fills the release trench 240. The formed first electrode wire 2100 and the second electrode wire 2101 are electrically isolated from each other and intersect.

[0064] Finally, step S6 is performed to form a pixel array comprising multiple pixel units in the epitaxial layer. Each pixel unit includes at least one photodiode region, at least one floating diffusion region, and at least one transistor. The photodiode region and the floating diffusion region are spaced apart.

[0065] In one example, such as Figure 17 and Figure 18 As shown, the step of forming a pixel array comprising multiple pixel units in the epitaxial layer 203 includes:

[0066] First, at least one photodiode region 214 is formed in the epitaxial layer 203. Specifically, a patterned photoresist layer is formed on the epitaxial layer 203, defining the regions of the photodiode (PD). Ion implantation is performed on the epitaxial layer 203 using the patterned photoresist layer as a mask to form at least one photodiode region 214 in the epitaxial layer 203. Each photodiode region 214 extends from the surface of the epitaxial layer 203 into the epitaxial layer 203. The photoresist layer is then removed. The type and concentration of ion implantation are selected based on actual conditions and are not specifically limited. The function of the photodiode region is to convert incident light signals into electrical signals and accumulate charge in the subsequent image sensor.

[0067] It is worth mentioning that forming a pixel array comprising multiple pixel units in the epitaxial layer 203 can mean that part of the structure of the pixel unit can be located in the epitaxial layer 203, while part of the structure is located on the epitaxial layer, such as the gate structure of a transistor.

[0068] Next, at least one floating diffusion region 215 is formed in the epitaxial layer 203. Specifically, a patterned photoresist layer is formed on the epitaxial layer 203, which defines the region of the floating diffusion region (FD). Ion implantation is performed on the epitaxial layer 203 using the patterned photoresist layer as a mask to form at least one floating diffusion region 215 in the epitaxial layer 203. Each floating diffusion region 215 extends from the surface of the epitaxial layer 203 into the epitaxial layer 203 and is spaced apart from the photodiode region 214. The photoresist layer is then removed. The floating diffusion region is used to collect the charge transferred from the photodiode and convert it into a voltage signal for the readout circuit processing.

[0069] It should be noted that annealing is performed after ion implantation. Since ion implantation can cause damage to the silicon wafer lattice, annealing can repair this damage. In addition, annealing can also activate the implanted ions, thereby improving the performance of the image sensor.

[0070] Finally, a transistor is formed, wherein the steps for forming a transistor may include:

[0071] First, an active region is defined using shallow trench isolation (STI) or localized oxidation (LOCOS) to isolate adjacent pixels. Then, a gate structure 216 is formed on the epitaxial layer 203. Specifically, first, a gate dielectric layer is formed on the epitaxial layer 203. The material of the gate dielectric layer includes, but is not limited to, silicon dioxide, and the method for forming the gate dielectric layer includes, but is not limited to, chemical vapor deposition (CVD) or thermal oxidation. Second, a gate layer is formed on the gate dielectric layer. The material of the gate layer includes, but is not limited to, polysilicon, and the method for forming the gate layer includes, but is not limited to, chemical... Methods such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) are used. Finally, a patterned photoresist layer is formed on the gate layer, defining the region and location of the gate structure. Using the patterned photoresist layer as a mask, the gate layer and gate dielectric layer are etched to form the gate structure 216 on the epitaxial layer. The photoresist layer is then removed. The etching of the gate layer and gate dielectric layer can be performed using dry etching, reactive ion etching (RIE), ion beam etching, plasma etching, or other conventional etching processes; no specific limitations are imposed. The gate structure is used to control the transfer of accumulated charge in the photodiode to the floating diffusion region, thereby achieving an efficient signal readout mechanism.

[0072] It is worth mentioning that the number of gate structures can be determined based on the number of transistors in the image sensor.

[0073] Next, after forming the gate structure 216, low-concentration impurities can be introduced into the epitaxial layer below both sides of the gate structure via ion implantation to form lightly doped regions, and sidewalls (not shown) can be formed on both sides of the gate structure. The sidewalls are used to protect the edges of the gate structure from damage during subsequent processes. The sidewall materials include, but are not limited to, insulating materials such as silicon nitride. The lightly doped regions improve the short-channel effect and enhance device reliability. Then, highly doped source and drain regions are formed outside the lightly doped regions to provide low-resistance paths and enhance current drive capability. The ion implantation concentration in the highly doped source and drain regions is greater than that in the lightly doped regions. Annealing is performed after ion implantation. Since ion implantation causes lattice damage to the silicon wafer, annealing can repair this damage. Furthermore, annealing can activate the implanted ions, thereby improving the performance of the image sensor.

[0074] In one example, such as Figure 19 As shown, after forming the pixel array, the process further includes forming an interlayer dielectric layer 218 covering the epitaxial layer 203 and the gate structure 216, and forming a metal interconnect layer 219 in the interlayer dielectric layer 218. Specifically, the step of forming the metal interconnect layer 219 includes:

[0075] Exemplarily, before forming the interlayer dielectric layer 218, the process further includes forming a dielectric layer 217 covering the gate structure 216 and the epitaxial layer 203. Exemplarily, the material of the dielectric layer 217 includes, but is not limited to, silicon dioxide, a low-dielectric-constant material, or other suitable dielectric materials. Methods for forming the dielectric layer 217 include, but are not limited to, deposition processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), and are not specifically limited thereto. The formed dielectric layer 217 covers the surfaces of the photodiode region 214, the floating diffusion region 215, the gate structure 216, and the epitaxial layer 203.

[0076] Next, an interlayer dielectric layer 218 is formed on the dielectric layer 217. The interlayer dielectric layer 218 may include multiple layers of interlayer dielectric material. Methods for forming the interlayer dielectric material layer include, but are not limited to, deposition processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), and are not specifically limited thereto. For example, the material of the metal interconnect layer 219 includes, but is not limited to, materials such as copper or aluminum, and methods for depositing the metal material include, but are not limited to, processes such as chemical vapor deposition (CVD), and are not specifically limited thereto.

[0077] It is worth mentioning that the metal interconnect layer may include multiple layers of metal stacked sequentially, and plugs disposed between adjacent metal layers, thereby forming a stacked metal interconnect layer. Specifically, the method for forming the metal interconnect layer can be any suitable method, which will not be elaborated here.

[0078] In one example, such as Figure 20 As shown, a passivation layer 220 is formed on the interlayer dielectric layer 218, covering the surface of the interlayer dielectric layer 218. Exemplarily, the material of the passivation layer 220 includes, but is not limited to, materials such as silicon dioxide or silicon oxynitride, and the method for forming the passivation layer 220 includes, but is not limited to, methods such as PECVD (plasma-enhanced chemical vapor deposition) or ALD (atomic layer deposition). The passivation layer helps reduce electrical crosstalk between adjacent pixels and reduces parasitic capacitance by optimizing the electrical properties of the metal layer, thereby improving signal transmission efficiency and image sharpness.

[0079] In one example, such as Figure 21As shown, multiple grid structures 221 are formed on the passivation layer 220, and grid openings 222 are formed between each grid structure 221. A grid structure 221 is disposed between adjacent pixel units. Specifically, firstly, a grid material layer is formed on the passivation layer 220. The material of the grid material layer includes, but is not limited to, tungsten (W), nickel (Ni), or titanium (Ti). The methods for forming the grid material layer include, but are not limited to, molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), and laser ablation deposition (LAD). Next, a patterned photoresist layer is formed on the grid material layer. This patterned photoresist layer defines the region and position of the grid structure 221. Using the patterned photoresist layer as a mask, the grid material layer is etched to form a grid structure 221 between adjacent pixel units. A grid opening 222 is formed between each grid structure 221, and the grid opening 222 exposes the surface of the passivation layer 220. Then, the photoresist layer is removed. The etching of the grid material layer can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching, without specific limitations. The grid structure can enhance image performance by suppressing optical crosstalk.

[0080] In one example, such as Figure 22 As shown, a color filter layer 223 is embedded in each grid opening 222. The main function of the color filter layer 223 is to separate the incident light according to color (i.e., different wavelengths), so that each pixel can only receive light of a specific color (usually one of red, green, and blue). This is the basis for the color image sensor to generate color images. Specifically, the material of the color filter layer can be deposited in each grid opening 222 using methods such as spin coating or inkjet printing, and then subjected to processes such as baking to ensure its stability and optical performance, ultimately forming the color filter layer 223 embedded in the grid opening 222. The material of the color filter layer 223 includes, but is not limited to, dye-based resins, pigment-based resins, or inorganic materials.

[0081] In one example, such as Figure 23As shown, multiple microlenses 225 are formed on the color filter layer 223, each microlens 225 corresponding to a multiple pixel unit; for example, one pixel unit corresponds to one or more microlenses 225. Before forming the microlenses 225, an anti-reflection layer 224 is formed on the color filter layer 223. Exemplarily, the anti-reflection layer 224 includes, but is not limited to, silicon dioxide or silicon nitride, and the process methods for forming the anti-reflection layer 224 include, but are not limited to, PECVD (plasma-enhanced chemical vapor deposition), atomic layer deposition (ALD), etc. When light enters another medium from one medium (e.g., a microlens entering a color filter layer), reflection loss occurs if the refractive index difference between the two is large. By optimizing its refractive index and thickness, the anti-reflection layer can effectively reduce this reflection loss at the interface, thereby increasing the effective light amount reaching the photodiode. By reducing reflection loss, more incident light energy can be effectively utilized by the image sensor, which directly improves the quantum efficiency and performance in low-light environments of the image sensor. The anti-reflection layer can also act as a transition layer, providing a flat surface for the microlenses, facilitating their fabrication. In other examples, an anti-reflective layer may not be formed, and there are no specific restrictions on this.

[0082] Finally, multiple microlenses 225 are formed on the color filter layer 223. Specifically, first, a photosensitive material layer suitable for fabricating microlenses (usually positive photoresist or high-temperature resin, etc.) is coated on the anti-reflection layer 224. A patterned photoresist layer is formed on the photosensitive material layer, defining the area and position of the microlenses 225. The photosensitive material layer is etched using the patterned photoresist layer as a mask to form the basic structure of the microlenses. Second, the photoresist is heated to a specific temperature, causing the remaining photoresist to melt and naturally form the desired hemispherical or near-spherical microlens structure due to surface tension. Finally, the formed microlens structure undergoes further curing treatment, such as ultraviolet curing or annealing, to form the final microlens 225. By focusing incident light, the microlenses allow more light to directly enter the photodiode, thereby compensating for this loss, improving light utilization, enhancing signal quality, and improving image quality.

[0083] It is worth mentioning that the above steps are only examples, and the order of the steps can be adjusted without conflict.

[0084] Thus, the process steps of the image sensor fabrication method according to the embodiments of this application are completed. It is understood that the image sensor fabrication method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included within the scope of the fabrication method of this embodiment.

[0085] In summary, the image sensor fabrication method of this application forms a cavity between the substrate and the epitaxial layer, and forms a capacitor structure in the cavity. Subsequently, a photodiode region is formed in the epitaxial layer. Since the capacitor structure is away from the light-incident side (i.e., the non-light-incident side) of the photodiode region, the situation where the capacitor structure blocks incident light from entering the photodiode region can be effectively avoided, thereby reducing light loss, improving the photosensitivity of the photodiode, thereby improving the sensitivity of the image sensor, and thus improving the image quality.

[0086] Example 2

[0087] This application also provides an image sensor, which can be prepared by the method described in Embodiment 1 above, or by other suitable preparation methods.

[0088] The following reference Figures 2 to 23 The image sensors in the embodiments of this application will be explained and described, wherein structures identical to those in the aforementioned Embodiment 1 will not be described in detail here.

[0089] Specifically, such as 2 to Figure 23 As shown, the image sensor of this application includes: a substrate 201; a capacitor structure 230 disposed on the surface of the substrate 201, wherein the capacitor structure 230 includes a first electrode layer 2081, a second electrode layer 2082, and a dielectric layer 209 disposed between the first electrode layer 2081 and the second electrode layer 2082; an epitaxial layer 203 disposed on the capacitor structure 230; and a pixel array comprising multiple pixel units formed in the epitaxial layer 203, each pixel unit including: at least one photodiode region 214, at least one floating diffusion region 215, and at least one transistor, wherein the photodiode region 214 and the floating diffusion region 215 are spaced apart, and the side of the photodiode region 214 away from the capacitor structure 230 is the light-incident side. By forming a cavity between the substrate and the epitaxial layer, and forming a capacitor structure in the cavity, the situation where the capacitor structure blocks incident light from entering the photodiode region can be effectively avoided, thereby improving the image quality.

[0090] For example, the image sensor further includes an isolation layer 207 disposed between the first electrode layer 2081 and the epitaxial layer 203, and between the second electrode layer 2082 and the substrate 201. The isolation layer provides a physical barrier to prevent damage caused by subsequent processing, thereby improving the reliability and stability of the device. The isolation layer also acts as an insulator to isolate the film layers on both sides so that they are not electrically connected.

[0091] For example, the image sensor further includes: at least one first electrode wire 2100, which penetrates the epitaxial layer 203 and is electrically connected to the first electrode layer 2081; and at least one second electrode wire 2101, which penetrates the epitaxial layer 203, the first electrode layer 2081, and the dielectric layer 209 and is electrically connected to the second electrode layer 2082. The first electrode wire 2100 and the second electrode wire 2101 are electrically isolated from each other. Electrical isolation can prevent current leakage, increase capacitance, reduce parasitic effects, and enhance the reliability of the device.

[0092] For example, a first electrode wire 2100 is disposed between two adjacent pixel units spaced apart in a first direction and extends along a second direction, and a second electrode wire 2101 is disposed between two adjacent pixel units spaced apart in the second direction and extends along the first direction, wherein the first direction and the second direction are perpendicular to each other.

[0093] For example, the first electrode wire 2100, the first electrode layer 2081, and the second electrode layer 2082 are formed simultaneously. Specifically, the first electrode wire 2100, the first electrode layer 2081, and the second electrode layer 2082 are formed simultaneously when the electrode material layer 208 is deposited through the release trench 240.

[0094] For example, the transistor includes a gate structure 216 disposed on the epitaxial layer 203, and the image sensor further includes: an interlayer dielectric layer 218 covering the epitaxial layer 203 and the gate structure 216, wherein a metal interconnect layer 219 is formed in the interlayer dielectric layer 218; a passivation layer 220 located on the interlayer dielectric layer 218; a plurality of grid structures 221, wherein a grid opening 222 is formed between adjacent grid structures 221, and the grid opening 222 exposes the passivation layer 220; a color filter layer 223 embedded in the grid opening 222; and a plurality of microlenses 225 located on the color filter layer 223, the plurality of microlenses 225 corresponding to a plurality of pixel units.

[0095] It is worth mentioning that the image sensor in this embodiment can be a front-illuminated CMOS image sensor.

[0096] The image sensor provided in this application forms a cavity between the substrate and the epitaxial layer, and forms a capacitor structure in the cavity. Subsequently, a photodiode region is formed in the epitaxial layer. Since the capacitor structure is away from the light-incident side (i.e., the non-light-incident side) of the photodiode region, the situation where the capacitor structure blocks incident light from entering the photodiode region can be effectively avoided, thereby reducing light loss, improving the photosensitivity of the photodiode, thereby improving the sensitivity of the image sensor, and thus improving the image quality.

[0097] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will be conceived by those skilled in the art, all of which will fall within the spirit and scope of the disclosed concept. More particularly, various modifications and changes can be made in terms of the arrangement and / or components of the subject matter within the scope of the disclosure, drawings, and appended claims. In addition to modifications and changes in components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A method of fabricating an image sensor, characterized by, The method comprises: providing a substrate, a sacrificial layer and an epitaxial layer are sequentially formed on the substrate; forming support columns penetrating through the epitaxial layer and the sacrificial layer, and the support columns are also arranged along a first direction, which is perpendicular to the thickness direction of the substrate; etching the epitaxial layer to form at least one release trench exposing part of the sacrificial layer; using the release trench as a release channel, etching to remove the sacrificial layer to form a cavity between the epitaxial layer and the substrate; forming a capacitor structure in the cavity, wherein the capacitor structure comprises a first electrode layer, a second electrode layer, and a dielectric layer arranged between the first electrode layer and the second electrode layer; forming a pixel array comprising a plurality of pixel units in the epitaxial layer, each pixel unit comprising: at least one photodiode region, at least one floating diffusion region, and at least one transistor, the photodiode region and the floating diffusion region are arranged apart, and the side of the photodiode region away from the capacitor structure is the light entrance side.

2. The method of producing an image sensor according to claim 1, wherein The step of forming a capacitor structure in the cavity comprises: forming an electrode material layer in the cavity, wherein the electrode material layer arranged on the side of the epitaxial layer facing the substrate is the first electrode layer, the electrode material layer arranged on the side of the substrate facing the epitaxial layer is the second electrode layer, and the first electrode layer and the second electrode layer have a spatial interval therebetween; forming the dielectric layer to fill the spatial interval.

3. The method of producing an image sensor according to claim 2, wherein Before forming the capacitor structure, the method further comprises: forming an isolation layer covering the surface of the substrate facing the epitaxial layer, the surface of the epitaxial layer, the sidewall of the release trench, and part of the sidewall of the support columns, wherein the first electrode layer covers the isolation layer on the side of the epitaxial layer facing the substrate, and the second electrode layer covers the isolation layer on the side of the substrate facing the epitaxial layer; the electrode material layer arranged in the release trench serves as a first electrode wire, the first electrode wire is electrically connected to the first electrode layer, and the dielectric layer also fills the release trench.

4. The method of claim 3, wherein the electrode material layer also covers the exposed isolation layer on the sidewall of the support column in the cavity, and the method further comprises: after forming the dielectric layer, removing the support column and part of the isolation layer, part of the electrode material layer, part of the dielectric layer, and part of the epitaxial layer outside the sidewall of the support column to form an isolation trench and electrically isolate the first electrode layer from the second electrode layer; filling an insulating material in the isolation trench to form an insulating isolation structure.

5. The method of producing an image sensor according to claim 1, wherein After forming the capacitor structure and before forming the pixel array, the method further comprises: forming at least one second electrode wire penetrating through the epitaxial layer, the first electrode layer, and the dielectric layer, and the second electrode wire is electrically connected to the second electrode layer.

6. The method for manufacturing an image sensor according to claim 5, wherein The step of forming at least one second electrode wire penetrating through the epitaxial layer, the first electrode layer, and the dielectric layer comprises: etching the epitaxial layer, the first electrode layer and the dielectric layer to form at least one contact hole, wherein a bottom of the contact hole is located in the second electrode layer; forming an insulating isolation layer on a sidewall of the contact hole; filling a conductive material in the contact hole to form the second electrode lead wire, the second electrode lead wire is also arranged along the first direction, wherein at least one second electrode lead wire is located between two adjacent pixel units in the second direction; each of the release trenches is arranged between two adjacent pixel units in the first direction, and the release trench also extends along the second direction, a first electrode lead wire is formed on a sidewall of the release trench, the first electrode lead wire and the first electrode layer are electrically connected; wherein the first direction and the second direction are perpendicular to each other, the first electrode lead wire and the second electrode lead wire are electrically isolated, and the two cross each other.

7. The method of producing an image sensor according to claim 1, wherein The transistor comprises a gate structure formed on the epitaxial layer, and after the pixel array is formed, it further comprises: forming an interlayer dielectric layer covering the epitaxial layer and the gate structure, and forming a metal wiring layer in the interlayer dielectric layer; forming a passivation layer on the interlayer dielectric layer, and a plurality of grid structures are formed on the passivation layer, wherein a grid structure is arranged between adjacent pixel units, and a grid opening is formed between adjacent grid structures, which exposes the surface of the passivation layer; embedding a color filter layer in the grid opening; forming a plurality of microlenses on the color filter layer, and a plurality of the microlenses correspond to a plurality of the pixel units.

8. An image sensor, comprising: It comprises: a substrate; a capacitor structure arranged on a surface of the substrate, wherein the capacitor structure comprises a first electrode layer, a second electrode layer and a dielectric layer arranged between the first electrode layer and the second electrode layer; an epitaxial layer arranged on the capacitor structure; a pixel array comprising a plurality of pixel units is formed in the epitaxial layer, each of the pixel units comprises: at least one photodiode region, at least one floating diffusion region and at least one transistor, the photodiode region and the floating diffusion region are arranged apart, and the side of the photodiode region away from the capacitor structure is the light entrance side; an isolation layer arranged between the first electrode layer and the epitaxial layer, and between the second electrode layer and the substrate; at least one first electrode lead wire penetrating through the epitaxial layer and electrically connected with the first electrode layer; at least one second electrode lead wire penetrating through the epitaxial layer, the first electrode layer and the dielectric layer, and electrically connected with the second electrode layer, the first electrode lead wire and the second electrode lead wire are electrically isolated; wherein the first electrode lead wire is arranged between two adjacent pixel units arranged apart in a first direction, and the first electrode lead wire extends along a second direction, the second electrode lead wire is arranged between two adjacent pixel units arranged apart in a second direction, and the second electrode lead wire extends along a first direction, the first direction and the second direction are perpendicular to each other.

9. The image sensor of claim 8, wherein, The transistor comprises a gate structure disposed on the epitaxial layer, and the image sensor further comprises: an interlayer dielectric layer covering the epitaxial layer and the gate structure, wherein a metal wiring layer is formed in the interlayer dielectric layer; a passivation layer on the interlayer dielectric layer; a plurality of grid structures on the passivation layer, wherein a grid structure is disposed between adjacent pixel units, and a grid opening is formed between adjacent grid structures, and the grid opening exposes the surface of the passivation layer; a color filter layer embedded in the grid opening; a plurality of microlenses on the color filter layer, and a plurality of microlenses correspond to a plurality of pixel units.

Images