Laminate and method for manufacturing circuit board

Abstract

A laminate (10) is provided with: a film (11); a resin layer (13) that contains a thermoplastic polyimide resin and is formed on at least one surface of the film; a catalyst layer (15) that contains palladium and a dispersant covering the palladium and is formed on the resin layer; and an electroless plating layer (17) that contains nickel and copper and is formed on the catalyst layer. The nickel content is 8.0% by mass or more and 13.0% by mass or less with respect to the total mass of the electroless plating layer (17).

Description

TECHNICAL FIELD

[0001] The present application relates to a laminate and a manufacturing method of a circuit substrate. BACKGROUND

[0002] A circuit substrate capable of fixing an integrated circuit (IC) is formed with a fine wiring.

[0003] In Patent Literature 1, as a member constituting a circuit substrate, a laminate is disclosed, which has: a base material; a plating formation layer laminated on the base material; and a metal plating layer laminated on the plating formation layer. The plating formation layer is composed of a thermoplastic resin and a plating catalyst.

[0004] In Patent Literature 2, a laminate is disclosed, which has: a substrate composed of a glass cloth and a resin; a copper layer formed on the substrate; a first insulating material layer formed on the copper layer; and a seed layer formed on the first insulating material layer. The first insulating material layer is composed of a thermosetting resin, and a catalyst is adsorbed on the surface. The seed layer is composed of an electroless plating including nickel and copper.

[0005] PRIOR ART DOCUMENTS

[0006] PATENT LITERATURE

[0007] Patent Literature 1: International Publication No. 2020 / 050338

[0008] Patent Literature 2: International Publication No. 2020 / 130101 SUMMARY

[0009] PROBLEMS TO BE SOLVED BY THE INVENTION

[0010] With regard to the laminate disclosed in Patent Literature 1, the following problem arises when forming a fine wiring on the laminate. A resist pattern composed of a resin is formed on the metal plating layer, and a wiring is formed by electrolytic plating. Then, the resist pattern is removed, and the metal plating layer exposed after the removal and the plating formation layer thereunder are removed using an acidic chemical solution. At this time, the metal plating layer under the wiring is easily eroded by the chemical solution. Therefore, there is a possibility that the laminate disclosed in Patent Literature 1 has poor acid resistance. As a result, there is a possibility that the reliability of a circuit of a circuit substrate using the laminate is poor.

[0011] In addition, the laminate disclosed in Patent Literature 2 has the following problem in the manufacturing process. The seed layer is formed on the first insulating material layer by electroless plating. In this process, stress is generated in the seed layer. The laminate cannot relieve the stress, and peeling is easily generated between the first insulating material layer and the seed layer. Therefore, there is a possibility that the laminate disclosed in Patent Literature 2 has poor interlayer adhesion between the first insulating material layer and the seed layer. As a result, there is a possibility that the reliability of the circuit of the circuit board using the laminate is poor.

[0012] The present application has been achieved in view of the above-described circumstances. That is, an object of the present application is to provide a laminate having excellent acid resistance and interlayer adhesion, and a manufacturing method of a circuit board using the laminate.

[0013] Means for solving the problem

[0014] The present application is as described below.

[0015] [1] The laminate according to the present application includes:

[0016] a film;

[0017] a resin layer containing a thermoplastic polyimide resin, and formed on at least one face of the film;

[0018] a catalyst layer containing palladium and a dispersant covering the palladium, and formed on the resin layer; and

[0019] an electroless plating layer containing nickel and copper, and formed on the catalyst layer,

[0020] the content of the nickel is 8.0 mass% or more and 13.0 mass% or less with respect to the total mass of the electroless plating layer.

[0021] [2] The amount of the palladium contained in the catalyst layer can be 0.05 mg or more and 0.18 mg or less with respect to 1 dm 2 the surface of the resin layer.

[0022] [3] The laminate can further include an electrolytic plating layer containing copper, and formed on the electroless plating layer.

[0023] [4] The manufacturing method of a circuit board according to the present application includes:

[0024] a resist layer forming step of forming a resist layer on the electroless plating layer constituting the laminate according to the above-mentioned [1];

[0025] an exposure step of exposing the resist layer;

[0026] a resist pattern forming step of forming a resist pattern corresponding to a wiring to be formed by developing the resist layer exposed in the exposure step;

[0027] a wiring layer forming step of forming a wiring layer having conductivity on the electroless plating layer exposed after the resist pattern forming step;

[0028] a resist pattern removing step of removing the resist pattern;

[0029] a rapid etching step of removing the electroless plating layer exposed after the resist pattern removing step; and

[0030] a catalyst layer removing step of removing the catalyst layer exposed after the rapid etching step.

[0031] [5] The manufacturing method of a circuit substrate according to the present application comprises:

[0032] an electrolytic plating layer forming step of forming an electrolytic plating layer on the electroless plating layer constituting the laminate according to the above [1];

[0033] a resist layer forming step of forming a resist layer on the electrolytic plating layer;

[0034] an exposure step of exposing the resist layer;

[0035] a resist pattern forming step of forming a resist pattern corresponding to a wiring to be formed by developing the resist layer exposed in the exposure step;

[0036] a wiring layer forming step of forming a wiring layer having conductivity on the electrolytic plating layer exposed after the resist pattern forming step;

[0037] a resist pattern removing step of removing the resist pattern;

[0038] a rapid etching step of removing the electrolytic plating layer exposed after the resist pattern removing step, and the electroless plating layer formed under the electrolytic plating layer; and

[0039] a catalyst layer removing step of removing the catalyst layer exposed after the rapid etching step.

[0040] [6] The manufacturing method of a circuit substrate according to the present application comprises:

[0041] a resist layer forming step of forming a resist layer on the electrolytic plating layer constituting the laminate according to the above [3];

[0042] an exposure step of exposing the resist layer;

[0043] a resist pattern forming step of developing the resist layer exposed in the exposure step to form a resist pattern corresponding to the wiring to be formed;

[0044] a wiring layer forming step of forming a conductive wiring layer on the electrolytic plating layer exposed after the resist pattern forming step;

[0045] a resist pattern removing step of removing the resist pattern;

[0046] a rapid etching step of removing the electrolytic plating layer exposed after the resist pattern removal step and the electroless plating layer formed under the electrolytic plating layer; and

[0047] The catalyst layer removal step removes the catalyst layer exposed after the rapid etching step.

[0048] Effects of the Invention

[0049] According to the present invention, there can be provided a laminate having excellent acid resistance and interlayer adhesion, and a method for producing a circuit board using the laminate. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] [ Figure 1 ] is a schematic cross-sectional view of a stacked body according to an embodiment.

[0051] [ Figure 2 ] is a schematic cross-sectional view of a stacked body according to an embodiment. DETAILED DESCRIPTION

[0052] Hereinafter, a method for manufacturing a laminate and a circuit substrate as a mode for implementing the present invention (hereinafter referred to as an embodiment) will be described in detail. The following embodiments are examples for illustrating the present invention and are not intended to limit the present invention to the following contents. The present invention can be implemented by appropriately modifying it within the scope of its main purpose.

[0053] [Laminated body 10]

[0054] like Figure 1 As shown, the laminate 10 of the embodiment includes: a membrane 11; a resin layer 13, which contains a thermoplastic polyimide resin and is formed on at least one surface of the membrane 11; a catalyst layer 15, which contains palladium and a dispersant covering the palladium and is formed on the resin layer 13; and an electroless plating layer 17, which contains nickel and copper and is formed on the catalyst layer 15.

[0055] The laminate 10 has excellent acid resistance and interlayer adhesion by being configured as described above. In addition, the reliability of the circuit of the circuit board using such a laminate 10 is improved. Hereinafter, the film 11, the resin layer 13, the catalyst layer 15, and the electroless plating layer 17 that constitute the laminate 10 will be described respectively.

[0056] (Film 11)

[0057] The film 11 is preferably a film having dimensional stability, heat resistance, dielectric properties, and the like. As a resin constituting a film having these properties, for example, thermosetting polyimide, polyamide-imide, liquid crystal polymer, polyphenylene sulfide, syndiotactic polystyrene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polybutylene terephthalate, polyether ether ketone, polyether sulfone, polyphenylene ether, fluorine-based resin, and the like can be given.

[0058] Among the resins described above, thermosetting polyimide having excellent heat resistance and dimensional stability, liquid crystal polymer having excellent dielectric properties, and fluorine-based resin are preferable. In addition, these resins are also preferable from the viewpoint of having excellent processability. The resin constituting the film 11 can be composed of one kind of resin or two or more kinds of resins.

[0059] From the viewpoint of relaxing stress generated when the electroless plating layer 17 is formed in the laminate 10 and the viewpoint of improving processability, the thickness of the film 11 is preferably, for example, 5 μm or more and 100 μm or less, more preferably 7.5 μm or more and 100 μm or less, and further preferably 10 μm or more and 50 μm or less.

[0060] From the viewpoint of relaxing stress generated when the electroless plating layer 17 is formed and the viewpoint of improving processability, the tensile elastic modulus of the film 11 is preferably, for example, 2 GPa or more and 10 GPa or less, and more preferably 3 GPa or more and 8 GPa or less. By this, stress generated when the electroless plating layer 17 is formed is relaxed, and peeling between the catalyst layer 15 and the electroless plating layer 17 is suppressed. That is, a laminate 10 having excellent interlayer adhesion can be obtained. The tensile elastic modulus of the film 11 can be measured by a measurement method according to JIS K 7161.

[0061] (Resin layer 13)

[0062] The resin constituting the resin layer 13 contains a thermoplastic polyimide resin. By causing the resin layer 13 to contain a thermoplastic polyimide resin, the interlayer adhesion of the resin layer 13 to the film 11 is improved. In addition, since the thermoplastic polyimide resin has high affinity with the dispersant contained in the catalyst layer 15, the interlayer adhesion of the resin layer 13 to the catalyst layer 15 is improved. The amount of the thermoplastic polyimide resin contained in the resin layer 13 is, for example, 1% by mass or more and 100% by mass or less, preferably 20% by mass or more and 100% by mass or less, and more preferably 40% by mass or more and 100% by mass or less, with respect to the mass of the entire resin layer 13. Note that the amount of the thermoplastic polyimide resin contained in the resin layer 13 indicates the amount of only the thermoplastic polyimide resin excluding volatile components such as organic solvents.

[0063] The thermoplastic polyimide contained in the resin layer 13 is composed of, for example, a condensation type polyimide. The condensation type polyimide is obtained by copolymerizing an acid dianhydride and a diamine.

[0064] As the acid dianhydride, an acid dianhydride that undergoes a condensation reaction with a diamine is sufficient. As the acid dianhydride, for example, 3,4,3',4'-biphenyltetracarboxylic dianhydride, 2,3,3',4'-biphenyltetracarboxylic dianhydride, 2,3,2',3'-biphenyltetracarboxylic dianhydride, pyromellitic dianhydride, 2,3,6,7-naphthalene tetracarboxylic dianhydride, 1,2,5,6-naphthalene tetracarboxylic dianhydride, 3,3',4,4'-benzophenonetetracarboxylic dianhydride, 4,4'-oxydiphthalic dianhydride, 2,2-bis(3,4-dicarboxyphenyl)propane dianhydride, 3,4,9,10-perylenetetracarboxylic dianhydride, bis(3,4-dicarboxyphenyl)propane dianhydride, 1,1-bis(2,3-dicarboxyphenyl)ethane dianhydride, 1,1-bis(3,4-dicarboxyphenyl)ethane dianhydride, bis(2,3-dicarboxyphenyl)methane dianhydride, bis(3,4-dicarboxyphenyl)ethane dianhydride, bis(3,4-dicarboxyphenyl)sulfone dianhydride, p-phenylene bis(trimellitic monoester anhydride), ethylene bis(trimellitic monoester anhydride), and bisphenol A bis(trimellitic monoester anhydride) can be mentioned.

[0065] As the diamine, only one that is used for the condensation reaction with the acid dianhydride is necessary. As the diamine, for example, p-phenylenediamine, m-phenylenediamine, 2,4-diaminotoluene, 4,4'-diaminobiphenyl, 4,4'-diamino-2,2'-bis(trifluoromethyl)biphenyl, 3,3'-diaminodiphenyl sulfone, 4,4'-diaminodiphenyl sulfone, 4,4'-diaminodiphenyl sulfide, 4,4'-diaminodiphenyl methane, 4,4'-diaminodiphenyl ether, 3,4'-diaminodiphenyl ether, 3,3'-diaminodiphenyl ether, 4,4'-bis(4-aminophenoxy)biphenyl, bis[4-(4-aminophenoxy)phenyl]sulfone, bis[4-(3-aminophenoxy)phenyl]sulfone, 2,2-bis[4-(4-aminophenoxy)phenyl]propane, 2,2-bis[4-(4-aminophenoxy)phenyl]hexafluoropropane, 1,3-bis[2-(4-aminophenyl)-2-propyl]benzene, 1,4-bis[2-(4-aminophenyl)-2-propyl]benzene, 2,2'-dimethyl-4,4'-diaminobiphenyl, 2,2'-bis(trifluoromethyl)benzidine, 2,2-bis(4-aminophenoxyphenyl)isopropane, 1,3-bis(4-aminophenoxy)benzene, 1,4-bis(4-aminophenoxy)benzene, 1,3-bis(3-aminophenoxy)benzene, and the like can be given.

[0066] Further, in the case of the thermoplastic polyimide resin contained in the resin layer 13, from the viewpoint of improving the interlayer adhesion of the resin layer 13 and the catalyst layer 15, for example, it is preferable that the value of the storage modulus at 300°C be less than 20% of the value of the storage modulus at 30°C. The storage modulus can be measured by a dynamic viscoelasticity measurement method.

[0067] The tensile elastic modulus of the resin layer 13 is, for example, preferably 5 GPa or less. By making the tensile elastic modulus of the resin layer 13 5 GPa or less, the stress generated when the electroless plating layer 17 is formed on the catalyst layer 15 to be described later is moderated by the resin layer 13, and the interlayer peeling of the catalyst layer 15 and the electroless plating layer 17 is suppressed. The tensile elastic modulus of the resin layer 13 can be measured in accordance with JIS K7161.

[0068] The resin layer 13 is formed on at least one side of the film 11. The thickness of the resin layer 13 can be, for example, 0.01 μm or more and 10.0 μm or less, and is preferably 0.02 μm or more and 1.0 μm or less, as long as the adhesion of the resin layer 13 and the catalyst layer 15 can be improved.

[0069] (Catalyst layer 15)

[0070] The catalyst layer 15 is laminated on the resin layer 13. The catalyst layer 15 contains palladium which binds to copper contained in the electroless plating layer 17, and a dispersing agent which covers the palladium. The electroless plating layer 17 is formed using the palladium as a base. Thus, the interlayer adhesion of the electroless plating layer 17 and the catalyst layer 15 is improved. The amount of palladium contained in the catalyst layer 15 is, for example, 0.05 mg or more and 0.18 mg or less, preferably 0.08 mg or more and 0.18 mg or less, and more preferably 0.10 mg or more and 0.16 mg or less, with respect to the surface of the resin layer 13 per unit area of 1 dm2. 2 The amount of palladium contained in the catalyst layer 15 is, for example, 0.05 mg or more and 0.18 mg or less, preferably 0.08 mg or more and 0.18 mg or less, and more preferably 0.10 mg or more and 0.16 mg or less, with respect to the surface of the resin layer 13 per unit area of 1 dm2.

[0071] The dispersing agent which covers the palladium is composed of a compound which can bond to palladium, and is, for example, a nitrogen-containing compound which contains nitrogen in a terminal functional group and / or a compound having an unsaturated bond. The bond of palladium to the compound is, for example, a coordination bond, an ionic bond, or a covalent bond. As the nitrogen-containing compound, for example, a polymer having an ammonium group in a terminal functional group can be given. As the compound having an unsaturated bond, for example, acrylic acid polyethylene glycol alkylether or the like can be given. From the viewpoint of improving the interlayer adhesion of the catalyst layer 15 and the resin layer 13, the dispersing agent is preferably a nitrogen-containing compound, and more specifically, a polymer having an ammonium group in a terminal functional group is preferred.

[0072] (Electroless plating layer 17)

[0073] The electroless plating layer 17 contains nickel and copper, and is laminated on the catalyst layer 15. The content of nickel is 8.0 mass% or more and 13.0 mass% or less with respect to the total mass of the electroless plating layer 17. The electroless plating layer 17 containing nickel in the above amount has a large amount of nickel at the boundary surface of the electroless plating layer 17 which is in contact with the catalyst layer 15. In other words, copper is less at the boundary surface of the electroless plating layer 17 which is in contact with the catalyst layer 15, and thus even if an acidic chemical solution intrudes into the interface between the catalyst layer 15 and the electroless plating layer 17, the electroless plating layer 17 is not easily eroded. Thus, the acid resistance of the laminate 10 composed of the electroless plating layer 17 containing nickel in the above amount is improved. Furthermore, since the content of nickel is the above content, the electroless plating layer 17 which should be removed in the rapid etching process described later can be reliably removed. The content of nickel can be found by inductively coupled plasma (ICP) emission spectroscopy.

[0074] The thickness of the electroless plating layer 17 can be, for example, 0.05 μm or more and 2.0 μm or less, and more preferably 0.10 μm or more and 2.0 μm or less, as long as a uniform electroless plating layer 17 can be formed on the catalyst layer 15.

[0075] The laminate 10 described above, which is composed of the film 11, the resin layer 13, the catalyst layer 15, and the electroless plating layer 17, has excellent acid resistance and interlayer adhesion. Therefore, the reliability of the circuit of the circuit board using the laminate 10 is improved.

[0076] Note that, regarding the film 11 described above, a gas barrier layer that suppresses the permeation of oxygen can be formed on at least one surface of the film 11 from the viewpoint of reducing the intrusion of oxygen into the laminate 10. By forming the gas barrier layer on the film 11, the intrusion of oxygen into the laminate 10 can be suppressed. The laminate 10 composed of such a film 11 has less intrusion of oxygen even when exposed to a high-temperature atmosphere of, for example, 150°C for 400 hours or more, and thus the oxidation of the electroless plating layer 17 can be suppressed. As a result, the interlayer adhesion between the catalyst layer 15 and the electroless plating layer 17 is improved. Further, since the permeation of oxygen through such a film 11 is small, the degradation of the resin layer 13 caused by oxygen can be suppressed, and the interlayer adhesion between the film 11 and the resin layer 13 is improved.

[0077] Further, the electroless plating layer 17, which is suppressed from being oxidized, has resistance to erosion by an acidic chemical solution. As a result, for example, even when an acidic chemical solution intrudes into the interface between the catalyst layer 15 and the electroless plating layer 17, the electroless plating layer 17 is not easily eroded. The laminate 10 composed of such a film 11 has improved acid resistance.

[0078] The gas barrier layer described above is composed of, for example, silicon dioxide, zinc oxide, or the like. The thickness of the gas barrier layer is, for example, preferably 10 nm or more and 100 nm or less.

[0079] In addition, an electrolytic plating layer 19 can be further formed on the electroless plating layer 17 of the laminate 10. That is, as shown in FIG. 2, the laminate 20 of the embodiment has a film 11, a resin layer 13 formed on at least one surface of the film 11, a catalyst layer 15 formed on the resin layer 13, an electroless plating layer 17 formed on the catalyst layer 15, and an electrolytic plating layer 19 formed on the electroless plating layer 17. Figure 2

[0080] ​In the case of the laminate 20, since the electrolytic plating layer 19 having superior conductivity to the non-electrolytic plating layer 17 is provided on the surface of the laminate, the surface resistivity of the surface can be reduced to, for example, 0.1 Ω / D. Further, in the production of a circuit substrate, a wiring layer having conductivity can be formed on the electrolytic plating layer 19 in a short time. From the viewpoint of interlayer adhesion with the non-electrolytic plating layer 17, the electrolytic plating layer 19 preferably contains copper. From the viewpoint of easy formation of a wiring layer, the thickness of the electrolytic plating layer 19 is, for example, preferably 0.1 μm or more and 35.0 μm or less, more preferably 0.2 μm or more and 18.0 μm or less. Note that the films, the resin layer, the catalyst layer, and the non-electrolytic plating layer constituting the laminate 20 are the same as those constituting the laminate 10, and thus the same reference numerals as those in the laminate 10 are given.

[0081] (Method for producing the laminate 10 in which the resin layer 13, the catalyst layer 15, and the non-electrolytic plating layer 17 are sequentially formed on one surface of the film 11)

[0082] The laminate 10 in which the resin layer 13, the catalyst layer 15, and the non-electrolytic plating layer 17 are sequentially formed on one surface of the film 11 can be produced, for example, by the following production method.

[0083] First, a resin composition containing polyamic acid as a thermoplastic polyimide resin precursor is applied to one surface of the film 11, and heated at 60°C or higher and 120°C or lower for 1 minute or more and 30 minutes or less to form the resin layer 13. A catalyst liquid containing palladium and a dispersant is applied to the resin layer 13, and heated at 80°C or higher and 150°C or lower for 1 minute or more and 60 minutes or less to form the catalyst layer 15. Then, the laminate 10 in which the resin layer 13 and the catalyst layer 15 are sequentially formed on one surface of the film 11 is heated at 200°C or higher and 300°C or lower for 1 minute or more and 30 minutes or less in order to imidize the polyamic acid contained in the resin composition to obtain a thermoplastic polyimide resin.

[0084] Next, the laminate 10 is immersed in a plating solution containing nickel and copper and having a pH of 7 or higher and 10 or lower for 30 seconds or more and 30 minutes or less to form the non-electrolytic plating layer 17 on the catalyst layer 15. Then, the laminate 10 is subjected to heat treatment (annealing treatment) at 120°C or higher and 350°C or lower for 1 minute or more and 60 minutes or less in a nitrogen atmosphere to obtain the laminate 10 in which the resin layer 13, the catalyst layer 15, and the non-electrolytic plating layer 17 are sequentially formed on one surface of the film 11.

[0085] As the plating solution which can be used, any solution can be used as long as an electroless plated layer 17 can be formed, and for example, an electroless nickel plating solution or the like can be given. As an example, OPC ALOCOPPER solution manufactured by Ono Pharmaceutical Co., Ltd. can be given. The concentration of nickel contained in the plating solution is, for example, 0.10 g / L or more and 0.40 g / L or less, and the concentration of copper is, for example, 2.0 g / L or more and 4.0 g / L or less.

[0086] Note that the laminate 10 obtained above can be immersed in an electrolytic plating solution containing copper, for example, at 0.05 A / dm2or more and 10.0 A / dm2or less for 1 minute or more and 60 minutes or less. 2 The above 10.0 A / dm2 2 The electrolytic plating treatment is performed for 1 minute or more and 60 minutes or less, and a laminate 20 in which an electrolytic plated layer 19 is further formed on the electroless plated layer 17 is obtained. As the electrolytic plating solution which can be used, for example, an electrolytic copper plating solution containing copper sulfate, an electrolytic copper plating solution containing copper pyrophosphate, an electrolytic copper plating solution containing copper cyanide, or the like can be given. As an example, Top Lucina SF solution manufactured by Ono Pharmaceutical Co., Ltd. can be given. The concentration of copper sulfate pentahydrate contained in the solution is, for example, 60 g / L or more and 110 g / L or less.

[0087] (Method for manufacturing laminate in which resin layer 13, catalyst layer 15, and electroless plated layer 17 are sequentially formed on both surfaces of film 11)

[0088] A laminate in which resin layers 13, catalyst layers 15, and electroless plated layers 17 are sequentially formed on both surfaces of a film 11 can be manufactured, for example, by the following manufacturing method. First, a resin composition containing polyamic acid which is a thermoplastic polyimide resin precursor is applied to both surfaces of the film, and heating is performed at 60°C or more and 250°C or less for 1 minute or more and 30 minutes or less, and resin layers 13 are formed on both surfaces of the film 11. A catalyst solution containing palladium and a dispersant is applied to the resin layers 13, and heating is performed at 80°C or more and 150°C or less for 1 minute or more and 60 minutes or less, and catalyst layers 15 are formed. Then, in order to imidize the polyamic acid contained in the resin composition and obtain a thermoplastic polyimide resin, the laminate in which resin layers 13 and catalyst layers 15 are sequentially formed on both surfaces of the film 11 is heated at 200°C or more and 300°C or less for 1 minute or more and 30 minutes or less.

[0089] Next, the laminate is immersed in a plating solution containing nickel and copper and having a pH of 7 or more and 10 or less for 30 seconds or more and 30 minutes or less, and an electroless plated layer 17 is formed on the catalyst layer 15. Then, the laminate is subjected to heat treatment at 120°C or more and 350°C or less in a nitrogen atmosphere for 1 minute or more and 60 minutes or less, and a laminate in which resin layers 13, catalyst layers 15, and electroless plated layers 17 are sequentially formed on both surfaces of the film 11 is obtained.

[0090] As the plating solution which can be used in the manufacturing method, the same plating solution as that used in the manufacturing method of the laminate 10 in which the resin layer 13, the catalyst layer 15, and the electroless plating layer 17 are sequentially formed on one surface of the film 11 can be cited.

[0091] Note that, by immersing the laminate obtained above in an electrolytic plating solution containing copper, for example, at 0.05 A / dm2for 1 minute or more and 60 minutes or less, the electroless plating layer 17 can be covered with an electrolytic plating layer 19. 2 The above 10.0 A / dm2 2 The electrolytic plating treatment is performed for 1 minute or more and 60 minutes or less, whereby a laminate in which the electroless plating layer 17 is further provided with an electrolytic plating layer 19 is obtained. As the electrolytic plating solution which can be used, for example, an electrolytic copper plating solution containing copper sulfate, an electrolytic copper plating solution containing copper pyrophosphate, an electrolytic copper plating solution containing copper cyanide, or the like can be cited. As an example, Top Lucina SF solution manufactured by Ono Pharmaceutical Co., Ltd. can be cited. The concentration of copper sulfate pentahydrate contained in this solution is, for example, 60 g / L or more and 110 g / L or less.

[0092] In addition, in the step of forming the catalyst layer 15 in the above-described two manufacturing methods of the laminate, as the catalyst solution which can be used, for example, a catalyst solution containing a dispersant, palladium covered with the dispersant, and a solvent can be cited. The dispersant is composed of a compound capable of bonding with palladium, and, for example, a nitrogen-containing compound in which a nitrogen-containing functional group is present at the terminal and / or a compound having an unsaturated bond can be cited. The bond between palladium and the compound is, for example, a coordination bond, an ionic bond, or a covalent bond, and, from the viewpoint of dispersibility, a coordination bond is preferred. As the nitrogen-containing compound, for example, a polymer having an ammonium group at the terminal can be cited. As the compound having an unsaturated bond, for example, an acrylic acid polyethylene glycol alkyl ether or the like can be cited. The content of the dispersant contained in the catalyst solution is 0.1% by mass or more and 90% by mass or less, preferably 0.2% by mass or more and 50% by mass or less, and more preferably 0.3% by mass or more and 30% by mass or less, with respect to the mass of the entire catalyst solution. By using such a catalyst solution, palladium can be uniformly attached to the surface of the resin layer.

[0093] [Manufacturing method of circuit board]

[0094] A manufacturing method of a circuit board using the laminate 10 will be described taking the laminate 10 in which the resin layer 13, the catalyst layer 15, and the electroless plating layer 17 are sequentially formed on one surface of the film 11 as an example.

[0095] The manufacturing method of the circuit board includes a resist layer forming step, an exposure step, a resist pattern forming step, a wiring layer forming step, a resist pattern removing step, a rapid etching step, and a catalyst layer removing step.

[0096] (resist layer forming step)

[0097] A resist layer for forming a resist pattern is formed on the electroless plating layer. As a resist material constituting the resist layer, a positive resist material and a negative resist material can be used as long as a resist pattern can be formed by developing after exposure. In the case of the positive resist material, it is dissolved in a developing solution by being exposed to light, and is not dissolved in the developing solution if not exposed to light. As a positive resist material, for example, a positive resist liquid and a positive dry film can be used. In the case of the negative resist material, it is not dissolved in the developing solution if exposed to light, and is dissolved in the developing solution if not exposed to light. As a negative resist material, for example, a negative resist liquid and a negative dry film can be used.

[0098] In the resist layer forming step, a positive resist material can be used to form the resist layer, or a negative resist material can be used to form the resist layer.

[0099] The resist layer forming step of the present embodiment is described taking the case of forming a resist layer using a negative dry film as an example. The negative dry film is laminated on the electroless plating layer, and is subjected to heat and pressure. The conditions of heat and pressure are such that the electroless plating layer and the negative dry film are tightly bonded, and, for example, in the case of using a vacuum laminator, are 30°C or higher and 100°C or lower, 0.1 MPa or higher and 1.0 MPa or lower, and 5 seconds or longer and 60 seconds or shorter. Thus, a resist layer is formed on the electroless plating layer. The heat and pressure can be applied in a reduced-pressure atmosphere.

[0100] Note that, in the case of using a negative resist liquid, the negative resist liquid can be applied on the electroless plating layer, and is subjected to heat. Thus, a resist layer composed of the negative resist liquid is formed on the electroless plating layer.

[0101] (exposure step)

[0102] In order to form a resist pattern, the resist layer is exposed to light through a photomask. The photomask used in this step is a photomask corresponding to a wiring to be formed, and, for example, has a light-shielding region that shields light and is formed in a desired circuit shape, and an opening region that allows light to pass through. The wavelength of light used at the time of exposure is a wavelength that allows a fine pattern to be formed, and, for example, is 200 nm or higher and 500 nm or lower. As the exposure conditions, conditions that allow a fine pattern to be formed can be used, and, for example, a high-pressure mercury lamp can be used, and the cumulative light amount can be set to 50 mJ / cm 2 1500 mJ / cm 2 The following conditions.

[0103] (resist pattern forming step)

[0104] The exposed resist layer is developed. If the resist layer is exposed through the photomask and developed, only the resist layer of the portion not exposed to light dissolves in the developer, and the electroless plating layer located directly below the dissolved resist layer is exposed. By the exposure and development, a resist pattern is formed in the resist layer. In the wiring layer forming step of the next step, by performing electrolytic plating on the layered body on which the resist pattern is formed, for example, a wiring layer having conductivity is formed.

[0105] Note that as the developer used at the time of development, a water-soluble solution having alkalinity such as a sodium carbonate aqueous solution can be mentioned, for example. Further, the resist pattern of the present embodiment means a resist layer formed into a shape corresponding to the profile of the opening region of the photomask by exposure and development.

[0106] (Wiring layer forming step)

[0107] A wiring layer having conductivity is formed on the exposed electroless plating layer 17. The wiring layer can be formed by electrolytic plating, for example. The method of performing electrolytic plating can be any method that can form a wiring layer on the electroless plating layer. For example, a method in which a device that can flow electricity in an electrolytic plating solution containing copper and can perform plating on the layered body 10 is prepared, and then the layered body 10 is immersed in the electrolytic plating solution at a current density of 0.05 A / dm2 or more and 10.0 A / dm2 or less for 1 minute or more and 60 minutes or less can be mentioned. 2 10.0 A / dm2 or less for 1 minute or more and 60 minutes or less can be mentioned. 2 The electrolytic plating treatment is performed for 1 minute or more and 60 minutes or less. As the electrolytic plating solution containing copper used at this time, a copper sulfate plating solution, a copper pyrophosphate plating solution, a copper cyanide plating solution can be mentioned, for example. As an example, Top Lucina SF solution manufactured by Ono Pharmaceutical Co., Ltd. can be mentioned. The concentration of copper sulfate pentahydrate contained in this solution is 60 g / L or more and 110 g / L or less.

[0108] (Resist pattern removing step)

[0109] After the wiring layer is formed in the wiring layer forming step, the resist pattern is removed. As the solvent used when the resist pattern is removed, a solvent that can remove the resist material constituting the resist pattern can be used, and an organic amine-based solvent, a ketone-based solvent, an alkali-based solvent, and the like can be mentioned, for example.

[0110] (Rapid etching step)

[0111] The electroless plating layer 17 exposed by removing the resist pattern is removed. As an etching solution used when the exposed electroless plating layer 17 is removed, for example, a sulfuric acid hydrogen peroxide-based etching solution, a sodium persulfate-based etching solution, a ferric chloride-based etching solution, a copper chloride-based etching solution, or the like can be given, as long as it is an etching solution capable of removing the electroless plating layer 17 containing nickel and copper. Note that since the wiring layer is thicker than the electroless plating layer 17, the fast etching process has a small effect on the wiring layer.

[0112] (Catalyst layer removing process)

[0113] The catalyst layer 15 exposed by removing the electroless plating layer 17 is removed. As a chemical solution used when the exposed catalyst layer 15 is removed, for example, a hydrochloric acid-based chemical solution, a nitric acid-based chemical solution, a permanganate-based chemical solution, or the like can be given, as long as it is a chemical solution capable of removing the catalyst layer 15 containing palladium.

[0114] Through the above processes, the circuit substrate can be obtained.

[0115] [Method for manufacturing circuit substrate including electroless plating layer forming process]

[0116] Next, a method for manufacturing a circuit substrate including an electroless plating layer forming process will be described with reference to the laminate 10 used also in the above-described method for manufacturing a circuit substrate, that is, the laminate 10 in which the resin layer 13, the catalyst layer 15, and the electroless plating layer 17 are sequentially formed on one surface of the film 11.

[0117] The method for manufacturing a circuit substrate includes an electroless plating layer forming process, a resist layer forming process, an exposure process, a resist pattern forming process, a wiring layer forming process, a resist pattern removing process, a fast etching process, and a catalyst layer removing process. Hereinafter, the method for manufacturing a circuit substrate including an electroless plating layer forming process differs from the above-described method for manufacturing a circuit substrate in that the method for manufacturing a circuit substrate including an electroless plating layer forming process includes the electroless plating layer forming process before the resist layer forming process. Hereinafter, the electroless plating layer forming process will be described in detail, and the processes other than the electroless plating layer forming process will be described only in outline.

[0118] (Electroless plating layer forming process)

[0119] On the electrolytic plating layer 19, a resist layer for forming a resist pattern corresponding to the wiring to be formed is formed. In the resist layer forming step, a positive resist material can be used to form the resist layer, or a negative resist material can be used to form the resist layer. In the resist layer forming step of the present embodiment, a resist layer forming step using a dry film type negative resist material is described as an example. A dry film is layered on the electrolytic plating layer 19, and heating and pressing are performed. The conditions for heating and pressing can be any conditions that allow the electrolytic plating layer 19 to adhere to the dry film, and, for example, in the case of using a vacuum laminator, 30°C or higher and 100°C or lower, 0.1 MPa or higher and 1.0 MPa or lower, and 5 seconds or longer and 60 seconds or shorter. As a result, a resist layer is formed on the electrolytic plating layer 19. The heating and pressing can also be performed in a reduced pressure atmosphere. 2 The above 10.0 A / dm 2 The electrolytic plating process is performed for 1 minute or longer and 60 minutes or shorter.

[0120] As the electrolytic plating solution containing copper used at this time, for example, a copper sulfate plating solution, a copper pyrophosphate plating solution, or a copper cyanide plating solution can be used. The concentration of copper contained in the electrolytic plating solution is, for example, 10 g / L or higher and 110 g / L or lower. As an example, Top Lucina SF solution manufactured by Ono Pharmaceutical Industrial Co., Ltd. can be used. The concentration of copper sulfate pentahydrate contained in this solution is 60 g / L or higher and 110 g / L or lower. By further layering the electrolytic plating layer 19 on the electroless plating layer 17 in this process, the electrolytic plating layer 19 having higher conductivity than the electroless plating layer 17 can be provided on the surface of the layered body. As a result, the surface resistivity of the surface of the layered body can be reduced to, for example, 0.1 Ω / □. In addition, by reducing the surface resistivity to 0.1 Ω / □, it is easy to form a wiring layer having conductivity on the electrolytic plating layer 19. The surface resistivity can be measured in accordance with JIS K7194.

[0121] (Resist layer forming step)

[0122] On the electrolytic plating layer 19, a resist layer for forming a resist pattern corresponding to the wiring to be formed is formed. In the resist layer forming step, a positive resist material can be used to form the resist layer, or a negative resist material can be used to form the resist layer. In the resist layer forming step of the present embodiment, a resist layer forming step using a dry film type negative resist material is described as an example. A dry film is layered on the electrolytic plating layer 19, and heating and pressing are performed. The conditions for heating and pressing can be any conditions that allow the electrolytic plating layer 19 to adhere to the dry film, and, for example, in the case of using a vacuum laminator, 30°C or higher and 100°C or lower, 0.1 MPa or higher and 1.0 MPa or lower, and 5 seconds or longer and 60 seconds or shorter. As a result, a resist layer is formed on the electrolytic plating layer 19. The heating and pressing can also be performed in a reduced pressure atmosphere.

[0123] Note that, in the case of using the resist liquid as the resist material, the resist liquid can be applied on the electrolytic plating layer 19 and heated. Thus, the resist layer composed of the resist liquid is formed on the electrolytic plating layer 19.

[0124] (exposure step)

[0125] In order to form the resist pattern, the resist layer is exposed through a photomask.

[0126] (resist pattern formation step)

[0127] The exposed resist layer is developed. Thus, the resist pattern corresponding to the wire to be formed is formed on the electrolytic plating layer 19.

[0128] (wire layer formation step)

[0129] The wire layer is formed on the exposed electrolytic plating layer 19 by electrolytic plating of the layered body 10 on which the resist pattern is formed.

[0130] (resist pattern removal step)

[0131] The resist pattern is removed.

[0132] (rapid etching step)

[0133] The electrolytic plating layer 19 exposed by the removal of the resist pattern and the electroless plating layer 17 formed under the electrolytic plating layer 19 are removed. As the etching liquid used when these layers are removed, an etching liquid capable of removing the electrolytic plating layer 19 containing copper and the electroless plating layer 17 containing nickel and copper, for example, a sulfuric acid hydrogen peroxide-based etching liquid, a sodium persulfate-based etching liquid, a ferric chloride-based etching liquid, a copper chloride-based etching liquid, and the like can be used.

[0134] (catalyst layer removal step)

[0135] The catalyst layer 15 exposed by the removal of the electroless plating layer 17 is removed.

[0136] Thus, according to the method for manufacturing a circuit substrate including the electrolytic plating layer formation step, the circuit substrate can be obtained.

[0137] [Method for manufacturing a circuit substrate using a layered body 20 on which an electrolytic plating layer 19 is formed on an electroless plating layer 17]

[0138] A manufacturing method of a circuit board using the laminate 20 will be described with the laminate 20 in which the electrolytic plating layer 19 is formed on the non-electrolytic plating layer 17, that is, the laminate 20 in which the resin layer 13, the catalyst layer 15, the non-electrolytic plating layer 17, and the electrolytic plating layer 19 are sequentially formed on one side of the film 11 as an example.

[0139] The manufacturing method of the circuit board includes a resist layer forming step, an exposure step, a resist pattern forming step, a wiring layer forming step, a resist pattern removing step, a rapid etching step, and a catalyst layer removing step. Hereinafter, the manufacturing method of the circuit board using the laminate 20 in which the electrolytic plating layer 19 is formed on the non-electrolytic plating layer 17 includes substantially the same steps as the above-described manufacturing method of the circuit board, and thus only a summary will be described.

[0140] (resist layer forming step)

[0141] A resist layer for forming a resist pattern is formed on the electrolytic plating layer 19.

[0142] (exposure step)

[0143] The resist layer is exposed through a photomask in order to form the resist pattern.

[0144] (resist pattern forming step)

[0145] The exposed resist layer is developed. Thus, the resist pattern corresponding to the wiring to be formed is formed on the electrolytic plating layer 19.

[0146] (wiring layer forming step)

[0147] The laminate 20 on which the resist pattern is formed is electrolytic-plated to form a conductive wiring layer on the exposed electrolytic plating layer 19.

[0148] (resist pattern removing step)

[0149] The resist pattern is removed.

[0150] (rapid etching step)

[0151] The electrolytic plating layer 19 exposed by removing the resist pattern and the non-electrolytic plating layer 17 formed under the electrolytic plating layer 19 are removed.

[0152] (catalyst layer removing step)

[0153] The catalyst layer 15 exposed by removing the non-electrolytic plating layer 17 is removed.

[0154] As described above, according to the manufacturing method of the circuit substrate using the laminate 20 in which the electrolytic plating layer 19 is further formed on the non-electrolytic plating layer 17, the circuit substrate can be obtained.

[0155] The manufacturing method of the circuit substrate of the present embodiment has been described above with the laminate 10 in which the resin layer 13, the catalyst layer 15, and the non-electrolytic plating layer 17 are sequentially formed on one side of the film 11, and the laminate 20 in which the electrolytic plating layer 19 is further formed on the non-electrolytic plating layer 17 as examples.

[0156] Note that, the laminates are not limited to these, and for example, a laminate in which the resin layer 13, the catalyst layer 15, and the non-electrolytic plating layer 17 are sequentially formed on both sides of the film 11, or a laminate in which the resin layer 13, the catalyst layer 15, the non-electrolytic plating layer 17, and the electrolytic plating layer 19 are sequentially formed on both sides of the film can be used. In the manufacturing method of the circuit substrate of the present embodiment, various photo-etching processes can be appropriately selected.

[0157] Example

[0158] The present application will be described in more detail by examples below. The present application is not limited to the following examples.

[0159] (Example 1)

[0160] (Production of the laminate)

[0161] (1) Production of the resin layer 13

[0162] (1-1) Preparation of the polyamic acid solution

[0163] In a reaction vessel, N,N-dimethylacetamide (manufactured by Mitsubishi Gas Chemical Company, Inc., DMAc) 85 g, 2,2-bis[4-(4-aminophenoxy)phenyl]propane (manufactured by Wako Pure Chemical Industries, Ltd., BAPP) 1.034 g (0.003 mol), and 1,3-bis(4-aminophenoxy)benzene (manufactured by Wako Pure Chemical Industries, Ltd., TPE-R) 6.628 g (0.023 mol) were added, and stirring was performed at room temperature to dissolve BAPP and TPE-R in DMAc. To the obtained solution, 3,4,3',4'-biphenyltetracarboxylic dianhydride (manufactured by Ube Industries, Ltd., BPDA) 7.338 g (0.025 mol) was gradually added, and stirring was performed at room temperature for 3 hours to obtain a resin composition containing polyamic acid. The obtained resin composition was diluted with DMAc so that the solid content concentration became 2% by mass, and a polyamic acid solution was obtained.

[0164] (1-2) Formation of the resin layer 13

[0165] The polyamide acid solution prepared in the above was applied to one side of a polyimide film (manufactured by DU PONT-TORAY Co., Ltd., Kapton (registered trademark) 100EN-C) having a thickness of 25 μm as the film 11 using a bar coater so that the thickness after heating became 100 nm. After the application, heating was performed at 120°C for 5 minutes to obtain a laminate in which the resin layer 13 was formed on one side of the polyimide film.

[0166] (2) Production of the catalyst layer 15

[0167] On the resin layer 13 of the laminate obtained in (1-2), a catalyst solution containing 0.45 mass% of palladium (manufactured by Nippon Shokubai Co., Ltd., CP-018) was applied using a bar coater. After the application, heating was performed at 120°C for 10 minutes to obtain a laminate in which the catalyst layer 15 was formed on the resin layer 13. The laminate was further heated at 240°C for 15 minutes. Note that it was confirmed that the surface of the resin layer 13 of the obtained laminate had 1 dm2per unit area. 2 0.15 mg of palladium was attached. The attached amount of palladium was measured by ICP emission spectroscopy. The device used at the time of measurement was ICPE-9800 series manufactured by Shimadzu Corporation.

[0168] (3) Production of the electroless plating layer 17

[0169] As an electroless plating solution used for laminating the electroless plating layer 17 on the catalyst layer 15, OPC ALOCOPPER (initial copper concentration 3.16 g / L, nickel concentration 0.14 g / L, sodium hypophosphite concentration 24 g / L) manufactured by Ono Pharmaceutical Co., Ltd. was prepared, and sodium hydroxide was added to the plating solution to prepare an electroless plating solution having a pH of 9.0. After the electroless plating solution was added to a plating bath, the liquid temperature was set to 50°C. The laminate obtained in (2) was immersed in the plating bath for 10 minutes. Then, the laminate was lifted, subjected to water washing and drying, and subjected to heat treatment at 300°C for 5 minutes in a nitrogen atmosphere. After the cooling, a laminate 10 in which the electroless plating layer 17 was formed on the catalyst layer 15 was obtained. Using the obtained laminate 10, the adhesion was evaluated.

[0170] The thickness of the electroless plating layer 17 of the obtained laminate 10 was 0.15 μm. The thickness of the electroless plating layer 17 was measured by ICP emission spectroscopy. The device used at the time of measurement was ICPE-9800 series manufactured by Shimadzu Corporation.

[0171] The content of nickel of the electroless plated layer 17 was 8.0 mass%. The content of nickel was found as follows. First, the laminate 10 on which the electroless plated layer 17 was formed was prepared by cutting into a square of 50 mm x 50 mm. Next, 15 mL of an aqueous solution obtained by mixing 60 mass% of a nitric acid aqueous solution, 35 mass% of a hydrochloric acid, and pure water in a ratio of 1 : 1 : 1 was put into a beaker. The beaker was heated, and after the aqueous solution boiled, the cut laminate 10 was put in, and stirred for 3 minutes while maintaining the boiling state. Then, it was cooled to room temperature, and the liquid in the beaker was all transferred to a 100 mL volumetric flask, and further, the residual liquid adhered to the beaker was washed with a small amount of pure water 3 times, and the liquid was also transferred to the volumetric flask. Then, pure water was added, and the volume was made 100 mL. Then, using an ICP emission spectroscopic analysis device, quantitative analysis of copper, nickel, and phosphorus contained in the obtained aqueous solution was performed. The weight of copper quantified by this measurement was 3.084 mg, the weight of nickel was 0.271 mg, and the weight of phosphorus was 0.024 mg. The obtained weights were substituted into (Y x 100) / (X + Y + Z) to calculate the weight of nickel with respect to the weight of the electroless plated layer 17.

[0172] (4) Production of the electrolytic plated layer 19

[0173] The electrolytic plating solution (Top Lucina SF manufactured by Ono Pharmaceutical Co., Ltd.) was filled in the plating bath, and the liquid temperature was made 25°C. The laminate 10 obtained in (3) was immersed in the plating bath at 1 A / dm2, and the electrolytic plating treatment was performed for 3 minutes. 2 The electrolytic plating treatment was performed for 3 minutes, and then the current density was changed to 2 A / dm2, and the electrolytic plating treatment was performed for 26 minutes. 2 The electrolytic plating treatment was performed for 26 minutes. Thus, the laminate 20 on which the electrolytic plated layer 19 having a thickness of 12 μm was formed was obtained. Using the obtained laminate 20, the acid resistance and the peeling strength were evaluated.

[0174] Note that, in the evaluation of the insulation resistance value, the following laminate 20 was used, that is, the laminate 10 obtained in (3) was immersed in the plating bath at 1 A / dm2, and the electrolytic plating treatment was performed for 10 minutes to form the laminate 20 on which the electrolytic plated layer 19 having a thickness of 2 μm was formed. 2 The electrolytic plating treatment was performed for 10 minutes to form the laminate 20 on which the electrolytic plated layer 19 having a thickness of 2 μm was formed.

[0175] The thickness of the electrolytic plated layer 19 of the obtained laminate 20 was measured using a micrometer.

[0176] (Acid resistance)

[0177] When the acid resistance was evaluated, a laminate 20 in which the thickness of the electrolytic plating layer 19 was 12 μm was used to prepare a sample. First, the laminate 20 cut into a square of 100 mm x 100 mm was prepared. Next, a photosensitive dry film was laminated on the electrolytic plating layer 19 of the laminate 20 using a vacuum laminator. The conditions were set to 50°C, 0.5 MPa, 10 seconds, and the vacuum degree was set to 3 hPa or less. The photosensitive dry film was a negative dry film, and Sunfort AQ-2075 manufactured by Asahi Kasei Corporation was used.

[0178] Next, a photomask having a rectangular shape with an opening area of 3 mm in width and 20 mm in length was interposed, and the laminate 20 was exposed to light at 80 mJ / cm2. 2 The surface of the dry film was exposed to light. Then, the unexposed portion of the dry film was removed (developed) with an aqueous sodium carbonate solution. The electrolytic plating layer 19 exposed by the development, the electroless plating layer 17 formed thereunder, and the catalyst layer 15 formed thereunder were removed. After this removal, the exposed dry film was removed using an aqueous sodium hydroxide solution. As for the electrolytic plating layer 19 exposed after the removal of the dry film, the electroless plating layer 17 formed thereunder, it was confirmed that the etching was a prescribed rectangle as viewed in a direction perpendicular to the main plane of the laminate 20. This was used as a sample. Note that the etching liquid used at the time of etching was an iron chloride liquid manufactured by Toagoseiki Co., Ltd.

[0179] Next, the obtained sample was heated at 160°C for 1 hour. After the heated sample was immersed in a 10% aqueous hydrochloric acid solution at 23°C for 30 minutes, it was washed with water and dried. Then, the electrolytic plating layer 19 and the electroless plating layer 17 formed in a rectangular shape were observed using an optical microscope (VHX-8000 manufactured by Keyence Corporation). Note that the sample was set so that a polyimide film surface was disposed on the lens side of the optical microscope at the time of observation. In addition, the degree of erosion was confirmed using software mounted on the VHX-8000. Furthermore, the evaluation was performed in accordance with the following criteria.

[0180] the electrolytic plating layer 19 and the electroless plating layer 17 formed in a rectangular shape had a depth of erosion of less than 5 μm;

[0181] the electrolytic plating layer 19 and the electroless plating layer 17 formed in a rectangular shape had a depth of erosion of 5 μm or more.

[0182] (interlayer adhesion)

[0183] The interlayer adhesion of the laminate was evaluated by the following (i) evaluation of adhesiveness and (ii) evaluation of peeling strength.

[0184] (i) Evaluation of Adhesiveness

[0185] The adhesion of the resin layer 13 to the catalyst layer 15 and the adhesion of the catalyst layer 15 to the electroless plating layer 17 in the laminate 10 obtained in (3) were observed visually. Specifically, whether or not peeling was present between the layers of the laminate on which the electroless plating layer 17 was formed, i.e., the laminate 10 obtained in (3) in the production of the electroless plating layer 17, cut into a square of 100 mm x 100 mm, was observed visually. In addition, five laminates were confirmed at the time of evaluation, and the evaluation was performed in accordance with the following criteria.

[0186] the number of laminates in which peeling occurred was less than 2,

[0187] the number of laminates in which peeling occurred was 2 or more.

[0188] (ii) Evaluation of Peeling Strength

[0189] The peeling strength of the electroless plating layer 19 before heat treatment and the peeling strength of the electroless plating layer 19 after heat treatment were measured in accordance with JIS C6471 with respect to the laminate 20 obtained in (4), specifically, the laminate 20 in which the thickness of the electroless plating layer 19 was 12 μm.

[0190] First, the laminate 20 cut into a square of 100 mm x 100 mm was prepared. Next, a photosensitive dry film was laminated on the electroless plating layer 19 of the laminate 20, and the lamination was performed using a vacuum laminator. The conditions were set to 50°C, 0.5 MPa, 10 seconds, and the degree of vacuum was set to 3 hPa or less. The photosensitive dry film was a negative-type dry film, and Sunfort AQ-2075 manufactured by Asahi Kasei Corporation was used.

[0191] Next, a photomask having a rectangular shape with an opening area of 3 mm in width and 20 mm in length was interposed, and the dry film was exposed to light at 80 mJ / cm 2 The surface of the dry film was exposed to light. Then, the unexposed portion of the dry film was removed (developed) with an aqueous sodium carbonate solution. The electroless plating layer 19 exposed by the development, the electroless plating layer 17 formed thereunder, and the catalyst layer 15 formed thereunder were removed. After this removal, the exposed dry film was removed using an aqueous sodium hydroxide solution. With respect to the electroless plating layer 19 exposed after the removal of the dry film and the electroless plating layer 17 formed thereunder, it was confirmed that etching was a prescribed rectangle when viewed in a direction perpendicular to the main plane of the laminate 20. This was used as a sample. Note that the etching liquid used at the time of etching was an iron chloride liquid manufactured by Toagoseiki Co., Ltd.

[0192] (ii-1) Peeling Strength Before Heat Treatment

[0193] The film constituting the obtained sample was laminated to a reinforcing plate made of stainless steel using a double-sided tape, and a sample for measurement was obtained.

[0194] (ii-2) Peeling strength after heat treatment

[0195] The obtained sample was stored in an atmosphere at 150°C for 240 hours. Then, after storage for 24 hours under conditions of 25°C, 50 RH%, the film constituting the obtained sample was adhered to a reinforcing plate made of stainless steel using a double-sided tape, to obtain a sample for measurement.

[0196] (ii-3) Measurement

[0197] The peeling strength in the 90° direction (direction perpendicular to the face of the sample for measurement) was measured using an Autograph AGS-500 manufactured by Shimadzu Corporation under the following measurement conditions.

[0198] The measurement conditions were set to copper peeling, and the test speed was set to 50 mm / min.

[0199] The evaluation criteria are described below.

[0200] Excellent: peeling strength of 5 N / cm or more,

[0201] Good: peeling strength of less than 5 N / cm and 3 N / cm or more,

[0202] Poor: peeling strength of less than 3 N / cm.

[0203] The results of the acid resistance and interlayer adhesion evaluated for the laminate of Example 1 are shown in Table 1. The laminate of Example 1 showed excellent acid resistance, and the adhesion and peeling strength also showed good results. Thus, the laminate of Example 1 had excellent acid resistance and interlayer adhesion. In addition, the reliability of the circuit of the circuit board using such a laminate was improved.

[0204] (Example 2)

[0205] A non-electrolytic plating solution in which the concentration of nickel (Ni) was changed to 0.2 g / L was used, and the laminate was produced in the same manner as the production method of the laminate of Example 1, except for this.

[0206] (Example 3)

[0207] A non-electrolytic plating solution in which the concentration of nickel (Ni) was changed to 0.34 g / L was used, and the laminate was produced in the same manner as the production method of the laminate of Example 1, except for this.

[0208] (Example 4)

[0209] The same method as the method of producing the laminate of Example 1 was used, except that a catalyst solution in which the amount of palladium was changed to 0.3 mass% and an electroless plating solution in which the concentration of nickel (Ni) was changed to 0.34 g / L were used. Note that it was confirmed that the surface of the resin layer 13 of the laminate obtained during the production of the laminate of Example 4 had 1 dm2of the surface of the resin layer 13 of the laminate of Example 4 had 0.08 mg of palladium adhered thereto. 2 0.08 mg of palladium adhered thereto.

[0210] (Example 5)

[0211] The same method as the method of producing the laminate of Example 1 was used, except that a catalyst solution in which the amount of palladium was changed to 0.57 mass% and an electroless plating solution in which the concentration of nickel (Ni) was changed to 0.34 g / L were used. Note that it was confirmed that the surface of the resin layer 13 of the laminate obtained during the production of the laminate of Example 5 had 1 dm2of the surface of the resin layer 13 of the laminate of Example 5 had 0.2 mg of palladium adhered thereto. 2 0.2 mg of palladium adhered thereto.

[0212] (Example 6)

[0213] The same method as the method of producing the laminate of Example 1 was used, except that a catalyst solution in which the amount of palladium was changed to 0.15 mass% and an electroless plating solution in which the concentration of nickel (Ni) was changed to 0.34 g / L were used. Note that it was confirmed that the surface of the resin layer 13 of the laminate obtained during the production of the laminate of Example 6 had 1 dm2of the surface of the resin layer 13 of the laminate of Example 6 had 0.05 mg of palladium adhered thereto. 2 0.05 mg of palladium adhered thereto.

[0214] (Comparative Example 1)

[0215] The same method as the method of producing the laminate of Example 1 was used, except that an electroless plating solution in which the concentration of nickel (Ni) was changed to 0.1 g / L was used.

[0216] (Comparative Example 2)

[0217] The same method as the method of producing the laminate of Example 1 was used, except that an electroless plating solution in which the concentration of nickel (Ni) was changed to 0.44 g / L was used.

[0218] The same method as the method of measuring and evaluating in Example 1 was used for measuring and evaluating the samples of Examples 2 to 6, Comparative Example 1, and Comparative Example 2.

[0219] The evaluation results of these examples and comparative examples are shown in Table 1 and Table 2. As is apparent from Table 1, the laminates of Examples 2 to 6 also have excellent acid resistance and interlayer adhesion. In addition, the reliability of the circuit of the circuit board using such a laminate is improved.

[0220] The laminates of Examples 1 to 6 have a film that relieves stress generated when the electroless plating layer 17 is formed, a resin layer 13 containing a thermoplastic polyimide resin, and a catalyst layer 15 containing palladium as a base for forming the electroless plating layer 17, and are therefore considered to have excellent interlayer adhesion. In addition, in the electroless plating layer 17 containing a prescribed amount of nickel, a large amount of nickel is present particularly at the boundary surface of the electroless plating layer 17 in contact with the catalyst layer 15. Therefore, even if an acidic chemical solution intrudes into the interface between the catalyst layer 15 and the electroless plating layer 17, the electroless plating layer 17 is not easily eroded. That is, the laminate has excellent acid resistance. In addition, the reliability of the circuit of the circuit board using such a laminate is improved.

[0221] [Table 1]

[0222]

[0223] [Table 2]

[0224]

[0225] For the laminates of Examples 1 to 6, further evaluation was performed on the surface resistivity, insulation resistance value, and solder heat resistance.

[0226] (Surface resistivity)

[0227] The surface resistivity of the laminate 10 on which the electroless plating layer 17 was formed before the electrolytic plating layer 19 was laminated, that is, the laminate 10 obtained in the production of the electroless plating layer 17 of (3) in the production process of the laminate 10 of Example 1 was measured. If the surface resistivity is low, when the electrolytic plating layer is formed on the electroless plating layer, sparks generated by an unexpectedly large current flowing therethrough and burn damage caused by concentration of current in a portion where current easily flows are less likely to occur in the electroless plating layer.

[0228] (Measurement of surface resistivity)

[0229] The surface resistivity was measured in accordance with JIS K7194. For the surface of the laminate cut into a quadrangle of 80 mm x 50 mm, five points were measured using a Loresta-GP MCP-T610 manufactured by Mitsubishi Chemical Corporation, using a four-probe probe. If the surface resistivity is 2.3 Ω / D or less, sparks and burn damage are less likely to occur, and it is rated as good. The surface resistivity of Example 1 was 0.8 Ω / D, which is good.

[0230] For the laminates of Examples 2 to 6, a laminate 10 in which the electroless plated layer 17 was formed before the electrolytic plating layer 19 was prepared as well. The surface resistivity of the laminate of each example was measured by the same method as that for measuring the surface resistivity of the laminate of Example 1. The surface resistivity of Example 2 was 1.2 Ω / D. The surface resistivity of Example 3 was 2.0 Ω / D. The surface resistivity of Example 4 was 2.0 Ω / D. The surface resistivity of Example 5 was 2.0 Ω / D. The surface resistivity of Example 6 was 2.0 Ω / D. It was found that any of the examples had a surface resistivity of 2.3 Ω / D or less, which was excellent.

[0231] (insulation resistance value)

[0232] The insulation resistance value of the laminate 20 obtained in the production of the (4) electrolytic plating layer 19 of Example 1, specifically, the laminate 20 in which the electrolytic plating layer having a thickness of 2 μm was formed, was measured. If the insulation resistance value between the wirings formed in the laminate is high, the conductive material such as copper remaining between the wirings during the formation of the wirings is small, and the conductive material can be reliably removed. In addition, the circuit substrate composed of such a laminate is less likely to be short-circuited.

[0233] (measurement of insulation resistance value)

[0234] The insulation resistance value was measured in accordance with JIS C6471. Specifically, a laminate cut into a square of 100 mm x 100 mm was prepared. Next, a photosensitive dry film was laminated on the electrolytic plating layer of the laminate, and was attached using a vacuum laminator. The conditions were set to 50°C, 0.5 MPa, 10 seconds, and the vacuum degree was set to 3 hPa or less. The photosensitive dry film was a negative dry film, and Sunfort AQ-2075 manufactured by Asahi Kasei Corporation was used.

[0235] Next, the laminate was exposed to light through a mask on which a pattern corresponding to the shape of the electrode for measuring the insulation resistance value in accordance with JIS C6471 was formed, at 80 mJ / cm2. 2 The surface of the dry film was exposed to light. Then, the dry film of the unexposed portion was removed (developed) with an aqueous sodium carbonate solution. The obtained laminate was immersed in a rapid etching aqueous solution for 60 seconds, and the electrolytic plating layer 19 exposed by the development and the electroless plated layer 17 formed thereunder were removed. Then, the exposed dry film was removed using an aqueous sodium hydroxide solution. Next, the laminate was immersed in a remover 1 (MEC Remover EM-1924 manufactured by Mec Corporation) for 10 seconds, and further immersed in a remover 2 (MEC Remover CH-1925 manufactured by Mec Corporation) for 40 seconds, and the catalyst layer 15 was removed. The sample for measurement was obtained through the above steps.

[0236] For the insulation resistance value between the electrodes formed in the sample for measurement, a digital ultra-high resistance 5451 manufactured by ADC Corporation was used to measure the insulation resistance value after application of a direct current voltage of 500 V for 1 minute. If the insulation resistance value was 1.0 x 10 12 Ω or more, the conductive material such as copper remaining between the wirings was small, and it was set to be good. The insulation resistance value of the laminate of Example 1 was 1.0 x 10 12 Ω or more, and it was good.

[0237] Note that the photomask used was manufactured in accordance with JIS C6471. In addition, the rapid etching aqueous solution used was an aqueous solution obtained by diluting CPE-800D manufactured by Mitsubishi Gas Chemical Company, Inc. to 5 times.

[0238] The laminates of Examples 2 to 6 were also measured by the same method as the measurement method of the insulation resistance value of the laminate of Example 1. The insulation resistance value of Examples 2 to 4 was 1.0 x 10 12 Ω or more. The insulation resistance value of Example 5 was 1.0 x 10 8 Ω or less. The insulation resistance value of Example 6 was 1.0 x 10 12 Ω or more.

[0239] The laminates of Examples 2 to 4 and Example 6 maintained a high insulation resistance value, and were good. The circuit substrate composed of these laminates was less likely to be short-circuited.

[0240] (Solder heat resistance)

[0241] The solder heat resistance was evaluated for the laminate 20 of Example 1 in which the (4) electrolytic plating layer 19 was formed, specifically, the laminate 20 in which the electrolytic plating layer 19 having a thickness of 12 μm was formed.

[0242] (Measurement of solder heat resistance)

[0243] A laminate cut into a square of 30 mm x 30 mm was prepared. The laminate was floated in a solder bath at 340°C for 60 seconds in a manner such that the electrolytic plating layer was in contact with the solder. Then, the laminate was lifted from the solder bath, and it was visually confirmed whether or not there was swelling or peeling. The laminate having no swelling or peeling had excellent solder heat resistance. It was found that the laminate of Example 1 had no swelling or peeling confirmed, and had excellent solder heat resistance.

[0244] The laminates of Examples 2 to 6 were also evaluated by the same method as the evaluation method of the solder heat resistance of Example 1. It was found that the laminate of any of the Examples had no swelling or peeling confirmed, and had excellent solder heat resistance.

[0245] As described above, it was found that the laminates of Example 1 to Example 6 had excellent acid resistance and interlayer adhesion, and also had low surface resistivity, and had excellent solder heat resistance. In addition, the laminates of Example 1 to Example 4 and Example 6 had high insulation resistance values. In addition, it was found that by using such a laminate, a circuit substrate that is less likely to short circuit can be provided. In addition, the reliability of the circuit of the circuit substrate using such a laminate was improved.

[0246] As to the present application, various embodiments and modifications can be implemented without departing from the broad spirit and scope of the present application. In addition, the above-described embodiments are for the purpose of illustrating the present application, and do not limit the scope of the present application. That is, the scope of the present application is indicated by the claims, not the embodiments. Furthermore, various modifications implemented within the scope of the claims and the equivalent meaning of the application are considered to be within the scope of the present application.

[0247] This application is based on Japanese Patent Application, Japanese Patent Application No. 2023-061292 filed on April 5, 2023. The specification, claims, and drawings of Japanese Patent Application, Japanese Patent Application No. 2023-061292 are incorporated herein by reference.

[0248] Explanation of Reference Numerals

[0249] 10, 20 laminate, 11 film, 13 resin layer, 15 catalyst layer, 17 electroless plating layer, 19 electrolytic plating layer.

Claims

1. A laminate comprising: membrane; a resin layer comprising a thermoplastic polyimide resin and formed on at least one surface of the film; a catalyst layer comprising palladium and a dispersant covering the palladium, and formed on the resin layer; and an electroless plating layer comprising nickel and copper and formed on the catalyst layer, The nickel content is 8.0 mass % or more and 13.0 mass % or less relative to the total mass of the electroless plating layer.

2. The laminate according to claim 1, wherein Relative to every 1dm 2 The amount of the palladium contained in the catalyst layer is 0.05 mg or more and 0.18 mg or less with respect to the surface of the resin layer. 3 . The laminate according to claim 1 , further comprising an electrolytic plating layer containing copper and formed on the electroless plating layer.

4. A method for manufacturing a circuit substrate, comprising: a resist layer forming step of forming a resist layer on the electroless plating layer constituting the laminate according to claim 1; An exposure step of exposing the resist layer; a resist pattern forming step of developing the resist layer exposed in the exposure step to form a resist pattern corresponding to a wiring to be formed; a wiring layer forming step of forming a conductive wiring layer on the electroless plating layer exposed after the resist pattern forming step; a resist pattern removing step of removing the resist pattern; a rapid etching step of removing the electroless plating layer exposed after the resist pattern removal step; and The catalyst layer removal step removes the catalyst layer exposed after the rapid etching step.

5. A method for manufacturing a circuit substrate, comprising: an electrolytic plating layer forming step of forming an electrolytic plating layer on the electroless plating layer constituting the laminate according to claim 1; a resist layer forming step of forming a resist layer on the electrolytic plating layer; An exposure step of exposing the resist layer; a resist pattern forming step of developing the resist layer exposed in the exposure step to form a resist pattern corresponding to a wiring to be formed; a wiring layer forming step of forming a conductive wiring layer on the electrolytic plating layer exposed after the resist pattern forming step; a resist pattern removing step of removing the resist pattern; a rapid etching step of removing the electrolytic plating layer exposed after the resist pattern removal step and the electroless plating layer formed under the electrolytic plating layer; and The catalyst layer removal step removes the catalyst layer exposed after the rapid etching step.

6. A method for manufacturing a circuit substrate, comprising: a resist layer forming step of forming a resist layer on the electrolytic plating layer constituting the laminate according to claim 3; An exposure step of exposing the resist layer; a resist pattern forming step of developing the resist layer exposed in the exposure step to form a resist pattern corresponding to a wiring to be formed; a wiring layer forming step of forming a conductive wiring layer on the electrolytic plating layer exposed after the resist pattern forming step; a resist pattern removing step of removing the resist pattern; a rapid etching step of removing the electrolytic plating layer exposed after the resist pattern removal step and the electroless plating layer formed under the electrolytic plating layer; and The catalyst layer removal step removes the catalyst layer exposed after the rapid etching step.

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