Satellite-borne time service synchronization system and method with time service signal monitoring based on FPGA (Field Programmable Gate Array)
By combining FPGA technology with Beidou timing information, we designed a differential receiving module and a monitoring module, achieving high-precision and reliable on-board time synchronization. This solves the accuracy, reliability and adaptability issues of traditional solutions and adapts to diverse on-board needs.
Patent Information
- Application Number
- CN202511273886.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-08
- Publication Date
- 2025-10-21
AI Technical Summary
Traditional on-board time synchronization solutions have the disadvantages of insufficient accuracy, poor reliability, and weak anti-interference capabilities, making it difficult to meet the requirements of high precision, reliability, and adaptability. In addition, dedicated time synchronization chips lack flexibility and scalability.
By employing FPGA technology combined with BeiDou timing information, a timing signal monitoring module and a master/backup communication switching unit are introduced. A differential receiving module, a timing signal monitoring module, a signal receiving and preprocessing module, a clock management module, and a synchronization timing data processing module are designed to achieve high-precision, reliable, and flexible time synchronization.
It achieves high-precision time synchronization, possesses high reliability and redundant backup capabilities, adapts to complex environments, supports real-time monitoring and maintenance, reduces management complexity, and meets the needs of aerospace missions such as remote sensing and communication.
Smart Images
Figure CN120821183A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of time synchronization of satellite-borne systems, and in particular to a satellite-borne timing synchronization system and method based on FPGA with timing signal monitoring. Background Art
[0002] In modern space missions, the coordinated work of onboard equipment requires extremely high time synchronization accuracy. This system is designed to provide a high-precision, high-reliability time reference for various payloads, communication modules, attitude control systems, etc. on satellite platforms, ensuring accurate coordination of various parts of the onboard system in the time dimension, thereby achieving efficient execution of complex tasks such as remote sensing data acquisition, inter-satellite communication, and scientific exploration, and meeting the strict requirements of the aerospace field for onboard time synchronization technology.
[0003] Traditional onboard time synchronization solutions have numerous limitations. Some early satellites used simple hardware timers or crystal oscillators as their time reference. However, due to factors such as temperature fluctuations and radiation effects in the space environment, the frequency of the crystal oscillator drifts, leading to the accumulation of time synchronization errors and making it difficult to meet the needs of long-term, high-precision time synchronization. Some onboard systems use dedicated time synchronization chips, but these chips lack flexibility and scalability, making them difficult to adapt to the diverse mission requirements and complex and changing operating modes of onboard systems. Furthermore, their high development costs and long development cycles hinder rapid iteration and optimization.
[0004] The BeiDou satellite navigation system provides highly accurate time signals, with its PPS (Pulse Per Second) signal achieving nanosecond accuracy, offering a new approach to onboard time synchronization. However, the application of BeiDou to onboard systems faces numerous challenges. Firstly, during low-orbit satellite operations, BeiDou signal reception may be interrupted or degraded due to Earth obstruction and ionospheric interference. Secondly, during deep-space exploration missions, satellites travel far from Earth, exceeding the effective coverage of BeiDou signals and unable to obtain time synchronization information. Furthermore, existing BeiDou-based onboard time synchronization solutions lack robustness against interference, adaptability to the unique onboard environment, and reliability, making them unable to meet the high-precision, high-reliability, and adaptability requirements of onboard systems.
[0005] Field-programmable gate arrays (FPGAs) offer advantages such as strong parallel processing capabilities, high reconfigurability, and short development cycles. They can flexibly configure logic functions based on the specific needs of onboard systems and precisely control timing. Combining FPGA technology with Beidou timing information, along with the introduction of a timing signal monitoring module and a primary-backup communication switching unit, is expected to overcome the shortcomings of traditional solutions and achieve a more efficient and reliable onboard time synchronization solution. Summary of the Invention
[0006] This invention aims to design a satellite-based timing synchronization system and method based on an FPGA with timing signal monitoring. This system utilizes timing information from the Beidou satellite navigation system, incorporates a timing signal monitoring module, and employs two timing links, one primary and one backup, to provide high-precision and highly reliable time synchronization services for onboard systems. By addressing the accuracy, reliability, anti-interference capability, and adaptability challenges of existing onboard time synchronization solutions, this system ensures precise timing coordination among various onboard devices, meeting the requirements of diverse space missions such as remote sensing, communications, and scientific exploration.
[0007] A satellite-borne timing synchronization system with FPGA-based timing signal monitoring, the system includes a differential receiving module, a timing signal monitoring module and an FPGA system;
[0008] The FPGA system includes a master-slave timing signal monitoring and switching module, a signal receiving and preprocessing module, a clock management module and a synchronous timing data processing module;
[0009] The differential receiving module is used to receive the timing signal and transmit it to the signal receiving and preprocessing module;
[0010] The signal receiving and preprocessing module performs beat processing on the received timing signal and transmits it to the synchronous timing data processing module;
[0011] The synchronous timing data processing module obtains the local clock signal output by the clock management module and synchronizes the received timing signal with the local clock signal; when the UTC time information in the timing signal is received, it is determined whether the UTC time information is valid. If the UTC time information is valid, the read UTC time information overwrites the UTC time of the system local clock signal; if the UTC time information is invalid, the internal time of the FPGA is maintained;
[0012] The timing signal monitoring module is used to monitor the quality of CAN signals and PPS signals and send them to the main and standby timing signal monitoring and switching modules;
[0013] The main and standby timing signal monitoring and switching module switches the main and standby timing links in a timely manner according to the CAN signal and PPS signal collected by the timing signal monitoring module;
[0014] The clock management module uses a high-precision, high-stability onboard crystal oscillator as the main clock source of the FPGA system to provide a reference clock signal for the FPGA system.
[0015] The present invention also provides a satellite-borne timing synchronization method based on FPGA with timing signal monitoring. The synchronization method is implemented by the synchronization system, and the specific steps are as follows:
[0016] Step 1: Connect the differential receiver module to the FPGA system interface correctly; turn on the system and the system will enter initialization;
[0017] Step 2: The FPGA internal timing system starts timing. At the same time, the timing signal monitoring module feeds the monitoring data back to the primary and backup timing signal monitoring and switching modules and generates a status report.
[0018] The master / slave timing signal monitoring and switching module determines whether the master / slave link has a fault and displays the working status through the CAN indicator light group and the PPS indicator light group;
[0019] Step 3: The synchronous timing data processing module determines whether the PPS second pulse has arrived. When the PPS second pulse arrives, the 16M crystal oscillator timer, millisecond counter, and second counter are all cleared. Then the FPGA system starts to determine whether the serial port has received the timing signal. When the serial port receives the timing signal, it determines whether it meets the timing requirements. If it meets the requirements, the FPGA system time is replaced with the UTC time in the timing signal.
[0020] Step 4: After the timing signal is received, the time mode is updated and displayed on the time mode light group; at the same time, the UTC time information is sent.
[0021] Beneficial effects of the present invention:
[0022] 1. Achieve high-precision time synchronization to meet the stringent accuracy requirements on board;
[0023] The present invention takes Beidou timing information and a high-precision crystal oscillator as its core, and ensures time synchronization accuracy through multiple technologies: the clock management module uses a high-precision, high-stability satellite-borne crystal oscillator as a benchmark, and integrates a phase-locked loop (PLL) circuit to implement clock frequency division and multiplication. The clock can be fine-tuned according to the FPGA control signal to eliminate crystal oscillator drift errors; the synchronous timing data processing module is designed with a three-level timing architecture of 16MHz clock counter, millisecond counter, and whole second counter. Combined with the core timing mechanism of "second pulse and time code" (process 4), it can force the alignment of whole second timing and PPS pulse, and correct the accumulated error of the crystal oscillator through continuous PPS signal, effectively solving the time error accumulation problem caused by temperature and radiation in traditional on-board solutions, and meeting the requirements of remote sensing data acquisition, inter-satellite communication and other tasks for high-precision time reference.
[0024] 2. High reliability and redundant backup capabilities to ensure uninterrupted system operation;
[0025] The system improves reliability through a dual backup mechanism of "primary and standby links + clock redundancy": the differential receiving module includes one primary and one standby CAN differential receiving module and a PPS differential receiving module. The timing signal monitoring module monitors the quality of CAN communication (signal-to-noise ratio, data frame integrity) and PPS signal (pulse period, level parameters) in real time. The primary and standby switching delay is ≤2us (only 2 clock cycles), which can quickly respond to main link failures; the clock management module has a built-in primary and standby crystal oscillator switching mechanism, which can quickly switch to the backup clock source when the main crystal oscillator fails to avoid clock interruption; at the same time, the synchronous timing data processing module can maintain short-term time accuracy through the internal high-precision crystal oscillator in scenarios such as "no second pulse and no time code" and "second pulse but no time code", further ensuring the system time continuity under extreme conditions, and solving the problems of weak anti-interference ability and easy failure due to signal loss of traditional solutions.
[0026] 3. Strong environmental adaptability and functional flexibility, adapting to complex scenarios on board;
[0027] Based on the reconfigurable characteristics of FPGA, the system can flexibly adapt to the diverse needs on board: the signal receiving and preprocessing module can monitor the Beidou signal strength and signal-to-noise ratio in real time, automatically select the optimal signal source, and adapt to complex environments such as earth obstruction and ionospheric interference of low-orbit satellites; the synchronous timing data processing module can handle five timing scenarios, such as "no second pulse and no time code" and "continuous second pulse with only one time code". It can rely on UTC time synchronization within the Beidou signal coverage range, and can also switch to internal time mode in scenarios without Beidou signals such as deep space exploration, breaking through the coverage range limitations of traditional Beidou timing solutions; in addition, FPGA supports dynamic configuration of logic functions, and can adjust the synchronization algorithm and interface protocol according to different space missions (remote sensing, scientific exploration), solving the problems of poor flexibility and insufficient scalability of dedicated time synchronization chips.
[0028] 4. Support real-time monitoring and operation and maintenance, reducing the complexity of onboard system management;
[0029] The system uses LED light groups to intuitively display the status of the main CAN / PPS link (steady on or flashing) and time mode (internal time or UTC time). Factory test personnel can quickly locate faults (for example, the main indicator light flashes when the main CAN fails). The main and standby timing signal monitoring and switching modules generate status reports to facilitate operation and maintenance personnel to locate faults, simplify system debugging and maintenance processes, and reduce on-board system management costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 This is a schematic diagram of a satellite-borne timing synchronization system based on FPGA with timing signal monitoring according to the present invention.
[0031] Figure 2 This is the schematic diagram of the FPGA system with second pulses but no time code;
[0032] Figure 3 This is a schematic diagram of the FPGA system with second pulses and time codes inside;
[0033] Figure 4 This is a workflow diagram of a satellite-borne timing synchronization method based on FPGA with timing signal monitoring according to the present invention. DETAILED DESCRIPTION
[0034] Specific implementation method 1. Combination Figure 1 and Figure 2 This embodiment describes an FPGA-based PPS timing synchronization system with timing signal monitoring, which consists of a differential receiving module (one primary and one backup), a timing signal monitoring module, an FPGA system, a power supply module, and an LED light group (a CAN working indicator light group, a PPS working indicator light group, and a time mode display light group). The power supply module supplies power to each module of the timing synchronization system. The FPGA system, differential receiving modules (one primary and one backup), the timing signal monitoring module, the power supply module, and the three LED light groups are integrated on a set of circuit boards.
[0035] In this embodiment, the FPGA system refers to a field programmable gate array (FPGA), which has the advantages of strong parallel processing capabilities, high reconfigurability, and a short development cycle. It can flexibly configure logical functions according to the specific needs of the onboard system and accurately control the timing.
[0036] The FPGA system includes a signal receiving and preprocessing module, a master / standby timing signal monitoring and switching module, a clock management module, and a synchronous timing data processing module;
[0037] The differential receiving module is used to receive the timing signal (UTC time information and PPS second pulse information) and input it into the FPGA system through differential communication;
[0038] The differential receiving module includes a primary and standby two-way CAN differential receiving module (CAN differential chip) and a primary and standby two-way PPS differential receiving module (PPS differential chip);
[0039] In this embodiment, the PPS differential chip receives two differential second pulses (one main and one backup); the CAN differential chip (one main and one backup) receives two channels of time data input by the Beidou timing system.
[0040] The timing signal monitoring module is used to monitor the quality of CAN communication and PPS signals, providing a basis for switching between the primary and backup links. The module uses the AD9280 chip as its core control unit. This chip has a sampling rate of up to 32MHz and a sampling resolution of up to 8 bits.
[0041] The signal receiving and preprocessing module receives the timing signal from the differential receiving module, and performs preprocessing such as temporary storage and filtering on the timing signal before transmitting it to the synchronous timing data processing module;
[0042] The signal receiving and preprocessing module performs beat processing on the received timing signals (PPS pulse-per-second information and UTC time information) to ensure that the timing signals input into the synchronous timing data processing module are stable and reliable. Furthermore, the signal receiving and preprocessing module also has signal detection and switching functions, capable of real-time monitoring of Beidou signal strength, signal-to-noise ratio, and other parameters. Based on signal quality, it automatically selects the optimal signal source for time synchronization. If the primary signal source is lost or its quality degrades, it quickly switches to the backup signal source.
[0043] In this embodiment, after preprocessing the timing signal, the signal receiving and preprocessing module packages and transmits it to the synchronous timing data processing module. The synchronous timing data processing module determines whether the received UTC time information is valid and displays it through the time mode display light group.
[0044] The master and standby timing signal monitoring and switching module switches the master and standby timing links in a timely manner mainly according to the communication signals collected by the timing signal monitoring module.
[0045] In this embodiment, the clock management module provides a stable and accurate clock signal to the system through a clock divider and multiplier, and has clock calibration and monitoring functions;
[0046] The clock management module uses a high-precision, high-stability satellite-borne crystal oscillator as the main clock source to provide a reference clock signal for the system. In order to meet the needs of the synchronous timing data processing module and other modules for clocks of different frequencies, the module integrates a phase-locked loop (PLL) circuit and a clock frequency multiplier. The PLL phase-locks and frequency-multiplies the output signal of the high-precision crystal oscillator, and then obtains high-precision clock signals of multiple frequencies through the clock divider. At the same time, the module also has a clock redundancy backup and switching mechanism. When the main crystal oscillator fails, it can quickly switch to the backup clock source to ensure an uninterrupted supply of system clocks. In addition, the module can fine-tune the system clock according to the control signal of the FPGA system to achieve precise synchronization with the timing signal.
[0047] In this embodiment, the synchronous timing data processing module is responsible for tasks such as signal processing, synchronization algorithm execution, and system logic control, and is the core of the timing synchronization system;
[0048] The synchronous timing data processing module is responsible for the detailed synchronization of timing data. During the data reception phase, the module collects timing signals from the signal reception and preprocessing module in real time, including PPS signal timestamps, and simultaneously obtains clock status parameters output by the clock management module, synchronizing the received timing signals with the local clock signal. Upon receiving UTC time information from the signal reception and preprocessing module, it determines whether the received UTC time information is valid. If the UTC time information is valid, the read UTC time information is overwritten with the UTC time of the system's local clock signal; if the UTC time information is invalid, the internal time is maintained.
[0049] like Figure 2 and Figure 3 As shown, the synchronous timing data processing module operates as follows: When a single device is powered on, timekeeping begins at time 0. The system time consists of three internal registers: a 16MHz clock counter, a millisecond counter, and a full second counter. The 16MHz clock counter increments by 1 per cycle and is reset when the count reaches 16000. The millisecond counter increments by 1 when the 16MHz clock counter overflows and is reset when the count reaches 1000. When the falling edge of the PPS second pulse arrives, all three counters, the 16MHz clock counter, the millisecond counter, and the full second counter, are reset. The full second counter increments by 1 when the millisecond counter overflows and is not automatically reset. These three counters maintain the system's internal seconds and milliseconds.
[0050] The synchronous timing data processing module is responsible for analyzing and processing the timing signal and synchronizing the received timing signal with the local clock signal. It mainly handles five situations of single-machine timing: no second pulse and no time code, with second pulse but no time code, with time code but no second pulse, with second pulse and time code, and with continuous second pulse and only one time code. The specific timing operations are as follows:
[0051] Single machine time synchronization includes five situations: no second pulse and no time code, with second pulse and no time code, no second pulse and time code, with second pulse and time code, and with continuous second pulse and only one time code. The specific time synchronization operations are as follows:
[0052] 1. No second pulse and no time code: The system is maintained by a high-precision crystal oscillator, the time mode is internal time, the 16MHz register and the millisecond register are reset after reaching the set value, and the second register is updated at the same time, such as Figure 2 As shown;
[0053] 2. With second pulse but no time code: The second pulse is considered reliable. When a single device detects the second pulse, if the millisecond timer value is greater than 500, the full second timer is incremented by 1; if the millisecond timer value is less than 500, the full second timer value remains unchanged. At the same time, the crystal oscillator timer and millisecond timer are reset to zero so that the full second timer is forced to align with the second pulse, but the time mode remains unchanged, such as Figure 2 shown.
[0054] 3. No second pulse but time code: The time code is considered to be sent incorrectly, and the time synchronization command is not responded to. The time mode remains unchanged at the internal time mode.
[0055] 4. There is a second pulse and a time code: After the second pulse arrives, follow the general second pulse time synchronization process (case 2) to align the whole second with the second pulse. At the same time, the FPGA timing detects the time code instruction. If the time code is received within 200ms after the second pulse arrives, it is considered that the time code is paired with the second pulse, and the internal integer counter is updated to the time code UTC time; if the time code is received 200ms after the second pulse arrives and before the next second pulse arrives, it is considered that the time code is sent incorrectly and the time synchronization instruction is not responded to. Figure 3 shown.
[0056] 5. There is a continuous second pulse, but only one time code: Situation 4 occurs after the second pulse arrives. At this time, the time mode is updated to UTC time. If the second pulse continues, the time mode will always be UTC time. If the second pulse is interrupted, the time mode will change to internal time, and you need to wait for the next situation 4.
[0057] Scenarios 2 and 4 above constitute an effective time synchronization mechanism. After the system is powered on, the synchronization process (including the second pulse and time code) must be executed at least once (i.e., Scenarios 4 above) to ensure the synchronization accuracy of the internal system time. Furthermore, a highly reliable second pulse signal is required to correct the accumulated error of the crystal oscillator count.
[0058] In this embodiment, the power module uses the MP2145 chip as its core control unit. This chip is a highly integrated synchronous step-down DC-DC converter designed for efficient power management, providing stable output voltage over a wide input voltage range. It connects to a 5V DC power supply via the DC connector on the circuit board, which then steps it down to 3.3V through the chip, providing a stable power supply for the entire synchronous timing system.
[0059] Specific implementation method 2: Figure 4 This embodiment is described as follows: a method for a satellite-borne timing synchronization system based on FPGA with timing signal monitoring as described in the first embodiment; the method is implemented by the following steps:
[0060] Step 1. Connect the differential receiver module to the FPGA system interface correctly; turn on the system and the system enters initialization;
[0061] Step 2: After initialization is completed, the FPGA internal timing system starts timing. At the same time, the timing signal monitoring module feeds the monitoring data back to the primary and backup timing signal monitoring and switching modules. The primary and backup timing signal monitoring and switching modules analyze the monitoring data in real time and generate a status report to determine whether there is a fault in the primary and backup links. The module also displays the working status through the CAN indicator group and the PPS indicator group.
[0062] In this embodiment, the main and standby timing signal monitoring and switching module workflow is as follows:
[0063] 1.CAN signal switching;
[0064] The master / standby timing signal monitoring and switching module receives the signal-to-noise ratio, data frame integrity and verification result of the CAN signal of the connected link (default main link), generates a status report every 1s, and stores it in the FPGA system. If the master / standby timing signal monitoring and switching module detects that the main link is fault-free, the master / standby CAN working indicator group (2 green LEDs) are both constantly on.
[0065] If three consecutive status reports (at 3-second intervals) indicate that the primary link is inoperative, the primary / backup timing signal monitoring and switching module switches to the backup link with a delay of ≤2µs (software switching takes two clock cycles, meeting the requirement for uninterrupted time synchronization of onboard equipment). The module also requests the central computer to send one frame of data via the backup link. The primary CAN working indicator flashes, indicating a primary CAN link failure. The backup CAN working indicator remains unchanged.
[0066] After the FPGA system receives one frame of backup link data, it immediately checks its signal-to-noise ratio and data validity. If the check passes, the switch is confirmed to be successful, and the status of the main and backup indicator lights remains unchanged; if the check fails (the backup link signal is also invalid), the link connection of the main link (even if invalid) is maintained, and the main and backup indicator lights flash.
[0067] 2.PPS signal switching;
[0068] The master-slave timing signal monitoring and switching module captures the falling edge of the connected link (default master link) PPS in real time, records the pulse period, low level width and high level voltage, and compares them with the preset threshold; determines whether the main link PPS has a fault and forms a status report;
[0069] When the main link PPS is working normally, the main and standby PPS working indicator light group (2 red LEDs) are always on; when it is detected that the quality of the main link PPS pulses is not up to standard for three consecutive times or the high-level voltage is lower than the threshold, the FPGA system sends a PPS main and standby switching instruction to the main and standby timing signal monitoring and switching module, switching the PPS receiving link from the main link to the standby link. At the same time, the main PPS working indicator light flashes, indicating that the main PPS is faulty, and the standby PPS working indicator light remains unchanged;
[0070] If after switching to the backup PPS receiving link, the backup link also fails, the link connection of the main link (even if it is invalid) is maintained, and the main and backup PPS indicators flash;
[0071] Step 3: The synchronous timing data processing module checks whether the PPS second pulse is coming. When the PPS second pulse comes, the 16M crystal oscillator timer, millisecond counter, and second counter are all cleared. Then the FPGA system starts to determine whether the serial port has received the timing signal. When the serial port receives the timing signal, it determines whether it meets the timing requirements. If it meets the requirements, the FPGA system time is replaced with UTC time.
[0072] Step 4: After the timing signal is received, the time mode is updated and displayed on the time mode light group (2 blue LEDs).
[0073] If both lights are on, that is, 11, it means that timing has been carried out since power-on and PPS signal reception has been carried out; if only the first light is on, that is, 01, it means that timing has not been carried out since power-on, but PPS signal reception has been carried out; if only the second light is on, that is, 10, it means that timing has been carried out since power-on, but PPS signal reception has been interrupted during the period, and then PPS signal reception has been restored; if both lights are off, that is, 00, it means that timing has not been carried out since power-on and no PPS signal has been received, or PPS signal reception has been interrupted during the period, and then PPS signal reception has not been restored.
[0074] Step 5: The system sends UTC time information;
[0075] In this embodiment, when sending UTC time information, the time mode is packaged and sent together (0 represents internal time, 1 represents UTC time).
[0076] like Figure 4 As shown, the specific process of the method described in this embodiment is:
[0077] Step A: The system is powered on and initialized, and the internal timing of the FPGA is started;
[0078] Step B: Determine whether the main CAN link is working normally. If not, the main and standby timing signal monitoring and switching modules switch the CAN communication link and execute step C; if yes, execute step D;
[0079] Step C: Determine whether the standby CAN link is working properly. If so, go to step D; otherwise, go to step I.
[0080] Step D: Determine whether the main PPS link is working properly. If not, the main and standby timing signal monitoring and switching modules perform PPS link switching and execute step E; if yes, execute step F;
[0081] Step E: Determine whether the standby PPS link is working properly. If so, proceed to step F; otherwise, proceed to step I.
[0082] Step F, determine whether the PPS signal exists. If yes, execute step G; otherwise, the timing data is invalid, execute step I;
[0083] Step G: Determine whether the UTC time data exists. If yes, go to step H; if not, go to step I.
[0084] Step H: Determine whether the time interval T between the arrival of the second pulse and the arrival of the UTC time is less than 200ms. If so, output the UTC time; end; if not, execute step I;
[0085] Step I: Output internal time; end.
[0086] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0087] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.
Claims
1. A satellite-borne timing synchronization system with timing signal monitoring based on FPGA, characterized by: The system includes a differential receiving module, a timing signal monitoring module and an FPGA system; The FPGA system includes a master-slave timing signal monitoring and switching module, a signal receiving and preprocessing module, a clock management module and a synchronous timing data processing module; The differential receiving module is used to receive the timing signal and transmit it to the signal receiving and preprocessing module; The signal receiving and preprocessing module performs beat processing on the received timing signal and transmits it to the synchronous timing data processing module; The synchronous timing data processing module obtains the local clock signal output by the clock management module and synchronizes the received timing signal with the local clock signal; when the UTC time information in the timing signal is received, it is determined whether the UTC time information is valid. If the UTC time information is valid, the read UTC time information overwrites the UTC time of the system local clock signal; if the UTC time information is invalid, the internal time of the FPGA is maintained; The timing signal monitoring module is used to monitor the quality of CAN signals and PPS signals and form a status report to be sent to the main and standby timing signal monitoring and switching modules; The main and standby timing signal monitoring and switching module switches the main and standby timing links in a timely manner according to the CAN signal and PPS signal collected by the timing signal monitoring module; The clock management module uses a high-precision, high-stability onboard crystal oscillator as the main clock source of the FPGA system to provide a reference clock signal for the FPGA system.
2. The satellite-borne timing synchronization system with FPGA-based timing signal monitoring according to claim 1, characterized in that: The differential receiving module is composed of a main and standby two-way CAN differential receiving module and a main and standby two-way PPS differential receiving module; The PPS differential receiving module receives two-channel differential second pulse signals; the CAN differential receiving module receives multiple-channel time data input by the Beidou timing system.
3. The satellite-borne timing synchronization system with FPGA-based timing signal monitoring according to claim 1, characterized in that: The main and backup timing signal monitoring and switching module has signal detection and switching functions, which is used to monitor the strength and signal-to-noise ratio parameters of the Beidou signal in real time, automatically select the optimal signal source for time synchronization based on the signal quality, and switch to the backup signal source when the main signal source is lost or the quality deteriorates.
4. The satellite-borne timing synchronization system with FPGA-based timing signal monitoring according to claim 1, characterized in that: The clock management module integrates a PLL circuit and a clock frequency multiplier, and uses the PLL circuit to phase-lock and frequency-multiply the high-precision crystal oscillator output signal to obtain a high-precision clock signal. At the same time, the clock management module also has a clock redundancy backup and switching mechanism, which can switch to the backup clock source when the main crystal oscillator fails. The clock management module fine-tunes the system clock according to the control signal of the FPGA system to achieve precise synchronization with the timing signal.
5. The satellite-borne timing synchronization system based on FPGA with timing signal monitoring according to claim 1, characterized in that: The working process of the synchronous timing data processing module is as follows: when a single machine is turned on, time is recorded from time 0, and the system time includes three internal counters: a 16MHz clock counter, a millisecond counter, and a whole second counter; the 16MHz clock counter accumulates 1 per cycle, and when the accumulation reaches 16000, it overflows and is cleared; the millisecond counter accumulates 1 when the 16MHz clock counter overflows and is cleared, and when the accumulation reaches 1000, it overflows and is cleared; when the falling edge of the PPS second pulse arrives, the 16MHz clock counter, the millisecond counter, and the whole second counter are all cleared; the whole second counter accumulates 1 when the millisecond counter overflows and is cleared, and is not actively cleared.
6. The satellite-borne timing synchronization system with FPGA-based timing signal monitoring according to claim 5, characterized in that: The synchronous timing data processing module synchronizes the received timing signal with the local clock signal; the stand-alone timing situations include the following five: Case 1: No second pulse and no time code: The system is maintained by a high-precision crystal oscillator. The time mode is internal time. The 16MHz register and millisecond register are reset after reaching the set value, and the second register is updated at the same time. The second case: with pulse-seconds but no time code: When a single device detects a second pulse, if the millisecond timer value is greater than 500, the full second timer is incremented by 1; if the millisecond timer value is less than 500, the full second value remains unchanged; at the same time, the crystal oscillator timer and millisecond timer are reset to force the full second time to align with the second pulse, and the time mode remains unchanged; The third case: no second pulse but time code: It thinks that the time code is sent incorrectly, does not respond to the time synchronization command, and maintains the internal time mode unchanged; The fourth case: with second pulse and time code: After the second pulse arrives, the second pulse synchronization process of the second case is followed to align the whole second with the second pulse. At the same time, the FPGA system detects the time code instruction. If the time code is received within 200ms after the second pulse arrives, it is considered that the time code is paired with the second pulse. At this time, the internal integer counter is updated to the time code UTC time. If the second pulse arrives after 200ms and the time code is received before the next second pulse arrives, it is considered that the time code was sent incorrectly and the synchronization instruction is not responded to. The fifth case: there is a continuous second pulse and only one time code: The fourth situation occurs after the second pulse arrives. At this time, the time mode is updated to UTC time. If the second pulse continues to exist, the time mode will always be UTC time. If the second pulse is interrupted, the time mode will be changed to internal time and wait for the next occurrence of the fourth situation.
7. A satellite-borne timing synchronization method based on FPGA with timing signal monitoring, characterized by: The method is implemented by a satellite-borne timing synchronization system based on FPGA with timing signal monitoring as described in any one of claims 1 to 6; the specific implementation steps of the method are: Step 1: Connect the differential receiver module to the FPGA system interface correctly; turn on the system and the system will enter initialization; Step 2: The FPGA internal timing system starts timing. At the same time, the timing signal monitoring module feeds the monitoring data back to the primary and backup timing signal monitoring and switching modules and generates a status report. The master / slave timing signal monitoring and switching module determines whether the master / slave link has a fault and displays the working status through the CAN indicator light group and the PPS indicator light group; Step 3: The synchronous timing data processing module determines whether the PPS second pulse has arrived. When the PPS second pulse arrives, the 16M crystal oscillator timer, millisecond counter, and second counter are all cleared. Then the FPGA system starts to determine whether the serial port has received the timing signal. When the serial port receives the timing signal, it determines whether it meets the timing requirements. If it meets the requirements, the FPGA system time is replaced with the UTC time in the timing signal. Step 4: After the timing signal is received, the time mode is updated and displayed on the time mode light group; at the same time, the UTC time information is sent.
8. The synchronization method according to claim 7, characterized in that: The CAN signal switching process of the main and standby timing signal monitoring and switching modules is as follows: The master-slave timing signal monitoring and switching module receives the signal-to-noise ratio, data frame integrity and verification results of the CAN signal of the main CAN link, generates a status report every 1s, and stores it in the FPGA system. If the master-slave timing signal monitoring and switching module detects that the main CAN link is fault-free, the master-slave CAN working indicator groups are all constantly on; When three consecutive status reports show that the main CAN link is invalid, the main and standby timing signal monitoring and switching module executes the standby CAN link switching task and requests the central computer to send one frame of data through the standby CAN link. The main CAN working indicator light flashes, indicating that the main CAN link is faulty, and the standby CAN working indicator light remains unchanged. After the FPGA system receives one frame of standby CAN link data, it verifies its signal-to-noise ratio and data validity. If the verification passes, it confirms that the switch is successful, and the status of the active and standby CAN indicators remains unchanged; If the verification fails, the link connection of the main CAN link is maintained, and the main and standby CAN indicators flash.
9. The synchronization method according to claim 7, wherein: The master-slave timing signal monitoring and switching module captures the falling edge of the PPS signal of the connected master PPS link in real time, records the pulse period, low-level width and high-level voltage, and compares them with the preset threshold value; determines whether the master PPS link has a fault and generates a status report; When the main PPS link is working normally, the main and standby PPS working indicator groups are always on; when it is detected that the quality of the PPS pulses of the main PPS link is not up to standard for three consecutive times or the high-level voltage is lower than the threshold, the FPGA system sends a PPS main-standby switching instruction to the main and standby timing signal monitoring and switching module, switching the PPS receiving link from the main link to the standby link. At the same time, the main PPS working indicator flashes, indicating that the main PPS is faulty, and the standby PPS working indicator remains unchanged. If after switching to the backup PPS receiving link, the backup link also fails, the link of the main PPS link will be maintained, and the main and backup PPS indicators will flash.