Approximate multiplication method and calculator based on posit data

Abstract

The application relates to the field of artificial intelligence, in particular to a Posit data-based approximate multiplication method and a calculator, the method comprises the following steps: performing analysis processing on acquired Posit data, performing splicing operation on the exponent extension bit and the exponent of each Posit data, and determining a mantissa truncation bit width control signal according to the equivalent exponent bit of the Posit data; converting two mantissas obtained through analysis into logarithmic domain mantissa values, compensating for the truncation error of the truncated logarithmic domain mantissa values, compensating for the error of the logarithmic domain mantissa product according to the numerical interval of the logarithmic domain mantissa value, processing the linear domain equivalent exponent, and splitting the exponent extension bit and the exponent bit of the product to obtain a final Posit format approximate multiplication result; through the design of a novel error compensation circuit, the application effectively reduces the calculation error by using a lower additional cost, and realizes the consideration of the energy efficiency and the calculation precision of the Posit multiplier.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence technology, and in particular to an approximate multiplication method and arithmetic unit based on Posit data. Background Technology

[0002] With the development of artificial intelligence technology, the demand for deploying artificial intelligence applications on edge devices is growing. However, artificial intelligence models, represented by deep neural networks, have high computing power requirements, while edge devices have limited computing power. This contradiction makes it difficult to deploy deep learning models efficiently on edge devices.

[0003] To address the aforementioned issues, hardware-software co-optimization has become a crucial technical approach. This involves reducing the bit width of the computational data to minimize energy consumption while maintaining the accuracy of the deep learning model. Furthermore, the Posit data format, with its cone-shaped data distribution, can meet model accuracy requirements with a relatively small bit width. However, the cone-shaped data distribution of the Posit format stems from the dynamic sharing of the total bit width among its components, resulting in non-deterministic bit widths for each component. This introduces additional overhead to the hardware implementation of the Posit multiplier. To reduce the hardware overhead of the Posit multiplier, approximation methods have been introduced into the computation of the Posit data format, primarily categorized into linear domain design and logarithmic domain design. Linear domain design is based on... While conventional multiplier structures have been improved by reducing overhead through methods such as truncating less significant bits, the improvement in hardware performance is limited. Logarithmic domain designs achieve greater hardware performance improvements by converting multiplication to addition, but introduce significant computational errors during the logarithmic domain data conversion process. Although the computational error of logarithmic domain approximation multipliers can be reduced through error compensation, it requires the construction of error calculation logic with a scale similar to that of the main computing circuit, introducing a large amount of additional hardware overhead. As a result, existing Posit approximation multipliers cannot balance hardware energy efficiency and computational accuracy, making it difficult to promote the application of the Posit data format in edge intelligent computing. At present, there is a need for an approximation multiplication operation method and arithmetic unit based on Posit data. Summary of the Invention

[0004] To address the issue that traditional Posit approximate multipliers cannot balance hardware energy efficiency and computational accuracy, this invention provides an approximate multiplication method and calculator based on Posit data.

[0005] Firstly, the present invention provides an approximate multiplication method based on Posit data, which employs the following technical solution:

[0006] An approximate multiplication method based on Posit data includes:

[0007] Two Posit data points are obtained as input, and the obtained Posit data points are parsed and processed to obtain the sign bit, exponent extension bit, exponent bit, and mantissa bit of the two Posit data points respectively;

[0008] The exponent extension bits and exponent bits of each Posit data are concatenated to obtain the equivalent exponent bits of each Posit data. The mantissa truncation bit width control signal is determined based on the equivalent exponent bits of the Posit data.

[0009] The mantissa of the two Posit data obtained by parsing is converted into the mantissa value of the logarithmic field. The mantissa truncation bit width control signal is used to truncate the mantissa value of the logarithmic field, and the truncation error is compensated for the truncated mantissa value of the logarithmic field.

[0010] The logarithmic mantissa and the equivalent exponent of the Posit data are added to generate the logarithmic mantissa product and the logarithmic equivalent exponent. The corresponding error compensation value is determined according to the numerical interval of the logarithmic mantissa of the two input Posit data, and the error compensation is performed on the logarithmic mantissa product.

[0011] Based on the magnitude of the corrected logarithmic mantissa product, the logarithmic mantissa product and the logarithmic equivalent exponent are inversely converted into the linear mantissa product and the linear equivalent exponent.

[0012] The equivalent exponent in the linear domain is processed and split to obtain the exponent extension bits and exponent bits of the product. These are then concatenated according to the Posit data format. The concatenated data is then normalized and rounded to obtain the final approximate multiplication result in the Posit format.

[0013] Further, the parsing and processing of the acquired Posit data includes obtaining Posit(nb,es) format data as input data IN1, performing a logical XOR operation on the lower nb-1 bits of IN1 and the sign bit S, and adding the result of the operation to the sign bit of IN1 to obtain the Posit sequence. The exponent extension bit and its bit width of IN1 are determined according to the state of the highest bit of the Posit sequence. The Posit sequence is left-shifted according to the bit width of the exponent extension bit to remove the exponent extension bit. The higher es bit is selected as the exponent bit based on the left-shifted Posit sequence. The lower nb-es-1 bits are the fractional part of the mantissa of IN1. A hidden bit 1 is added to the highest bit of the fractional part to obtain the complete mantissa. Here, nb is the total bit width of the Posit data, and es is the exponent bit width of the Posit data.

[0014] Furthermore, the step of determining the exponent extension bit and its width of IN1 based on the highest bit state of the Posit sequence includes performing a bitwise inversion operation on the Posit sequence when the highest bit of the Posit sequence is 1, then inputting the inverted Posit sequence into the leading zero counting module to calculate the length of the leading zero sequence; when the highest bit of the Posit sequence is 0, directly inputting it into the leading zero counting module to calculate the length of the leading zero sequence; and finally determining the exponent extension bit and its width based on the length of the leading zero sequence.

[0015] Furthermore, the step of determining the mantissa truncation width control signal based on the equivalent exponent bits of the Posit data includes: extracting the exponent extension bit and exponent bit of each Posit data from the two decoded Posit data, concatenating them into binary bits to generate the equivalent exponent bit of each Posit data, performing an addition operation on the equivalent exponent bits of the two Posit data to obtain the equivalent exponent bit of the product, extracting the values ​​of the product exponent bit and the product exponent extension bit based on the equivalent exponent bit of the product, determining the width of the product exponent extension bit by combining the highest bit of the product exponent extension bit, and calculating the mantissa width of the product based on the total width of the Posit data.

[0016] Furthermore, the step of converting the two mantissa bits obtained from parsing into logarithmic domain mantissa values ​​includes performing a linear-to-logarithmic domain conversion on F1 and F2 respectively using the Mitchell approximation algorithm, removing the hidden bit 1 in F1 and F2, taking the remaining fractional part as its corresponding logarithmic domain mantissa values ​​FL1 and FL2, truncating the binary sequences of FL1 and FL2 according to the product mantissa bit width FLen, retaining only the FLen bits of data starting from the most significant bit in FL1 and FL2, and discarding all low-order bits after the FLen bits;

[0017] Where F1 is the mantissa of the first Posit data IN1, F2 is the mantissa of the second Posit data IN2, Flen is the bit width of the product mantissa, FL1 is the logarithmic field mantissa of F1, and FL2 is the logarithmic field mantissa of F2.

[0018] Furthermore, based on the numerical intervals of the logarithmic domain tail values ​​of the two input Posit data, the corresponding error compensation values ​​are determined. This includes dividing the range of logarithmic domain tail values ​​[0,1) into multiple sub-intervals, extracting the high-order bits of FL1 and FL2 respectively, determining the sub-intervals of FL1 and FL2 based on the number of 0s in the high-order bits, generating segmentation flag 1 and segmentation flag 2 respectively, selecting a value that is not less than the average error between log2(1+x) and x in the interval and has only 1 bit in its binary representation as the compensation value for each sub-interval that needs to be compensated, determining the total compensation vector based on segmentation flag 1 and segmentation flag 2, and performing an addition operation on the total compensation vector and the logarithmic domain tail product to obtain the corrected logarithmic domain tail product.

[0019] Where log2(1+x) represents the exact logarithmic value of the mantissa of the Posit data, and x represents the fractional part of the mantissa of the Posit data.

[0020] Furthermore, the step of inversely converting the logarithmic domain mantissa product and the logarithmic domain equivalent exponent into the linear domain mantissa product and the linear domain equivalent exponent includes, after obtaining the logarithmic domain product, performing the inverse conversion based on the numerical relationship between the logarithmic domain mantissa product FLP and 1, combined with the Mitchell approximation algorithm. When FLP is less than 1, the linear domain mantissa product FNP is the sum of 1 and FLP, and the linear domain equivalent exponent EffN is the logarithmic domain equivalent exponent EffL. When FLP is greater than or equal to 1, the linear domain mantissa product FNP is FLP, and the linear domain equivalent exponent EffN is EffL plus 1.

[0021] Where FLP is the sum of the logarithmic mantissas of the two input operands, EffL is the sum of the equivalent exponents of the two input operands, EffN is the equivalent exponent in the linear field, and FNP is the mantissa product in the linear field.

[0022] Furthermore, the process of processing the equivalent exponent of the linear field and splitting it to obtain the exponent extension bits and exponent bits of the product includes performing two's complement calculation on the equivalent exponent of the linear field when the equivalent exponent of the linear field is negative, and keeping it unchanged when the equivalent exponent of the linear field is positive. The lower es bits of the processed equivalent exponent of the linear field are extracted as the exponent bits of the product, and the remaining higher bits are used as the values ​​of the product exponent extension bits. The product exponent extension sequence is generated according to the sign of the equivalent exponent of the linear field, where es is the bit width of the exponent part of the Posit data.

[0023] Furthermore, the normalization and rounding operations on the concatenated data include overflow detection based on the displacement of the right shift operation and the total bit width of the Posit data. When overflow occurs, the displacement is set to 0, and the final product result is set to NaR format. When no overflow occurs, the exponent extension bits, the exponent bits, and the mantissa bits of the product are concatenated, an arithmetic right shift operation is performed on the concatenated data, and the sequence after the arithmetic right shift is corrected using two's complement based on the product sign bit to obtain the final Posit data product.

[0024] Secondly, an approximate multiplication operator based on Posit data includes:

[0025] The operand decoding module is configured to: acquire two Posit data as input, and parse the acquired Posit data to obtain the sign bit, exponent extension bit, exponent bit and mantissa bit of the two Posit data respectively;

[0026] The preprocessing module is configured to: concatenate the exponent extension bits and the exponent of each Posit data to obtain the equivalent exponent bits of each Posit data, and determine the mantissa truncation bit width control signal based on the equivalent exponent bits of the Posit data;

[0027] The logarithm field conversion module is configured to: convert the two mantissa bits obtained from parsing into logarithm field mantissa values, truncate the logarithm field mantissa values ​​using the mantissa truncation bit width control signal, and compensate for truncation errors in the truncated logarithm field mantissa values.

[0028] The multiplication and compensation module is configured to: perform addition operations on the logarithmic mantissa and the equivalent exponent of the Posit data respectively to generate the logarithmic mantissa product and the logarithmic equivalent exponent; determine the corresponding error compensation value according to the numerical interval of the logarithmic mantissa of the two input Posit data; and perform error compensation on the logarithmic mantissa product.

[0029] The logarithmic field inverse conversion module is configured to convert the logarithmic field mantissa product and the logarithmic field equivalent exponent into the linear field mantissa product and the linear field equivalent exponent based on the magnitude of the corrected logarithmic field mantissa product.

[0030] The product encoding module is configured to process and split the equivalent exponent in the linear field to obtain the exponent extension bits and exponent bits of the product, and then concatenate them according to the Posit data format. The concatenated data is then normalized and rounded to obtain the final Posit format approximate multiplication result.

[0031] In summary, the present invention has the following beneficial technical effects:

[0032] 1. This invention utilizes the dynamic bit width characteristics of the Posit data format through a logarithmic field approximation calculation method. It determines the effective data bit width based on the bit width requirement of the calculation result, truncates redundant bits to reduce the amount of computation, effectively improves the energy efficiency of the Posit multiplier, and can meet the needs of edge intelligent computing.

[0033] 2. This invention designs an efficient error compensation method, adopts a simple piecewise error compensation strategy and uses hardware-friendly compensation vector values. Without affecting the hardware computing efficiency, it effectively improves the error of Posit approximate multiplication calculation and enhances the accuracy of the calculation results.

[0034] 3. This invention effectively reduces the hardware overhead of the Posit multiplier through approximate calculation. Combined with a hardware-friendly error compensation strategy, it effectively improves the calculation error with minimal additional overhead, which can promote the application of the Posit data format and computing unit in edge intelligent computing. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the overall operation flow of an approximate multiplication method based on Posit data according to an embodiment of the present invention.

[0036] Figure 2 This is a schematic diagram of the Posit data format in an approximate multiplication operation method based on Posit data according to an embodiment of the present invention.

[0037] Figure 3 This is a schematic diagram of decoding the Posit data in an approximate multiplication operation method based on Posit data according to an embodiment of the present invention.

[0038] Figure 4 This is a circuit diagram for generating the mask sequence in an embodiment of the present invention.

[0039] Figure 5 This is a circuit diagram for generating segmentation flags from the last digit value in an embodiment of the present invention.

[0040] Figure 6 This is a circuit diagram for generating compensation vectors according to an embodiment of the present invention.

[0041] Figure 7 This is a schematic diagram illustrating the addition and merging of the compensation vector and the mantissa of the logarithmic field in an embodiment of the present invention.

[0042] Figure 8 This is a schematic diagram of the product Posit format encoding operation according to an embodiment of the present invention. Detailed Implementation

[0043] The present invention will be further described in detail below with reference to the accompanying drawings.

[0044] Example 1

[0045] Reference Figure 1 This embodiment provides an approximate multiplication method based on Posit data, comprising:

[0046] S1. Obtain two Posit data as input, and parse the obtained Posit data to obtain the sign bit, exponent extension bit, exponent bit and mantissa bit of the two Posit data respectively.

[0047] S2. Concatenate the exponent extension bits and exponent of each Posit data to obtain the equivalent exponent bits of each Posit data. Determine the mantissa truncation bit width control signal based on the equivalent exponent bits of the Posit data.

[0048] S3. Convert the two mantissa bits obtained from parsing into logarithmic field mantissa values, use the mantissa truncation bit width control signal to truncate the logarithmic field mantissa values, and compensate for the truncation error of the truncated logarithmic field mantissa values.

[0049] S4. Generate a logarithmic mant product and a logarithmic equivalent exponent from the logarithmic mant value and the equivalent exponent of the Posit data. Perform error compensation on the logarithmic mant product based on the numerical interval in which the logarithmic mant value is located.

[0050] S5. Based on the magnitude of the corrected logarithmic mantissa product, convert the logarithmic mantissa product and the logarithmic equivalent exponent into the linear mantissa product and the linear equivalent exponent.

[0051] S6. Process and split the equivalent exponent of the linear domain to obtain the exponent extension bits and exponent bits of the product, and concatenate them according to the Posit data format. Perform normalization and rounding operations on the concatenated data to obtain the final Posit format approximate multiplication result.

[0052] Specifically, an approximate multiplication method based on Posit data includes the following:

[0053] First, two data points in Posit format are obtained as operands. The two input operands IN1 and IN2 in Posit format are decoded according to the definition of the Posit data format to obtain the values ​​of each component. The Posit data is defined as Posit(nb, es), where nb represents the total bit width and es represents the bit width of the exponent part. The Posit data format contains four components: the sign bit S, the exponent extension bit Rg, the exponent bit E, and the mantissa bit F. The exponent bit S is fixed at 1 bit. The exponent extension bit Rg, the exponent bit E, and the mantissa bit F are arranged in sequence, with a total bit width of nb-1 bits. The exponent extension bit is a sequence of consecutive 0s or 1s, ending with the opposite bit (1 or 0). The bit width of the consecutive sequence in the exponent extension bit is set to r. When the consecutive sequence is a sequence of 0s, i.e., the structure of Rg is "00…01", r 0s and 1 terminating bit 1, the value of the exponent extension bit Rg is -r. When the consecutive sequence is a sequence of 1s, the value of the exponent extension bit Rg is r-1.

[0054] Both the exponent E and the mantissa F are unsigned numbers. The mantissa F is a normalized number, and its highest bit 1 is a hidden bit that does not appear in the Posit data format. When encoding in Posit format, the exponent extension bit Rg has the highest priority. If it does not occupy all nb-1 bits, then the exponent E appears in the Posit format. The maximum bit width of the exponent E is es bits. If the bit width of the exponent extension bit Rg and the exponent E still does not reach nb-1 bits, then the mantissa F appears in the Posit format, occupying all remaining bits. According to the above rules, the value represented by the Posit(nb,es) format can be expressed by the following formula:

[0055] ;

[0056] Where S represents the sign bit of the Posit data, es represents the bit width of the exponent part of the Posit data, Rg represents the exponent extension bits of the Posit data, E represents the exponent bits of the Posit data, and F represents the mantissa bits of the Posit data.

[0057] like Figure 2 As shown, the sign bit S has a fixed width of 1 bit. The remaining bits are shared by the exponent extension bit Rg, the exponent E, and the mantissa F, totaling nb-1 bits. The exponent extension bit Rg has the highest priority and can occupy all nb-1 bits. When the width of the exponent extension bit Rg is less than nb-1 bits, the exponent E and the mantissa F appear in the data format sequentially. Figure 2The two sections below illustrate the bit width of each component when representing different values ​​using the same data format. It can be seen that the bit width of the components is not fixed for different values. This design of component bit width in the data format allows for a larger data representation range, but it also incurs significant hardware overhead during computation. This significant hardware overhead stems from two sources: first, because the component bit width is uncertain, dedicated encoding / decoding circuits are needed to extract the values ​​of each component or encode the calculation results into the Posit data format; second, in integrated circuit design, all modules must be designed according to the maximum possible bit width of the operands. Therefore, the processing circuit for the exponent extension bit Rg has a bit width of nb-1 bits, and the calculation circuit for mantissa multiplication has a bit width of nb-5 bits. Their total overhead is far greater than that of a calculation circuit with a total bit width of nb bits and fixed component bit widths. Therefore, the overhead of the Posit arithmetic unit is far greater than that of a floating-point arithmetic unit with the same bit width.

[0058] like Figure 1 As shown, for neural network computation, due to the fault-tolerant nature of neural networks, it is possible to consider using approximate computational units to reduce energy consumption during the computation process and improve computational performance. Figure 1 This is a schematic diagram of the data path of the Posit approximation multiplier proposed in this invention. It includes operand decoding processing, exponent, sign processing and bit width control processing, logarithmic field conversion processing, operand value interval detection processing, logarithmic field mantissa multiplication processing, approximation error compensation processing, logarithmic field inverse conversion and product encoding.

[0059] First, operand decoding is performed. The operand decoding module receives two input data IN1 and IN2 in the format Posit(nb, es), where nb is the total bit width and es is the exponent part bit width. It then parses out the sign bit S, exponent extension bit Rg, exponent bit E, and mantissa bit F for each data point. Specifically, the decoding circuitry is as follows: Figure 3 As shown, firstly, based on the sign bit of the input operand, it is determined whether two's complement calculation is needed. If the sign bit is 0, i.e., the input operand is positive, two's complement calculation is not needed. However, if the sign bit is 1, two's complement calculation is needed. Two's complement calculation involves two logical operations: first, all bits of the input operand are inverted, and then 1 is added to the least significant bit. After the two's complement calculation is completed, in order to use a unified leading zero counter to detect the bit width of the exponent extension bit Rg, the most significant bit of the exponent extension bit Rg, i.e., the sign bit of the exponent extension bit, needs to be XORed with each bit of the sequence to be decoded. That is, when the leading sequence of the exponent extension bit Rg is a sequence of 1s, the leading sequence is converted into a sequence of 0s so that the bit width can be calculated using the leading zero counter.

[0060] The processed sequence is fed into a leading zero counter for counting. The count value is the number of leading zeros, r, in the sequence. Based on the number of leading zeros and the value of the leading sequence in the original exponent extension bit, the value of the exponent extension bit, Rg, can be calculated: when the leading sequence in the exponent extension bit, Rg, is a sequence of 1s, the value of the exponent extension bit is r–1; when the leading sequence in the exponent extension bit, Rg, is a sequence of 0s, the value of the exponent extension bit is -r. The value of -r can be obtained by calculating the two's complement of r. After the leading zero counting module calculates the number of leading zeros, r, the bit width of the exponent extension bit, Rg, can be obtained, which is r+1. Then, the sequence to be decoded after the two's complement calculation of the original input operand is logically left-shifted by r+1 bits. After the shift is complete, the exponent extension bit, Rg, has been removed. The high es bits of the remaining sequence are the exponent E, and the remaining part is the fractional part of the mantissa F. After filling its highest bit with a hidden bit 1, the complete mantissa F can be obtained.

[0061] After the operands are decoded, a logarithmic approximation multiplication operation is performed on the mantissas F1 and F2 of the two operands. First, the mantissas F1 and F2 are transformed from the linear domain to the logarithmic domain. The transformation process uses the Mitchell approximation algorithm, i.e. In this context, log2(1+x) represents the exact logarithmic value of the mantissa of the Posit data, and x represents the fractional part of the mantissa. Since the mantissas F1 and F2 in the Posit data format are normalized numbers, the hidden bit 1 and its right-hand fractional part can be directly separated after decoding. Therefore, the part after removing the hidden bit 1 is the mantissa converted to the logarithmic field, denoted as FL1 and FL2. The Mitchell approximation algorithm is a simplified method to convert linear multiplication into logarithmic addition. Its mathematical essence is to directly approximate the logarithmic transformation value of the mantissa in the linear field with the fractional part of the mantissa.

[0062] Conventional logarithmic transformations require lookup table operations or complex transcendental function calculations, resulting in significant overhead in terms of computational delay or circuit area. The approximate logarithmic domain transformation process used in this embodiment requires no additional computation. Although the transformation process is simple, since the true value of log2(1+x) is always slightly greater than x in the range x∈[0,1), for example, when x=0.5, log2(1.5)≈0.58496, which is greater than x=0.5, using x to approximate log2(1+x) will introduce a negative error. Therefore, the error compensation technique described later in this embodiment is needed to reduce the impact of the error on the final result. After obtaining the mantissas FL1 and FL2 of the logarithmic domain, in order to further reduce the overhead of subsequent calculations, the mantissas FL1 and FL2 of the logarithmic domain need to be truncated. The truncation is based on the mantissa bit width in the calculated Posit product.

[0063] Step 2 mainly includes three operations: calculating the sign bit of the product, calculating the equivalent exponents of the two operands, and calculating the mantissa width of the product. The sign bit is calculated by XORing the signs of the two operands. The equivalent exponent is obtained by concatenating the exponent extension bits Rg and the exponent E of the two operands. After obtaining the equivalent exponents, they are added together to obtain the equivalent exponent of the product. The obtained equivalent exponent is then decomposed; after removing the lower exponent E, the remaining part is the value of the exponent extension bits Rg of the product, from which the exponent extension bits can be calculated. The bit width is used to obtain the exponent extension bits of the product according to the encoding method of the Posit data format. After determining the bit width, since the bit widths of the sign bit and exponent bit are both fixed values, the mantissa in the product can be calculated. The bit width Fw is such that only the mantissa of Fw bits appears in the final product, while other redundant bits are discarded. Therefore, to further improve computational energy efficiency, redundant bits can be truncated to reduce the number of logical operations. Since the value of Fw varies depending on the exponent extension bit width, where Fw is the mantissa in the product... bit width, such as Figure 4 As shown, in this invention, the value of the exponent extension bits is used to generate a mask sequence through combinational circuitry. This mask sequence corresponds to the mantissa product. The mask sequence corresponding to the bits that need to be retained in the mantissa product has a value of 1, and the mask sequence corresponding to the bits that need to be discarded has a value of 0. Before performing the mantissa multiplication, a logical AND operation is performed between the mantissa F and the mask sequence to discard redundant bits, thereby improving computational efficiency.

[0064] The principle of the combinational circuit is as follows: For a typical Posit data format with a bit width of nb, the mask sequence is generated as follows: For an nb-bit Posit format, the bit width of its exponent extension bit value is nd = log2(nb). Since the minimum bit width of the exponent extension bit is 2 bits, the sign bit occupies 1 bit, and the exponent bit occupies es bits, the maximum bit width of the mantissa bits is nb – es – 3 bits. For the mask sequence, the generated mask sequence is the same whether the exponent extension bit is positive or negative. Therefore, in the design, only the case where the exponent extension bit value is positive is considered. The logical truth table for generating the mask sequence from the exponent extension bit value is shown in Table 1.

[0065] Table 1 is the logical truth table for generating the mask sequence of the exponential extension bits:

[0066]

[0067] To simplify the process of generating a mask sequence from the exponent extension bit values, this invention sets up an intermediate vector. First, the intermediate vector is generated from the exponent extension bit values, and then the final mask sequence is generated from the intermediate vector. The intermediate vector is set to one-hot encoding, meaning that only one bit in the entire vector sequence has a value of 1. The rule for generating the intermediate vector from the exponent extension bit values ​​is: when the exponent extension bit value is i in binary encoding, the i-th bit of the intermediate vector is 1. Therefore, first, a binary encoding with the same number of bits as the exponent extension bit value, i, is generated. Then, this encoding is bitwise XORed with the exponent extension bit value. Finally, the resulting sequence is bitwise ANDed to obtain the value of the i-th bit in the intermediate vector. Finally, when generating the mask sequence from the intermediate vector, a logical OR operation is performed: for each bit, all bits with weights no higher than the current bit are ORed to obtain the final mask sequence. For a specific bit width, the circuit can be simplified logically when generating the mask sequence using the above method. When nb=16 and es=2, the circuit after logical simplification is as follows: Figure 4 As shown.

[0068] like Figure 5 As shown, the mantissa of the decoded operands is converted from the linear domain to the logarithmic domain. A mask sequence generated by bit-width control is used to truncate the mantissa of the converted logarithmic domain. During the logarithmic domain conversion, since the mantissa is already a normalized number, the fractional part of the mantissa is directly extracted as the mantissa value of the converted logarithmic domain. During the masking operation, the mask sequence generated by the bit-width control module is logically ANDed with the high-order bits of the two operand mantissas. Excess bits in the mantissa are set to zero. To compensate for the precision loss caused by mantissa truncation, bits after the effective mantissa bits are set to 1. This module ultimately outputs the mantissas of the two logarithmic domains, ready for logarithmic domain multiplication operations.

[0069] While performing logarithmic field transformation and mantissa masking operations, the numerical range of the operand is detected to generate the required error compensation value based on the range it falls within. Here, we take the four-segment error compensation method as an example to introduce the detailed implementation scheme. The eight-segment method is similar to the four-segment method, specifically:

[0070] In the calculation, for the mantissa (1+x), its logarithmic field transformation value log2(1+x) is approximated by x. By analyzing the values ​​of the two functions y=x and y=log2(1+x) in the interval [0,1), it can be seen that the logarithmic field transformation value obtained by the approximation method is always less than the logarithmic field value obtained by the exact transformation, and the difference (i.e., the error) between the two is different in different subintervals.

[0071] The error between log2(1+x) and x varies at different positions within the [0,1) interval. To effectively compensate for this error, this invention divides the entire [0,1) interval into multiple sub-intervals, and then uses the average error between log2(1+x) and x within each sub-interval for error compensation. The more sub-intervals there are, the more accurate the error compensation; however, this also increases the circuit resources consumed in detecting the sub-interval where the operand resides and in error compensation. In practical applications, different sub-interval division methods can be set according to different hardware overhead and computational error requirements.

[0072] When higher circuit overhead requirements exist, fewer sub-intervals can be used for segmented error compensation. For example, a four-segment method can be used to divide the entire [0,1) interval into four parts. Since digital integrated circuit design uses binary digital logic, binary values ​​are used to represent the start and end values ​​of the intervals when dividing them. Because the error values ​​between the numerical intervals 0~0.000012 and 0.111112~1 are very small, these two intervals are treated as two separate sub-intervals without error compensation. The remaining interval is divided into four sub-intervals: 0.000012~0.012, 0.012~0.12, 0.12~0.112, and 0.112~0.111112. Since the error is largest when x=0.5, the closer to 0.5, the smaller the interval range; conversely, the closer to 0 and 1, the larger the interval range.

[0073] When performing interval detection, since the interval boundary values ​​are represented in binary, it is only necessary to check the value of the high 5 bits of the operand. The interval in which the operand belongs can be determined based on the number of 0s in the high 5 bits. Performing the same numerical interval detection on both operands produces two three-bit output values, indicating which interval each operand belongs to (for example, 00 represents that the operand is in the 0th interval, i.e., 0.000012~0.012).

[0074] When performing error compensation in the error compensation module, different compensation vector values ​​are set according to the interval where the operands are located. These values ​​are then added to the result obtained from the logarithmic field multiplication. The calculation process for the compensation value is as follows: First, the average error value between log2(1+x) and x within the interval is calculated. Then, the binary number that is numerically closest to the average error value and has only one bit set to 1 is used as the error compensation value. Since the value of x is always less than log2(1+x), a value greater than the average error value is generally selected when choosing the compensation value to offset the negative error generated during the logarithmic field conversion. In this invention, the compensation value for the interval 0.000012~0.012 is 0.00001, the compensation value for the interval 0.012~0.12 is 0.0001, the compensation value for the interval 0.12~0.112 is 0.0001, and the compensation value for the interval 0.112~0.111112 is 0.00001. For each of the two operands, select the corresponding compensation vector, and add the two compensation vectors to the product of the logarithmic field to complete the error compensation of the approximate multiplication result in the logarithmic field.

[0075] When higher computational precision is required, more sub-intervals can be used for piecewise error compensation. For example, an eight-segment method can be used to divide the entire [0,1) interval into eight parts. Between the numerical intervals 0~0.0000012 and 0.1111112~1, since the difference between log2(1+x) and x is very small, no error compensation is performed in these two intervals. The remaining interval is divided into eight sub-intervals: 0.0000012~0.0012, 0.0012~0.012, 0.012~0.0112, 0.0112~0.12, 0.12~0.1012, 0.1012~0.112, 0.112~0.1112, and 0.1112~0.1111112. Since the error is largest at x=0.5, the closer to 0.5, the smaller the interval range; conversely, the closer to 0 and 1, the larger the interval range. When performing interval detection, since the interval boundary values ​​are represented in binary, only the value of the high 6 bits of the operand needs to be checked. The number of 0s in the high 6 bits determines the interval in which the operand belongs. Performing the same numerical interval detection on both operands produces two three-bit output values, each indicating which interval each operand belongs to (e.g., 000 represents the operand being in the 0th interval, i.e., 0.0000012~0.0012).

[0076] When performing error compensation in the error compensation module, different compensation vector values ​​are set according to the interval where the operand is located. These values ​​are then added to the result obtained by multiplying the logarithmic field. The calculation process for the compensation value is as follows: First, the average error value of log2(1+x) and x within the interval is calculated. Then, the binary number that is numerically closest to the average error value and has only one bit set to 1 is used as the error compensation value. Since the value of x is always less than log2(1+x), when selecting the compensation value, a number greater than the average error value is generally chosen to offset the negative error generated during the logarithmic domain conversion. In this invention, the compensation value for the interval 0.0000012~0.0012 is 0.000001, the compensation value for the interval 0.0012~0.012 is 0.00001, the compensation value for the interval 0.012~0.0112 is 0.0001, the compensation value for the interval 0.0112~0.12 is 0.0001, the compensation value for the interval 0.12~0.1012 is 0.0001, the compensation value for the interval 0.1012~0.112 is 0.0001, the compensation value for the interval 0.112~0.1112 is 0.00001, and the compensation value for the interval 0.1112~0.1111112 is 0.000001. For each of the two operands, select the corresponding compensation vector, and add the two compensation vectors to the product of the logarithmic field to complete the error compensation of the approximate multiplication result in the logarithmic field.

[0077] Traditional iterative compensation methods require additional logic resources of a similar scale to the main computing circuit, resulting in significant overhead. The error compensation method of this invention incorporates hardware characteristics into the design of interval partitioning and compensation vector settings, ensuring that the additional hardware consumption generated during the error compensation process is sufficiently small, achieving effective approximate error compensation with minimal hardware overhead.

[0078] The hardware design characteristics have been considered during interval partitioning, effectively simplifying the design of the interval detection circuit. In the four-segment method, segments are formed according to the values ​​listed in Table 2, where segmentation flags are used to indicate the numerical sub-intervals of the operands in the circuit. The segmentation flag values ​​are not set in the order of natural values, but rather based on the principle of simplifying logic circuits, using the fewest possible logic gates to generate flag vectors that distinguish different sub-intervals. The circuit for generating segmentation flags based on the mantissa value is shown below. Figure 5 As shown, when using it, only the high 5 bits of the mantissa are needed.

[0079] Table 2 is a table of numerical segments:

[0080]

[0081] The error compensation value for each sub-interval is determined through numerical analysis. Specifically, firstly, the average difference between log2(1+x) and x in each sub-interval is calculated. Then, for each sub-interval, a binary number is selected whose value is not less than the average difference obtained in that sub-interval, and whose binary representation has only one bit valued as 1, with the remaining bits all being 0. Based on this rule, the error compensation value for each sub-interval is calculated, as shown in the third column of Table 2. During error compensation, the compensation value is simply added to the high 5 bits of the logarithm field mantissa. Since the high bits of the compensation value are 0, only the low 3 bits of the high 5 bits of the logarithm field mantissa need to be considered during addition. Based on this, a 3-bit compensation vector is generated for hardware calculation of error compensation. Since each logarithmic field mantissa requires error compensation, to reduce the number of sequences involved in the superposition, this invention first superimposes two error compensation values ​​to generate a total compensation vector. During error compensation, only one vector needs to be added to the logarithmic field mantissa. The method for generating the total compensation vector is shown in Table 3. The circuit for obtaining the final total compensation vector through the segmentation flags of the two operands is shown below. Figure 6 As shown in the diagram, the process of combining the compensation vector with the mantissa of the logarithmic field is illustrated below. Figure 7 As shown.

[0082] Table 3 is the compensation vector table:

[0083]

[0084] After obtaining the logarithmic domain product, an inverse logarithmic domain transformation is performed on the result to generate the mantissa product FNP and the equivalent exponent EffN in the linear domain. During the inverse transformation, based on the value of the logarithmic domain mantissa product FLP, when FLP is less than 1, the linear domain mantissa product FNP is 1 + FLP, and the linear domain equivalent exponent EffN is EffL; conversely, when FLP is greater than or equal to 1, the linear domain mantissa product FNP is FLP, and the linear domain equivalent exponent EffN is EffL + 1. The core of generating the linear domain mantissa product FNP and the equivalent exponent EffN is based on the Mitchell approximation algorithm and the Posit mantissa normalization property. When two input operands A and B undergo logarithmic domain transformation and addition, the result of the logarithmic domain product is obtained. This result includes the logarithmic domain equivalent exponent EffL and the logarithmic domain mantissa product FLP. The specific principle is as follows: First, it is necessary to clarify the mathematical representation of the operands in the linear domain. Assume that the mantissa (decimal part) of the first operand A is represented by... This indicates that the equivalent index is used This indicates that the mantissa (decimal part) of the second operand B is represented by... This indicates that the equivalent index is used If we express A as follows, then A in the linear domain can be represented as Similarly, B can be represented as ,in, and These represent the fractional parts of the first operand A and the second operand B, respectively. and Let A and B be the equivalent exponents of the first operand A and the second operand B, respectively. During the logarithmic field transformation, the operands are processed using the Mitchell approximation algorithm: taking the base-2 logarithm of A and B, we obtain:

[0085] ,

[0086] ,

[0087] because For decimals less than 1 It can be approximated as ,therefore Similarly, Addition in the logarithmic field yields a product in the logarithmic field:

[0088] ,in, The equivalent exponent for the product of logarithmic fields is... It is the logarithmic mantissa product (FLP).

[0089] Transforming from the logarithmic field to the linear field yields a product in the linear field:

[0090] The product of the mantissas of the linear domain is ;

[0091] ① When the product value of the logarithmic field That is, if the FLP in the main text is less than 1, the Mitchell algorithm is used again. Substituting this into the expression for the product of the mantissas in the linear domain, we get: That is, 1+FLP.

[0092] ② When the product value of the logarithmic field That is, when FLP is greater than 1 in the text, the expression for product of linear domains is rewritten as follows: Therefore, the equivalent exponent of the linear field changes to ,because and All are less than 1 (the decimal part of the last digit), therefore... The value must be less than 2, when When the value is greater than 1, subtract 1 from it. It must be less than 1, so Mitchell's algorithm is used again. Substituting this into the expression for the product of the mantissas in the linear domain, we get... This is known as FLP.

[0093] Combining the equivalent exponent and sign bit of the product, the final product is encoded in Posit format. The specific circuit calculation process is as follows: Figure 8 As shown, firstly, the equivalent exponent is calculated using two's complement based on its sign: if the equivalent exponent is positive, no two's complement calculation is needed; if the equivalent exponent is negative, two's complement calculation is required. In the result, the lower es bits are taken as the exponent of the product, and the remaining bits are the absolute value R of the product's exponent extension bits. Then, the width of the exponent extension bits is determined by the value of the exponent extension bits: if the equivalent exponent is positive, the preceding sequence in the exponent extension bits is 1, and the length of the preceding sequence is R+1. Considering the terminating bit of the exponent extension bits, the total number of exponent extension bits is R+1. 2; Conversely, if the equivalent exponent is negative, the preceding sequence in the exponent extension is 0, and the length of the preceding sequence is R. Considering the termination position, the total number of bits in the exponent extension is R+1. When finally generating the exponent extension, a 2-bit sequence is first generated. This initial 2-bit sequence is the basis for generating the exponent extension. Its two bits correspond to the preceding sequence characteristics and the termination position characteristics of the exponent extension, respectively. The highest bit is the same as the value of the preceding sequence in the exponent extension, and the lowest bit is the value of the termination position of the exponent extension (opposite to the highest bit). Then, the final exponent extension is generated by an arithmetic right shift. Since the exponent extension already has two bits before the shift, the shift amount of the arithmetic right shift is the total number of bits in the exponent extension minus 2. Therefore, if... Figure 8 As shown, when the equivalent exponent is positive, the displacement is R, and the initial two-bit sequence value is 10; when the equivalent exponent is negative, the displacement is R–1, and the initial two-bit sequence value is 01. In actual calculations, multiplication of large numbers may cause overflow, meaning that data formats of the same bit width cannot accurately represent the product. In this case, the number of bits extended by the exponent of the product exceeds the total data bit width nb. In the Posit calculation rule, if overflow occurs, the calculation result is directly taken as NaR, which is encoded as a sign bit of 1 and all other bits nb–1 of 0. Therefore, if overflow occurs, no shift operation is required, and even if a shift operation is performed, the final result will be replaced by the NaR format. Therefore, to reduce redundant operation steps, this invention controls the maximum displacement. When overflow occurs, i.e., when the displacement is greater than the data bit width nb, the displacement is directly set to 0.

[0094] The data involved in the arithmetic right shift, besides the initial two exponent extension bits, also includes the exponent and mantissa bits of the product. These three are concatenated before the final arithmetic right shift operation. Since the main part of the calculation uses approximation, the final shifted result is not rounded to further reduce computational overhead. Finally, based on the sign of the calculated product, the two's complement of the shifted sequence is calculated: if the product is positive, no two's complement calculation is needed; conversely, if the product is negative, two's complement calculation is required. After the two's complement calculation is completed, the final Posit format product is obtained. This invention discloses an approximate multiplication method based on the Posit format, aiming to reduce hardware overhead while ensuring computational accuracy through approximate calculation in the number field and efficient error compensation strategies. It is suitable for high-energy-efficiency chip design in the field of edge intelligent computing.

[0095] Example 2

[0096] The difference between this embodiment and Embodiment 1 is that this embodiment provides an approximate multiplication operator based on Posit data, including:

[0097] The operand decoding module is configured to: acquire two Posit data as input, and parse the acquired Posit data to obtain the sign bit, exponent extension bit, exponent bit and mantissa bit of the two Posit data respectively;

[0098] The preprocessing module is configured to: concatenate the exponent extension bits and the exponent of each Posit data to obtain the equivalent exponent bits of each Posit data, and determine the mantissa truncation bit width control signal based on the equivalent exponent bits of the Posit data;

[0099] The logarithm field conversion module is configured to: convert the two mantissa bits obtained from parsing into logarithm field mantissa values, truncate the logarithm field mantissa values ​​using the mantissa truncation bit width control signal, and compensate for truncation errors in the truncated logarithm field mantissa values.

[0100] The multiplication and compensation module is configured to generate a logarithmic mantissa product and a logarithmic equivalent exponent from the logarithmic mantissa value and the equivalent exponent of the Posit data, and to perform error compensation on the logarithmic mantissa product according to the numerical interval in which the logarithmic mantissa value is located.

[0101] The logarithmic field inverse conversion module is configured to convert the logarithmic field mantissa product and the logarithmic field equivalent exponent into the linear field mantissa product and the linear field equivalent exponent based on the magnitude of the corrected logarithmic field mantissa product.

[0102] The product encoding module is configured to process and split the equivalent exponent in the linear field to obtain the exponent extension bits and exponent bits of the product, and then concatenate them according to the Posit data format. The concatenated data is then normalized and rounded to obtain the final Posit format approximate multiplication result.

[0103] The above are all preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Therefore, all equivalent changes made in accordance with the structure, shape and principle of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A method of approximate multiplication based on Posit data, characterized by, The application relates to a posit data multiplication method and device. Two posit data are acquired as inputs, and the acquired posit data are parsed, the sign bits of the two posit data are obtained through a sign bit exclusive or operation, the exponent extension bits of the two posit data are obtained through a two's complement operation, the exponent bits of the two posit data are obtained through a pre-zero counting circuit, and the mantissa bits of the two posit data are obtained through a left shifter. The exponent extension bits and the exponent bits of each posit data are spliced to obtain the equivalent exponent bits of each posit data, and the mantissa bit width control signal is determined according to the equivalent exponent bits of the posit data. The mantissa bits of the two parsed posit data are converted into logarithmic domain mantissa values, the logarithmic domain mantissa values are truncated by using the mantissa bit width control signal, and the truncated logarithmic domain mantissa values are compensated for truncation errors. The logarithmic domain mantissa values and the equivalent exponent bits of the posit data are respectively subjected to addition operation to generate logarithmic domain mantissa products and logarithmic domain equivalent exponents, error compensation values corresponding to the number intervals of the logarithmic domain mantissa values of the two input posit data are determined, and the logarithmic domain mantissa products are subjected to error compensation. The error compensation values corresponding to the number intervals of the logarithmic domain mantissa values of the two input posit data are determined by dividing the value range [0, 1) of the logarithmic domain mantissa values into multiple subintervals, extracting the high bits of FL1 and FL2, determining the subintervals where FL1 and FL2 are located according to the number of 0 in the high bits, respectively generating a segmented flag 1 and a segmented flag 2, selecting a value not less than the average error of log2(1+x) and x in the interval and having only one bit as 1 in binary representation as a compensation value for each subinterval that needs to be compensated, determining a total compensation vector according to the segmented flag 1 and the segmented flag 2, and performing addition operation on the total compensation vector and the logarithmic domain mantissa products to obtain the modified logarithmic domain mantissa products. Wherein, log2(1+x) represents the logarithmic domain accurate value of the mantissa of the posit data, and x represents the decimal part of the mantissa of the posit data. The error compensation strategy realizes effective improvement of calculation errors with introduction of a small additional overhead, and promotes the application of the posit data format and the operation component in edge intelligent calculation. According to the value size of the modified logarithmic domain mantissa products, the logarithmic domain mantissa products and the logarithmic domain equivalent exponents are converted into linear domain mantissa products and linear domain equivalent exponents. The linear domain equivalent exponents are processed and split to obtain the exponent extension bits and the exponent bits of the products, and the spliced data is normalized and rounded to obtain the final posit format approximate multiplication result. The logarithmic domain approximate calculation and the efficient error compensation strategy can reduce the hardware overhead while ensuring the calculation accuracy, and are used for high-energy efficient chip design in the field of edge intelligent calculation.

2. The method of claim 1, wherein, The parsing processing of the obtained Posit data includes: taking the Posit(nb, es) format data as input data IN1, performing a logical exclusive OR operation on the low nb-1 bits of IN1 and the sign bit S, adding the operation result to the sign bit of IN1 to obtain a Posit sequence, determining the exponent extension bit and the bit width of IN1 according to the highest bit state of the Posit sequence, performing left shift on the Posit sequence according to the bit width of the exponent extension bit to remove the exponent extension bit, selecting the high es bits as the exponent bits based on the left-shifted Posit sequence, taking the low nb-es-1 bits as the decimal part of the mantissa of IN1, and supplementing a hidden bit 1 at the highest bit of the decimal part to obtain a complete mantissa, wherein nb is the total bit width of the Posit data, and es is the exponent bit width of the Posit data.

3. The method of claim 2, wherein, The determination of the exponent extension bit and the bit width of IN1 according to the highest bit state of the Posit sequence includes: when the highest bit of the Posit sequence is 1, performing a bitwise negation operation on the Posit sequence, and then inputting the negated Posit sequence into a front zero counting module to calculate the length of a front zero sequence; when the highest bit of the Posit sequence is 0, directly inputting the Posit sequence into the front zero counting module to calculate the length of the front zero sequence; and finally determining the exponent extension bit and the bit width according to the length of the front zero sequence, respectively.

4. The method of claim 1, wherein, The determination of the mantissa truncation bit width control signal according to the equivalent exponent bits of the Posit data includes: based on the decoded two Posit data, extracting the exponent extension bit and the exponent bit of each Posit data to perform binary bit splicing to generate the equivalent exponent bit of each Posit data, performing an addition operation on the equivalent exponent bits of the two Posit data to obtain the equivalent exponent bits of the product, extracting the values of the product exponent bit and the product exponent extension bit according to the equivalent exponent bits of the product, determining the bit width of the product exponent extension bit in combination with the highest bit of the product exponent extension bit, and calculating the product mantissa bit width according to the total bit width of the Posit data.

5. The method of claim 1, wherein, The conversion of the two parsed mantissa bits into log domain mantissa values includes: performing linear domain to log domain conversion on F1 and F2 respectively by using the Mitchell approximation algorithm, removing the hidden bit 1 in F1 and F2, taking the remaining decimal part as the corresponding log domain mantissa values FL1 and FL2, performing low bit truncation on the binary sequences of FL1 and FL2 according to the product mantissa bit width FLen, and only retaining the FLen bit data from the highest bit of FL1 and FL2, and discarding all low bit data after the FLen bit. Wherein, F1 is the mantissa bit of the first Posit data IN1, F2 is the mantissa bit of the second Posit data IN2, Flen is the bit width of the product mantissa, FL1 is the log domain mantissa value of F1, and FL2 is the log domain mantissa value of F2.

6. The method of claim 1, wherein, The reversing the logarithm domain mantissa product and the logarithm domain equivalent exponent into the linear domain mantissa product and the linear domain equivalent exponent comprises, after obtaining the logarithm domain product, based on the numerical relationship between the logarithm domain mantissa product FLP and 1, combining the Mitchell approximation algorithm to perform the reversing, when FLP is less than 1, the linear domain mantissa product FNP is the sum of 1 and FLP, and the linear domain equivalent exponent EffN is the logarithm domain equivalent exponent EffL, when FLP is greater than or equal to 1, the linear domain mantissa product FNP is FLP, and the linear domain equivalent exponent EffN is EffL plus 1. Wherein, FLP is the sum of the logarithm domain mantissa values of the two input operands, EffL is the sum of the equivalent exponents of the two input operands, EffN is the linear domain equivalent exponent, and FNP is the linear domain mantissa product.

7. The method of claim 1, wherein, The processing of the linear domain equivalent exponent and the splitting to obtain the exponent extension bit and the exponent bit of the product comprise that when the linear domain equivalent exponent is negative, the two's complement calculation is performed on the linear domain equivalent exponent, when the linear domain equivalent exponent is positive, the linear domain equivalent exponent is kept unchanged, the low es bit of the processed linear domain equivalent exponent is extracted as the exponent bit of the product, the remaining high bit is the numerical value of the product exponent extension bit, and the product exponent extension sequence is generated according to the sign of the linear domain equivalent exponent, wherein es is the Posit data exponent part bit width.

8. The method of claim 1, wherein, The normalization and rounding operation on the spliced data comprise that according to the bit shift amount of the right shift operation and the total bit width of the Posit data, the overflow is detected, when the overflow occurs, the bit shift amount is set to 0, and the final product result is set to the NaR format, when the detection result does not occur overflow, the exponent extension bit of the product, the exponent bit and the mantissa bit of the product are spliced, the arithmetic right shift operation is performed on the spliced data, and the two's complement correction is performed on the sequence after the arithmetic right shift according to the product sign bit to obtain the final Posit data product.

9. An approximate multiplier based on Posit data, performing the method of claim 1, characterized by, Comprise: The operand decoding module is configured to obtain two Posit data as input, and parse the obtained Posit data to obtain the sign bit, the exponent extension bit, the exponent bit and the mantissa bit of the two Posit data respectively; The preprocessing module is configured to splice the exponent extension bit and the exponent of each Posit data to obtain the equivalent exponent bit of each Posit data respectively, and determine the mantissa truncation bit width control signal according to the equivalent exponent bit of the Posit data; The logarithm domain conversion module is configured to convert the two mantissa bits obtained by parsing into logarithm domain mantissa values, truncate the logarithm domain mantissa values by using the mantissa truncation bit width control signal, and compensate the truncation error of the truncated logarithm domain mantissa values; The multiplication and compensation module is configured to perform addition operation on the logarithm domain mantissa values and the equivalent exponent bits of the Posit data respectively to generate the logarithm domain mantissa product and the logarithm domain equivalent exponent, determine the error compensation value corresponding to the numerical interval of the logarithm domain mantissa values of the two input Posit data, and perform error compensation on the logarithm domain mantissa product. The log domain reverse conversion module is configured to convert the log domain mantissa product and the log domain equivalent exponent into a linear domain mantissa product and a linear domain equivalent exponent according to a numerical size of the corrected log domain mantissa product; The product encoding module is configured to process the linear domain equivalent exponent, split the linear domain equivalent exponent to obtain an exponent extension bit and an exponent bit of the product, splice the exponent extension bit and the exponent bit according to the Posit data format, and perform normalization and rounding operations on the spliced data to obtain a final Posit format approximate multiplication result.

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