Chip, processor, computer equipment and instruction execution method

Abstract

The invention discloses a chip, a processor, computer equipment and an instruction execution method, and relates to the field of chips. The chip comprises a memory unit used for obtaining instruction configuration information of a first instruction; sending the instruction configuration information to a decoding unit; the decoding unit is used for decoding the instruction configuration information to obtain a loading instruction and an operation instruction; the loading unit is used for responding to the received loading instruction, executing the loading instruction and obtaining an operand; sending the operands to an arithmetic unit; and the operation unit is used for responding to the operand received at the first moment under the condition that the operation instruction is received, starting to execute the operation instruction from the first moment, and obtaining an operation result of the operand. When the loading instruction is executed to obtain the operand, the operation instruction can be executed in a seamless connection manner, so that an idle clock period caused by waiting for receiving the operation instruction is avoided, the waste of chip execution resources is reduced, and the chip performance is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chips, and in particular to a chip, a processor, a computer device, and an instruction execution method. Background Art

[0002] Under the Reduced Instruction Set Computer (RISC) architecture, the processor is designed to process relatively simple instructions. The processor can implement complex data processing flows through the combination of multiple simple instructions.

[0003] In related technologies, using addition as an example, a compiler compiles the source code to generate a load instruction packet and an operation instruction packet. Typically, developers reserve sufficient preset clock cycles for the processor to process the load instruction packet. This means that after the processor begins processing the load instruction packet, it delays by one preset clock cycle before starting to process the operation instruction packet.

[0004] However, if the processing time of the processor for the load instruction packet is less than the preset clock cycle, there are idle clock cycles within the preset clock cycle, thereby wasting the execution resources of the processor and causing the processor performance to degrade. Summary of the Invention

[0005] The present invention provides a chip, a processor, a computer device, and an instruction execution method, which can prevent the chip from generating idle clock cycles and improve chip performance. The technical solution is as follows:

[0006] In one aspect, a chip is provided, comprising: a memory unit, a decoding unit, a loading unit, and an operation unit;

[0007] The memory unit is configured to obtain instruction configuration information of a first instruction, the instruction configuration information being used to indicate execution information of an operation performed on an operand based on the first instruction; and send the instruction configuration information to the decoding unit;

[0008] The decoding unit is configured to decode the instruction configuration information to obtain a load instruction and an operation instruction, wherein the load instruction and the operation instruction are configured to implement the operation task of the operand indicated by the first instruction;

[0009] The loading unit is configured to, in response to receiving the loading instruction, execute the loading instruction to obtain the operand; and send the operand to the operation unit;

[0010] The operation unit is configured to, upon receiving the operation instruction, execute the operation instruction starting from the first moment in response to receiving the operand at the first moment, and obtain an operation result of the operand.

[0011] On the other hand, a processor is provided, comprising the chip as described above.

[0012] On the other hand, a computer device is provided, comprising the chip as described above.

[0013] On the other hand, an instruction execution method is provided, which is executed by a chip, wherein the chip includes: a memory unit, a decoding unit, a loading unit, and an operation unit; the method includes:

[0014] The memory unit acquires instruction configuration information of a first instruction, the instruction configuration information being used to indicate execution information of performing an operation on an operand based on the first instruction; and sends the instruction configuration information to a decoding unit;

[0015] The decoding unit decodes the instruction configuration information to obtain a load instruction and an operation instruction, wherein the load instruction and the operation instruction are used to implement the operation task of the operand indicated by the first instruction;

[0016] In response to receiving the load instruction, the load unit executes the load instruction to obtain the operand; and sends the operand to the operation unit;

[0017] When receiving the operation instruction, the operation unit executes the operation instruction starting from the first moment in response to receiving the operand at the first moment, and obtains the operation result of the operand.

[0018] On the other hand, a computer device is provided, comprising: a processor and a memory, wherein the memory stores a computer program, and the computer program is loaded and executed by the processor to implement the instruction execution method described above.

[0019] On the other hand, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and the computer program is loaded and executed by a processor to implement the instruction execution method as described above.

[0020] On the other hand, a computer program product is provided, which includes a computer program stored in a computer-readable storage medium, and a processor obtains the computer program from the computer-readable storage medium, so that the processor loads and executes it to implement the instruction execution method as described above.

[0021] The beneficial effects of the technical solutions provided in the embodiments of the present application include at least:

[0022] The decoding unit decodes the instruction configuration information obtained from the memory unit, and automatically splits the first instruction into a decoded load instruction and an operation instruction. When the load unit receives the load instruction, it executes the load instruction to obtain the operand and sends the operand to the operation unit. When the operation unit receives the operand, it executes the operation instruction to obtain the operation result. On the one hand, while decoding the first instruction, the task of splitting the first instruction is completed, thereby improving the execution efficiency of the first instruction. On the other hand, the load instruction and the operation instruction are decoded in parallel. After decoding, the chip can schedule and execute the load instruction and the operation instruction at any time. When the load instruction is executed to obtain the operand, the operation instruction can be executed seamlessly, avoiding the idle clock cycle caused by waiting for the operation instruction after obtaining the operand, thereby reducing the waste of chip execution resources and improving chip performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 is a structural block diagram of a computer system provided by an exemplary embodiment of the present application;

[0025] Figure 2 This is a structural block diagram of a chip provided by an exemplary embodiment of the present application;

[0026] Figure 3 is a schematic diagram of an instruction execution process provided by an exemplary embodiment of the present application;

[0027] Figure 4 is a structural block diagram of a chip provided by another exemplary embodiment of the present application;

[0028] Figure 5 is a parallel schematic diagram of the configuration and execution provided by an exemplary embodiment;

[0029] Figure 6 is a structural block diagram of a chip provided by another exemplary embodiment of the present application;

[0030] Figure 7 is a structural block diagram of a chip provided by yet another exemplary embodiment of the present application;

[0031] Figure 8 is a schematic diagram of instruction splitting provided by an exemplary embodiment of the present application;

[0032] Figure 9is a structural block diagram of a loading unit provided by an exemplary embodiment of the present application;

[0033] Figure 10 is a schematic diagram of data synchronization provided by an exemplary embodiment of the present application;

[0034] Figure 11 is a structural block diagram of a computing unit provided by an exemplary embodiment of the present application;

[0035] Figure 12 is a structural block diagram of a storage unit provided by an exemplary embodiment of the present application;

[0036] Figure 13 is a structural block diagram of a chip provided by another exemplary embodiment;

[0037] Figure 14 is a flowchart of an instruction execution method provided by an exemplary embodiment of the present application;

[0038] Figure 15 It is a structural block diagram of a computer device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0039] To make the objectives, technical solutions, and advantages of this application more clear, the following will further describe the embodiments of this application in detail with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0040] In this application, the terms "first", "second", etc. are used to distinguish identical or similar items with substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first" and "second", nor is there any limitation on the quantity and execution order.

[0041] Figure 1 The following is a block diagram of a computer system 100 according to an exemplary embodiment of the present application. This computer system 100 can implement the system architecture of the instruction execution method provided herein. This computer system 100 includes a terminal 110 and a server 120. The terminal 110 and / or the server 120 are provided with a chip provided herein, and the instruction execution method described above can be implemented using the chip provided in the terminal 110 and / or the server 120.

[0042] The terminal 110 can be an electronic device such as a mobile phone, a tablet computer, a vehicle-mounted terminal (vehicle computer), a wearable device, a PC (Personal Computer), a drone terminal, an AI (Artificial Intelligence) training terminal, etc. The terminal 110 can install and run a client with a target application. The target application can be an application for processing various instructions, which is not limited in this application. In addition, this application does not limit the form of the target application, including but not limited to App (Application, application) installed in the terminal 110, applet, etc., and can also be in the form of a web page.

[0043] Server 120 can be a standalone physical server, a server cluster or distributed system consisting of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud computing services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms. Server 120 can be the backend server of the target application described above, used to provide backend services to the client of the target application.

[0044] Cloud technology refers to a hosting technology that unifies hardware, software, and network resources within a wide area network (WAN) or local area network (LAN) to enable data computing, storage, processing, and sharing. Cloud technology is a general term for network technology, information technology, integration technology, management platform technology, and application technology, all based on the cloud computing business model. It can form a resource pool that can be used on demand with flexibility and convenience. Cloud computing technology will become a crucial support. Backend services for technical network systems, such as video websites, image websites, and more portals, require extensive computing and storage resources. With the rapid development and application of the internet industry, every item will likely have its own unique identification mark and will need to be transmitted to backend systems for logical processing. Data of varying levels will be processed separately, and data from all industries will require a strong system backend, which can only be achieved through cloud computing.

[0045] In some embodiments, the server 120 can also be implemented as a node in a blockchain system. Blockchain is a novel application model for computer technologies such as distributed data storage, peer-to-peer transmission, consensus mechanisms, and encryption algorithms. Blockchain is essentially a decentralized database, a series of data blocks generated using cryptographic methods. Each data block contains information about a batch of network transactions, which is used to verify the validity of the information (anti-counterfeiting) and generate the next block. Blockchain can include the blockchain underlying platform, the platform product service layer, and the application service layer.

[0046] The terminal 110 and the server 120 may communicate with each other via a network, such as a wired or wireless network.

[0047] In the instruction execution method provided in the embodiment of the present application, the execution subject of each step can be a computer device, specifically a chip as described above (which can be implemented as a processor) set in the computer device. The computer device refers to an electronic device with data calculation, processing and storage capabilities.

[0048] by Figure 1 As shown in the example, the above-mentioned instruction execution method can be executed by the terminal 110 (such as: the above-mentioned instruction execution method is executed by the processor set in the terminal 110), or the above-mentioned instruction execution method can be executed by the server 120 (such as: the above-mentioned instruction execution method is executed by the processor set in the server 120), or the terminal 110 and the server 120 interact and cooperate to execute the above-mentioned instruction execution method (such as: the processors respectively set in the terminal 110 and the server 120 interact and cooperate to execute the above-mentioned instruction execution method), and this application does not limit this.

[0049] Those skilled in the art will appreciate that the number of terminals 110 may be greater or less. For example, there may be only one terminal 110, or there may be dozens, hundreds, or even more terminals 110. The embodiments of the present application do not limit the number or device type of terminals 110.

[0050] In the Reduced Instruction Set Computer (RISC) architecture, the processor is designed to process relatively simple instructions. The processor can implement complex data processing processes by combining multiple simple instructions. In the related art, taking the addition operation as an example, the compiler compiles the source code to obtain a load instruction package and an operation instruction package. Usually, the developer will reserve sufficient preset clock cycles for the processor to process the load instruction package, that is, after the processor starts processing the load instruction package, it will start processing the operation instruction package after a delay of one preset clock cycle.

[0051] For example, at time t0, a load instruction is sent to the processor, and after receiving the load instruction, the processor executes the load instruction to obtain the operand; at time t6, an operation instruction is sent to the processor, and after receiving the operation instruction, the processor executes the operation instruction.

[0052] However, if the processor's processing time for the loaded instruction packet is less than the preset clock cycle, there will be idle clock cycles within the preset clock cycle. For example, if the actual completion time of instruction packet 1 is t3, then the processor does not execute any instructions from t3 to t6, that is, t3 to t6 belongs to the idle clock cycle (the idle clock cycle can be called an "instruction bubble"). The generation of idle clock cycles will waste the processor's execution resources and cause the processor performance to deteriorate.

[0053] The present application provides a chip which, on the one hand, completes the task of splitting the first instruction while decoding the first instruction, thereby improving the execution efficiency of the first instruction; on the other hand, decodes the load instruction and the operation instruction in parallel. After the decoding is completed, the chip can schedule and execute the load instruction and the operation instruction at any time. When the load instruction is executed to obtain the operand, the operation instruction can be executed seamlessly, avoiding the idle clock cycle caused by waiting for the reception of the operation instruction after obtaining the operand, thereby reducing the waste of chip execution resources and improving chip performance.

[0054] The chip provided in the embodiments of the present application is introduced below.

[0055] Please refer to Figure 2 , which shows a schematic diagram of a chip 200 provided by an exemplary embodiment. The chip 200 includes a memory unit 210, a decoding unit 220, a loading unit 230, and an arithmetic unit 240. The memory unit 210 is connected to the decoding unit 220, the decoding unit 220 is connected to the loading unit 230 and the arithmetic unit 240 respectively, and the loading unit 230 is connected to the arithmetic unit 240.

[0056] Optionally, the chip can be a processor with data processing functions, or a part of a processor. Schematically, the chip can be implemented as an AI processor, which is used for model training; the chip can also be implemented as a GPU (Graphics Processing Unit), which is used for image processing; the chip can also be implemented as an FPGA (Field-Programmable Gate Array), which is a programmable logic circuit that can be configured to implement different computing functions as needed. This embodiment of the present application is not limited to this.

[0057] First, each execution unit in the chip is introduced.

[0058] Memory unit 210

[0059] Illustratively, the memory unit is used to transmit and store data, which includes instruction-related information, operation results, etc.

[0060] In some embodiments, the memory unit can be implemented as a register, which can provide high-speed data storage and access so that the chip can quickly perform various computing tasks. It should be noted that in addition to registers, the memory unit can also be implemented as a cache, random access memory, etc., which is not limited in the embodiments of the present application.

[0061] Optionally, the number of memory units in the chip can be one or more. When multiple memory units are implemented, different memory units are used to transmit and store different types of data. For example, memory unit 1 and memory unit 2 are provided in the chip, with memory unit 1 being used to transmit and store instruction-related information, and memory unit 2 being used to transmit and store operation results.

[0062] Decoding unit 220

[0063] Illustratively, the decoding unit is used to decode instruction-related information and convert it into control signals that the hardware can understand and execute. For example, the decoding unit can determine the specific operation type of the instruction based on information such as the instruction's opcode (e.g., binary digits 001) and generate corresponding control signals for subsequent execution. Optionally, the number of decoding units in the chip can be one or more.

[0064] Loading unit 230

[0065] Schematically, the loading unit is mainly used for data transmission between the chip and other units, for example, responsible for loading required data from the memory into the chip. Optionally, the number of loading units in the chip can be one or more.

[0066] In some embodiments, the loading unit is also used to store data. For example, the loading unit loads required data from the memory and temporarily stores the data.

[0067] Arithmetic unit 240

[0068] Illustratively, the arithmetic unit is the core component of a chip that performs operations. Upon receiving data, the arithmetic unit can perform operations such as addition, subtraction, multiplication, division, and, or negation. Optionally, the number of arithmetic units in a chip can be one or more.

[0069] Secondly, the instruction execution process handled by each execution unit in the chip is introduced.

[0070] The memory unit 210 is configured to obtain instruction configuration information of the first instruction and send the instruction configuration information to the decoding unit.

[0071] Optionally, the first instruction is used to implement an operation task on an operand.

[0072] The operand is used to indicate the data involved in the operation indicated by the first instruction. For example, in an addition operation, data 1 and data 2 are added, and data 1 and data 2 are two operands.

[0073] Optionally, the operands may be in the form of, but not limited to, vectors, scalars (eg, integers, floating-point numbers, Boolean values, etc.), matrices, strings, graphs, arrays, etc.

[0074] For vector operands, the instructions typically perform the same operation on each element in the vector simultaneously. For example, for an addition operation on two vectors A = [1, 2, 3] and B = [4, 5, 6], the execution unit can perform the addition operation on the corresponding elements in A and B simultaneously, resulting in a result vector C = [5, 7, 9].

[0075] Illustratively, the first instruction includes at least one of the following instructions:

[0076] 1. Arithmetic operation instructions, such as addition instructions, subtraction instructions, multiplication instructions, division instructions, etc.;

[0077] 2. Logical operation instructions, such as AND instruction, OR instruction, NOT instruction, XOR instruction, etc.;

[0078] 3. Conversion operation instructions, such as fixed-point to floating-point conversion operation instructions, integer to floating-point conversion operation instructions, unit conversion, etc.;

[0079] 4. Shift operation instructions: Shift operation instructions are used to shift data left or right by a specified number of bits.

[0080] It should be noted that the above example of the first instruction is only a schematic illustration. The embodiment of the present application does not limit the instruction type of the first instruction. For example, the first instruction can also be implemented as a compound arithmetic-logical operation instruction. The compound arithmetic-logical operation instruction corresponds to a compound arithmetic-logical operation task, such as performing a negation operation on operands a and b respectively and then adding them together.

[0081] The instruction configuration information is used to indicate execution information for performing an operation on an operand based on the first instruction.

[0082] Optionally, the operand indicates data involved in the first instruction, and the number of operands may be one or more. For example, when the first instruction is an addition instruction, the operands involved in the addition operation are operand a and operand b; when the first instruction is a negation instruction, the operand involved in the logical negation operation may be only operand c.

[0083] Optionally, the instruction configuration information includes operand address and instruction type.

[0084] Illustratively, the operand address refers to the address where the operand is stored, that is, the storage location of the operand is specified in the instruction configuration information. The operand address can be implemented as a memory address, a memory address, etc., wherein the memory address can be used to indicate the above-mentioned memory unit, or to indicate other memories. The embodiments of the present application do not limit this.

[0085] Illustratively, the instruction type is used to determine the calculation task that the first instruction instructs to execute. For example, the instruction type can be implemented in the form of "001", indicating that the calculation task that the current first instruction instructs to execute is an addition operation.

[0086] After acquiring the instruction configuration information, the memory unit sends the instruction configuration information to the memory unit.

[0087] The decoding unit 220 is used to decode the instruction configuration information to obtain the load instruction and the operation instruction.

[0088] The load instruction and the operation instruction are used to implement the operation task of the operand indicated by the first instruction.

[0089] Illustratively, for the first instruction, the decoding unit decodes two basic operations: a load instruction and an operation instruction, wherein the load instruction and the operation instruction are control signals that can be recognized and executed by hardware (such as the load unit and the operation unit).

[0090] The load instruction is used to obtain an operand based on the operand address. Schematically, the control signal indicated by the load instruction controls the load unit to load the operand involved in the operation from the memory or other storage location (such as a register).

[0091] Optionally, the decoding unit is used to decode the operand address in the instruction configuration information to obtain a load instruction, where the load instruction includes a first address code representing the operand address.

[0092] The operation instruction is used to obtain the operation result of the operand based on the operation task indicated by the instruction type. Schematically, the control signal indicated by the operation instruction controls the operation unit to execute the operation task indicated by the instruction type.

[0093] Optionally, the decoding unit is used to decode the instruction type in the instruction configuration information to obtain an operation instruction, which includes an operation code. The operation code is used to represent the operation task indicated by the instruction type, such as addition operation, subtraction operation, etc.

[0094] Optionally, the decoding unit is used to decode the instruction configuration information and output the load instruction and the operation instruction at the same time; or, the decoding unit is used to decode the instruction configuration information and output the load instruction and the operation instruction according to the decoding speed.

[0095] Illustratively, after the decoding unit finishes decoding the load instruction and the operation instruction, it outputs the load instruction and the operation instruction simultaneously, that is, the load instruction is sent to the load unit and the storage instruction is sent to the storage unit in parallel.

[0096] Please refer to Figure 3 , which shows a schematic diagram of an instruction execution process, such as Figure 3 As shown in schematic diagram 300, assuming that the decoding unit requires one clock cycle to decode the instruction configuration information, the decoding unit decodes and obtains the load instruction, the operation instruction and the storage instruction in clock cycle T0; assuming that the decoding unit requires one clock cycle to send the load instruction, the operation instruction and the storage instruction, the decoding unit sends the load instruction to the loading unit, the operation instruction to the operation unit, and the storage instruction to the storage unit in clock cycle T1; the loading unit receives the load instruction at the start of clock cycle T2, the operation unit receives the operation instruction at the start of clock cycle T2, and the storage unit receives the storage instruction at the start of clock cycle T2.

[0097] Alternatively, the decoding unit decodes the execution configuration information. If a load instruction is decoded first, the load instruction is sent to the loading unit. If an operation instruction is decoded later, the operation instruction is sent to the operation unit. If an operation instruction is decoded first, the operation instruction is sent to the operation unit. If a load instruction is decoded later, the load instruction is sent to the loading unit.

[0098] The loading unit 230 is configured to, in response to receiving a load instruction, execute the load instruction, obtain an operand, and send the operand to the operation unit.

[0099] Optionally, after receiving the load instruction, the load unit immediately executes the load instruction and obtains the operand according to the storage location indicated by the first address code in the load instruction. Schematically, the load unit identifies the first address code in the load instruction to determine the storage location of the operand; after determining the storage location, the load unit performs a validity check on the storage location (for example, checking whether it has access rights to the storage location). If valid, the load unit reads the operand from the storage location, and the storage location feeds back the operand to the load unit. If invalid, the load instruction triggers an exception notification or interrupt.

[0100] Optionally, if the operand address is a memory address, the storage location indicated by the first address code in the load instruction is the memory, and the loading unit obtains the operand from the specified memory location after executing the load instruction; if the operand address is a memory address, the storage location indicated by the first address code in the load instruction is the memory, and the loading unit obtains the operand from the target memory after executing the load instruction, where the target memory can be the memory unit as described above, or other memory, and the embodiments of the present application are not limited to this.

[0101] After the load unit obtains the operand, the load unit sends the operand to the operation unit, and the operation unit performs the operation of the operand.

[0102] The operation unit 240 is configured to, upon receiving an operation instruction, execute the operation instruction starting from the first moment in response to receiving an operand at a first moment, and obtain an operation result of the operand.

[0103] Schematically, an operation instruction is an instruction that has been decoded and sent to the operation unit. When the operation unit has not received an operand, the operation instruction is in a waiting state; when the load instruction completes data loading and generates an operand, if the operation unit receives the operand, the operation instruction is executed immediately to generate the operation result of the operand.

[0104] In some embodiments, the basic time unit of the chip is a time cycle, and the first moment is the start moment of the clock cycle when the operation unit receives the operand.

[0105] Please refer to Figure 3 In schematic diagram 300, the load unit starts executing the load instruction at the moment it receives the load instruction (i.e., the start time of clock cycle T2). Assuming that the load unit needs one clock cycle to execute the load instruction, the load unit executes the load instruction in clock cycle T2; assuming that it takes one clock cycle to obtain the operand after executing the load instruction, the load unit obtains the operand in clock cycle T3; assuming that the load unit needs one clock cycle to send the operand to the operation unit, the load unit sends the operand to the operation unit in clock cycle T4.

[0106] The operation unit starts executing the operation instruction at the moment it receives the operand (that is, the start time of clock cycle T5). Assuming that the operation unit needs one clock cycle to complete the operation instruction, the operation unit executes the operation instruction in clock cycle T5 to obtain the operation result.

[0107] Optionally, the operation unit is further configured to send the operation result to a designated location. Optionally, the designated location includes at least one of the following locations:

[0108] 1. Register. Schematically, the arithmetic unit outputs the operation result directly to a register, for example, a register used to store intermediate operation results.

[0109] 2. Memory. Schematically, the arithmetic unit is not directly connected to the memory, and the calculation result can be written from the arithmetic unit to the memory through a storage unit.

[0110] 3. Cache. Schematically, a chip includes a cache, which is used to store recently used or upcoming data. The arithmetic unit can write calculation results directly into the cache.

[0111] 4. Other chips: Illustratively, the calculation results obtained by the calculation unit may need to be sent to other chips for further processing.

[0112] The above examples of designated locations are merely illustrative and are not limited to these in the embodiments of the present application.

[0113] In summary, the chip provided by the embodiment of the present application decodes the instruction configuration information obtained by the memory unit through the decoding unit, and automatically splits the first instruction into a decoded load instruction and an operation instruction; when the load unit receives the load instruction, it executes the load instruction to obtain the operand and sends the operand to the operation unit; when the operation unit receives the operand, it executes the operation instruction to obtain the operation result. On the one hand, while decoding the first instruction, the splitting task of the first instruction is completed, thereby improving the execution efficiency of the first instruction; on the other hand, the load instruction and the operation instruction are decoded in parallel. After the decoding is completed, the chip can schedule and execute the load instruction and the operation instruction at any time. When the load instruction is executed to obtain the operand, the operation instruction can be executed seamlessly, avoiding the idle clock cycle caused by waiting for the reception of the operation instruction after obtaining the operand, thereby reducing the waste of execution resources and improving chip performance.

[0114] In some embodiments, the chip provided by the present application further includes a storage unit, please refer to Figure 4 The chip 200 further includes a storage unit 250 . The storage unit 250 is connected to the decoding unit 220 , and the operation unit 240 is connected to the storage unit 250 .

[0115] Storage unit 250

[0116] Optionally, the storage unit is used to store data (e.g., calculation results, intermediate calculation results, etc.), or the storage unit is used to send data to a designated location for storage. For instructions on the designated location, please refer to the above description of "Sending the calculation result to the designated location", which will not be repeated here.

[0117] Optionally, the number of storage units in the chip may be one or more.

[0118] The following describes the instruction execution process of a chip including a storage unit.

[0119] The memory unit 210 is configured to obtain instruction configuration information of the first instruction and send the instruction configuration information to the decoding unit.

[0120] The instruction configuration information is used to indicate execution information for performing an operation on an operand based on the first instruction.

[0121] Optionally, the instruction configuration information includes operands or operand addresses, instruction types, and target addresses.

[0122] Illustratively, the operand address indicates the storage location of the operand; the instruction type refers to the type of the first instruction; and the target address indicates the storage address of the execution result of the first instruction. That is, the storage location of the operand operation result. The target address can be implemented as a memory address (such as a register address), a memory address, etc.

[0123] Optionally, the instruction configuration information further includes at least one of the following information: data length, instruction mode.

[0124] The data length is used to indicate the amount of data to be processed by the first instruction, that is, the total amount of data that needs to be processed by the current first instruction.

[0125] The instruction mode refers to the encoding length of the instruction, usually 32 bits or 16 bits. The instruction mode indicates the chip's data processing capabilities and accuracy. For example, a 32-bit addition instruction indicates that the chip can perform an addition operation on two 32-bit data.

[0126] In some embodiments, the chip further includes a start register.

[0127] Optionally, the start register is used to update the state identifier of the start register to the first state identifier when the instruction configuration information is stored in the memory unit; the memory unit is also used to send the instruction configuration information to the decoding unit when the state identifier of the start register is the first state identifier.

[0128] Schematically, the status identifier of the start register is used to indicate whether the chip is currently in the instruction execution stage. For example, if the status identifier is 1 (i.e., the first status identifier), it indicates that the chip is currently in the instruction execution stage; if the status identifier is 0 (the second status identifier), it indicates that the chip is not currently in the instruction execution stage.

[0129] When the instruction configuration information is successfully stored in the memory unit, the state flag of the start register can be updated to 1, thereby triggering the decoding of the instruction configuration information. In the embodiment of the present application, the execution process of the instruction is triggered by the state of the start register. Once the state of the start register changes, the instruction can be executed immediately. The control logic inside the chip is simplified, making the hardware design The design is simpler. In addition, relevant personnel can directly obtain the current chip execution status by checking the status flag of the start register. Improved work efficiency.

[0130] In some embodiments, the memory unit is further configured to obtain instruction configuration information of a second instruction within an execution time period corresponding to the first instruction, where the second instruction is the next instruction to be executed after the first instruction.

[0131] Schematically, the configuration of the memory unit (i.e., the memory unit obtains and stores the configuration information) and the instruction can be processed in parallel, that is, the configuration of the next instruction is completed within the current instruction execution time period, and then after the current instruction is executed (for example: after executing the first instruction to obtain the calculation result and storing it in the specified location), the instruction configuration information of the next instruction can be decoded immediately.

[0132] For schematic illustration, please refer to the figure, as shown in Figure 5 As shown, during the execution process 501 of instruction 1, the configuration operation of the next instruction 2 can be performed synchronously. When the execution process 501 of instruction 1 is completed, the configuration of instruction 2 is also completed, and the execution process 502 of instruction 2 can be directly performed. When the execution process 502 of instruction 2 is completed, the configuration of instruction 3 is also completed, and the execution process 503 of instruction 3 can be directly performed. This enables seamless execution of multiple instruction execution processes, avoids idle time periods, and improves chip performance. performance.

[0133] Optionally, the start register is used to update the status identifier of the start register to the first status identifier when the instruction configuration information corresponding to the second instruction is stored in the memory unit; the memory unit is also used to send the instruction configuration information corresponding to the second instruction to the decoding unit when the status identifier of the start register is the first status identifier and the execution of the first instruction is completed.

[0134] Illustratively, in the chip, the value of the start register is checked when the first instruction is completed. If the value of the start register is still 1, the chip can check whether there is another instruction to be executed (i.e., the second instruction). If the second instruction is detected, the chip starts executing the second instruction.

[0135] In some embodiments, the method for the memory unit to obtain instruction configuration information includes at least one of the following methods:

[0136] Method 1: Write the command configuration information into the memory unit through the programmer.

[0137] Illustratively, a compiler is a software program. Compiler software is installed in a computer device, and the computer device includes the above-mentioned chip. The compiler software compiles the code written by the programmer using a high-level language (such as C, C++, Python, etc.) to obtain an executable file (including the above-mentioned instruction configuration information). The executable file is stored in the memory of the computer device, and the memory unit in the chip can obtain the instruction configuration information in the executable file from the memory.

[0138] Method 2: Write the instruction configuration information into the memory unit through the target processor.

[0139] Wherein, the target processor is connected to the memory unit.

[0140] Illustratively, the target processor executes a configuration instruction, which includes instruction configuration information and an address of a memory unit. The target processor executes the configuration instruction and sends the instruction configuration information to the memory unit based on the address of the memory unit.

[0141] The decoding unit 220 is used to decode the instruction configuration information to obtain load instructions, operation instructions and storage instructions.

[0142] The load instruction, the operation instruction and the storage instruction are used to implement the operation task of the operand indicated by the first instruction.

[0143] Load instructions are used to fetch operands based on the operand address.

[0144] The operation instruction is used to obtain the operation result of the operand based on the operation indicated by the instruction type.

[0145] The store instruction is used to store the result of an operation to a target address. Schematically, the store instruction is responsible for storing the result of the operation of the operand to the storage location indicated by the target address.

[0146] Optionally, the target address in the decoding instruction configuration information is obtained to obtain a storage instruction, and the storage instruction includes a second address code representing the target address.

[0147] Optionally, the decoding unit is used to decode the instruction configuration information and output the load instruction, the operation instruction and the store instruction simultaneously. Alternatively, the decoding unit is used to decode the instruction configuration information and output the load instruction, the operation instruction and the store instruction according to the decoding speed.

[0148] The loading unit 230 is configured to, in response to receiving a load instruction, execute the load instruction, obtain an operand, and send the operand to the operation unit.

[0149] The operation unit 240 is used to, in response to receiving an operand at a first moment, execute the operation instruction from the first moment, obtain the operation result of the operand, and send the operation result to the storage unit.

[0150] The storage unit 250 is configured to, upon receiving a storage instruction, execute the storage instruction starting from the second moment in response to receiving a calculation result at the second moment.

[0151] Schematically, a storage instruction is an instruction that has been decoded and sent to a storage unit. When the storage unit does not receive an operand, the storage instruction is in a waiting state. When the operation instruction completes the operation and obtains the operation result, if the storage unit receives the operation result, the storage instruction is executed immediately.

[0152] In some embodiments, the basic time unit of the chip is a time cycle, and the second moment is the start moment of the clock cycle when the storage unit receives the storage result.

[0153] Please refer to Figure 3 In the schematic diagram 300, assuming that the operation unit needs one clock cycle to send the operation result, the operation unit sends the operation result to the storage unit in the clock cycle T6, and the storage unit starts to execute the storage instruction at the moment of receiving the operation result (that is, the start time of the clock cycle T7). Assuming that the storage unit needs one clock cycle to execute the storage instruction, the storage unit executes the storage instruction in the clock cycle T7.

[0154] Among them, the storage instruction is used to store the operation result.

[0155] Optionally, the store instruction is used to store the result of the operation of the operand according to the target address indicated in the store instruction. Illustratively, when the target address is the address of the aforementioned memory unit, after the storage unit executes the store instruction, the operation result is sent to and stored in the memory unit. When the target address is another memory address, after the storage unit executes the store instruction, the operation result is sent to and stored in the other memory. When the target address is a memory address, after the storage unit executes the store instruction, the operation result is sent to and stored in the memory.

[0156] In other embodiments, the decoding unit is used to decode instruction configuration information and output load instructions, operation instructions and storage instructions according to the decoding speed. The storage unit is also used to, in response to receiving a storage instruction at a fifth moment, execute the storage instruction starting from the fifth moment when a calculation result is received but no storage instruction is received.

[0157] Illustratively, if the decoding unit outputs instructions based on the decoding speed, and the decoding of the storage instruction is delayed (e.g., due to aging of the hardware that decodes the storage instruction), the decoding process of the storage instruction may be longer, meaning that the storage unit may receive the storage instruction later. Consequently, the storage unit may have already obtained the operation result but not yet obtained the storage instruction. In this case, when the storage unit obtains the storage instruction, it will execute the storage instruction from the time it obtained the storage instruction.

[0158] In summary, the chip decodes load instructions, operation instructions, and storage instructions in parallel. After decoding is completed, the chip can schedule and execute instructions at any time. That is to say, when the load instruction is executed to obtain the operand, the operation instruction can be executed seamlessly. When the operation instruction is executed to obtain the operation result, the storage instruction can be executed seamlessly, avoiding the idle clock cycles caused by waiting for the reception of operation instructions and storage instructions. This reduces the waste of execution resources and improves chip performance.

[0159] In some embodiments, the chip has multiple decoding units, and different instructions are decoded by different decoding units. The example of decoding instruction configuration information to obtain a load instruction, a calculation instruction, and a store instruction is used for illustration.

[0160] Optionally, the chip further includes: a first decoding unit and a second decoding unit.

[0161] Optionally, the memory unit is used to send instruction configuration information to the first decoding unit and the second decoding unit in parallel; the first decoding unit is used to decode the instruction configuration information to obtain a load instruction; and the second decoding unit is used to decode the instruction configuration information to obtain an operation instruction.

[0162] Illustratively, the instruction configuration information is sent to the first decoding unit and the second decoding unit in parallel for decoding. The first decoding unit and the second decoding unit can perform decoding operations simultaneously, thereby reducing the total time required to decode the first instruction and improving the execution efficiency of the first instruction.

[0163] Optionally, the case where the instruction configuration information is decoded by the first decoding unit and the second decoding unit includes at least one of the following cases:

[0164] Case 1: Parallel decoding and simultaneous output of load instructions and operation instructions.

[0165] The first decoding unit is used to send a load instruction to the loading unit at a third moment; the second decoding unit is used to send an operation instruction to the operation unit at the third moment.

[0166] Illustratively, after both the first decoding unit and the second decoding unit complete the instruction decoding operation, at the same time, the first decoding unit sends the decoded load instruction to the load unit, and the second decoding unit sends the decoded operation instruction to the operation unit.

[0167] When the load unit receives the load instruction, the operation unit also receives the operation instruction, so Make sure When the operation instruction receives the operand, the operation instruction can be executed immediately to obtain the operation result, avoiding idle time. clock cycle to improve chip performance.

[0168] Case 2: Parallel decoding and output of load instructions and operation instructions according to the decoding speed.

[0169] The first decoding unit is used to send the load instruction to the load unit in response to completion of decoding the load instruction; the second decoding unit is used to send the operation instruction to the operation unit in response to completion of decoding the operation instruction.

[0170] Schematically, the first decoding unit and the second decoding unit decode instruction configuration information simultaneously, wherein the time required for the first decoding unit to decode the load instruction and the time required for the second decoding unit to decode the operation instruction are different. Therefore, after the first decoding unit decodes the load instruction, the load instruction is immediately sent to the load unit for execution, and after the second decoding unit decodes the operation instruction, the operation instruction is immediately sent to the operation unit.

[0171] Optionally, the operation unit is further configured to, in response to receiving an operation instruction at a fourth moment, execute the operation instruction starting from the fourth moment to obtain an operation result of the operand when an operand is received but no operation instruction is received.

[0172] Illustratively, if the decoding unit outputs instructions based on the decoding speed, and the arithmetic task indicated by the first instruction in the instruction configuration information is complex or the decoding of the arithmetic instruction is slow (e.g., due to aging of some hardware that decodes the arithmetic instruction), the decoding process of the arithmetic instruction may be longer, that is, the arithmetic unit may receive the arithmetic instruction later. In this case, the arithmetic unit may have already obtained the operand but has not yet obtained the arithmetic instruction. In this case, when the arithmetic unit obtains the arithmetic instruction, it will start executing the arithmetic instruction from the time it obtained the arithmetic instruction.

[0173] That is to say, if the operation instruction is not decoded, the load instruction can be directly sent to the load unit for execution after being decoded first. There is no need to wait for the operation instruction to be decoded. The load unit can load the instruction while the operation instruction is being decoded. Loading instructions improves the instruction execution efficiency in the chip.

[0174] In some embodiments, the above chip further includes: a third decoding unit.

[0175] Please refer to Figure 6, which shows a schematic diagram of a chip provided by an exemplary embodiment. The chip 200 includes: a first decoding unit 221, a second decoding unit 222, and a third decoding unit 223. The memory unit 210 is connected to the first decoding unit 221, the second decoding unit 222, and the third decoding unit 223, respectively. The first decoding unit 221 is connected to the loading unit 230, the second decoding unit 222 is connected to the operation unit 240, and the third decoding unit 223 is connected to the storage unit 250.

[0176] Optionally, the case where the instruction configuration information is decoded by the first decoding unit, the second decoding unit, and the third decoding unit includes at least one of the following cases:

[0177] Case 1: Parallel decoding and simultaneous output of load instructions, operation instructions, and storage instructions.

[0178] The instruction execution process of the chip corresponding to situation 1 is introduced below.

[0179] The memory unit 210 is configured to obtain instruction configuration information of the first instruction; and send the instruction configuration information to the first decoding unit, the second decoding unit, and the third decoding unit in parallel.

[0180] Illustratively, after the memory unit obtains the instruction configuration information, it sends the instruction configuration information to the first decoding unit, the second decoding unit, and the third decoding unit simultaneously.

[0181] Optionally, the instruction configuration information sent to the first decoding unit, the second decoding unit, and the third decoding unit is the same. Schematically, after obtaining the instruction configuration information, three identical instruction configuration information are sent to the first decoding unit, the second decoding unit, and the third decoding unit respectively. Sending multiple identical instruction configuration information to different decoding units, the decoding logic of the first instruction is relatively simple, and no additional signal processing is required. Information distribution and processing operations.

[0182] Alternatively, the instruction configuration information sent to the first decoding unit, the second decoding unit, and the third decoding unit is different. Schematically, the instruction configuration information sent to the first decoding unit is the information required for decoding to obtain the load instruction, such as: operand address, instruction mode, data length, etc. The instruction configuration information sent to the second decoding unit is the information required for decoding to obtain the operation instruction, such as: instruction type, instruction mode, data length, etc. The instruction configuration information sent to the third decoding unit is the information required for decoding to obtain the storage instruction, such as: target address, instruction mode, data length, etc. Each decoding unit only receives and processes the instruction information it needs, It can make more efficient use of hardware resources and avoid the processing of unnecessary information. Management and waste.

[0183] The first decoding unit 221 is configured to decode the instruction configuration information to obtain a load instruction; the second decoding unit 222 is configured to decode the instruction configuration information to obtain a calculation instruction; and the third decoding unit 223 is configured to decode the instruction configuration information to obtain a store instruction. The first decoding unit 221 is configured to send the load instruction to the load unit at a third time; the second decoding unit 222 is configured to send the calculation instruction to the calculation unit at a third time; and the third decoding unit 223 is configured to send the store instruction to the store unit at a third time.

[0184] The third moment refers to the moment when the load instruction, the operation instruction, and the storage instruction are all decoded.

[0185] Illustratively, after each decoding unit completes the instruction decoding operation, each decoding unit simultaneously sends the decoded instruction to the corresponding execution unit.

[0186] The loading unit 230 is configured to, in response to receiving a load instruction, execute the load instruction, obtain an operand, and send the operand to the operation unit.

[0187] The operation unit 240 is used to, in response to receiving an operand at a first moment, execute the operation instruction from the first moment, obtain the operation result of the operand, and send the operation result to the storage unit.

[0188] The storage unit 250 is configured to, upon receiving a storage instruction, execute the storage instruction starting from the second moment in response to receiving the operation result at the second moment, where the storage instruction is used to store the operation result.

[0189] Case 2: Parallel decoding and output of load instructions, operation instructions and storage instructions according to the decoding speed.

[0190] The instruction execution process of the chip corresponding to Case 2 is introduced below.

[0191] The memory unit 210 is configured to obtain instruction configuration information of the first instruction; and send the instruction configuration information to the first decoding unit, the second decoding unit, and the third decoding unit in parallel.

[0192] The first decoding unit 221 is configured to decode the instruction configuration information to obtain a load instruction; upon completion of decoding the load instruction, the load instruction is sent to the load unit. The second decoding unit 222 is configured to decode the instruction configuration information to obtain a calculation instruction; upon completion of decoding the calculation instruction, the calculation instruction is sent to the calculation unit. The third decoding unit 223 is configured to decode the instruction configuration information to obtain a store instruction; upon completion of decoding the store instruction, the store instruction is sent to the store unit.

[0193] The loading unit 230 is configured to, in response to receiving a load instruction, execute the load instruction, obtain an operand, and send the operand to the operation unit.

[0194] Optionally, the arithmetic unit is further configured to, in response to receiving the arithmetic instruction at a fourth moment, execute the arithmetic instruction starting at the fourth moment and obtain the arithmetic result of the operand when the operand is received but the arithmetic instruction is not received. Illustratively, the decoding process of the arithmetic instruction may be long, that is, the arithmetic unit may receive the arithmetic instruction later. In this case, the arithmetic unit may have obtained the operand but has not yet obtained the arithmetic instruction. In this case, after the arithmetic unit obtains the arithmetic instruction, it will execute the arithmetic instruction starting at the moment the arithmetic instruction was obtained.

[0195] The operation unit 240 is used to, in response to receiving an operand at a first moment, execute the operation instruction from the first moment, obtain the operation result of the operand, and send the operation result to the storage unit.

[0196] The storage unit 250 is configured to, upon receiving a storage instruction, execute the storage instruction starting from the second moment in response to receiving the operation result at the second moment, where the storage instruction is used to store the operation result.

[0197] Optionally, the storage unit is further configured to, in response to receiving the store instruction at a fifth moment, execute the store instruction starting at the fifth moment, if the operation result is received but the store instruction is not received. Illustratively, the decoding process of the store instruction may be lengthy, i.e., the storage unit may receive the store instruction later. In this case, the storage unit may have received the operation result but not yet received the store instruction. In this case, after the storage unit receives the store instruction, it will execute the store instruction starting at the moment the store instruction was received.

[0198] Schematically, clock cycles 1-7 are consecutive clock cycles. Assume that in clock cycle 1, the memory unit sends the instruction configuration information to the decoding unit. The following example shows the number of clock cycles required for the chip to execute the first instruction based on different decoding output conditions:

[0199] Example 1: It takes 1 clock cycle for the first decoding unit to decode the instruction configuration information to obtain the load instruction, 4 clock cycles for the second decoding unit to decode the instruction configuration information to obtain the operation instruction, and 1 clock cycle for the third decoding unit to decode the instruction configuration information to obtain the store instruction.

[0200] If load instructions, operation instructions and storage instructions are output at the same time:

[0201] In clock cycles 2-5, the instruction configuration information is decoded to obtain the load instruction, the operation instruction, and the store instruction; assuming that in clock cycle 6, the next clock cycle after clock cycle 5, the first decoding unit sends the load instruction to the load unit, the second decoding unit sends the operation instruction to the operation unit, and the third decoding unit sends the store instruction to the store unit, then clock cycle 6 is Figure 3In the previous clock cycle of the clock cycle T2 shown, at the start time of the clock cycle T2, the load unit receives a load instruction, the operation unit receives an operation instruction, and the storage unit receives a storage instruction.

[0202] The arithmetic unit has received the arithmetic instruction before receiving the operand. The arithmetic unit can execute the arithmetic instruction immediately after receiving the operand. Figure 3 , the operation instruction starts to be executed at the beginning of the clock cycle T5; the storage unit has received the storage instruction before receiving the operation result, and the storage unit can immediately execute the storage instruction when receiving the operation result, refer to Figure 3 , starts executing the store instruction at the beginning of clock cycle T7. That is, the chip needs 6 (clock cycles 1-6) + 6 ( Figure 3 T2-T7)=12 clock cycles.

[0203] If load instructions, operation instructions and storage instructions are output according to the decoding speed:

[0204] In the next clock cycle 2 of clock cycle 1, the first decoding unit decodes the instruction configuration information to obtain the load instruction, and the third decoding unit decodes the instruction configuration information to obtain the store instruction; assuming that in the next clock cycle 3 of clock cycle 2, the first decoding unit sends the load instruction to the load unit and the third decoding unit sends the store instruction to the store unit, then clock cycle 3 is Figure 3 In the previous clock cycle of the clock cycle T2 shown, at the start time of the clock cycle T2, the load unit receives a load instruction and the store unit receives a store instruction.

[0205] In clock cycles 2-5, the second decoding unit decodes the instruction configuration information to obtain the operation instruction; assuming that in clock cycle 6, the next clock cycle after clock cycle 5, the second decoding unit sends the operation instruction to the operation unit, then clock cycle 6 is Figure 3 In the clock cycle T4 shown, at the beginning of the clock cycle T5, the operation unit receives the operation instruction.

[0206] The arithmetic unit receives the arithmetic instruction at the same time as the operand, so the arithmetic unit can execute the arithmetic instruction immediately after receiving the operand. Figure 3 , the operation instruction starts to be executed at the beginning of the clock cycle T5; the storage unit has received the storage instruction before receiving the operation result, and the storage unit can immediately execute the storage instruction when receiving the operation result, refer to Figure 3 , starts executing the store instruction at the beginning of clock cycle T7. That is, the chip needs 3 (clock cycles 1-3) + 6 (referring to Figure 3 T2-T7)=9 clock cycles.

[0207] Example 2: It takes 1 clock cycle for the first decoding unit to decode the instruction configuration information to obtain the load instruction, 5 clock cycles for the second decoding unit to decode the instruction configuration information to obtain the operation instruction, and 1 clock cycle for the third decoding unit to decode the instruction configuration information to obtain the store instruction.

[0208] If load instructions, operation instructions and storage instructions are output at the same time:

[0209] In clock cycles 2-6, the instruction configuration information is decoded to obtain the load instruction, the operation instruction, and the store instruction; assuming that in the next clock cycle 7 after clock cycle 6, the first decoding unit sends the load instruction to the load unit, the second decoding unit sends the operation instruction to the operation unit, and the third decoding unit sends the store instruction to the store unit, then clock cycle 7 is Figure 3 In the previous clock cycle of the clock cycle T2 shown, at the start time of the clock cycle T2, the load unit receives a load instruction, the operation unit receives an operation instruction, and the storage unit receives a storage instruction.

[0210] The arithmetic unit has received the arithmetic instruction before receiving the operand. The arithmetic unit can execute the arithmetic instruction immediately after receiving the operand. Figure 3 , the operation instruction starts to be executed at the beginning of the clock cycle T5; the storage unit has received the storage instruction before receiving the operation result, and the storage unit can immediately execute the storage instruction when receiving the operation result, refer to Figure 3 , the storage instruction starts to be executed at the beginning of clock cycle T7. That is, the chip needs 7 (clock cycles 1-7) + 6 ( Figure 3 T2-T7)=13 clock cycles.

[0211] If load instructions, operation instructions and storage instructions are output according to the decoding speed:

[0212] In the next clock cycle 2 of clock cycle 1, the first decoding unit decodes the instruction configuration information to obtain the load instruction, and the third decoding unit decodes the instruction configuration information to obtain the store instruction; assuming that in the next clock cycle 3 of clock cycle 2, the first decoding unit sends the load instruction to the load unit and the third decoding unit sends the store instruction to the store unit, then clock cycle 3 is Figure 3 In the previous clock cycle of the clock cycle T2 shown, at the start time of the clock cycle T2, the load unit receives a load instruction and the store unit receives a store instruction.

[0213] In clock cycles 2-6, the second decoding unit decodes the instruction configuration information to obtain the operation instruction; assuming that in clock cycle 7, the next clock cycle after clock cycle 6, the second decoding unit sends the operation instruction to the operation unit, then clock cycle 7 is Figure 3 In the clock cycle T5 shown, at the beginning of the clock cycle T6, the operation unit receives the operation instruction.

[0214] The arithmetic unit does not receive the arithmetic instruction when it receives the operand. The arithmetic unit executes the arithmetic instruction immediately when it receives the arithmetic instruction. Figure 3 , at the beginning of clock cycle T6, the moment when the storage unit receives the operation result is the end of clock cycle T7; the storage unit has received the storage instruction before receiving the operation result, and the storage unit can execute the storage instruction immediately after receiving the operation result, refer to Figure 3 , starts executing the store instruction at the end of clock cycle T7. That is, the chip needs 3 (clock cycles 1-3) + 6 (referring to Figure 3 T2-T7)+1( Figure 3 The next clock cycle of the middle clock cycle T7) = 10 clock cycles.

[0215] To sum up, in the above chip, the first decoding unit, the second decoding unit and the third decoding unit perform decoding operations at the same time, and after waiting for the loading instruction, the operation instruction and the storage instruction to be decoded, the loading instruction, the operation instruction and the storage instruction are sent in parallel. When the loading unit receives the loading instruction, the operation unit also receives the operation instruction, and the storage unit also receives the storage instruction, thereby ensuring that when the operation instruction receives the operand, the operation instruction can be executed immediately to obtain the operation result, and when the storage instruction receives the operation result, the storage instruction can be executed immediately, thereby achieving seamless connection of instruction execution and improving chip performance.

[0216] In the above chip, the first decoding unit, the second decoding unit and the third decoding unit perform decoding operations at the same time. After decoding, each decoding unit sends the obtained instruction to the corresponding execution unit, avoiding the waste of clock cycles caused by waiting for other instructions to be decoded. For example: after the load instruction is decoded, it can be directly sent to the load unit for execution without waiting for other instructions to be decoded, thereby improving the instruction execution efficiency in the chip.

[0217] In some embodiments, the data length that can be processed by the execution unit in the chip (for example, the loading unit, the operation unit, and the storage unit, etc.) in a single clock cycle is a preset length. Therefore, when the data length in the current instruction configuration information is greater than the preset length, the data to be processed by the data length indication needs to be processed in batches.

[0218] Please refer to Figure 7 , which shows a schematic diagram of a chip provided by an exemplary embodiment, the chip 200 further includes: a splitting unit 260. The decoding unit 220 is connected to the splitting unit 260, and the splitting unit 260 is connected to the loading unit 230, the operation unit 240 and the storage unit 250 respectively.

[0219] The following describes the instruction execution process of a chip including a split unit.

[0220] The memory unit 210 is configured to obtain instruction configuration information of the first instruction and send the instruction configuration information to the decoding unit.

[0221] The decoding unit 220 is configured to decode the instruction configuration information to obtain a load instruction and an operation instruction; and send the load instruction and the operation instruction to the splitting unit.

[0222] In some embodiments, the decoding unit includes a first decoding unit and a second decoding unit; the splitting unit includes a first A first split unit and a second split unit.

[0223] Illustratively, at a first target time, the first decoding unit sends a load instruction to the first splitting unit, and the second decoding unit sends an operation instruction to the second splitting unit. The first target time refers to the time when both the load instruction and the operation instruction are decoded.

[0224] Alternatively, in response to completion of decoding the load instruction, the first decoding unit sends the load instruction to the first splitting unit; in response to completion of decoding the operation instruction, the second decoding unit sends the operation instruction to the second splitting unit.

[0225] In some embodiments, the decoding unit further includes a third decoding unit; and the splitting unit further includes a third splitting unit.

[0226] Among them, the first decoding unit is connected to the first splitting unit, and the first splitting unit is connected to the loading unit; the second decoding unit is connected to the second splitting unit, and the second splitting unit is connected to the operation unit; the third decoding unit is connected to the third splitting unit, and the third splitting unit is connected to the storage unit.

[0227] Illustratively, at the second target time, the first decoding unit sends a load instruction to the first splitting unit, the second decoding unit sends an arithmetic instruction to the second splitting unit, and the third decoding unit sends an arithmetic instruction to the second splitting unit. The second target time refers to the time when the load instruction, the arithmetic instruction, and the store instruction are all decoded.

[0228] Alternatively, in response to the completion of decoding the load instruction, the first decoding unit sends the load instruction to the first splitting unit; in response to the completion of decoding the operation instruction, the second decoding unit sends the operation instruction to the second splitting unit; in response to the completion of decoding the storage instruction, the third decoding unit sends the storage instruction to the second splitting unit.

[0229] The splitting unit 260 is configured to split a load instruction into n sub-load instructions and split an operation instruction into n sub-operation instructions based on the preset length when the data length is greater than the preset length.

[0230] Among them, the i-th sub-load instruction and the i-th sub-operation instruction indicate the same amount of sub-data to be processed, n>1 and n is an integer, i≤n and i is a positive integer; the preset data amount corresponding to the preset length refers to the amount of data processed by a single clock cycle of the chip, and the sub-data amount is less than or equal to the preset data amount.

[0231] Schematically, the amount of data processed in a single clock cycle of the chip can be understood as the maximum amount of data that the loading unit can load at a single time, the maximum amount of data that the computing unit can compute at a single time, and the maximum amount of data that the storage unit can store at a single time. Normally, the maximum amount of data that these three execution units can process at a single time is the same.

[0232] In the embodiment of the present application, the splitting rules of the load instruction and the operation instruction (and the storage instruction) are the same. The splitting of the load instruction is taken as an example for explanation. The case of splitting the load instruction includes at least one of the following cases:

[0233] Case 1: Split the load instruction into units of a preset length.

[0234] Assuming that the data length is 16 and the preset length is 4, the load instruction is split into 4 sub-load instructions, and the length of the data processed by each sub-load instruction is 4.

[0235] Please refer to Figure 8 , which shows a schematic diagram of the splitting of a load instruction, such as Figure 8 As shown, the length of the vector that the load instruction 810 needs to process is 16. If the length of the vector that can be processed by the execution unit in a single clock cycle in the chip is 4, the load instruction can be split into microinstructions 811, microinstructions 812, microinstructions 813 and microinstructions 814, and the length of the vector processed by each microinstruction is 4.

[0236] Assuming that the data length is 15 and the preset length is 4, the load instruction is split into 4 sub-load instructions. The length of the data processed by the first 3 sub-load instructions is 4, and the length of the data processed by the last sub-load instruction is 3.

[0237] Case 2: If the load instruction cannot be evenly split using the preset length as the splitting unit, and the load instruction can be evenly split, the load instruction is evenly split using the target length as the splitting unit.

[0238] The target length is the maximum split unit that is smaller than the preset length.

[0239] Assuming that the data length is 15 and the preset length is 4, the load instruction can be split into 3 sub-load instructions according to the split unit of 3, and the length of the data processed by each sub-load instruction is 3.

[0240] Optionally, the splitting unit is also used to split the load instruction into n sub-load instructions, split the operation instruction into n sub-operation instructions, and split the storage instruction into n sub-storage instructions based on the preset length when the data length is greater than the preset length.

[0241] Among them, the i-th sub-load instruction, the i-th sub-operation instruction and the i-th sub-storage instruction indicate the same amount of sub-data to be processed, n>1 and n is an integer, i≤n and i is a positive integer; the preset data amount corresponding to the preset length refers to the amount of data processed by a single clock cycle of the chip, and the sub-data amount is less than or equal to the preset data amount.

[0242] In some embodiments, after the split unit obtains n sub-load instructions and n sub-operation instructions, it sends n sub-load instructions to the load unit and n sub-operation instructions to the operation unit at the same time.

[0243] In the case where the split unit includes a first split unit and a second split unit:

[0244] At a third target time, the first splitting unit sends n sub-load instructions to the load unit, and the second splitting unit sends n sub-operation instructions to the operation unit. The third target time is the time when the n sub-load instructions and the n sub-operation instructions are all split.

[0245] In the case where the split unit also includes a third split unit:

[0246] At a fourth target time, the first splitting unit sends n sub-load instructions to the load unit, the second splitting unit sends n sub-operation instructions to the operation unit, and the third splitting unit sends n sub-store instructions to the store unit. The fourth target time is the time when the n sub-load instructions, n sub-operation instructions, and n sub-store instructions are all split.

[0247] In some other embodiments, the splitting unit, in response to receiving a load instruction, splits the load instruction into n sub-load instructions, and sends the n sub-load instructions to the load unit. The splitting unit, in response to receiving an operation instruction, splits the operation instruction into n sub-operation instructions, and sends the n sub-operation instructions to the operation unit.

[0248] In the case where the split unit includes a first split unit and a second split unit:

[0249] The first splitting unit is configured to, in response to receiving a load instruction, split the load instruction into n sub-load instructions and send the n sub-load instructions to the load unit. The second splitting unit is configured to, in response to receiving an operation instruction, split the operation instruction into n sub-operation instructions and send the n sub-operation instructions to the operation unit.

[0250] Schematically, when the first decoding unit decodes and obtains a load instruction, the first decoding unit outputs and sends the load instruction to the first splitting unit for splitting, thereby obtaining n sub-load instructions. After the first splitting unit obtains the n sub-load instructions, the n sub-load instructions can be immediately sent to the load unit; when the second decoding unit decodes and obtains an operation instruction, the second decoding unit outputs and sends the operation instruction to the second splitting unit for splitting, thereby obtaining n sub-operation instructions. After the second splitting unit obtains the n sub-operation instructions, the n sub-operation instructions can be immediately sent to the operation unit.

[0251] In the case where the split unit also includes a third split unit:

[0252] The first splitting unit is configured to, in response to receiving a load instruction, split the load instruction into n sub-load instructions and send the n sub-load instructions to the load unit. The second splitting unit is configured to, in response to receiving an operation instruction, split the operation instruction into n sub-operation instructions and send the n sub-operation instructions to the operation unit. The third splitting unit is configured to, in response to receiving a store instruction, split the store instruction into n sub-store instructions.

[0253] Schematically, when the third decoding unit decodes and obtains a storage instruction, the third decoding unit outputs and sends the storage instruction to the third splitting unit for splitting, thereby obtaining n sub-storage instructions. After the third splitting unit obtains the n sub-storage instructions, it can immediately send the n sub-storage instructions to the storage unit.

[0254] Optionally, the above-mentioned loading unit includes a first instruction queue, the operation unit includes a second instruction queue, and the storage unit includes a third instruction queue, wherein the first instruction queue is used to store n sub-load instructions, the second instruction queue is used to store n sub-operation instructions, and the third instruction queue is used to store n sub-storage instructions.

[0255] Schematically, the above instruction queue can be implemented as a FIFO (First In First Out) queue. Taking the first instruction queue as an example, n sub-load instructions are stored in the first instruction queue in sequence, and the n sub-load instructions are processed in the order in which the instructions enter the queue.

[0256] In summary, a splitting unit is designed in the chip, which can split the instruction when the amount of data to be processed by the first instruction exceeds the maximum processing capacity of the chip in a single time cycle, thereby processing the data in batches to obtain the operation result corresponding to the first instruction. By splitting instructions to process large-scale data, the chip utilization and application scope are improved. When splitting, the splitting units may include multiple ones, so that different instructions are split in parallel by multiple splitting units. Improved instruction splitting efficiency.

[0257] In some embodiments, after the instructions are split, the split instructions are executed in sequence. The following is an example of splitting into n sub-load instructions, n sub-operation instructions, and n sub-storage instructions. Among them, the i-th sub-load instruction, the i-th sub-operation instruction, and the i-th sub-storage instruction are the i-th group of instructions, and n groups of instructions are executed in sequence.

[0258] The load unit is configured to, in response to receiving an i-th sub-load instruction, execute the i-th sub-load instruction to obtain an i-th operand; and send the i-th operand to the operation unit.

[0259] The operation unit is used to, in response to receiving the i-th sub-operation instruction and receiving the i-th operand at the first moment, execute the i-th sub-operation instruction from the first moment, obtain the i-th operation result of the i-th operand; and send the i-th operation result to the storage unit.

[0260] The storage unit is configured to, upon receiving the i-th sub-storage instruction, execute the i-th sub-storage instruction starting from the second moment in response to receiving the i-th operation result at the second moment.

[0261] Indicatively, after the execution of the i-th sub-storage instruction is completed and the i-th operation result is stored, it means that the execution of the i-th group of instructions is completed, and the i+1-th group of instructions can be executed at this time.

[0262] Among them, the execution details of the i-th sub-load instruction, i-th sub-operation instruction and i-th sub-store instruction in the i-th group of instructions can refer to the execution process of the above-mentioned load instruction, operation instruction and storage instruction, which will not be repeated here.

[0263] Optionally, the loading unit is further used to execute the i+1th sub-load instruction in response to receiving the completion of execution of the i-th sub-storage instruction. Schematically, the chip includes a program counter, which is used to save the address of the instruction currently being executed. When an instruction is executed, the program counter is automatically updated to the address of the next instruction. Assume that there is currently a first group of instructions: load instruction 1, operation instruction 1, storage instruction 1 and a second group of instructions: load instruction 2, operation instruction 2, storage instruction 2, and their addresses are 0, 1, 2, 3, 4, and 5 respectively. The current address saved in the program counter is 2, indicating that the instruction currently being executed is storage instruction 1. When the execution of storage instruction 1 is completed, the current address saved in the program counter is updated to 3, and the execution of load instruction 2 begins.

[0264] Optionally, executing n sub-load instructions, n sub-operation instructions, and n sub-store instructions may obtain n operation results, and these n operation results are the task results of the operation task indicated by the first instruction.

[0265] Next, the internal instruction execution processes of the loading unit 230 , the operation unit 240 , and the storage unit 250 are described respectively.

[0266] 1. Loading unit 230

[0267] In some embodiments, the load sheet further includes: a request transmission subunit.

[0268] Optionally, the request issuing subunit is configured to issue a load request based on an operand address in response to a load instruction, and use response data of the load request as an operand.

[0269] Schematically, taking the operand address indicating the specified memory location as an example, the request emission sub-unit sends a load request to the specified memory location (such as: the address code is 0) according to the operand address, reads data of the corresponding size from the specified memory location (such as: reads data with address code 0 to address code 3), and feeds the data back to the loading unit as response data. The response data is the operand.

[0270] In the above embodiment, a request issuing subunit is designed in the chip, and the request issuing subunit can directly respond to the load instruction and issue a load request, thereby quickly obtaining the required operands. This speeds up the execution of instructions.

[0271] In some embodiments, if the first instruction indicates a plurality of operands, the request issuing subunit is set according to the number of operands.

[0272] Optionally, description is given by taking an example where the operands include a first operand and a second operand.

[0273] For illustration, please refer to Figure 9 The loading unit 230 includes: a first request transmitting subunit 231 and a second request transmitting subunit 232.

[0274] Among them, the first request transmitting subunit is used to respond to the load instruction, transmit a first load request based on the operand address corresponding to the first operand, and use the first response data corresponding to the first load request as the first operand; the second request transmitting subunit is used to respond to the load instruction, transmit a second load request based on the operand address corresponding to the second operand, and use the second response data corresponding to the second load request as the second operand.

[0275] In the above embodiment, a corresponding number of request transmitting subunits is set according to the number of operands. Loading is implemented The parallel execution of instructions improves the chip's efficiency in loading and executing instructions.

[0276] In some embodiments, if the first instruction indicates multiple operands, the loading unit may obtain the multiple operands at different times.

[0277] like Figure 9 As shown, the time when the loading unit receives the first response data corresponding to the first load request and the second response data corresponding to the second load request may not be the same. In order to synchronously send multiple operands to the operation unit, an operand queue can be set in the loading unit, and the operands can be temporarily stored in the operand queue. After the loading unit obtains all the operands, these operands are read out synchronously.

[0278] The operand queue may be implemented as a FIFO (First In First Out) queue.

[0279] For illustration, please refer to Figure 9 The loading unit 230 also includes: a first operand queue, a second operand queue and a synchronization subunit 233.

[0280] Optionally, the first operand queue is used to store the first operand; the second operand queue is used to store the second operand; the synchronization subunit is used to read the first operand from the first operand queue and the second operand from the second operand queue, and the first operand and the second operand are read out at the same time; the first operand and the second operand are sent to the operation unit synchronously.

[0281] For illustration, please refer to Figure 10 , which shows a schematic diagram of data synchronization. Assuming that the second response data 1002 is acquired by the load unit two clock cycles later than the first response data 1001, the first response data is temporarily stored in the first operand queue, and the second response data is temporarily stored in the second operand queue. The synchronization subunit then reads them synchronously, obtaining aligned operands a (i.e., the first response data) and b (i.e., the second response data).

[0282] In the above embodiment, an operand queue and a synchronization subunit are designed in the chip to implement synchronous operations on multiple operands. The synchronization subunit ensures the clock cycle consistency of multiple operands, avoiding the clock cycle consistency of the operation unit due to timing It can solve the operation errors caused by sequence errors or data conflicts and improve the operation accuracy.

[0283] 2. Arithmetic unit 240

[0284] In some embodiments, the chip includes multiple execution subunits, which are used to perform various calculation operations. In order to correctly send operands to the execution subunit corresponding to the calculation operation indicated by the first instruction, a dispatch subunit can be set in the chip.

[0285] For illustration, please refer to Figure 11 The computing unit 240 further includes a dispatching subunit 241 and a plurality of executing subunits. The dispatching subunits are connected to the plurality of executing subunits respectively.

[0286] Optionally, the multiple execution subunits include at least one of the following subunits:

[0287] Arithmetic operation subunit 242, used to perform arithmetic operations;

[0288] The logic operation subunit 243 is used to perform logic operation operations;

[0289] The conversion operation subunit 244 is used to perform numerical conversion operations;

[0290] Illustratively, the arithmetic operator subunit is used to perform various arithmetic operations. These operations include, but are not limited to, basic mathematical operations such as addition, subtraction, multiplication, and division. The arithmetic operator subunit typically includes multiple arithmetic logic units (ALUs), which can process data in parallel, thereby accelerating the calculation process.

[0291] The logic operation subunit is used to perform logic operations. Logical operations mainly include basic logic operations such as AND, OR, NOT, and XOR.

[0292] The conversion operator unit is used to perform numerical conversion operations. It can convert one data format or type into another data format or type to meet different calculation or storage requirements. Optionally, the conversion operator unit can perform multiple types of conversion operations, including but not limited to: data type conversion, for example, converting a fixed-point number to a floating-point number, or converting an integer to a floating-point number, or converting a signed number to an unsigned number; data format conversion, such as converting a binary number to a decimal number; data precision conversion, for example, in image processing, converting a high-resolution image to a low-resolution image to save storage space; data encoding conversion, such as converting text from one character encoding to another to adapt to different language environments.

[0293] It should be noted that the above description of the execution sub-unit is only an illustrative example, and the embodiments of the present application do not limit this. For example, multiple execution sub-units may also include a shift operation sub-unit, and the bit operation sub-unit is used to execute shift operation instructions, and the shift operation instruction is used to shift data left or right by a specified number of bits.

[0294] In the above embodiment, a plurality of different sub-execution units are designed in the chip to perform a variety of different operations. This enables the chip to perform a wider range of calculation types, allowing the chip to adapt to more diverse application scenarios and needs.

[0295] Optionally, the dispatch subunit is used to send the operand to a target execution subunit among the multiple execution subunits; the target execution subunit is used to perform the operation indicated by the instruction type to obtain the operation result of the operand.

[0296] Schematically, the dispatch subunit identifies the operation code in the operation instruction, thereby determining the current operation on the operand. After determining the operation, the dispatch subunit can determine the execution subunit corresponding to the operation, such as: if the operation is an addition operation, the corresponding execution subunit is the arithmetic operation subunit; then, the dispatch subunit sends the received operand to the arithmetic operation subunit.

[0297] In the above embodiment, a dispatch subunit is designed in the chip so that when a first instruction is received, the first instruction is sent to the corresponding execution subunit for execution. , ensuring that the operation instructions are executed in the correct way, avoiding the instruction Incorrect execution situation.

[0298] In some embodiments, please refer to Figure 11 , the loading unit 240 also includes: a multiplexer 245.

[0299] The target execution subunit is further used to send the operation result to the multiplexer; the multiplexer is used to send the operation result to the storage unit.

[0300] Schematically, a multiplexer (MUX) is a basic digital logic circuit used to select an output signal from multiple input signals.

[0301] Optionally, the multiplexer has multiple input terminals, and the output terminals corresponding to the multiple execution subunits are connected to the corresponding input terminals of the multiplexer, wherein one input terminal is connected to one output terminal; and the output terminal of the multiplexer is connected to the input terminal of the storage unit. Illustratively, after the target execution subunit completes the operation, it sends the operation result through the output terminal of the target execution subunit to the input terminal of the multiplexer connected to the output terminal of the target execution subunit. The multiplexer then sends the operation result through the output terminal of the multiplexer to the input terminal of the storage unit.

[0302] 3. Storage unit 250

[0303] For illustration, please refer to Figure 12 The storage unit 250 also includes: an operation result queue and a request generation subunit 251.

[0304] Optionally, the operation result queue is used to store the operation results, and the request generation subunit is used to generate the storage request. The operation result queue can be implemented as a FIFO (First In First Out) queue.

[0305] Schematically, the calculation result is sent to the storage unit to complete the writing operation of the calculation result, that is, in the storage unit, a storage request is generated by the request generation subunit, and the storage request includes a storage address (that is, the target address). The calculation result queue is used to store the calculation result. After the storage request is generated, the storage request and the calculation result are sent to the storage location indicated by the target address to complete the task of writing the calculation result to the storage location.

[0306] The request generation subunit can quickly generate storage requests, allowing the calculation results to be written more quickly. Storage location improves the execution efficiency of instructions.

[0307] For illustration, the above memory unit is implemented as a register as an example, please refer to Figure 13 , which shows a structural block diagram of a chip.

[0308] like Figure 13 As shown, the RISC (processor 1300) sends the instruction configuration information to the register of the chip 1310 to configure the execution information required during the execution of the first instruction. The instruction configuration information includes:

[0309] Operand address: operand a address and operand b address;

[0310] Data length: the total amount of data that needs to be processed this time;

[0311] Instruction mode: For example, whether the addition instruction is 32-bit or 16-bit;

[0312] Instruction type: which instruction the hardware is to execute;

[0313] Target address: the storage address where the calculation result is written;

[0314] Start register configuration information; when all configuration information is configured, the start register can be configured to 1 to start the execution of the first instruction.

[0315] After completing the configuration of the instruction information, the execution of the first instruction can begin. This process is divided into three parts: the execution of the load instruction, the execution of the operation instruction, and the execution of the store instruction. Before the first instruction is executed, these three instructions need to be decoded. The decoding operation is performed in the load decoding unit, the operation decoding unit, and the store decoding unit respectively. The load decoding unit, the operation decoding unit, and the store decoding unit perform parallel decoding to obtain the load instruction, the operation instruction, and the store instruction. The decoding process parses the above instruction information into control signals that are easily recognized by the hardware.

[0316] After the instruction decoding is completed, it is sent to the instruction splitting unit (the load instruction, operation instruction and storage instruction are split and processed in splitting unit 1, splitting unit 2 and splitting unit 3 respectively, and splitting unit 1, splitting unit 2 and splitting unit 3 are split in parallel). After the instruction splitting is completed, the split instructions are sent to three execution units: load unit, operation unit and storage unit. Among them:

[0317] (1) The loading unit completes the data loading operation.

[0318] The loading unit includes two loading request transmitting units, namely loading request transmitting unit 1 and loading request transmitting unit 2. The loading request transmitting unit sends loading request 1 and loading request 2 to the memory, and the memory returns response data, namely loading request response data 1 and loading request response data 2.

[0319] The load request response data 1 is temporarily stored in the operand a queue, and the load request response data 2 is temporarily stored in the operand b queue. Since the time when the memory returns the response data may be different, the synchronization subunit needs to complete the synchronization operation of the two operands.

[0320] For illustration, assuming that the load request response data 2 is two clock cycles slower than the load request response data 1, the two data are temporarily stored in the queue and then read out synchronously to obtain two aligned operands.

[0321] (2) The arithmetic unit completes the execution of the arithmetic instructions.

[0322] The dispatch subunit in the load unit dispatches operands a (response data 1) and b (response data 2) sent by the load unit to the corresponding execution unit based on the instruction type. These execution units include arithmetic subunits for performing operations such as addition, subtraction, multiplication, and division; logical subunits for performing operations such as AND, OR, and NOT; and conversion subunits for converting fixed-point numbers to floating-point numbers. After the operation is completed, the result is selected through a multiplexer.

[0323] (3) The calculation result is sent to the storage unit to complete the data writing operation.

[0324] The storage request generation subunit completes the generation of the storage request, wherein the storage request includes the storage address of the operation result. The operation result queue temporarily stores the operation result to be written out, and aligns the operation result to be written with the storage request before writing it out.

[0325] The following are examples of the methods of the present application. For details not disclosed in the examples of the methods of the present application, please refer to the examples of the chips of the present application. Figure 14This is a flowchart of an instruction execution method provided by an exemplary embodiment of the present application, which is executed by the above-mentioned chip 200. The chip 200 includes: a memory unit, a decoding unit, a loading unit and an operation unit.

[0326] Step 1401: The memory unit obtains instruction configuration information of a first instruction.

[0327] The instruction configuration information is used to indicate execution information for performing an operation on an operand based on the first instruction.

[0328] In some embodiments, the chip also includes a start register.

[0329] Illustratively, when the instruction configuration information is stored in the memory unit, the start register updates the state identifier of the start register to the first state identifier; when the state identifier of the start register is the first state identifier, the memory unit sends the instruction configuration information to the decoding unit.

[0330] In some embodiments, the memory unit obtains instruction configuration information of a second instruction within an execution time period corresponding to a first instruction, where the second instruction is the next instruction to be executed after the first instruction.

[0331] Step 1402: The register unit sends instruction configuration information to the decoding unit.

[0332] Step 1403: The decoding unit decodes the instruction configuration information to obtain a load instruction and an operation instruction.

[0333] The load instruction and the operation instruction are used to implement the operation task of the operand indicated by the first instruction.

[0334] In some embodiments, the decoding unit includes a first decoding unit and a second decoding unit.

[0335] Optionally, the memory unit sends instruction configuration information to the first decoding unit and the second decoding unit in parallel; the first decoding unit decodes the instruction configuration information to obtain a load instruction; and the second decoding unit decodes the instruction configuration information to obtain an operation instruction.

[0336] The situation where the decoding unit decodes the instruction includes at least one of the following situations:

[0337] Case 1: the first decoding unit sends a load instruction to the loading unit at the third time; the second decoding unit sends an operation instruction to the operation unit at the third time.

[0338] Case 2: In response to the completion of decoding the load instruction, the first decoding unit sends the load instruction to the load unit; in response to the completion of decoding the operation instruction, the second decoding unit sends the operation instruction to the operation unit.

[0339] In some embodiments, the instruction configuration information includes a data length, where the data length is used to indicate the amount of data to be processed based on the first instruction.

[0340] Optionally, when the data length is greater than a preset length, the splitting unit splits the load instruction into n sub-load instructions and splits the operation instruction into n sub-operation instructions based on the preset length.

[0341] Among them, the i-th sub-load instruction and the i-th sub-operation instruction indicate the same amount of sub-data to be processed, n>1 and n is an integer, i≤n and i is a positive integer; the preset data amount corresponding to the preset length refers to the amount of data processed by a single clock cycle of the chip, and the sub-data amount is less than or equal to the preset data amount.

[0342] In some embodiments, the splitting unit includes a first splitting unit and a second splitting unit.

[0343] Optionally, the first splitting unit splits the load instruction to obtain n sub-load instructions; the second splitting unit splits the operation instruction to obtain n sub-operation instructions.

[0344] Schematically, the first decoding unit sends a load instruction to the first splitting unit, which splits the load instruction into n sub-load instructions; the second decoding unit sends an operation instruction to the second splitting unit, which splits the operation instruction into n sub-operation instructions.

[0345] Step 1404 : In response to receiving the load instruction, the load unit executes the load instruction and obtains an operand.

[0346] In some embodiments, the instruction configuration information includes an operand address, and the load instruction is used to obtain the operand based on the operand address; the load unit includes a request emission subunit.

[0347] Optionally, the request issuing subunit issues a load request based on an operand address in response to a load instruction, and uses response data of the load request as an operand.

[0348] Step 1405: Send the operand to the arithmetic unit.

[0349] In some embodiments, the operands include a first operand and a second operand, and the load unit further includes a first operand queue, a second operand queue, and a synchronization subunit.

[0350] Schematically, the first operand queue stores the first operand; the second operand queue stores the second operand; the synchronization subunit reads the first operand from the first operand queue and reads the second operand from the second operand queue, and the reading time of the first operand and the second operand is the same; the first operand and the second operand are synchronously sent to the operation unit.

[0351] Step 1406 , when the operation instruction is received, in response to receiving the operand at the first moment, the operation instruction is executed from the first moment to obtain the operation result of the operand.

[0352] In some embodiments, when the situation in which the above-mentioned decoding unit decodes the instruction is situation two, the operation unit receives the operand but does not receive the operation instruction. In response to receiving the operation instruction at the fourth moment, the operation instruction is executed from the fourth moment to obtain the operation result of the operand.

[0353] In some embodiments, the instruction configuration information includes the instruction type of the first instruction; the operation unit further includes a dispatch subunit and multiple execution subunits.

[0354] Optionally, the dispatch subunit sends the operand to a target execution subunit among the multiple execution subunits; the target execution subunit executes the operation indicated by the instruction type to obtain the operation result of the operand.

[0355] Optionally, the multiple execution subunits include at least one of the following subunits:

[0356] The arithmetic operation subunit is used to perform arithmetic operations;

[0357] Logical operation subunit, used to perform logical operation operations;

[0358] The conversion operator unit is used to perform numerical conversion operations.

[0359] In some embodiments, the chip 200 further includes: a storage unit; the decoding unit further includes a third decoding unit. Optionally, the storage unit sends instruction configuration information to the first decoding unit, the second decoding unit, and the third decoding unit in parallel; the first decoding unit decodes the instruction configuration information to obtain a load instruction; the second decoding unit decodes the instruction configuration information to obtain a calculation instruction; and the third decoding unit decodes the instruction configuration information to obtain a store instruction.

[0360] Optionally, the splitting unit is further configured to split the storage instruction into n sub-storage instructions based on the preset length when the data length is greater than the preset length.

[0361] Among them, the i-th sub-load instruction, the i-th sub-operation instruction and the i-th sub-storage instruction indicate the same amount of sub-data to be processed, n>1 and n is an integer, i≤n and i is a positive integer; the preset data amount corresponding to the preset length refers to the amount of data processed by a single clock cycle of the chip, and the sub-data amount is less than or equal to the preset data amount.

[0362] Optionally, the splitting unit further includes a third splitting unit, the third decoding unit sends the storage instruction to the third splitting unit, and the third splitting unit splits the storage instruction to obtain n sub-storage instructions.

[0363] Optionally, after the operation unit obtains the operation result of the operand, it also includes: the operation unit sends the operation result to the storage unit; when the storage unit receives the storage instruction, in response to receiving the operation result at the second moment, executes the storage instruction from the second moment, and the storage instruction is used to store the operation result.

[0364] In some embodiments, the instruction configuration information includes a target address, and the storage instruction is used to store the operation result at the target address; the storage unit also includes a request generation subunit and an operation result queue.

[0365] Schematically, the operation result queue stores the operation result; the request generation subunit generates a storage request, and the storage request is used to request to store the operation result to the target address.

[0366] In summary, the instruction execution method provided by the present application can obtain the instruction configuration information of the first instruction through the memory unit, and then decode the instruction configuration information through the decoding unit, thereby decoding the first instruction into a load instruction and an operation instruction. Then, the load instruction is executed by the loading unit to obtain the operand, and the operand is sent to the operation unit; the operation unit executes the operation instruction at the moment of receiving the operand to obtain the operation result. Among them, the load instruction and the operation instruction are decoded in parallel in the chip, and the chip can schedule and execute the instruction at any time after the decoding is completed. That is to say, when the load instruction is executed to obtain the operand, the operation instruction can be executed seamlessly, avoiding the idle clock cycle caused by waiting for the reception of the operation instruction after obtaining the operand, thereby reducing the waste of execution resources and improving chip performance.

[0367] The chip provided in this application can be applied to a variety of scenarios requiring data operations. Optionally, the chip provided in this application can be applied to AI training scenarios, where the chip is installed in an AI training device to perform the operations required for AI training.

[0368] Optionally, the chip provided in this application can also be applied to AI reasoning scenarios. The chip can be installed on a target device and perform the operations required for AI reasoning through the chip. For example, AI reasoning scenarios can be implemented in autonomous driving scenarios, mobile device control scenarios, etc., which are not limited in this embodiment of the application.

[0369] The following describes the instruction execution methods implemented in AI training scenarios, autonomous driving scenarios, and mobile device control scenarios.

[0370] (1) AI training scenarios

[0371] The above chip can be implemented as a vector execution device in an AI processor. The vector execution device includes a register unit, a start register, a first decoding unit, a second decoding unit, a third decoding unit, a first splitting unit, a second splitting unit, a third splitting unit, a loading unit, an operation unit, and a storage unit.

[0372] Schematically, the steps of the instruction execution method applied to the vector execution device are briefly described as follows.

[0373] Step 1: The register unit obtains instruction configuration information of the target instruction.

[0374] Among them, the target instruction is used to perform vector (i.e., operand) operations corresponding to the AI ​​training task.

[0375] Optionally, the vector operation types include but are not limited to:

[0376] Vector addition and subtraction: Add or subtract elements at corresponding positions of two vectors, such as matrix addition and vector addition.

[0377] Vector multiplication: including inner product and cross product outer product, used to calculate the product between two vectors.

[0378] Vector multiplication and accumulation: Multiply each element of one vector by the corresponding element of another vector and accumulate the results to obtain a scalar value.

[0379] Vector multiplication and accumulation: Multiply each element of a vector with the corresponding element of another vector, and then accumulate and sum all the products to obtain a scalar value.

[0380] Vector multiplication and accumulation averaging: Multiply each element of one vector with the corresponding element of another vector and accumulate and average all the products to obtain a scalar value.

[0381] Vector scalar multiplication: Multiply each element of a vector by a scalar (constant).

[0382] Vector division: Divides each element of a vector by a scalar.

[0383] Vector negation and modulo: negate or modulo each element of a vector.

[0384] Vector logical operations: including logical operations such as AND, OR, and NOT, used to process logical relationships in vectors.

[0385] Step 2: When the register unit completes configuration based on the instruction configuration information, the state flag of the start register is updated to the first state flag.

[0386] Illustratively, the register unit completing configuration based on the instruction configuration information may be understood as the register unit successfully storing the instruction configuration information.

[0387] Step 3: The register unit sends the instruction configuration information to the first decoding unit, the second decoding unit, and the third decoding unit in parallel.

[0388] Step 4: The first decoding unit decodes the instruction configuration information to obtain a load instruction; the second decoding unit decodes the instruction configuration information to obtain a calculation instruction; and the third decoding unit decodes the instruction configuration information to obtain a store instruction.

[0389] In step 5, the first decoding unit sends the load instruction to the first splitting unit for splitting, and obtains n sub-load instructions; the second decoding unit sends the operation instruction to the second splitting unit for splitting, and obtains n sub-operation instructions; the third decoding unit sends the storage instruction to the third splitting unit for splitting, and obtains n sub-storage instructions.

[0390] In step 6, the first splitting unit sends the n sub-load instructions to the load unit; the second splitting unit sends the n sub-operation instructions to the operation unit; and the third splitting unit sends the n sub-store instructions to the storage unit.

[0391] Step 7: In response to receiving the i-th sub-load instruction, the load unit executes the i-th sub-load instruction to obtain the i-th vector; and sends the i-th vector to the operation unit.

[0392] Step 8: When the operation unit receives the i-th sub-operation instruction, in response to receiving the i-th vector at the first moment, it executes the i-th sub-operation instruction starting from the first moment, obtains the i-th operation result of the i-th vector; and sends the i-th operation result to the storage unit.

[0393] Step 9: When the storage unit receives the i-th sub-storage instruction, in response to receiving the i-th operation result at the second moment, it executes the i-th sub-storage instruction from the second moment.

[0394] Optionally, the i-th sub-storage instruction is also used to send the i-th operation result to the target vector execution device, and the target vector execution device and the above-mentioned vector execution device are used to execute the same AI training task.

[0395] Schematically, during AI training, the model's training data is divided into multiple batches, and each batch of data is processed in parallel on multiple different vector execution devices. The arithmetic unit on each vector execution device is responsible for calculating the gradient of the corresponding batch of data and updating the model's parameters. When the arithmetic unit on one vector execution device completes the gradient calculation for a batch of data, it needs to send the gradient result to other vector execution devices for global gradient aggregation or parameter update.

[0396] Optionally, executing n sub-load instructions, n sub-operation instructions and n sub-store instructions may obtain n operation results, and these n operation results are the task results of the vector operation task indicated by the target instruction.

[0397] In summary, the instruction execution method provided by the embodiments of the present application allows programmers to simply configure the relevant registers according to the vector operation task and then start the target instruction execution unit to obtain the task result of the vector operation task, thereby reducing the programming difficulty. The hardware (vector execution device) automatically handles the process of splitting the target instruction into microinstructions such as load instructions, and no instruction bubbles are generated during the splitting process, which greatly improves the performance of the vector execution device and the training efficiency of AI training.

[0398] (2) Autonomous driving scenarios

[0399] The chip can be implemented as an object recognition device in an autonomous vehicle. The object recognition device includes a register unit, a start register, a first decoding unit, a second decoding unit, a third decoding unit, a first splitting unit, a second splitting unit, a third splitting unit, a loading unit, a computing unit, and a storage unit.

[0400] Schematically, the steps of the instruction execution method applied to the object recognition device are briefly described as follows.

[0401] Step 1: The register unit obtains instruction configuration information of the object recognition instruction.

[0402] Alternatively, the operands processed by the object recognition device instructions can be implemented as image vectors, that is, the object recognition instructions are used to perform image vector operations corresponding to the object recognition task. The image vectors are used to represent image data collected by the autonomous vehicle.

[0403] Schematically, raw data is collected by image acquisition devices such as cameras in self-driving cars. The raw data usually exists in the form of images. The raw data is converted into image vectors through preprocessing and feature extraction.

[0404] Optionally, the above object recognition tasks include but are not limited to:

[0405] Vehicle recognition: Identify other vehicles on the road, including cars, trucks, motorcycles, etc.

[0406] Pedestrian Recognition: The recognition command is used to identify pedestrians on the road.

[0407] Traffic sign and signal light recognition: Identify the status of various traffic signs (such as speed limit signs, no-entry signs, etc.) and signal lights (such as traffic lights).

[0408] Road feature recognition: identifying lane lines, road edges, intersections, etc.

[0409] Obstacle recognition: Identify obstacles on the road, such as construction facilities, fallen objects, animals, etc.

[0410] Step 2: When the register unit completes configuration based on the instruction configuration information, the state flag of the start register is updated to the first state flag.

[0411] Illustratively, the register unit completing configuration based on the instruction configuration information may be understood as the register unit successfully storing the instruction configuration information.

[0412] Step 3: The register unit sends the instruction configuration information to the first decoding unit, the second decoding unit, and the third decoding unit in parallel.

[0413] Step 4: The first decoding unit decodes the instruction configuration information to obtain a load instruction; the second decoding unit decodes the instruction configuration information to obtain a calculation instruction; and the third decoding unit decodes the instruction configuration information to obtain a store instruction.

[0414] In step 5, the first decoding unit sends the load instruction to the first splitting unit for splitting, and obtains n sub-load instructions; the second decoding unit sends the operation instruction to the second splitting unit for splitting, and obtains n sub-operation instructions; the third decoding unit sends the storage instruction to the third splitting unit for splitting, and obtains n sub-storage instructions.

[0415] In step 6, the first splitting unit sends the n sub-load instructions to the load unit; the second splitting unit sends the n sub-operation instructions to the operation unit; and the third splitting unit sends the n sub-store instructions to the storage unit.

[0416] Step 7: In response to receiving the i-th sub-load instruction, the loading unit executes the i-th sub-load instruction to obtain the i-th image vector; and sends the i-th image vector to the operation unit.

[0417] Step 8: When the operation unit receives the i-th sub-operation instruction, in response to receiving the i-th image vector at the first moment, it executes the i-th sub-operation instruction starting from the first moment, obtains the i-th operation result of the i-th image vector; and sends the i-th operation result to the storage unit.

[0418] Step 9: When the storage unit receives the i-th sub-storage instruction, in response to receiving the i-th operation result at the second moment, it executes the i-th sub-storage instruction from the second moment.

[0419] Optionally, executing n sub-load instructions, n sub-operation instructions and n sub-store instructions can obtain n operation results, and these n operation results are the task results of the image vector operation task indicated by the object recognition instruction.

[0420] Schematically, n calculation results are stored in the decision-making module of the autonomous vehicle. After receiving the task results, the decision-making module will combine other sensor data (such as GPS positioning, vehicle status, etc.) and map information for comprehensive analysis and judgment to formulate appropriate driving strategies, such as adjusting vehicle speed, steering, and avoiding obstacles.

[0421] In summary, the instruction execution method provided in the embodiment of the present application automatically handles the splitting process of object recognition instructions into microinstructions such as loading instructions by the object recognition device, and no instruction bubbles are generated during the splitting process, which greatly improves the performance of the object recognition device and improves the object recognition efficiency in the autonomous driving scenario.

[0422] (3) Mobile device control scenario

[0423] The chip can be implemented as a voice recognition device in a smartphone, wherein the voice recognition device includes a register unit, a start register, a first decoding unit, a second decoding unit, a third decoding unit, a first splitting unit, a second splitting unit, a third splitting unit, a loading unit, a calculation unit, and a storage unit.

[0424] Schematically, the steps of the instruction execution method applied to the speech recognition device are briefly described as follows.

[0425] Step 1: The register unit obtains instruction configuration information of the speech recognition instruction.

[0426] Optionally, the operand indicated by the speech recognition device for processing can be implemented as a speech vector, that is, the speech recognition device is used to perform speech vector operations corresponding to the speech recognition task, wherein the speech vector is used to represent the speech data collected by the smartphone.

[0427] Schematically, raw data is collected through voice collection devices such as microphones in smartphones. The raw data usually exists in the form of voice signals. The raw data is preprocessed and feature extracted to convert it into a voice vector.

[0428] Optionally, the above-mentioned speech recognition tasks include but are not limited to:

[0429] Voice Unlock: Unlock your phone with voice commands, without having to press any physical buttons or touch anything.

[0430] Voice search: Users speak search terms or questions directly, and the smartphone recognizes them and searches for relevant information in the search engine.

[0431] Voice dialing: Dial a contact using voice commands.

[0432] Voice command execution: Use voice commands to control the phone to perform various operations, such as opening applications, sending text messages, setting reminders, etc.

[0433] Speech translation: Recognizes user speech and translates it into other languages.

[0434] Smart assistant interaction: Have voice conversations with the phone's smart assistant, such as asking for information such as weather, news, and schedules.

[0435] Voice input: In the text input box, use voice input instead of manual typing.

[0436] Step 2: When the register unit completes configuration based on the instruction configuration information, the state flag of the start register is updated to the first state flag.

[0437] Illustratively, the register unit completing configuration based on the instruction configuration information may be understood as the register unit successfully storing the instruction configuration information.

[0438] Step 3: The register unit sends the instruction configuration information to the first decoding unit, the second decoding unit, and the third decoding unit in parallel.

[0439] Step 4: The first decoding unit decodes the instruction configuration information to obtain a load instruction; the second decoding unit decodes the instruction configuration information to obtain a calculation instruction; and the third decoding unit decodes the instruction configuration information to obtain a store instruction.

[0440] In step 5, the first decoding unit sends the load instruction to the first splitting unit for splitting, and obtains n sub-load instructions; the second decoding unit sends the operation instruction to the second splitting unit for splitting, and obtains n sub-operation instructions; the third decoding unit sends the storage instruction to the third splitting unit for splitting, and obtains n sub-storage instructions.

[0441] In step 6, the first splitting unit sends the n sub-load instructions to the load unit; the second splitting unit sends the n sub-operation instructions to the operation unit; and the third splitting unit sends the n sub-store instructions to the storage unit.

[0442] Step 7: In response to receiving the i-th sub-load instruction, the loading unit executes the i-th sub-load instruction to obtain the i-th voice vector; and sends the i-th voice vector to the operation unit.

[0443] Step 8: When the operation unit receives the i-th sub-operation instruction, in response to receiving the i-th voice vector at the first moment, it executes the i-th sub-operation instruction starting from the first moment, obtains the i-th operation result of the i-th voice vector; and sends the i-th operation result to the storage unit.

[0444] Step 9: When the storage unit receives the i-th sub-storage instruction, in response to receiving the i-th operation result at the second moment, it executes the i-th sub-storage instruction from the second moment.

[0445] Optionally, executing n sub-load instructions, n sub-operation instructions and n sub-storage instructions can obtain n operation results, and these n operation results are the task results of the speech vector operation task indicated by the speech recognition instruction.

[0446] Schematically, n operation results are stored in a voice command generation module in the smartphone, and the voice command generation module is used to generate voice commands based on the n operation results, and the voice commands are used to control the smartphone to perform the above-mentioned voice recognition task.

[0447] To sum up, the instruction execution method provided in the embodiment of the present application automatically handles the splitting process of voice recognition instructions into microinstructions such as loading instructions by the voice recognition device, and no instruction bubbles are generated during the splitting process, which greatly improves the performance of the voice recognition device and improves the control efficiency in the mobile device control scenario.

[0448] In some embodiments, the present application also provides a processor comprising the chip described above.

[0449] In some embodiments, an embodiment of the present application further provides a computer device comprising: a processor and a memory, wherein a computer program is stored in the memory; the processor comprises the above-mentioned chip, which is used to execute the computer program in the memory to implement the above-mentioned instruction execution method.

[0450] Indicative, Figure 15 FIG. 1 is a block diagram of a computer device 1500 provided in an exemplary embodiment of the present application. Optionally, the computer device 1500 is a server 1500 .

[0451] Typically, the server 1500 includes a processor 1501 and a memory 1502 .

[0452] The processor 1501 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor 1501 may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 1501 may also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 1501 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 1501 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0453] Memory 1502 may include one or more computer-readable storage media, which may be non-transitory. Memory 1502 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in memory 1502 is used to store at least one instruction, which is executed by processor 1501 to perform the above-described instruction execution method.

[0454] In some embodiments, the server 1500 may further optionally include: an input interface 1503 and an output interface 1504. The processor 1501, the memory 1502, and the input interface 1503 and the output interface 1504 may be connected via a bus or a signal line. Each peripheral device may be connected to the input interface 1503 and the output interface 1504 via a bus, a signal line, or a circuit board. The input interface 1503 and the output interface 1504 may be used to connect at least one peripheral device related to input / output (I / O) to the processor 1501 and the memory 1502. In some embodiments, the processor 1501, the memory 1502, the input interface 1503, and the output interface 1504 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 1501, the memory 1502, the input interface 1503, and the output interface 1504 may be implemented on a separate chip or circuit board, which is not limited in the embodiments of the present application.

[0455] Those skilled in the art will understand that Figure 15 The structure shown in the figure does not constitute a limitation on the computer device 1500, and the computer device 1500 may include more or fewer components than shown in the figure, or combine some components, or adopt a different component arrangement.

[0456] The present application provides a computer-readable storage medium, which stores a computer program. The computer program is loaded and executed by a processor to implement the above-mentioned instruction execution method.

[0457] The present application provides a computer program product or computer program, wherein the computer program product or computer program includes computer instructions, wherein the computer instructions are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, so that the processor of the computer device loads and executes the computer instructions to implement the above-mentioned instruction execution method.

[0458] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0459] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or may be accomplished by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0460] Those skilled in the art will appreciate that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0461] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A chip, characterized in that: The chip includes: a memory unit, a decoding unit, a loading unit and an operation unit; the memory unit is connected to the decoding unit, the decoding unit is connected to the loading unit and the operation unit respectively, and the loading unit is connected to the operation unit; The memory unit is configured to obtain instruction configuration information of a first instruction, the instruction configuration information being used to indicate execution information of an operation performed on an operand based on the first instruction; and send the instruction configuration information to the decoding unit; The decoding unit is configured to decode the instruction configuration information to obtain a load instruction and an operation instruction, wherein the load instruction and the operation instruction are configured to implement the operation task of the operand indicated by the first instruction; The loading unit is configured to, in response to receiving the loading instruction, execute the loading instruction to obtain the operand; and send the operand to the operation unit; The operation unit is configured to, upon receiving the operation instruction, execute the operation instruction starting from the first moment in response to receiving the operand at the first moment, and obtain an operation result of the operand.

2. The chip according to claim 1, characterized in that The decoding unit includes: a first decoding unit and a second decoding unit; the first decoding unit is connected to the loading unit, and the second decoding unit is connected to the operation unit; The memory unit is configured to send the instruction configuration information to the first decoding unit and the second decoding unit in parallel; The first decoding unit is configured to decode the instruction configuration information to obtain the load instruction; The second decoding unit is configured to decode the instruction configuration information to obtain the operation instruction.

3. The chip according to claim 2, characterized in that The chip further includes: a storage unit; the decoding unit further includes: a third decoding unit; the third decoding unit is connected to the storage unit, and the storage unit is connected to the operation unit; The third decoding unit is used to decode the instruction configuration information to obtain a storage instruction; The computing unit is further configured to send the computing result to the storage unit; The storage unit is configured to, upon receiving the storage instruction, execute the storage instruction starting from the second moment in response to receiving the operation result at the second moment, wherein the storage instruction is configured to store the operation result.

4. The chip according to claim 2, characterized in that The first decoding unit is configured to send the load instruction to the loading unit at a third moment; The second decoding unit is configured to send the operation instruction to the operation unit at the third moment.

5. The chip according to claim 2, characterized in that The first decoding unit is configured to send the load instruction to the loading unit in response to completion of decoding the load instruction; The second decoding unit is configured to send the operation instruction to the operation unit in response to completion of decoding the operation instruction.

6. The chip according to claim 5, characterized in that The operation unit is further configured to, in response to receiving the operation instruction at a fourth moment, execute the operation instruction starting from the fourth moment to obtain the operation result of the operand when the operand is received but the operation instruction is not received.

7. The chip according to any one of claims 1 to 6, characterized in that: The instruction configuration information includes a data length, and the data length is used to indicate the amount of data to be operated based on the first instruction; the chip further includes: a splitting unit; the decoding unit is connected to the splitting unit, and the splitting unit is respectively connected to the loading unit and the operation unit; The splitting unit is configured to split the load instruction into n sub-load instructions and split the operation instruction into n sub-operation instructions based on the preset length when the data length is greater than the preset length; Among them, the i-th sub-load instruction and the i-th sub-operation instruction indicate the same amount of sub-data to be processed, n>1 and n is an integer, i≤n and i is a positive integer; the preset data amount corresponding to the preset length refers to the amount of data processed by a single clock cycle of the chip, and the sub-data amount is less than or equal to the preset data amount.

8. The chip according to claim 7, characterized in that The splitting unit includes: a first splitting unit and a second splitting unit; the first splitting unit is connected to the loading unit, and the second splitting unit is connected to the operation unit; The first splitting unit is configured to split the load instruction to obtain the n sub-load instructions; The second splitting unit is used to split the operation instruction to obtain the n sub-operation instructions.

9. The chip according to any one of claims 1 to 6, characterized in that: The instruction configuration information includes an operand address, and the load instruction is used to obtain the operand based on the operand address; the load unit includes: a request emission subunit; The request issuing subunit is configured to issue a load request based on the operand address in response to the load instruction, and use response data of the load request as the operand.

10. The chip according to claim 9, characterized in that The operands include a first operand and a second operand, and the loading unit further includes: a first operand queue, a second operand queue and a synchronization subunit; The first operand queue is used to store the first operand; The second operand queue is used to store the second operand; The synchronization subunit is used to read the first operand from the first operand queue and read the second operand from the second operand queue, the first operand and the second operand are read at the same time; and the first operand and the second operand are synchronously sent to the operation unit.

11. The chip according to any one of claims 1 to 6, characterized in that: The instruction configuration information includes the instruction type of the first instruction; the operation unit further includes: a dispatch subunit and a plurality of execution subunits; the dispatch subunit is connected to the plurality of execution subunits respectively; The dispatch subunit is configured to send the operand to a target execution subunit among the plurality of execution subunits; The target execution subunit is used to execute the operation indicated by the instruction type to obtain the operation result of the operand.

12. The chip according to claim 11, characterized in that The plurality of execution subunits include at least one of the following subunits: The arithmetic operation subunit is used to perform arithmetic operations; Logical operation subunit, used to perform logical operation operations; The conversion operator unit is used to perform numerical conversion operations.

13. The chip according to claim 3, characterized in that The instruction configuration information includes a target address, and the storage instruction is used to store the operation result to the target address; The storage unit also includes: a request generation subunit and an operation result queue; The operation result queue is used to store the operation result; The request generation subunit is used to generate a storage request, and the storage request is used to request to store the operation result to the target address.

14. The chip according to any one of claims 1 to 6, characterized in that: The chip further includes: a start register; The start register is configured to update a state flag of the start register to a first state flag when the instruction configuration information is stored in the memory unit; The memory unit is further configured to send the instruction configuration information to the decoding unit when the state identifier of the start register is the first state identifier.

15. The chip according to any one of claims 1 to 6, characterized in that: The memory unit is further configured to obtain instruction configuration information of a second instruction within an execution time period corresponding to the first instruction, where the second instruction is an instruction to be executed next after the first instruction.

16. A processor, characterized in that: The processor comprises the chip according to any one of claims 1 to 15.

17. A computer device, characterized in that: The computer device comprises the chip according to any one of claims 1 to 15.

18. A method for executing an instruction, characterized in that: The method is executed by a chip, the chip including: a memory unit, a decoding unit, a loading unit and an operation unit; the method includes: The memory unit acquires instruction configuration information of a first instruction, the instruction configuration information being used to indicate execution information of performing an operation on an operand based on the first instruction; and sends the instruction configuration information to a decoding unit; The decoding unit decodes the instruction configuration information to obtain a load instruction and an operation instruction, wherein the load instruction and the operation instruction are used to implement the operation task of the operand indicated by the first instruction; The load unit executes the load instruction in response to receiving the load instruction, obtains the operand, and sends the operand to the operation unit; When receiving the operation instruction, the operation unit executes the operation instruction starting from the first moment in response to receiving the operand at the first moment, and obtains the operation result of the operand.

19. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which is loaded and executed by a processor to implement the instruction execution method according to claim 18.

20. A computer program product, characterized in that The computer program product includes a computer program, which is stored in a computer-readable storage medium. The processor obtains the computer program from the computer-readable storage medium, so that the processor loads and executes the computer program to implement the instruction execution method according to claim 18.

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