Methods, apparatus, storage media, and software products for controlling the IR voltage drop of control chips

Abstract

This disclosure relates to a method, apparatus, storage medium, and program product for controlling the IR voltage drop of a chip. The method includes: determining the predicted power of the chip based on information from an instruction to be executed by the chip; determining a predicted current-resistance IR voltage drop value for the chip based on the predicted power; determining a predicted IR voltage drop exceedance amount for the chip based on the predicted IR voltage drop value and the maximum instantaneous allowable voltage drop; and performing power control on the chip based on the predicted IR voltage drop exceedance amount. This disclosure predicts chip power changes in advance through instruction-level analysis, rather than passively responding to voltage fluctuations. It can generate optimized power control strategies in advance, proactively adjusting the chip's operating state before current surges cause IR voltage drops. This allows for dynamic suppression of IR voltage drops without altering the hardware design, thereby reducing performance loss caused by IR voltage drops.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a method for controlling the IR voltage drop of a control chip, an apparatus for controlling the IR voltage drop of a control chip, a non-volatile computer-readable storage medium, and a computer program product. Background Technology

[0002] In chip applications, such as GPUs (Graphics Processing Units), the IR drop (current resistance drop) has always been a key factor affecting performance and stability. In IR drop, I represents current and R represents resistance. IR drop refers to the voltage loss that occurs in a circuit element or line due to factors such as resistance and reactance when current flows through it. According to Ohm's law, when current flows through a conductor with a certain resistance, a voltage difference is formed across the conductor; this voltage difference is the IR drop. The magnitude of the IR drop is directly proportional to the current magnitude and the resistance or impedance of the conductor. How to reduce the intensity of the IR drop to improve chip performance and stability is a pressing technical problem that needs to be solved. Summary of the Invention

[0003] In view of this, this disclosure provides a technical solution for controlling the IR voltage drop of a chip.

[0004] According to one aspect of this disclosure, a method for controlling the IR voltage drop of a chip is provided, comprising:

[0005] The predicted power of the chip is determined based on the information of the instruction to be executed by the chip.

[0006] Based on the predicted power, determine the predicted current-resistance IR voltage drop value of the chip;

[0007] Based on the predicted IR voltage drop value and the maximum instantaneous allowable voltage drop, determine the predicted amount of IR voltage drop exceeding the limit for the chip;

[0008] Based on the predicted amount of IR voltage drop exceeding the standard, the chip's power is controlled.

[0009] In one possible implementation, determining the predicted power of the chip based on the information of the chip's instructions to be executed includes:

[0010] Obtain the type and number of instructions to be executed from the chip;

[0011] The predicted power of the chip is determined based on the power level corresponding to each type of instruction to be executed and the number of instructions to be executed for each type.

[0012] In one possible implementation, obtaining the type and number of instructions to be executed from the chip includes:

[0013] Obtain the type and number of instructions to be executed from the instruction cache of each processor execution engine of the chip;

[0014] The type and number of instructions to be executed by the chip are determined based on the type and number of instructions to be executed by each processor execution engine.

[0015] In one possible implementation, the instruction cache of each processor execution engine is configured with a counter corresponding to each type of instruction to be executed; the counter corresponding to any type of instruction to be executed in the instruction cache of any processor execution engine is used to count the number of instructions of that type to be executed in the instruction cache of the processor execution engine.

[0016] In one possible implementation, determining the predicted power of the chip based on the power level corresponding to each type of instruction to be executed and the number of instructions to be executed of each type includes:

[0017] The instruction weighting coefficient of the chip is determined based on the power level corresponding to each type of instruction to be executed and the number of instructions to be executed of each type.

[0018] The predicted power of the chip is determined based on the chip's real-time operating parameters and the instruction weighting coefficient.

[0019] In one possible implementation, the real-time operating parameters include at least a portion of real-time operating voltage, real-time operating frequency, real-time current, and real-time temperature coefficient.

[0020] In one possible implementation, determining the predicted current-resistance IR voltage drop of the chip based on the predicted power includes:

[0021] The predicted power change of the chip is determined based on the difference between the predicted power and the current power of the chip.

[0022] The predicted IR drop value of the chip is determined based on the predicted power change, the chip's real-time operating voltage, and the path resistance from the voltage regulation module to the chip.

[0023] In one possible implementation, the step of performing power control on the chip based on the predicted IR drop exceedance includes:

[0024] Based on the predicted amount of IR voltage drop exceeding the standard, the power control parameters of the chip are determined;

[0025] The chip is powered according to the power control parameters.

[0026] In one possible implementation, determining the power control parameters of the chip based on the predicted IR drop exceedance includes:

[0027] The predicted value of the IR voltage drop exceeding the standard is input into a preset proportional-integral-derivative PID controller, and the power control parameters of the chip are output through the PID controller.

[0028] In one possible implementation, the step of power control of the chip based on the power control parameters includes:

[0029] Based on the power control parameters, a clock gating sequence corresponding to each processor execution engine in the chip is generated;

[0030] Based on the clock gating sequence corresponding to each processor execution engine, the clock gating operation of each processor execution engine is controlled, wherein at least one processor execution engine is kept on clock in each clock cycle.

[0031] In one possible implementation, when the power control parameters indicate a non-maximum power operating mode, the clock gating sequence corresponding to each processor execution engine is used to control each processor execution engine to turn off its clock in turn during different clock cycles.

[0032] According to another aspect of this disclosure, an apparatus for controlling the IR voltage drop of a chip is provided, comprising:

[0033] The prediction module is used to determine the predicted power of the chip based on the information of the instruction to be executed by the chip.

[0034] The first determining module is used to determine the predicted current-resistance IR voltage drop value of the chip based on the predicted power;

[0035] The second determining module is used to determine the predicted amount of IR voltage drop exceeding the limit of the chip based on the predicted IR voltage drop value and the maximum instantaneous allowable voltage drop.

[0036] The control module is used to control the power of the chip based on the predicted amount of IR voltage drop exceeding the standard.

[0037] In one possible implementation, the prediction module is used for:

[0038] Obtain the type and number of instructions to be executed from the chip;

[0039] The predicted power of the chip is determined based on the power level corresponding to each type of instruction to be executed and the number of instructions to be executed for each type.

[0040] In one possible implementation, the prediction module is used for:

[0041] Obtain the type and number of instructions to be executed from the instruction cache of each processor execution engine of the chip;

[0042] The type and number of instructions to be executed by the chip are determined based on the type and number of instructions to be executed by each processor execution engine.

[0043] In one possible implementation, the instruction cache of each processor execution engine is configured with a counter corresponding to each type of instruction to be executed; the counter corresponding to any type of instruction to be executed in the instruction cache of any processor execution engine is used to count the number of instructions of that type to be executed in the instruction cache of the processor execution engine.

[0044] In one possible implementation, the prediction module is used for:

[0045] The instruction weighting coefficient of the chip is determined based on the power level corresponding to each type of instruction to be executed and the number of instructions to be executed of each type.

[0046] The predicted power of the chip is determined based on the chip's real-time operating parameters and the instruction weighting coefficient.

[0047] In one possible implementation, the real-time operating parameters include at least a portion of real-time operating voltage, real-time operating frequency, real-time current, and real-time temperature coefficient.

[0048] In one possible implementation, the first determining module is used to:

[0049] The predicted power change of the chip is determined based on the difference between the predicted power and the current power of the chip.

[0050] The predicted IR drop value of the chip is determined based on the predicted power change, the chip's real-time operating voltage, and the path resistance from the voltage regulation module to the chip.

[0051] In one possible implementation, the control module is used to:

[0052] Based on the predicted amount of IR voltage drop exceeding the standard, the power control parameters of the chip are determined;

[0053] The chip is powered according to the power control parameters.

[0054] In one possible implementation, the control module is used to:

[0055] The predicted value of the IR voltage drop exceeding the standard is input into a preset proportional-integral-derivative PID controller, and the power control parameters of the chip are output through the PID controller.

[0056] In one possible implementation, the control module is used to:

[0057] Based on the power control parameters, a clock gating sequence corresponding to each processor execution engine in the chip is generated;

[0058] Based on the clock gating sequence corresponding to each processor execution engine, the clock gating operation of each processor execution engine is controlled, wherein at least one processor execution engine is kept on clock in each clock cycle.

[0059] In one possible implementation, when the power control parameters indicate a non-maximum power operating mode, the clock gating sequence corresponding to each processor execution engine is used to control each processor execution engine to turn off its clock in turn during different clock cycles.

[0060] According to another aspect of this disclosure, an apparatus for controlling the IR voltage drop of a chip is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0061] According to another aspect of this disclosure, a non-volatile computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the above-described method.

[0062] According to another aspect of this disclosure, a computer program product is provided, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above-described method.

[0063] In this embodiment, the predicted power of the chip is determined based on the information of the instruction to be executed by the chip. Based on the predicted power, the predicted current-resistance (IR) voltage drop of the chip is determined. Based on the predicted IR voltage drop and the maximum instantaneous allowable voltage drop, the predicted IR voltage drop exceedance is determined. Power control of the chip is then performed based on the predicted IR voltage drop exceedance. This approach, through instruction-level analysis, anticipates changes in chip power in advance, rather than passively responding to voltage fluctuations. It enables the generation of optimized power control strategies in advance, proactively adjusting the chip's operating state before current surges cause IR voltage drops. This allows for dynamic suppression of IR voltage drops without altering the hardware design, thereby reducing performance loss caused by IR voltage drops. This embodiment significantly improves voltage stability under high-load transients (such as a sudden increase in GPU power from 300W to 1000W), and is particularly suitable for low-voltage, high-current operating scenarios (such as DVFS 0.7V mode).

[0064] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0065] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0066] Figure 1 This diagram illustrates the connection between the voltage regulation module and the GPU.

[0067] Figure 2 A flowchart illustrating a method for controlling the IR voltage drop of a control chip provided in an embodiment of this disclosure is shown.

[0068] Figure 3 A schematic diagram illustrating a method for controlling the IR voltage drop of a control chip provided in an embodiment of this disclosure is shown.

[0069] Figure 4 A block diagram illustrating an apparatus for the IR voltage drop of a control chip provided in an embodiment of this disclosure is shown.

[0070] Figure 5 This is a block diagram illustrating an apparatus 1900 for controlling the IR voltage drop of a control chip according to an exemplary embodiment. Detailed Implementation

[0071] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0072] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0073] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0074] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0075] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0076] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0077] Figure 1 This diagram illustrates the connection between the voltage regulator module and the GPU. In related technologies, the board-level system employs a closed-loop control method where voltage data collected from voltage sampling points is input to the voltage regulator module (VRM). When the GPU (Graphics Processing Unit) load increases, the current flowing through the voltage regulator module to the GPU die increases. Due to the path resistance (R), according to Ohm's law (ΔV = IR), this leads to an increase in the IR voltage drop, thereby reducing the actual operating voltage at the GPU die. To compensate for the IR voltage drop, the closed-loop feedback mechanism of the voltage regulator module is needed to boost the voltage on the virtual GPU (vGPU) side.

[0078] However, when the GPU power increases from 300W to 1000W in an instant, the voltage provided by the voltage regulation module often needs to be increased accordingly to avoid voltage drop problems caused by IR voltage drop.

[0079] Taking the test data from a certain testing platform as an example, when the voltage output by the voltage regulation module is 941mV and the voltage detected by the voltage sampling point is 900mV, the path resistance R can be calculated as: R = 3.85810092980232408236010384878 × 10 -5 Ω. Based on this, the derivation is as follows: If the operating voltage of the GPU's DVFS (Dynamic Voltage and Frequency Scaling) module drops to 0.7V, while maintaining a power output of 1000W, according to Joule's law P = I... 2 At this point, the power loss on the path resistance will increase to 78.7W, accounting for 7.8% of the total power. Therefore, under constant power conditions, a decrease in operating voltage will lead to an inverse increase in operating current, while the IR voltage drop (ΔV = IR) is directly proportional to the current. Thus, the IR voltage drop effect will be exacerbated under low-voltage conditions.

[0080] Therefore, reducing the path resistance from the GPU die to the voltage regulation module is crucial during chip design. This not only reduces ineffective power loss and improves the GPU's overall energy efficiency but also enhances the stability of the operating voltage. However, once the package and board-level design are complete, this resistance value is essentially fixed and difficult to further optimize using traditional methods.

[0081] To address technical problems similar to those described above, this disclosure provides a method for controlling the IR voltage drop of a chip. By determining the predicted power of the chip based on the information of the chip's instruction to be executed, and then determining the predicted current-resistance IR voltage drop based on the predicted power, the predicted IR voltage drop overshoot of the chip is determined based on the predicted IR voltage drop and the maximum instantaneous allowable voltage drop. Based on the predicted IR voltage drop overshoot, power control is applied to the chip. This method, through instruction-level analysis, anticipates chip power changes in advance, rather than passively responding to voltage fluctuations. It enables the generation of optimized power control strategies in advance, proactively adjusting the chip's operating state before current surges cause IR voltage drops. This allows for dynamic suppression of IR voltage drops without altering the hardware design, thereby reducing performance loss caused by IR voltage drops. This disclosure significantly improves voltage stability under high-load transients (such as a sudden increase in GPU power from 300W to 1000W), and is particularly suitable for low-voltage, high-current operating scenarios (such as DVFS 0.7V mode).

[0082] The method for controlling the IR voltage drop of the control chip provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0083] Figure 2A flowchart illustrating a method for IR voltage drop of a control chip according to an embodiment of this disclosure is provided. In one possible implementation, the execution entity of the method for IR voltage drop of the control chip can be a device for IR voltage drop of the control chip. For example, the method for IR voltage drop of the control chip can be executed by a terminal device, a server, or other electronic equipment. The terminal device can be a user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, in-vehicle device, or wearable device, etc. In some possible implementations, the method for IR voltage drop of the control chip can be implemented by a processor calling computer-readable instructions stored in memory. Figure 2 As shown, the method for controlling the IR voltage drop of the control chip includes steps S21 to S24.

[0084] In step S21, the predicted power of the chip is determined based on the information of the instruction to be executed by the chip.

[0085] In step S22, the predicted current-resistance IR voltage drop of the chip is determined based on the predicted power.

[0086] In step S23, the predicted IR voltage drop of the chip is determined based on the predicted IR voltage drop value and the maximum instantaneous allowable voltage drop.

[0087] In step S24, the chip is power controlled according to the predicted amount of IR voltage drop exceeding the standard.

[0088] In this embodiment of the disclosure, the instruction to be executed may refer to an instruction that has been stored in the chip's instruction cache (I-Cache) but has not yet been processed. The instruction to be executed is updated in real time as the program runs, reflecting the task load that the chip is about to execute.

[0089] The information about the instructions to be executed can represent a set of data describing the characteristics of the instructions. In one possible implementation, the information may include at least some of the following: the number of instructions to be executed, the type of instructions to be executed, and the power level of the instructions to be executed. The number of instructions to be executed may refer to the total number of instructions to be executed in the instruction cache. The type of instructions to be executed may include computation instructions, memory access instructions, control instructions, etc., and is not limited thereto. The power level of the instructions to be executed may represent the weight value of the power impact of different types of instructions to be executed. For example, the power level of a multiplication instruction is higher than that of an addition instruction.

[0090] Information about the instruction to be executed can be used to provide input for power prediction. By quantifying the power characteristics of the instruction to be executed, the basic parameters of the power model can be established.

[0091] In this embodiment of the disclosure, the predicted power can represent the estimated power value of the chip at a future point in time, calculated based on the information of the current instructions to be executed. The predicted power of the chip can be determined based on the information of the instructions to be executed.

[0092] In one possible implementation, determining the predicted power of the chip based on the information of the instructions to be executed by the chip includes: obtaining the type and number of instructions to be executed by the chip; and determining the predicted power of the chip based on the power level corresponding to each type of instruction to be executed and the number of instructions to be executed of each type.

[0093] The type and number of instructions to be executed directly affect the chip's power consumption. In this implementation, the type and number of instructions to be executed can be obtained in real time from the chip's instruction cache. The instruction type reflects the operational complexity (e.g., multiplication instructions consume more power than addition instructions), while the number is directly related to the future load scale. Each instruction type can correspond to a preset power level (weighting coefficient), for example, the power level for multiplication instructions is 5, and the power level for addition instructions is 2. Based on the power level corresponding to each type of instruction to be executed, and the number of instructions of each type, the predicted power of the chip can be determined.

[0094] In one example, a counter can be used to count the number of instructions of various types to be executed in the instruction cache.

[0095] In this implementation, by considering the type of instruction to be executed and its corresponding power level, the power changes of the chip can be predicted more accurately, because the execution of different instructions has significantly different effects on the chip load (e.g., multiplication instructions consume more power than addition instructions). This fine-grained power modeling makes the prediction results closer to the actual operating conditions, thereby dynamically adjusting the chip's operating state before IR voltage drop occurs (e.g., time-sharing control of the execution engine's switching), effectively suppressing voltage fluctuations, and improving the chip's stability and energy efficiency under transient high load or low voltage scenarios.

[0096] In one possible implementation, obtaining the type and number of instructions to be executed by the chip includes: obtaining the type and number of instructions to be executed by each processor execution engine from the instruction cache of each processor execution engine of the chip; and determining the type and number of instructions to be executed by the chip based on the type and number of instructions to be executed by each processor execution engine.

[0097] In one example, the processor execution engine may include MPX (Musa Processor eXecutionengine).

[0098] In this implementation, the information about the instructions to be executed on the chip can be obtained by aggregating the instruction cache data of each processor's execution engine. For example, the type and number of instructions to be executed can be extracted in real time from the instruction cache of each processor's execution engine, and then these scattered data can be integrated into global chip-level instruction statistics. For example, if a chip has 4 MPXs, the instruction queues to be executed in the instruction cache of each MPX can be read separately, and the type distribution and total number of all instructions to be executed can be calculated by combining them, thereby reflecting the overall workload of the chip.

[0099] This implementation method, through distributed acquisition and centralized processing of instructions to be executed, can more comprehensively and accurately reflect the real-time load status of the chip. Since different processor execution engines may process different types of tasks in parallel (e.g., some processor execution engines run high-power computing instructions, while others process low-power control instructions), global aggregation can avoid local sampling bias.

[0100] In one possible implementation, the instruction cache of each processor execution engine is configured with a counter corresponding to each type of instruction to be executed; the counter corresponding to any type of instruction to be executed in the instruction cache of any processor execution engine is used to count the number of instructions of that type to be executed in the instruction cache of the processor execution engine.

[0101] In this implementation, each processor execution engine (such as MPX) of the chip can be configured with an independent counter for different types of instructions to be executed in its instruction cache (such as L1 cache). Each counter can count the number of specific types of instructions to be executed in the current instruction cache in real time, thereby dynamically reflecting the instruction load distribution of each processor execution engine.

[0102] In this implementation, when a certain type of instruction to be executed is prefetched into the instruction cache, its corresponding counter is incremented by 1; when a certain type of instruction to be executed is retrieved from the instruction cache, its corresponding counter is decremented by 1.

[0103] By adopting this implementation method, the number of various types of instructions to be executed in the instruction cache of each processor's execution engine can be accurately counted, providing a data basis for power prediction.

[0104] In another possible implementation, instructions to be executed can be periodically extracted from the pipelines of each processor execution engine and categorized and statistically analyzed to obtain the type and quantity of instructions to be executed for each processor execution engine. This implementation allows for real-time monitoring of instruction load without increasing the overhead of dedicated counter hardware.

[0105] In one possible implementation, determining the predicted power of the chip based on the power level corresponding to each type of instruction to be executed and the number of instructions to be executed of each type includes: determining the instruction weighting coefficient of the chip based on the power level corresponding to each type of instruction to be executed and the number of instructions to be executed of each type; and determining the predicted power of the chip based on the real-time operating parameters of the chip and the instruction weighting coefficient.

[0106] In this implementation, a comprehensive instruction weight coefficient (C1) can be calculated by analyzing the distribution of instruction types and their corresponding power levels, combined with the number of instructions of each type. This coefficient is used to quantify the overall impact of the current instruction on the chip power. For example, the instruction weight coefficient C1 = ∑(α_n × N_n), where α_n represents the weight corresponding to the power level of the nth instruction and N_n represents the number of the nth instruction.

[0107] After calculating the instruction weighting coefficients of the chip, the predicted power of the chip can be determined by combining the chip's real-time operating parameters. These real-time operating parameters refer to the dynamic state variables of the chip during operation that directly affect its power and performance.

[0108] This implementation improves the accuracy of power prediction by combining information about the chip's instructions to be executed with information about the chip's dynamic operating environment (real-time operating parameters). By using power levels, the system can differentiate the varying power contributions of different types of instructions to be executed (e.g., identifying sudden loads from computationally intensive instructions), while the introduction of real-time operating parameters captures the actual impact of dynamic factors on chip power. This prediction method is particularly suitable for handling sudden load changes in chips such as GPUs, and can generate optimized throttling strategies in advance (e.g., dynamically adjusting clock gating) to proactively stabilize the voltage before IR drop occurs. Compared to traditional passive response schemes based on historical power consumption, this method more effectively reduces performance loss and energy waste.

[0109] In one possible implementation, the real-time operating parameters include at least a portion of real-time operating voltage, real-time operating frequency, real-time current, and real-time temperature coefficient.

[0110] In this implementation, the chip's real-time operating voltage refers to the actual supply voltage currently received by the chip. The chip's real-time operating voltage can fluctuate dynamically with changes in load. Under DVFS technology, the chip's real-time operating voltage directly affects its computing performance and power consumption. Increasing the voltage can improve operating speed but increase energy consumption, while decreasing the voltage has the opposite effect. IR drop issues can cause the actual operating voltage to fall below the set value; therefore, real-time monitoring is crucial for power control.

[0111] A chip's real-time operating frequency represents its current clock frequency, determining the instruction execution speed. A chip's power consumption is positively correlated with its operating frequency; while higher frequencies increase computing power, they also significantly increase dynamic power consumption. Since the power consumption of the same instruction can vary greatly at different operating frequencies, combining real-time operating frequency with power prediction can improve the accuracy of power forecasting.

[0112] The real-time current of a chip reflects the total current it is currently drawing from the power supply, and is directly related to ohmic losses (P=IV) and IR voltage drop (ΔV=IR). High current operation will exacerbate the heating of path resistance and voltage loss. By monitoring the real-time current, the risk of IR voltage drop can be predicted, especially for low-voltage high-current scenarios (such as 0.7V DVFS mode), which has an early warning function.

[0113] The real-time temperature coefficient of a chip can be used to quantify the impact of chip temperature on chip power correction. High temperatures lead to increased leakage current and changes in transistor on-resistance, thereby raising the quiescent power. Real-time temperature systems, obtained through temperature sensors or electrothermal models, can correct for additional losses caused by temperature rise in predicted power.

[0114] In one example, the predicted power of the chip can be P1 = C1 × V. 2 ×f+V×I×temp. Where C1 can represent the command weighting coefficient, V can represent the real-time operating voltage, f can represent the real-time operating frequency, I can represent the real-time current, and temp can represent the real-time temperature coefficient.

[0115] By integrating these real-time operating parameters, a more accurate dynamic mapping relationship between power, instruction load, and environmental conditions can be established. Compared to predictions that rely solely on instruction characteristics, this approach can capture the impact of actual operating conditions such as voltage regulation delay, frequency switching transients, and temperature drift, making the IR drop control strategy more environmentally adaptable, especially suitable for high-performance chips such as GPUs that have stringent voltage stability requirements.

[0116] In this embodiment of the disclosure, after determining the predicted power of the chip, the predicted IR voltage drop of the chip can be calculated based on the predicted power of the chip.

[0117] In one possible implementation, determining the predicted current-resistance IR voltage drop of the chip based on the predicted power includes: determining the predicted power change of the chip based on the difference between the predicted power and the current power of the chip; and determining the predicted IR voltage drop of the chip based on the predicted power change, the real-time operating voltage of the chip, and the path resistance from the voltage regulation module to the chip.

[0118] In this implementation, the difference between the chip's predicted power and its current power can be calculated to obtain the predicted power change Δp1. The predicted power change Δp1 reflects the intensity of the load change.

[0119] In one example, the predicted IR voltage drop of the chip is ΔV1 = |Δp1| / V×R. Here, V represents the chip's real-time operating voltage, and R represents the path resistance from the voltage regulation module to the chip.

[0120] This approach dynamically integrates predicted power, current power, real-time operating voltage, and path resistance parameters to quantify IR voltage drop risks in advance. This allows the system to proactively take throttling measures before a sudden current change causes an actual voltage drop. Compared to traditional passive response voltage regulation, this significantly improves the chip's voltage stability under transient high loads (such as a sudden increase in GPU power from 300W to 1000W) or low-voltage operating modes (such as 0.7V DVFS). At the same time, it avoids the hardware modification costs associated with reducing path resistance, achieving the technical effect of suppressing IR voltage drop through algorithm optimization without changing the physical design.

[0121] In this embodiment, the predicted IR drop value ΔV1 of the chip can be compared with the maximum instantaneous allowable voltage drop ΔV2 set by the system. The difference (V3 = ΔV1 - ΔV2) is used to calculate the predicted IR drop exceedance of the chip. The maximum instantaneous allowable voltage drop refers to the maximum voltage drop threshold that the chip can withstand under transient operating conditions; exceeding this value will lead to degraded circuit performance or malfunction. The maximum instantaneous allowable voltage drop can be determined by the adjustment capability of the voltage regulation module, system stability requirements, etc., and is not limited here. The predicted IR drop exceedance refers to the deviation of the predicted IR drop value during chip operation from the maximum allowable instantaneous voltage drop threshold of the system, and can be used to characterize the degree of risk to voltage stability.

[0122] In this embodiment, the chip's power control strategy can be dynamically adjusted based on the predicted IR drop exceedance. In one possible implementation, when the predicted IR drop exceedance is greater than 0, it can be understood as the voltage drop that needs to be compensated. If the predicted IR drop exceedance is less than or equal to 0, the current state can be considered safe and no intervention is required.

[0123] In one possible implementation, the step of power control of the chip based on the predicted IR drop exceedance includes: determining power control parameters of the chip based on the predicted IR drop exceedance; and performing power control on the chip based on the power control parameters.

[0124] In this implementation, the predicted IR voltage drop can be used as input to dynamically generate appropriate power control parameters (such as throttling level, frequency adjustment range, etc.).

[0125] As an example of this implementation, the required power reduction and execution strategy (such as shutting down some execution engines or inserting empty instruction cycles) can be calculated using a preset algorithm based on the magnitude and / or trend of the predicted IR voltage drop exceeding the standard. These parameters are then sent to the chip's power management unit in real time to achieve precise adjustment of the workload, thereby keeping the IR voltage drop within a safe range.

[0126] This implementation method can actively suppress the risk of excessive IR voltage drop by dynamically adjusting the chip power control parameters. It can make precise interventions before the IR voltage drop actually occurs, which not only avoids the time delay problem of traditional passive adjustment methods, but also reduces performance loss while improving voltage stability.

[0127] In one possible implementation, determining the power control parameters of the chip based on the predicted IR drop exceedance includes: inputting the predicted IR drop exceedance into a preset proportional-integral-derivative (PID) controller, and outputting the power control parameters of the chip through the PID controller.

[0128] In this implementation, the predicted IR voltage drop can be input into a PID (Proportional-Integral-Derivative) controller. By combining the calculations of the three control links (proportional, integral, and derivative), appropriate power control parameters can be dynamically generated.

[0129] In this implementation, the PID control method achieves precise suppression of IR voltage drop through multi-dimensional dynamic adjustment. Proportional control ensures rapid response to instantaneous voltage drop, integral control eliminates steady-state error, and derivative control prevents future fluctuations. The three work together to improve voltage stability while optimizing energy efficiency. Compared with fixed threshold control strategies, it has better dynamic adaptability and control accuracy, and is particularly suitable for handling complex voltage drop problems of chips such as GPUs under sudden loads.

[0130] In this implementation, the power control parameters can be throttling level, throttling ratio, power level, power percentage, etc., and are not limited here.

[0131] In one possible implementation, the step of power control of the chip according to the power control parameters includes: generating a clock gating sequence corresponding to each processor execution engine in the chip according to the power control parameters; and controlling the clock gating operation of each processor execution engine according to the clock gating sequence corresponding to each processor execution engine, wherein at least one processor execution engine is kept on in each clock cycle.

[0132] In this implementation, the power control parameters reflect the required power reduction level. Based on these parameters, clock gating sequences corresponding to each processor execution engine within the chip can be generated. Different processor execution engines can correspond to different clock gating sequences.

[0133] Clock gating sequences can be dynamically generated periodic control signal sequences for each processor execution engine, used to turn their clock signals on or off according to predetermined rules. The clock gating sequence for each processor execution engine can stagger the shutdown timing through a cyclic right shift or polling strategy (e.g., MPX0 is turned off in the first clock cycle, MPX1 is turned off in the second clock cycle), ensuring that only a portion of the processor execution engines' clocks are turned off in each clock cycle (at least one processor execution engine remains running), thereby evenly distributing the power load and suppressing IR voltage drops caused by transient current surges.

[0134] In one possible implementation, when the power control parameters indicate a non-maximum power operating mode, the clock gating sequence corresponding to each processor execution engine is used to control each processor execution engine to turn off its clock in turn during different clock cycles.

[0135] In this implementation, when the chip needs to reduce power consumption (non-maximum power mode), the clock of each processor execution engine is turned off in turn according to the clock gating sequence corresponding to each processor execution engine.

[0136] For example, a chip has four processor execution engines (MPX0 to MPX3). When it is determined that the power needs to be reduced by 25% based on the predicted amount of IR voltage drop exceeding the limit, a "3 on, 1 off" cyclic mode can be adopted. The clock of one processor execution engine is turned off every clock cycle, and the clocks of each processor execution engine are turned off in turn. For example, MPX0 is turned off in the first clock cycle, MPX1 in the second clock cycle, MPX2 in the third clock cycle, MPX3 in the fourth clock cycle, and MPX0 in the fifth clock cycle, and so on. In this example, three processor execution engines remain running in each clock cycle (e.g., in cycle 1: MPX1 / 2 / 3 are working). The turned-off processor execution engines achieve zero dynamic power consumption through clock gating, but because they are not completely powered off, they can be woken up immediately in the next clock cycle. Compared to the static solution of directly turning off one processor execution engine, this cyclic method distributes the 25% power reduction evenly across all processor execution engines, avoiding load imbalance and instantaneous current fluctuations caused by the long-term shutdown of a single processor execution engine.

[0137] For example, for a chip with eight processor execution engines (MPX0 to MPX7), when a 50% power reduction is needed, a grouped clock gating sequence can be generated: the MPXs are divided into group A (MPX0-3) and group B (MPX4-7), and one group is alternately shut down each clock cycle (e.g., group A is shut down in clock cycle 1, group B is shut down in clock cycle 2), ensuring that four MPXs are always running. This grouped round-robin method can reduce peak current by 50% to suppress IR voltage drop, maintain 50% parallel computing power, and avoid local overheating. If further energy saving (e.g., a 75% reduction) is required, it can be switched to "2 on, 6 off," dynamically adjusting the balance between power consumption and performance.

[0138] The method for controlling the IR voltage drop of a control chip provided in this disclosure can be applied to the fields of chip, chip control and other technical fields, and is not limited thereto.

[0139] The following describes the method for controlling the IR voltage drop of the control chip provided in this embodiment through a specific application scenario. Figure 3 A schematic diagram illustrating a method for controlling the IR voltage drop of a control chip provided in an embodiment of this disclosure is shown.

[0140] exist Figure 3 In the example shown, the chip includes N processor execution engines (MPX 0 to N-1) and their instruction caches. The types and quantities of instructions to be executed from each of the N processor execution engines can be read from the N instruction caches, and the data for each type of instruction to be executed can be statistically obtained. The instruction weighting coefficient C1 of the chip can be determined based on the power level corresponding to each type of instruction to be executed and the quantity of each type of instruction to be executed.

[0141] The power prediction module can be based on P1 = C1 × V 2 The predicted power of the chip is calculated as ×f + V × I × temp. Here, V represents the real-time operating voltage, f represents the real-time operating frequency, I represents the real-time current, and temp represents the real-time temperature coefficient. I can include both dynamic current and leakage current. The real-time temperature coefficient can be obtained through the PVT (Process-Voltage-Temperature) monitoring module.

[0142] The power throttling controller can calculate the difference between the chip's predicted power P1 and its current power, obtaining the predicted power change Δp1. The predicted IR voltage drop of the chip can then be calculated using ΔV1 = |Δp1| / V × R, where V represents the chip's real-time operating voltage and R represents the path resistance from the voltage regulation module to the chip.

[0143] The predicted IR drop of the chip, ΔV1, can be compared with the maximum instantaneous allowable IR drop, ΔV2, set by the system. The difference (V3 = ΔV1 - ΔV2) is used to calculate the predicted IR drop exceedance. The predicted IR drop exceedance, V3, can be input to a PID controller to generate power control parameters. The time-sharing control module can generate clock gating sequences corresponding to MPX 0 to N-1 based on the power control parameters, and control the clock gating operations of MPX 0 to N-1 respectively according to these sequences. At least one processor execution engine's clock is kept on in each clock cycle.

[0144] It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0145] In addition, this disclosure also provides an apparatus for IR voltage drop of a control chip, a non-volatile computer-readable storage medium, and a computer program product. All of the above can be used to implement the method for IR voltage drop of any control chip provided in this disclosure. The corresponding technical solutions and technical effects can be found in the corresponding descriptions in the method section, and will not be repeated here.

[0146] Figure 4 A block diagram illustrating an apparatus for the IR voltage drop of a control chip provided in an embodiment of this disclosure is shown. Figure 4 As shown, the device for controlling the IR voltage drop of the control chip includes:

[0147] The prediction module 41 is used to determine the predicted power of the chip based on the information of the instruction to be executed by the chip.

[0148] The first determining module 42 is used to determine the predicted current-resistance IR voltage drop value of the chip based on the predicted power.

[0149] The second determining module 43 is used to determine the predicted amount of IR voltage drop exceeding the limit of the chip based on the predicted IR voltage drop value and the maximum instantaneous allowable voltage drop.

[0150] The control module 44 is used to control the power of the chip based on the predicted amount of IR voltage drop exceeding the standard.

[0151] In one possible implementation, the prediction module 41 is used for:

[0152] Obtain the type and number of instructions to be executed from the chip;

[0153] The predicted power of the chip is determined based on the power level corresponding to each type of instruction to be executed and the number of instructions to be executed for each type.

[0154] In one possible implementation, the prediction module 41 is used for:

[0155] Obtain the type and number of instructions to be executed from the instruction cache of each processor execution engine of the chip;

[0156] The type and number of instructions to be executed by the chip are determined based on the type and number of instructions to be executed by each processor execution engine.

[0157] In one possible implementation, the instruction cache of each processor execution engine is configured with a counter corresponding to each type of instruction to be executed; the counter corresponding to any type of instruction to be executed in the instruction cache of any processor execution engine is used to count the number of instructions of that type to be executed in the instruction cache of the processor execution engine.

[0158] In one possible implementation, the prediction module 41 is used for:

[0159] The instruction weighting coefficient of the chip is determined based on the power level corresponding to each type of instruction to be executed and the number of instructions to be executed of each type.

[0160] The predicted power of the chip is determined based on the chip's real-time operating parameters and the instruction weighting coefficient.

[0161] In one possible implementation, the real-time operating parameters include at least a portion of real-time operating voltage, real-time operating frequency, real-time current, and real-time temperature coefficient.

[0162] In one possible implementation, the first determining module 42 is used to:

[0163] The predicted power change of the chip is determined based on the difference between the predicted power and the current power of the chip.

[0164] The predicted IR drop value of the chip is determined based on the predicted power change, the chip's real-time operating voltage, and the path resistance from the voltage regulation module to the chip.

[0165] In one possible implementation, the control module 44 is used for:

[0166] Based on the predicted amount of IR voltage drop exceeding the standard, the power control parameters of the chip are determined;

[0167] The chip is powered according to the power control parameters.

[0168] In one possible implementation, the control module 44 is used for:

[0169] The predicted value of the IR voltage drop exceeding the standard is input into a preset proportional-integral-derivative PID controller, and the power control parameters of the chip are output through the PID controller.

[0170] In one possible implementation, the control module 44 is used for:

[0171] Based on the power control parameters, a clock gating sequence corresponding to each processor execution engine in the chip is generated;

[0172] Based on the clock gating sequence corresponding to each processor execution engine, the clock gating operation of each processor execution engine is controlled, wherein at least one processor execution engine is kept on clock in each clock cycle.

[0173] In one possible implementation, when the power control parameters indicate a non-maximum power operating mode, the clock gating sequence corresponding to each processor execution engine is used to control each processor execution engine to turn off its clock in turn during different clock cycles.

[0174] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation and technical effects can be referred to the description of the above method embodiments. For the sake of brevity, they will not be repeated here.

[0175] This disclosure also provides an apparatus for controlling the IR voltage drop of a chip, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0176] This disclosure also provides a non-volatile computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described method.

[0177] This disclosure also provides a computer program product, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above method.

[0178] Figure 5 This is a block diagram illustrating an apparatus 1900 for controlling the IR voltage drop of a control chip according to an exemplary embodiment. For example, apparatus 1900 may be provided as a server or terminal device. (Refer to...) Figure 5 The apparatus 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0179] Device 1900 may also include a power supply component 1926 configured to perform power management of device 1900, a wired or wireless network interface 1950 configured to connect device 1900 to a network, and an input / output interface 1958 (I / O interface). Device 1900 can operate on an operating system, such as Windows Server, stored in memory 1932. TM macOS X TM Unix TM Linux TM FreeBSD TM Or similar.

[0180] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of the device 1900 to perform the above-described method.

[0181] Computer-readable storage media can be tangible devices capable of holding and storing programs / instructions used by instruction execution devices. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0182] The computer program (or computer-readable program instructions) described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage medium in the respective computing / processing device.

[0183] The computer program (or computer program instructions) used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits, such as programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), are personalized by utilizing state information of computer-readable program instructions. These electronic circuits can execute computer-readable program instructions to implement various aspects of this disclosure.

[0184] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0185] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0186] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0187] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0188] Computer program products can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0189] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0190] If the technical solution of this disclosure involves personal information, the product applying the technical solution of this disclosure has clearly informed the user of the personal information processing rules and obtained the user's voluntary consent before processing the personal information. If the technical solution of this disclosure involves sensitive personal information, the product applying the technical solution of this disclosure has obtained the user's separate consent before processing the sensitive personal information, and also meets the requirement of "express consent". For example, at personal information collection devices such as cameras, clear and prominent signs are set up to indicate that the user has entered the scope of personal information collection and that personal information will be collected. If the user voluntarily enters the collection scope, it is deemed to have consented to the collection of their personal information; or on the personal information processing device, with clear signs / information informing the user of the personal information processing rules, authorization is obtained from the user through pop-up information or by asking the user to upload their personal information; wherein, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the types of personal information processed.

[0191] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method of controlling IR drop of a chip, the method comprising: The method comprises the following steps: determining a predicted power of the chip according to information of instructions to be executed by the chip; determining an IR drop prediction value of the chip according to the predicted power, a current power of the chip, a real-time working voltage of the chip, and a path resistance from a voltage regulation module to the chip; determining an IR drop overproof prediction value of the chip according to the IR drop prediction value and a maximum instantaneous allowable voltage drop; controlling the power of the chip according to the IR drop overproof prediction value.

2. The method of claim 1, wherein, The method of determining the predicted power of the chip according to the information of instructions to be executed by the chip comprises the following steps: obtaining the type and quantity of instructions to be executed by the chip; determining the predicted power of the chip according to the power level corresponding to each type of instructions to be executed and the quantity of each type of instructions to be executed.

3. The method of claim 2, wherein, The method of obtaining the type and quantity of instructions to be executed by the chip comprises the following steps: obtaining the type and quantity of instructions to be executed by each processor execution engine of the chip from the instruction cache of each processor execution engine of the chip; determining the type and quantity of instructions to be executed by the chip according to the type and quantity of instructions to be executed by each processor execution engine.

4. The method of claim 3, wherein, The instruction cache of each processor execution engine is respectively configured with a counter corresponding to each type of instructions to be executed; the counter corresponding to any type of instructions to be executed in the instruction cache of any processor execution engine is used to count the quantity of instructions to be executed of the type in the instruction cache of the processor execution engine.

5. The method of claim 2, wherein, The method of determining the predicted power of the chip according to the power level corresponding to each type of instructions to be executed and the quantity of each type of instructions to be executed comprises the following steps: determining an instruction weight coefficient of the chip according to the power level corresponding to each type of instructions to be executed and the quantity of each type of instructions to be executed; determining the predicted power of the chip according to the real-time working parameter of the chip and the instruction weight coefficient.

6. The method of claim 5, wherein, The real-time working parameter comprises at least part of a real-time working voltage, a real-time working frequency, a real-time current, and a real-time temperature coefficient.

7. The method of claim 1, wherein, The method of determining the IR drop prediction value of the chip according to the predicted power, the current power of the chip, the real-time working voltage of the chip, and the path resistance from the voltage regulation module to the chip comprises the following steps: determining a predicted power change amount of the chip according to the difference between the predicted power and the current power of the chip; determining the IR drop prediction value of the chip according to the predicted power change amount, the real-time working voltage of the chip, and the path resistance from the voltage regulation module to the chip.

8. The method of claim 1, wherein, The method of controlling the power of the chip according to the IR drop overproof prediction value comprises the following steps: determining a power control parameter of the chip according to the IR drop overproof prediction value; controlling the power of the chip according to the power control parameter.

9. The method of claim 8, wherein, The method of determining the power control parameter of the chip according to the IR drop overproof prediction value comprises the following steps: inputting the IR drop overproof prediction value into a preset proportional-integral-derivative (PID) controller, and outputting the power control parameter of the chip through the PID controller.

10. The method of claim 8, wherein, The power control on the chip according to the power control parameter comprises: generating a clock gating sequence corresponding to each processor execution engine in the chip according to the power control parameter; controlling clock gating operation of the processor execution engine according to the clock gating sequence corresponding to each processor execution engine, wherein at least one processor execution engine is clocked on in each clock cycle.

11. The method of claim 10, wherein, In the case that the power control parameter indicates a non-highest power working mode, the clock gating sequence corresponding to each processor execution engine is used to control the processor execution engine to be clocked off in different clock cycles in turn.

12. An apparatus for controlling IR drop of a chip, the apparatus comprising: The method comprises: a prediction module configured to determine a predicted power of the chip according to information of instructions to be executed by the chip; a first determination module configured to determine an IR drop prediction value of the chip according to the predicted power, a current power of the chip, a real-time working voltage of the chip, and a path resistance from the voltage adjustment module to the chip; a second determination module configured to determine an IR drop exceeding prediction of the chip according to the IR drop prediction value and a maximum instantaneous allowable IR drop; a control module configured to control power of the chip according to the IR drop exceeding prediction.

13. A device for controlling the IR voltage drop of a chip, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method in any one of claims 1 to 11.

14. A non-transitory computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 11.

15. A computer program product comprising a computer program or a non-transitory computer readable storage medium bearing a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 11.

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