Electromagnetic modeling method and system for chip packaging power supply network

Abstract

The invention relates to the technical field of packaging, and discloses a chip packaging power network electromagnetic modeling method and system, and the method comprises the steps: dividing chip packaging into three sub-regions: a chip-level conductive layer, the thickness of a concerned metal layer, the width of a power line, the device spacing, and the size of a through hole; an intermediate layer conducting layer, wherein the depth-to-width ratio of the silicon through hole, the diameter of the micro bump and the spacing ratio are concerned; according to the substrate-level conducting layer, the power line width ratio, the via hole density, the via hole pitch ratio and the substrate depth-to-width ratio are concerned, extracted geometric parameters are subjected to standardization processing, the dimensional influence is eliminated, a quantitative evaluation model is constructed for each sub-region, a layout coefficient is calculated through a mathematical formula, and the design quality is measured; and comparing the comprehensive modeling index coefficient of each sub-region with a preset threshold value, judging whether optimization is needed or not, and if not, adjusting modeling parameters and recalculating until performance requirements are met.

Description

Technical Field

[0001] The present invention relates to the field of packaging technology, and in particular to a chip packaging power supply network electromagnetic modeling method and system. Background Art

[0002] Chip packaging is a key link in connecting semiconductor chips (Die) to external circuits and achieving physical protection. It directly affects the chip's electrical performance, heat dissipation capacity and reliability. As chips develop towards high integration and high frequency, the electromagnetic characteristics of the chip packaging power network are becoming increasingly complex.

[0003] Most existing electromagnetic modeling methods for chip package power networks have the following problems: 1. Most of them are based on simplified equivalent circuit models to process package power networks with complex three-dimensional structures. The modeling process is time-consuming and difficult to adapt to the rapidly iterative chip design process; 2. Existing methods analyze each level in isolation, resulting in conflicts between local optimization and global goals. Therefore, the present invention provides a method and system for electromagnetic modeling of chip package power networks. Summary of the Invention

[0004] The purpose of the present invention is to provide a chip packaging power supply network electromagnetic modeling method and system to solve the above technical problems.

[0005] A chip packaging power supply network electromagnetic modeling method, the method comprising the following steps:

[0006] Step S1: Scan the chip package power network using a scanning device or extract data required for the modeling process from the design file;

[0007] Step S2: Divide the power network into chip-level conductive layer, interposer-level conductive layer, and substrate-level conductive layer sub-regions;

[0008] Step S3: extracting characteristic parameters of each sub-region respectively and normalizing the parameters;

[0009] Step S4: Analyze the characteristic parameters of each sub-region to evaluate whether the modeling structure of the current sub-region needs to be optimized;

[0010] Step S5: Evaluate the optimized modeling schemes for each sub-region, and determine whether they meet the performance requirements based on the evaluation results. If they do, output the final modeling scheme; if they do not, adjust the modeling based on the evaluation results until a modeling scheme that meets the requirements is obtained.

[0011] As a further description of the technical solution of the present invention, the working process of step S3 includes:

[0012] According to modeling requirements, the chip-level conductive layer is divided into n sub-regions, and each region is numbered in the order of: 1, 2, ..., n;

[0013] Obtain the characteristic parameters of the i-th sub-region including: metal layer thickness D i , Power line width L i , device spacing d i , through hole size R i and through-hole pitch P i , where i belongs to n.

[0014] As a further description of the technical solution of the present invention, the working process of step S4 includes:

[0015] Construct the calculation model of the modeling index coefficient of the i-th sub-region, and the expression is:

[0016]

[0017] Where α, β, and γ are the weight coefficients of power line width, device spacing, and through-hole size, respectively; δ is the influence coefficient of metal layer thickness; and D i0 is the reference data of metal layer width, P0 is the reference data of through-hole spacing, and i belongs to [1, n], ρ i is the modeling index coefficient of the i-th sub-region.

[0018] As a further description of the technical solution of the present invention, the working process of step S3 further includes:

[0019] According to modeling requirements, the intermediate layer conductive layer is divided into m sub-regions, and each region is numbered in the order of: 1, 2, ..., m;

[0020] The characteristic parameters of the jth sub-region are obtained including: TSV aspect ratio A j , micro bump diameter B j and the ratio of the center distance of the micro-bump to its diameter C j Among them, j belongs to m.

[0021] As a further description of the technical solution of the present invention, the working process of step S4 also includes:

[0022] Construct the calculation model of the modeling index coefficient of the j-th sub-region, and the expression is:

[0023]

[0024] Where a, b, and c are weight coefficients corresponding to the aspect ratio of the through-silicon via, the diameter of the microbump, and the ratio of the center-to-center spacing of the microbump to its diameter, respectively. k is a conversion constant. By fitting experimental or simulation data, the combination of various dimensionless parameters is mapped to a numerical range of practical engineering significance, and j belongs to [1, m]. σ j is the modeling index coefficient of the j-th sub-region.

[0025] As a further description of the technical solution of the present invention, the working process of step S3 further includes:

[0026] According to modeling requirements, the substrate-level conductive layer is divided into y sub-regions, and each region is numbered in the order of: 1, 2, ..., y;

[0027] Obtain the characteristic parameters of the xth sub-area including: power line width ratio W x , via density E x , via spacing ratio T x and substrate aspect ratio O x , where x belongs to y.

[0028] As a further description of the technical solution of the present invention, the working process of step S4 also includes:

[0029] Construct the calculation model of the modeling index coefficient of the x-th sub-region, the expression is:

[0030]

[0031] Where ω1, ω2, ω3 and ω4 are the weight coefficients corresponding to the power line width ratio, via density, via pitch ratio and substrate aspect ratio, respectively. θ is the conversion constant. Through fitting of experimental or simulation data, the combination of various dimensionless parameters is mapped to the numerical range of practical engineering significance. T x0 Set the reference value of the via pitch ratio for the system, x belongs to y, τ x is the modeling index coefficient of the x-th sub-region.

[0032] As a further description of the technical solution of the present invention, the working process of step S4 also includes:

[0033] The comprehensive modeling index coefficient of the chip-level conductive layer is obtained by weighted summing of the modeling index coefficients of the n sub-regions of the chip-level conductive layer, the comprehensive modeling index coefficient of the interposer-level conductive layer is obtained by weighted summing of the modeling index coefficients of the m sub-regions of the interposer-level conductive layer, and the comprehensive modeling index coefficient of the substrate-level conductive layer is obtained by weighted summing of the modeling index coefficients of the y sub-regions of the substrate-level conductive layer;

[0034] The comprehensive modeling index coefficients of the chip-level conductive layer, the intermediate layer-level conductive layer and the substrate-level conductive layer are compared with the corresponding threshold intervals set by the system. If any one of them does not belong to the corresponding threshold interval, it means that the modeling structure of the conductive layer in the current sub-region needs to be optimized.

[0035] As a further description of the technical solution of the present invention, the working process of step S5 includes:

[0036] Obtain the performance parameters of the current modeling scheme and construct a calculation model for the performance index coefficient of the current modeling scheme. The expression is:

[0037]

[0038] Where, ∈ is the number of performance parameters, ε belongs to ∈, is the εth performance parameter value,

[0039] is the reference value of the εth performance parameter set for the system, is the weight coefficient of the εth performance parameter, is the performance index coefficient of the modeling scheme;

[0040] Will Compared with the threshold set by the system, if If the value is greater than or equal to the threshold set by the system, it means that the current modeling scheme meets the requirements and the current modeling scheme is output. If it is lower than the threshold set by the system, it means that the current modeling scheme does not meet the requirements and needs to be further adjusted.

[0041] A chip package power supply network electromagnetic modeling system is provided, and the system is used to implement a chip package power supply network electromagnetic modeling method.

[0042] Beneficial effects of the present invention:

[0043] The present invention divides chip packaging into three sub-areas: chip-level conductive layer: focusing on metal layer thickness, power line width, device spacing, and through-hole size; intermediate layer-level conductive layer: focusing on silicon via aspect ratio, micro-bump diameter, and spacing ratio; substrate-level conductive layer: analyzing power line width ratio, via density, via spacing ratio, and substrate aspect ratio, standardizing the extracted geometric parameters to eliminate dimensional influence, constructing a quantitative evaluation model for each sub-area, calculating the layout coefficient through mathematical formulas to measure the design quality, and comparing the comprehensive modeling index coefficient of each sub-area with a preset threshold to determine whether optimization is needed. If it does not meet the standard, the modeling parameters are adjusted and recalculated until the performance requirements are met, which significantly improves the accuracy of electromagnetic characteristic prediction, and is particularly suitable for high-frequency and three-dimensional complex structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The present invention will be further described below with reference to the accompanying drawings.

[0045] Figure 1 It is a partial flow chart of the chip packaging power supply network electromagnetic modeling method provided by the present invention. DETAILED DESCRIPTION

[0046] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0047] See also Figure 1 As shown, the present invention is a chip packaging power supply network electromagnetic modeling method, the method comprising the following steps:

[0048] Step S1: Scan the chip package power network using a scanning device or extract data required for the modeling process from the design file;

[0049] Step S2: Divide the power network into chip-level conductive layer, interposer-level conductive layer, and substrate-level conductive layer sub-regions;

[0050] Step S3: extracting characteristic parameters of each sub-region respectively and normalizing the parameters;

[0051] Step S4: Analyze the characteristic parameters of each sub-region to evaluate whether the modeling structure of the current sub-region needs to be optimized;

[0052] Step S5: Evaluate the optimized modeling schemes for each sub-region, and determine whether they meet the performance requirements based on the evaluation results. If they do, output the final modeling scheme; if they do not, adjust the modeling based on the evaluation results until a modeling scheme that meets the requirements is obtained.

[0053] Through the above technical solution, the chip package is divided into three sub-areas: chip-level conductive layer: focus on metal layer thickness, power line width, device spacing, and through-hole size; interposer-level conductive layer: focus on silicon hole aspect ratio, micro-bump diameter, and spacing ratio; substrate-level conductive layer: analyze power line width ratio, via density, via spacing ratio, and substrate aspect ratio, standardize the extracted geometric parameters, eliminate dimensional influence, and construct a quantitative evaluation model for each sub-area. The layout coefficient is calculated by mathematical formula to measure the design quality. The comprehensive modeling index coefficient (weighted sum) of each sub-area is compared with the preset threshold to determine whether optimization is needed. If it does not meet the standard, adjust the modeling parameters (such as increasing via density, optimizing line width) and recalculate until the performance requirements are met.

[0054] As a further description of the technical solution of the present invention, the working process of step S3 includes:

[0055] According to modeling requirements, the chip-level conductive layer is divided into n sub-regions, and each region is numbered in the order of: 1, 2, ..., n;

[0056] Obtain the characteristic parameters of the i-th sub-region including: metal layer thickness D i , Power line width L i , device spacing d i , through hole size R i and through-hole pitch P i , where i belongs to n.

[0057] Power line width, the width of the power line in the current sub-area, the larger the better; device spacing, the center distance between adjacent devices / traces, the closer to the reference value, the better; through-hole size, the through-hole diameter, the larger the better; metal layer thickness, the conductive layer thickness, the closer to the reference value, the better; through-hole spacing, the ratio of through-hole center spacing to diameter, the closer to the reference value, the better.

[0058] As a further description of the technical solution of the present invention, the working process of step S4 includes:

[0059] Construct the calculation model of the modeling index coefficient of the i-th sub-region, and the expression is:

[0060]

[0061] Where α, β, and γ are the weight coefficients of power line width, device spacing, and through-hole size, respectively; δ is the influence coefficient of metal layer thickness; and D i0 is the reference data of metal layer width, P0 is the reference data of through-hole spacing, and i belongs to [1, n], ρ i is the modeling index coefficient of the i-th sub-region.

[0062] Through the above technical solution, this embodiment involves a modeling index coefficient calculation model for the chip-level conductive layer sub-region. Its core working principle is to quantitatively evaluate the modeling optimization degree of the chip-level conductive layer through parametric modeling to guide the optimization of the electromagnetic performance of the power supply network. Specifically, for the i-th sub-region of the chip-level conductive layer, the following characteristic parameters are extracted: the metal layer thickness D i , Power line width L i , device spacing d i , through hole size R i and through-hole pitch P i , using a nonlinear weighted formula

[0063] Calculate the degree of optimization of the sub-region.

[0064] As a further description of the technical solution of the present invention, the working process of step S3 further includes:

[0065] According to modeling requirements, the intermediate layer conductive layer is divided into m sub-regions, and each region is numbered in the order of: 1, 2, ..., m;

[0066] The characteristic parameters of the jth sub-region are obtained including: TSV aspect ratio A j , micro bump diameter B j and the ratio of the center distance of the micro-bump to its diameter C j Among them, j belongs to m.

[0067] The aspect ratio of the through-silicon via reflects the process difficulty parameter, the diameter of the micro-bump affects the current carrying capacity and mechanical reliability, and the ratio of the center spacing of the micro-bumps to their diameter determines the wiring density and crosstalk.

[0068] As a further description of the technical solution of the present invention, the working process of step S4 also includes:

[0069] Construct the calculation model of the modeling index coefficient of the j-th sub-region, and the expression is:

[0070]

[0071] Where a, b, and c are weight coefficients corresponding to the aspect ratio of the through-silicon via, the diameter of the microbump, and the ratio of the center-to-center spacing of the microbump to its diameter, respectively. k is a conversion constant. By fitting experimental or simulation data, the combination of various dimensionless parameters is mapped to a numerical range of practical engineering significance, and j belongs to [1, m]. σ j is the modeling index coefficient of the j-th sub-region.

[0072] Through the above working method, this embodiment involves a modeling index coefficient calculation model for the sub-region of the intermediate-level conductive layer. Its core working principle is to quantitatively evaluate the modeling optimization degree of the intermediate-level conductive layer (such as the silicon intermediate layer or the interconnect structure in the 2.5D package) through parameterized modeling to optimize power integrity and signal integrity. For the j-th sub-region of the intermediate-level conductive layer, the following characteristic parameters are extracted: the aspect ratio of the silicon via A j , micro bump diameter B j and the ratio of the center distance of the micro-bump to its diameter C j , using the nonlinear formula Calculate the degree of optimization of the sub-region.

[0073] Where k is the proportional coefficient, which is used for normalization and process adaptation, and the numerator B j bThe larger the diameter of the micro-bump, the stronger the current capacity. The ratio of the center distance of the micro-bump to its diameter C j The closer to the reference value, the better. The denominator A j a The larger the aspect ratio, the more significant the process difficulty.

[0074] As a further description of the technical solution of the present invention, the working process of step S3 further includes:

[0075] According to modeling requirements, the substrate-level conductive layer is divided into y sub-regions, and each region is numbered in the order of: 1, 2, ..., y;

[0076] Obtain the characteristic parameters of the xth sub-area including: power line width ratio W x , via density E x , via spacing ratio T x and substrate aspect ratio O x , where x belongs to y.

[0077] Power line width ratio, the ratio of the actual power line width to the minimum process line width; via density, the number of vias per unit area. The higher the density, the more uniform the current distribution; via pitch ratio, the ratio of the via pitch to the diameter; substrate aspect ratio, the substrate thickness divided by the longest side length. The larger the value, the higher the resonance risk.

[0078] As a further description of the technical solution of the present invention, the working process of step S4 also includes:

[0079] Construct the calculation model of the modeling index coefficient of the x-th sub-region, the expression is:

[0080]

[0081] Where ω1, ω2, ω3 and ω4 are the weight coefficients corresponding to the power line width ratio, via density, via pitch ratio and substrate aspect ratio, respectively. θ is the conversion constant. Through fitting of experimental or simulation data, the combination of various dimensionless parameters is mapped to the numerical range of practical engineering significance. T x0 Set the reference value of the via pitch ratio for the system, x belongs to y, τ x is the modeling index coefficient of the x-th sub-region.

[0082] Through the above technical solution, this embodiment involves a calculation model for the modeling index coefficient of the substrate-level conductive layer sub-region. Its core working principle is to quantitatively evaluate the modeling optimization degree of the substrate-level conductive layer through a parametric modeling method to optimize the electromagnetic performance and reliability of the power distribution network. For the x-th sub-region of the substrate-level conductive layer, the following key characteristic parameters are extracted: the power line width ratio W x , via density E x , via spacing ratio Tx and substrate aspect ratio O x , using the nonlinear formula

[0083] Calculate the degree of optimization of the sub-region.

[0084] Where θ is the proportional coefficient used for normalization and process adaptation, and the numerator is the power line width ratio W. x The larger the value, the smaller the voltage drop and the via density E x The higher the value, the more uniform the current distribution is, and the via spacing is better than T x The closer to the reference value, the better the performance, so with τ x Positive correlation, denominator: substrate aspect ratio O x The larger the value, the higher the risk of resonance. Therefore, with τ x There is a negative correlation.

[0085] As a further description of the technical solution of the present invention, the working process of step S4 also includes:

[0086] The comprehensive modeling index coefficient of the chip-level conductive layer is obtained by weighted summing of the modeling index coefficients of the n sub-regions of the chip-level conductive layer, the comprehensive modeling index coefficient of the interposer-level conductive layer is obtained by weighted summing of the modeling index coefficients of the m sub-regions of the interposer-level conductive layer, and the comprehensive modeling index coefficient of the substrate-level conductive layer is obtained by weighted summing of the modeling index coefficients of the y sub-regions of the substrate-level conductive layer;

[0087] The comprehensive modeling index coefficients of the chip-level conductive layer, the intermediate layer-level conductive layer and the substrate-level conductive layer are compared with the corresponding threshold intervals set by the system. If any one of them does not belong to the corresponding threshold interval, it means that the modeling structure of the conductive layer in the current sub-region needs to be optimized.

[0088] As a further description of the technical solution of the present invention, the working process of step S5 includes:

[0089] Obtain the performance parameters of the current modeling scheme and construct a calculation model for the performance index coefficient of the current modeling scheme. The expression is:

[0090]

[0091] Where, ∈ is the number of performance parameters, ε belongs to ∈, is the εth performance parameter value, is the reference value of the εth performance parameter set for the system, is the weight coefficient of the εth performance parameter, is the performance index coefficient of the modeling scheme;

[0092] Will Compared with the threshold set by the system, if If the value is greater than or equal to the threshold set by the system, it means that the current modeling scheme meets the requirements and the current modeling scheme is output. If it is lower than the threshold set by the system, it means that the current modeling scheme does not meet the requirements and needs to be further adjusted.

[0093] Through the above technical solutions, this embodiment jointly constitutes an overall performance evaluation and optimization system for the chip packaging power supply network. Its core working principle is to ensure that the entire power supply network design meets the electromagnetic performance requirements through hierarchical comprehensive evaluation and global performance verification. The modeling index coefficients of each sub-region at the chip level, interposer level, and substrate level are weighted and summed to generate three key comprehensive indicators. The comprehensive indicators are compared with the preset threshold range: if any indicator exceeds the threshold range → the corresponding level needs to be optimized, and all indicators are within the threshold → enter the global performance verification stage, and establish a multi-dimensional performance evaluation model. Will Compared with the threshold set by the system, if If the value is greater than or equal to the threshold set by the system, it means that the current modeling scheme meets the requirements and the current modeling scheme is output. If it is lower than the threshold set by the system, it means that the current modeling scheme does not meet the requirements and needs to be further adjusted.

[0094] A chip package power supply network electromagnetic modeling system is provided, and the system is used to implement a chip package power supply network electromagnetic modeling method.

[0095] It should be noted that all weight coefficients, reference values, and thresholds in the present invention are empirical values, and the weight coefficients can be modified in combination with the characteristics of the type of data to be evaluated.

[0096] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and should not be considered to limit the scope of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A chip packaging power network electromagnetic modeling method, characterized in that: The method comprises the following steps: Step S1: Scan the chip package power network using a scanning device or extract data required for the modeling process from the design file; Step S2: Divide the power network into chip-level conductive layer, interposer-level conductive layer, and substrate-level conductive layer sub-regions; Step S3: extracting characteristic parameters of each sub-region respectively and normalizing the parameters; Step S4: Analyze the characteristic parameters of each sub-region to evaluate whether the modeling structure of the current sub-region needs to be optimized; Step S5: Evaluate the optimized modeling schemes for each sub-region, and determine whether they meet the performance requirements based on the evaluation results. If they do, output the final modeling scheme. If the requirements are not met, the modeling will be adjusted according to the evaluation results until a modeling solution that meets the requirements is obtained.

2. The chip packaging power supply network electromagnetic modeling method according to claim 1, characterized in that: The working process of step S3 includes: According to modeling requirements, the chip-level conductive layer is divided into n sub-regions, and each region is numbered in the order of: 1, 2, ..., n; Obtain the characteristic parameters of the i-th sub-region including: metal layer thickness D i , Power line width L i , device spacing d i , through hole size R i and through-hole pitch P i , where i belongs to n.

3. The chip packaging power supply network electromagnetic modeling method according to claim 2, characterized in that: The working process of step S4 includes: Construct the calculation model of the modeling index coefficient of the i-th sub-region, and the expression is: Where α, β, and γ are the weight coefficients of power line width, device spacing, and through-hole size, respectively; δ is the influence coefficient of metal layer thickness; and D i0 is the reference data of metal layer width, P0 is the reference data of through-hole spacing, and i belongs to [1, n], ρ i is the modeling index coefficient of the i-th sub-region.

4. The chip packaging power supply network electromagnetic modeling method according to claim 2, characterized in that: The working process of step S3 also includes: According to modeling requirements, the intermediate layer conductive layer is divided into m sub-regions, and each region is numbered in the order of: 1, 2, ..., m; The characteristic parameters of the jth sub-region are obtained including: TSV aspect ratio A j , micro bump diameter B j and the ratio of the center distance of the micro-bump to its diameter C j Among them, j belongs to m.

5. The chip packaging power supply network electromagnetic modeling method according to claim 4, characterized in that: The working process of step S4 also includes: Construct the calculation model of the modeling index coefficient of the j-th sub-region, and the expression is: Where a, b, and c are weight coefficients corresponding to the aspect ratio of the through-silicon via, the diameter of the microbump, and the ratio of the center-to-center spacing of the microbump to its diameter, respectively. k is a conversion constant. By fitting experimental or simulation data, the combination of various dimensionless parameters is mapped to a numerical range of practical engineering significance, and j belongs to [1, m]. σ j is the modeling index coefficient of the j-th sub-region.

6. The chip packaging power supply network electromagnetic modeling method according to claim 2, characterized in that: The working process of step S3 also includes: According to modeling requirements, the substrate-level conductive layer is divided into y sub-regions, and each region is numbered in the order of: 1, 2, ..., y; Obtain the characteristic parameters of the xth sub-area including: power line width ratio W x , via density E x , via spacing ratio T x and substrate aspect ratio O x , where x belongs to y.

7. The chip packaging power supply network electromagnetic modeling method according to claim 6, characterized in that: The working process of step S4 also includes: Construct the calculation model of the modeling index coefficient of the x-th sub-region, the expression is: Where ω1, ω2, ω3 and ω4 are the weight coefficients corresponding to the power line width ratio, via density, via pitch ratio and substrate aspect ratio, respectively. θ is the conversion constant. Through fitting of experimental or simulation data, the combination of various dimensionless parameters is mapped to the numerical range of practical engineering significance. T x0 Set the reference value of the via pitch ratio for the system, x belongs to y, τ x is the modeling index coefficient of the x-th sub-region.

8. The chip packaging power supply network electromagnetic modeling method according to claim 1, characterized in that: The working process of step S4 also includes: The comprehensive modeling index coefficient of the chip-level conductive layer is obtained by weighted summing of the modeling index coefficients of the n sub-regions of the chip-level conductive layer, the comprehensive modeling index coefficient of the interposer-level conductive layer is obtained by weighted summing of the modeling index coefficients of the m sub-regions of the interposer-level conductive layer, and the comprehensive modeling index coefficient of the substrate-level conductive layer is obtained by weighted summing of the modeling index coefficients of the y sub-regions of the substrate-level conductive layer; The comprehensive modeling index coefficients of the chip-level conductive layer, the intermediate layer-level conductive layer and the substrate-level conductive layer are compared with the corresponding threshold intervals set by the system. If any one of them does not belong to the corresponding threshold interval, it means that the modeling structure of the conductive layer in the current sub-region needs to be optimized.

9. The chip packaging power supply network electromagnetic modeling method according to claim 1, characterized in that: The working process of step S5 includes: Obtain the performance parameters of the current modeling scheme and construct a calculation model for the performance index coefficient of the current modeling scheme. The expression is: Where ∈ is the number of performance parameters, ε belongs to ∈, θ ε is the performance parameter value of the εth item, θ ε0 is the reference value of the εth performance parameter set for the system, is the weight coefficient of the εth performance parameter, is the performance index coefficient of the modeling scheme; Will Compared with the threshold set by the system, if If the value is greater than or equal to the threshold set by the system, it means that the current modeling scheme meets the requirements and the current modeling scheme is output. If it is lower than the threshold set by the system, it means that the current modeling scheme does not meet the requirements and needs to be further adjusted.

10. A chip packaging power network electromagnetic modeling system, characterized in that: The system is used to implement the chip packaging power supply network electromagnetic modeling method according to any one of claims 1-9.

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