Pass-through circuit, signal pass-through method, processor, chip and electronic device

Abstract

The application discloses a through circuit, a signal through method, a processor, a chip and an electronic device, and belongs to the chip field. The through circuit comprises a sending circuit unit, an intermediate circuit unit and a target circuit unit, and a first register is arranged in the intermediate circuit unit. The sending circuit unit is used for splitting a first signal to be passed through into a plurality of second signals, and sequentially sending the plurality of second signals to the intermediate circuit unit. The intermediate circuit unit is used for writing each second signal into the first register, reading out the second signal from the first register, and forwarding the second signal to the target circuit unit. The size of the first signal is greater than the size of each second signal. The first signal to be passed through is split into a plurality of second signals, and the second signals are sequentially sent, so that the first register on the intermediate circuit unit can be multiplexed multiple times, and a large number of first registers do not need to be arranged on the intermediate circuit unit.

Description

Technical Field

[0001] This application relates to the field of chips, and in particular to a pass-through circuit, a signal pass-through method, a processor, a chip, and an electronic device. Background Technology

[0002] Feedthrough (FT) refers to the process in a processor where a signal emitted by a transmitting circuit unit passes through at least one intermediate circuit unit to reach a target circuit unit. During this process, the signal's feedthrough path may be relatively long, and signal attenuation may occur.

[0003] To address the signal attenuation issue during pass-through, related technologies add registers (regslices) to the pass-through path to enhance signal drive capability. By adding registers, the long pass-through path is divided into multiple shorter segments, each of which undergoes signal pass-through processing within one clock cycle.

[0004] However, as processor integration increases, the area of ​​each unit on the processor also becomes larger. At this point, signals need to travel through a longer path to reach the target circuit unit. Related technologies will add more registers along the path to improve signal quality, which will occupy a larger area. Summary of the Invention

[0005] This application provides a pass-through circuit, a signal pass-through method, a processor, a chip, and an electronic device. By splitting the first signal to be passed through into multiple second signals and sending the second signals sequentially, this application can achieve multiple reuse of the first register on the intermediate circuit unit, eliminating the need to set up a large number of first registers on the intermediate circuit unit.

[0006] According to one aspect of this application, a pass-through circuit is provided, the pass-through circuit including a transmitting circuit unit, an intermediate circuit unit and a target circuit unit, wherein a first register is provided in the intermediate circuit unit;

[0007] The transmitting circuit unit is used to split the first signal to be penetrated into multiple second signals, and send the multiple second signals to the intermediate circuit unit in sequence;

[0008] An intermediate circuit unit is used to write each second signal into a first register, read the second signal from the first register, and forward the second signal to the target circuit unit.

[0009] The size of the first signal is larger than the size of each of the second signals.

[0010] According to one aspect of this application, a signal pass-through method is provided, the method comprising the following steps.

[0011] The transmitting circuit unit splits the first signal to be penetrated into multiple second signals, and sends the multiple second signals to the intermediate circuit unit in sequence.

[0012] The intermediate circuit unit writes each second signal into the first register, reads the second signal from the first register, and forwards the second signal to the target circuit unit.

[0013] The size of the first signal is larger than the size of each of the second signals.

[0014] According to another aspect of this application, a signal pass-through device is provided, which includes the following modules.

[0015] The transmitting module is used to split the first signal to be penetrated into multiple second signals, and send the multiple second signals to the intermediate module in sequence.

[0016] The intermediate module is used to write each second signal into the first register, read the second signal from the first register, and forward the second signal to the target module.

[0017] The size of the first signal is larger than the size of each of the second signals.

[0018] According to one aspect of this application, a processor is provided, the processor including the above-described pass-through circuit.

[0019] According to one aspect of this application, a chip is provided, the chip including a processor, the processor including the aforementioned pass-through circuit.

[0020] According to one aspect of this application, a server is provided, the server including the above-described pass-through circuit.

[0021] According to one aspect of this application, an electronic device is provided, the electronic device including a processor, the processor including the above-described pass-through circuit.

[0022] The beneficial effects of the technical solutions provided in this application include at least the following:

[0023] This application embodiment splits the first signal to be passed through into multiple second signals, thereby transforming the task of passing through the first signal into the task of passing through multiple second signals. Each second signal is passed through sequentially in the pass-through circuit, allowing each second signal to reuse the first register on the intermediate circuit unit to enhance its driving capability. Therefore, the intermediate circuit unit in the pass-through circuit provided by this application does not need to have a large number of first registers. If the first signal is directly passed through, due to the large size of the first signal, the intermediate circuit unit needs to have a large number of first registers to temporarily store the first signal. However, this application embodiment splits the first signal into multiple second signals using time-division multiplexing, with each second signal being smaller than the first signal. In this case, the intermediate circuit unit only needs to have a few more first registers to temporarily store the second signals. This application can effectively reduce the area occupied by the first registers on the intermediate circuit unit, thereby reducing the static power consumption caused by the first registers. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of a through-circuit provided by related technologies.

[0026] Figure 2 This is a schematic diagram of a through-circuit provided in an exemplary embodiment of this application.

[0027] Figure 3 This is a signal timing diagram provided in an exemplary embodiment of this application.

[0028] Figure 4 This is a schematic diagram of a through-circuit provided in another exemplary embodiment of this application.

[0029] Figure 5 This is a flowchart of a signal pass-through method provided in an exemplary embodiment of this application.

[0030] Figure 6 This is a flowchart of a signal pass-through method provided in another exemplary embodiment of this application.

[0031] Figure 7 This is a flowchart of a signal pass-through method provided in another exemplary embodiment of this application.

[0032] Figure 8 This is a structural block diagram of a signal penetration device provided in an exemplary embodiment of this application.

[0033] Figure 9 This is a structural block diagram of an electronic device provided in an exemplary embodiment of this application.

[0034] Figure 10 This is a schematic diagram of the structure of a server provided in an exemplary embodiment of this application. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0036] First, some terms used in the embodiments of this application will be introduced.

[0037] Register slicing: In hardware design and Verilog programming, register slicing is a common circuit design technique used to optimize circuit timing, improve performance, and reduce power consumption. Register slicing involves inserting registers into the data transfer path, dividing long combinational logic paths into shorter segments to improve timing performance. This technique is also known as pipelining or register insertion.

[0038] In complex circuit designs, long combinational logic paths often lead to the following problems: (1) Timing violations: The path delay of a long combinational logic path may exceed the clock cycle, causing data to fail to arrive at the expected time; (2) System clock frequency limitation: The system clock frequency must be lower than the delay of the long combinational logic path; (3) Increased power consumption: Long combinational logic paths may cause more gates to flip simultaneously, resulting in increased system power consumption.

[0039] Register slicing allows registers to be inserted into long combinational logic paths, breaking them down into smaller parts that can be processed in multiple clock cycles. Each clock cycle handles a portion of the logic. Register slicing reduces latency in long combinational logic paths, increases clock frequency, balances load across stages, optimizes throughput, and reduces dynamic power consumption by minimizing simultaneous gate toggling.

[0040] A pass-through circuit is a circuit in which signal pass-through occurs. Typically, a pass-through circuit includes a transmitting circuit unit, intermediate circuit units, and a target circuit unit. The signal emitted by the transmitting circuit unit passes through the intermediate circuit units to reach the target circuit unit. Optionally, the transmitting circuit unit refers to the circuit unit used to emit the signal, the intermediate circuit unit refers to the circuit unit the signal passes through during transmission, and the target circuit unit refers to the circuit unit used to receive the signal. Typically, due to the long physical distance and numerous intermediate circuit units in a pass-through circuit, signal attenuation may occur during the pass-through process. Therefore, related technologies add registers to the intermediate circuit units to divide the entire pass-through path into multiple shorter segments, each processed by the signal pass-through in one clock cycle, thereby increasing the signal driving capability.

[0041] Figure 1 A schematic diagram of a through-circuit in the related art is shown, such as... Figure 1 As shown, Figure 1 Signal A emitted by circuit unit A will be relayed through circuit units 1, 2, and 3 before finally reaching circuit unit B. Furthermore, circuit units 1, 2, and 3 each have two levels of registers. When signal A passes through circuit units 1, 2, and 3, it will be temporarily stored in each level of register before being relayed again. This temporary storage in registers enhances the driving capability of signal A.

[0042] Similarly, circuit unit B may also send signal B. Signal B will eventually reach circuit unit A after being forwarded by circuit unit 3, circuit unit 2 and circuit unit 1. Furthermore, circuit units 3, 2 and 1 each have two additional levels of registers. When signal B passes through circuit units 3, 2 and 1, it will be temporarily stored by each level of register and then forwarded again to enhance the driving capability of signal B.

[0043] However, as chip integration increases, the signals emitted by the transmitting circuit unit will have to pass through more and more intermediate circuit units before reaching the target circuit unit. Consequently, more and more registers will be set up on the entire chip to meet the signal driving capability requirements. At this point, the area occupied by the registers on the entire pass-through circuit will become larger and larger, resulting in a lot of static power consumption.

[0044] Figure 2The diagram shows a pass-through circuit provided in an exemplary embodiment of this application. Optionally, the pass-through circuit 200 can be applied to various processors, such as a central processing unit (CPU), a graphics processing unit (GPU), a video processing unit (VPU), or a neural network processing unit (NPU).

[0045] like Figure 2 As shown, the through-circuit 200 includes a transmitting circuit unit 210, an intermediate circuit unit 220, and a target circuit unit 230. The intermediate circuit unit 220 includes a first register.

[0046] The transmitting circuit unit 210 is configured to split the first signal to be penetrated into a plurality of second signals, wherein the size of the first signal is larger than the size of each of the plurality of second signals obtained by splitting. The transmitting circuit unit 210 is also configured to sequentially transmit the plurality of second signals to the intermediate circuit unit 220.

[0047] The intermediate circuit unit 220 is used to write each second signal into the first register after receiving each second signal, and to read the second signal from the first register and forward the second signal to the target circuit unit 230; that is, the intermediate circuit unit 220 is used to temporarily store the second signal in the first register after receiving each second signal, and then forward each second signal to the target circuit unit 230.

[0048] In one embodiment, the transmitting circuit unit 210 is configured to sequentially transmit a plurality of second signals to the intermediate circuit unit 220 over multiple clock cycles, wherein each clock cycle corresponds one-to-one with a plurality of second signals. The transmitting circuit unit 210 transmits a second signal once per clock cycle. Optionally, the transmitting circuit unit 210 transmits a second signal once on the rising edge of the clock in a clock cycle, or optionally, the transmitting circuit unit 210 transmits a second signal once on the falling edge of the clock in a clock cycle.

[0049] Optionally, the transmitting circuit unit 210 transmits multiple second signals to the intermediate circuit unit 220 over several consecutive clock cycles. For example, the transmitting circuit unit 210 transmits one second signal in cycle 1, a second second signal in cycle 2, a third second signal in cycle 3, and so on. If the multiple second signals are split into N signals, the total transmission duration spans N cycles. It is understandable that by having the transmitting circuit unit 210 continuously transmit the second signals, it avoids the transmitting circuit unit 210 transmitting other signals to be passed through or signals split from other signals to be passed through. For example, if there is a third signal to be passed through on the pass-through circuit 200, and this third signal will be split into multiple fourth signals, by having the transmitting circuit unit 210 continuously transmit the second signals, while the fourth signals are only transmitted after all the second signals have been transmitted, it avoids the downstream module mistakenly believing that the second and fourth signals are split from the same signal, and thus incorrectly reassembling the original signal.

[0050] In one embodiment, the first signal is a slowly varying signal, meaning its value changes only after a relatively long period of time. That is, the first signal passes through the target circuit unit 230 once every first duration, where the first duration satisfies a duration condition. Optionally, if the first duration is longer than an interval duration threshold, the first signal will only pass through the target circuit unit 230 once after a relatively long period of time. In this case, the longer time interval will allow sufficient time for multiple second signals to be sent sequentially. When the time interval between two passes of the first signal is sufficiently large, the additional clock cycles required to send multiple second signals are negligible. Therefore, the embodiments of this application have a significant optimization effect on the slowly varying first signal.

[0051] In one embodiment, the transmitting circuit unit 210 transmits multiple second signals sequentially. For example, the transmitting circuit unit 210 splits the first signal into multiple second signals according to the bit order from high to low, and transmits the second signals sequentially according to the bit order of each second signal in the first signal. In another embodiment, the transmitting circuit unit 210 transmits multiple second signals out of order. For example, when splitting the first signal, the transmitting circuit unit 210 immediately transmits each second signal obtained after splitting, regardless of the position of the split second signal in the first signal.

[0052] In one embodiment, the transmitting circuit unit 210 is configured to split the first signal to be penetrated into multiple second signals of the same size, and sequentially transmit the multiple second signals to the intermediate circuit unit 220. Each second signal is temporarily stored in the first register of the intermediate circuit unit 220 before being forwarded to the target circuit unit 230. It is understood that the number of first registers in the intermediate circuit unit 220 is related to the size of the signal stored in the first registers. When the signal size stored in the first registers is large, more first registers are required in the intermediate circuit unit 220; when the signal size stored in the first registers is small, fewer first registers can be used in the intermediate circuit unit 220. Therefore, by splitting the first signal into multiple second signals of the same size, the transmitting circuit unit 210 minimizes the number of first registers in the intermediate circuit unit 220. When using the minimum number of first registers, each second signal can be effectively temporarily stored, thus effectively reducing the number of first registers.

[0053] In another embodiment, the transmitting circuit unit 210 is used to split the first signal to be penetrated into multiple second signals of different sizes, and sequentially transmit the multiple second signals to the intermediate circuit unit 220. Each second signal is temporarily stored in the first register of the intermediate circuit unit 220 before being forwarded to the target circuit unit 230. In this case, the number of first registers set in the intermediate circuit unit 220 depends on the largest second signal. For other second signals, there will be ample register storage space to cope with unexpected situations. For example, to prevent signal loss or errors, the second signals can be backed up in the extra register storage space.

[0054] In one embodiment, the number of stages in the first register on the intermediate circuit unit 220 depends on the path distance of the second signal through the intermediate circuit unit 220. If the second signal needs to travel a long path through the intermediate circuit unit 220, more stages of the first register can be set on the intermediate circuit unit 220 to divide it into more segments and enhance the signal driving capability. If the second signal needs to travel a short path through the intermediate circuit unit 220, fewer stages of the first register can be set on the intermediate circuit unit 220 to save the area resources occupied by the first register.

[0055] In one embodiment, the pass-through circuit 200 includes a plurality of intermediate circuit units 220, each of which includes a first register. Among the plurality of intermediate circuit units 220, the first intermediate circuit unit 220 receives a second signal sent by the transmitting circuit unit 210, temporarily stores it in its internal first register, and then forwards it to the second intermediate circuit unit 220. The second intermediate circuit unit 220 temporarily stores the received second signal in its internal first register and then forwards it to the third intermediate circuit unit 220. The third intermediate circuit unit 220 temporarily stores the received second signal in its internal first register and then forwards it to the fourth intermediate circuit unit 220, and so on. The last intermediate circuit unit 220 temporarily stores the received second signal in its internal first register and then forwards it to the target circuit unit 230.

[0056] In summary, this application embodiment splits the first signal to be passed through into multiple second signals, thereby transforming the task of passing through the first signal into the task of passing through multiple second signals. Each second signal is sequentially passed through in the pass-through circuit 200, allowing each second signal to reuse the first register on the intermediate circuit unit 220 to enhance its driving capability. Therefore, the intermediate circuit unit 220 of the pass-through circuit 200 provided in this application does not need to have a large number of first registers. If the first signal is directly passed through, due to its large size, the intermediate circuit unit 220 needs to have a large number of first registers to temporarily store the first signal. However, this application embodiment splits the first signal into multiple second signals using time-division multiplexing, with each second signal smaller than the first signal. In this case, the intermediate circuit unit 220 only needs to have a few more first registers to temporarily store the second signals. This application can effectively reduce the area occupied by the first registers on the intermediate circuit unit 220, thereby reducing the static power consumption caused by the first registers.

[0057] An example will be given below to illustrate the beneficial effects of the punch-through circuit provided in this application.

[0058] Indicatively, assuming the first signal to be passed through includes 128 bits, the pass-through circuit 200 includes 5 intermediate circuit units 220, each of which includes two levels of first registers.

[0059] If the method provided in this application is not used, and the 128-bit first signal is directly passed through, the passing circuit 200 would need to set up a total of 5*128*2=1280 first registers.

[0060] When the method provided in this application is used to split the 128-bit first signal into eight 16-bit second signals and pass them through sequentially, the pass-through circuit 200 needs to set up a total of 5*16*2=160 first registers.

[0061] As can be seen, by using the method provided in this application, the number of first registers can be reduced from 1280 to 160, the area resources occupied by the registers are reduced by 87.5%, and only 7 more clock cycles are required.

[0062] In one embodiment, the transmitting circuit unit 210 is configured to split the first signal into a plurality of second signals based on the first bit width of the first signal to be passed through, wherein the second bit width of each of the plurality of second signals is smaller than the first bit width.

[0063] Optionally, the second bit width of each of the multiple second signals is the same. For example, if the first signal includes 128 bits, the transmitting circuit unit 210 divides the first signal into 8 second signals, each including 16 bits. Optionally, the second bit width of the multiple second signals is not the same. For example, if the first signal includes 128 bits, the transmitting circuit unit 210 divides the first signal into 9 second signals, the 9 second signals including 4, 4, 8, 8, 8, 16, 16, 32, and 32 bits respectively.

[0064] In one embodiment, the transmitting circuit unit 210 is configured to determine a target bit width and / or a target quantity based on a first bit width of a first signal to be penetrated; and to split the first signal into a plurality of second signals according to the target bit width and / or the target quantity, wherein the number of the plurality of second signals is the target quantity, and the second bit width of each of the plurality of second signals is the target bit width.

[0065] Optionally, the transmitting circuit unit 210 is configured to determine a target bit width based on the first bit width of the first signal to be transmitted; and to divide the first signal into multiple second signals according to the target bit width, wherein any two of the multiple second signals contain no repetition of bits. For example, the transmitting circuit unit 210 determines that the target bit width is 16 bits based on the 128-bit first signal, and divides the first signal into 8 second signals according to the target bit width, wherein any two of the 8 second signals contain no repetition of bits.

[0066] Optionally, the target bit width is determined based on the reduction effect of register area resources. For example, when the target bit width is reduced from 16 bits to 8 bits, the number of clock cycles used to send the second signal will increase from 8 to 16. Correspondingly, the register area reduction ratio will change from 7 / 8 to 15 / 16. At this point, the further reduction in register area ratio (from 7 / 8 to 15 / 16) is not worth spending an additional 8 clock cycles. In this case, a register area reduction ratio of 7 / 8 is already a relatively good register area reduction effect.

[0067] Optionally, the transmitting circuit unit 210 is configured to determine the target quantity based on the first bit width of the first signal to be penetrated; and to divide the first signal into multiple second signals according to the target quantity, wherein any two second signals contain no duplicate bits. For example, the transmitting circuit unit 210 determines the target quantity to be 8 based on the 128-bit first signal, and divides the first signal into 8 second signals according to the target quantity, each second signal containing 16 bits, and any two second signals contain no duplicate bits.

[0068] Optionally, the target number is determined based on the reduction effect of register area resources. For example, when the target number increases from 8 to 16, the number of clock cycles used to send the second signal will increase from 8 to 16. Correspondingly, the register area reduction ratio will change from 7 / 8 to 15 / 16. At this point, the further reduction in register area ratio (from 7 / 8 to 15 / 16) is not worth spending an additional 8 clock cycles. In this case, a register area reduction ratio of 7 / 8 is already a relatively good register area reduction effect.

[0069] Optionally, the transmitting circuit unit 210 is configured to determine the target bit width and target quantity based on the first bit width of the first signal to be penetrated; and to split the first signal into multiple second signals according to the target quantity and target bit width, wherein any two second signals contain no duplicate bits. For example, the transmitting circuit unit 210 determines that the target quantity is 8 and the target bit width is 16 bits based on the 128-bit first signal, and splits the first signal into 8 second signals according to the target quantity and target bit width, each second signal containing 16 bits, and any two second signals contain no duplicate bits.

[0070] Optionally, the target number and target bit width are determined based on the reduction effect of register area resources. For example, when the target number increases from 8 to 16, the number of clock cycles used to send the second signal will increase from 8 to 16. Correspondingly, the register area reduction ratio will change from 7 / 8 to 15 / 16. At this point, the further reduction in register area ratio (from 7 / 8 to 15 / 16) is not worth spending an additional 8 clock cycles. In this case, a register area reduction ratio of 7 / 8 is already a relatively good register area reduction effect.

[0071] Next, we will conduct a time series analysis. Figure 3 This is a timing diagram provided in an exemplary embodiment of this application.

[0072] Figure 3Part (A) illustrates a case where the first signal is directly passed through to the target circuit unit 230 without using the method provided in this application. As can be seen from the figure, the first signal will be passed through to the target circuit unit 230 again after multiple clock cycles, and each time the first signal is passed through, it only takes one clock cycle.

[0073] Figure 3 Part (B) illustrates a scenario where, using the method provided in this application, the first signal is split into two second signals and then transmitted sequentially. As can be seen from the figure, each pass-through of the first signal requires two clock cycles, with each of the two clock cycles used to transmit one second signal.

[0074] If the first signal is a slowly varying signal, meaning the time interval between two passes through the first signal is relatively long, then the additional clock cycles required to split it into multiple second signals for separate transmission are negligible. For example, if the first signal will only pass through again after 10240 clock cycles, according to... Figure 3 As shown in section (B), 10240 clock cycles will only consume an extra clock cycle, an increase of only one ten-thousandth. In this case, the extra performance required to perform one more transmission operation is negligible.

[0075] Figure 4 This is a schematic diagram of a pass-through circuit provided in an exemplary embodiment of this application. The pass-through circuit 200 includes a transmitting circuit unit 210, an intermediate circuit unit 220, and a target circuit unit 230. The intermediate circuit unit 220 includes a first register.

[0076] The transmitting circuit unit 210 is configured to split the first signal to be penetrated into a plurality of second signals, wherein the size of the first signal is larger than the size of each of the plurality of second signals obtained by splitting. The transmitting circuit unit 210 is also configured to sequentially transmit the plurality of second signals to the intermediate circuit unit 220.

[0077] The intermediate circuit unit 220 is used to write each second signal into the first register after receiving each second signal, and to read the second signal from the first register and forward the second signal to the target circuit unit 230; that is, the intermediate circuit unit 220 is used to temporarily store the second signal in the first register after receiving each second signal, and then forward each second signal to the target circuit unit 230.

[0078] The target circuit unit 230 is used to receive multiple second signals in sequence and splice the multiple second signals to obtain a first signal.

[0079] In one embodiment, each time the target circuit unit 230 receives a second signal, it concatenates that second signal with the previous concatenation result to obtain an updated concatenation result. Illustratively, when the target circuit unit 230 receives the i-th second signal, it concatenates the i-th second signal with the (i-1)-th concatenation result to obtain the i-th concatenation result. When i equals one, the (i-1)-th concatenation result is empty. When i equals two, the (i-1)-th concatenation result is the first second signal; when i equals the total number N of multiple second signals, the i-th concatenation result is the final concatenation result, i.e., the first signal.

[0080] In the above embodiment, the target circuit unit 230 enters the splicing process as soon as it receives a second signal, which can save all the time used for splicing the second signal and speed up the transmission speed of the entire first signal.

[0081] In another embodiment, after the target circuit unit 230 receives all the second signals, it splices multiple second signals to obtain the first signal. In this case, the target circuit unit 230 can perform splicing only after all the second signals have passed the check, ensuring the correctness of the final splicing result and avoiding invalid splicing operations caused by starting splicing in advance but ultimately failing to splice successfully.

[0082] In one embodiment, such as Figure 4 As shown, the transmitting circuit unit 210 includes a second register; the transmitting circuit unit 210 is also used to store the second signal to be transmitted among a plurality of second signals in the second register; read the second signal to be transmitted from the second register and transmit it to the intermediate circuit unit 220.

[0083] For example, after the transmitting circuit unit 210 splits the signal into multiple second signals, it stores these signals in a second register. After the previous second signal is transmitted, the transmitting circuit unit 210 reads the next second signal from the second register and transmits it to the intermediate circuit unit 220. At this time, the configuration of the second register allows the transmitting circuit unit 210 to transmit the second signals in a scheduled manner.

[0084] In one embodiment, such as Figure 4 As shown, the target circuit unit 230 includes a third register; the target circuit unit 230 is also used to store the second signal to be spliced ​​among a plurality of second signals in the third register; read the second signal to be spliced ​​from the third register, and splice the plurality of second signals to obtain a first signal.

[0085] For example, after receiving the second signal, the target circuit unit 230 stores the second signal in the third register. After the previous second signal is assembled, the target circuit unit 230 reads the next second signal from the third register and assembles the next second signal. At this time, the setting of the third register enables the target circuit unit 230 to assemble the second signals in a scheduled manner, and finally restore the first signal.

[0086] It is understandable that when the size of the first signal is large and the number of second signals obtained by splitting is large, it is only necessary to set more second registers in the transmitting circuit unit 210 and more third registers in the target circuit unit 230 to perform splitting and splicing. At this time, even if more registers need to be set in the transmitting circuit unit 210 and the target circuit unit 230, the number of additional registers added in the transmitting circuit unit 210 and the target circuit unit 230 will not be more than the number of additional first registers added in the intermediate circuit unit 220, because the number of intermediate circuit units 220 and the number of first register levels set in each intermediate circuit unit 220 are often large. That is, this application can effectively reduce the area occupied by registers.

[0087] Figure 5 This is a flowchart of a signal pass-through method provided in an exemplary embodiment of this application. The method is illustrated by example when it is applied to a pass-through circuit. The method includes the following steps.

[0088] Step 520: The transmitting circuit unit splits the first signal to be penetrated into multiple second signals, and sends the multiple second signals to the intermediate circuit unit in sequence.

[0089] The size of the first signal is larger than the size of each of the second signals.

[0090] The transmitting circuit unit refers to the circuit unit used to transmit signals.

[0091] In one embodiment, the transmitting circuit unit sequentially transmits multiple second signals to the intermediate circuit unit over multiple clock cycles, with each clock cycle corresponding to one of the multiple second signals. The transmitting circuit unit transmits a second signal once per clock cycle; optionally, it transmits the second signal once on the rising edge of the clock in a clock cycle, or optionally, it transmits the second signal once on the falling edge of the clock in a clock cycle.

[0092] Optionally, the transmitting circuit unit sends multiple second signals to the intermediate circuit unit over several consecutive clock cycles. For example, the transmitting circuit unit sends one second signal in cycle 1, a second second signal in cycle 2, a third second signal in cycle 3, and so on. In this case, if the multiple second signals are split into N signals, the total transmission duration spans N cycles. It is understandable that by having the transmitting circuit unit continuously send second signals, it avoids the transmitting circuit unit interspersing the transmission of other signals to be passed through or signals split from other signals to be passed through. For example, if there is a third signal to be passed through in the pass-through circuit, and this third signal will be split into multiple fourth signals, by having the transmitting circuit unit continuously send second signals, while the fourth signals are only sent after all the second signals have been sent, it avoids the downstream module mistakenly believing that the second and fourth signals are split from the same signal, and thus incorrectly assembling and restoring the signal.

[0093] In one embodiment, the first signal is a slowly varying signal, meaning its value changes only after a relatively long period of time. That is, the first signal is a signal that passes through to the target circuit unit once every first duration, where the first duration satisfies a duration condition. Optionally, if the first duration is longer than an interval duration threshold, the first signal will only pass through to the target circuit unit once after a relatively long period of time. In this case, the longer time interval will allow sufficient time for multiple second signals to be sent sequentially. When the time interval between two passes of the first signal is sufficiently large, the additional clock cycles required to send multiple second signals are negligible. Therefore, the embodiments of this application have a significant optimization effect on the slowly varying first signal.

[0094] In one embodiment, the transmitting circuit unit transmits multiple second signals sequentially. For example, the transmitting circuit unit splits the first signal into multiple second signals according to the bit order from high to low, and transmits the second signals sequentially according to the bit order of each second signal in the first signal. In another embodiment, the transmitting circuit unit transmits multiple second signals out of order. For example, when splitting the first signal, the transmitting circuit unit immediately transmits each second signal obtained after splitting, regardless of the position of the split second signal in the first signal.

[0095] In one embodiment, the transmitting circuit unit splits the first signal to be transmitted into multiple second signals of the same size, and sequentially transmits the multiple second signals to an intermediate circuit unit. Each second signal is temporarily stored in a first register of the intermediate circuit unit before being forwarded to the target circuit unit. It is understood that the number of first registers in the intermediate circuit unit is related to the size of the signal stored in the first registers. When the signal size stored in the first register is large, more first registers are required in the intermediate circuit unit; when the signal size stored in the first register is small, fewer first registers can be used in the intermediate circuit unit. Therefore, by splitting the first signal into multiple second signals of the same size, the transmitting circuit unit minimizes the number of first registers required in the intermediate circuit unit. When using the minimum number of first registers, each second signal can be effectively temporarily stored, thus effectively reducing the number of first registers required.

[0096] In another embodiment, the transmitting circuit unit splits the first signal to be transmitted into multiple second signals of different sizes, and sequentially transmits these second signals to an intermediate circuit unit. Each second signal is temporarily stored in a first register of the intermediate circuit unit before being forwarded to the target circuit unit. In this case, the number of first registers in the intermediate circuit unit depends on the largest second signal; for other second signals, there will be ample register storage space to handle unexpected situations. For example, to prevent signal loss or errors, the second signals can be backed up in the extra register storage space.

[0097] In step 540, the intermediate circuit unit writes each second signal into the first register, reads the second signal from the first register, and forwards the second signal to the target circuit unit.

[0098] Intermediate circuit units refer to the circuit units that signals must pass through during transmission. An intermediate circuit unit temporarily stores each of the multiple second signals in a first register before forwarding it to the target circuit unit.

[0099] In one embodiment, the number of stages in the first register on the intermediate circuit unit depends on the path distance of the second signal through the intermediate circuit unit. If the second signal needs to travel a long path through the intermediate circuit unit, more stages of the first register can be set on the intermediate circuit unit to divide it into more segments and enhance the signal driving capability. If the second signal needs to travel a short path through the intermediate circuit unit, fewer stages of the first register can be set on the intermediate circuit unit to save the area resources occupied by the first register.

[0100] In one embodiment, the pass-through circuit includes multiple intermediate circuit units, each of which includes a first register. Among the multiple intermediate circuit units, the first intermediate circuit unit receives a second signal sent by the transmitting circuit unit, temporarily stores it in its internal first register, and then forwards it to the second intermediate circuit unit. The second intermediate circuit unit then temporarily stores the received second signal in its internal first register and forwards it to the third intermediate circuit unit, which in turn temporarily stores it in its internal first register and forwards it to the fourth intermediate circuit unit, and so on. The last intermediate circuit unit temporarily stores the received second signal in its internal first register and then forwards it to the target circuit unit.

[0101] In summary, this application embodiment splits the first signal to be passed through into multiple second signals, thereby transforming the task of passing through the first signal into the task of passing through multiple second signals. Each second signal is passed through sequentially in the pass-through circuit, allowing each second signal to reuse the first register on the intermediate circuit unit to enhance its driving capability. Therefore, the intermediate circuit unit in the pass-through circuit provided by this application does not need to have a large number of first registers. If the first signal is directly passed through, due to the large size of the first signal, the intermediate circuit unit needs to have a large number of first registers to temporarily store the first signal. However, this application embodiment splits the first signal into multiple second signals using time-division multiplexing, with each second signal being smaller than the first signal. In this case, the intermediate circuit unit only needs to have a few more first registers to temporarily store the second signals. This application can effectively reduce the area occupied by the first registers on the intermediate circuit unit, thereby reducing the static power consumption caused by the first registers.

[0102] based on Figure 5 In the optional embodiment shown, step 520 includes Figure 6 Step 620 in the process.

[0103] Step 620: The transmitting circuit unit splits the first signal into multiple second signals based on the first bit width of the first signal to be passed through, wherein the second bit width of each of the multiple second signals is smaller than the first bit width.

[0104] Optionally, the second bit width of each of the multiple second signals is the same. For example, if the first signal includes 128 bits, the transmitting circuit unit splits the first signal into 8 second signals, each including 16 bits. Optionally, the second bit width of the multiple second signals is not the same. For example, if the first signal includes 128 bits, the transmitting circuit unit splits the first signal into 9 second signals, with the 9 second signals including 4, 4, 8, 8, 8, 16, 16, 32, and 32 bits respectively.

[0105] In one embodiment, the transmitting circuit unit determines the target bit width and / or target quantity based on the first bit width of the first signal to be passed through; and splits the first signal into multiple second signals according to the target bit width and / or target quantity, the number of multiple second signals being the target quantity, and the second bit width of each of the multiple second signals being the target bit width.

[0106] Optionally, the transmitting circuit unit determines the target bit width based on the first bit width of the first signal to be transmitted; according to the target bit width, the first signal is divided into multiple second signals, wherein any two of the multiple second signals contain no repetition of bits. For example, the transmitting circuit unit determines the target bit width to be 16 bits based on the 128-bit first signal, and divides the first signal into 8 second signals according to the target bit width, wherein any two of the 8 second signals contain no repetition of bits.

[0107] Optionally, the target bit width is determined based on the reduction effect of register area resources. For example, when the target bit width is reduced from 16 bits to 8 bits, the number of clock cycles used to send the second signal will increase from 8 to 16. Correspondingly, the register area reduction ratio will change from 7 / 8 to 15 / 16. At this point, the further reduction in register area ratio (from 7 / 8 to 15 / 16) is not worth spending an additional 8 clock cycles. In this case, a register area reduction ratio of 7 / 8 is already a relatively good register area reduction effect.

[0108] Optionally, the transmitting circuit unit determines the target quantity based on the first bit width of the first signal to be transmitted; according to the target quantity, the first signal is divided into multiple second signals, wherein no two second signals contain duplicate bits. For example, the transmitting circuit unit determines the target quantity to be 8 based on the 128-bit first signal, and divides the first signal into 8 second signals, each containing 16 bits, and no two second signals contain duplicate bits.

[0109] Optionally, the target number is determined based on the reduction effect of register area resources. For example, when the target number increases from 8 to 16, the number of clock cycles used to send the second signal will increase from 8 to 16. Correspondingly, the register area reduction ratio will change from 7 / 8 to 15 / 16. At this point, the further reduction in register area ratio (from 7 / 8 to 15 / 16) is not worth spending an additional 8 clock cycles. In this case, a register area reduction ratio of 7 / 8 is already a relatively good register area reduction effect.

[0110] Optionally, the transmitting circuit unit determines the target bit width and target quantity based on the first bit width of the first signal to be penetrated; according to the target quantity and target bit width, the first signal is split into multiple second signals, wherein no two second signals contain repeated bits. For example, based on the 128-bit first signal, the transmitting circuit unit determines that the target quantity is 8 and the target bit width is 16 bits, and splits the first signal into 8 second signals according to the target quantity and target bit width, each second signal containing 16 bits, and no two second signals contain repeated bits.

[0111] Optionally, the target number and target bit width are determined based on the reduction effect of register area resources. For example, when the target number increases from 8 to 16, the number of clock cycles used to send the second signal will increase from 8 to 16. Correspondingly, the register area reduction ratio will change from 7 / 8 to 15 / 16. At this point, the further reduction in register area ratio (from 7 / 8 to 15 / 16) is not worth spending an additional 8 clock cycles. A register area reduction ratio of 7 / 8 is already a relatively good register area reduction effect.

[0112] Figure 7 A flowchart of a signal pass-through method provided in an exemplary embodiment of this application is shown, illustrated by way of example, the method being performed by a pass-through circuit, the method including the following steps.

[0113] Step 720: The transmitting circuit unit splits the first signal to be penetrated into multiple second signals and sends the multiple second signals to the intermediate circuit unit in sequence.

[0114] The size of the first signal is larger than the size of each of the second signals.

[0115] The transmitting circuit unit refers to the circuit unit used to transmit signals.

[0116] In one embodiment, the transmitting circuit unit includes a second register; the transmitting circuit unit is further configured to store a second signal to be transmitted among a plurality of second signals in the second register; read the second signal to be transmitted from the second register and transmit it to the intermediate circuit unit.

[0117] For example, after the transmitting circuit unit splits into multiple second signals, it stores the multiple second signals in a second register. After the previous second signal is sent, the transmitting circuit unit reads the next second signal from the second register and sends the next second signal to the intermediate circuit unit.

[0118] Step 740: The intermediate circuit unit writes each second signal into the first register, reads the second signal from the first register, and forwards the second signal to the target circuit unit.

[0119] Step 760: The target circuit unit receives multiple second signals in sequence and splices the multiple second signals to obtain the first signal.

[0120] The target circuit unit refers to the circuit unit used to receive signals.

[0121] In one embodiment, each time the target circuit unit receives a second signal, it concatenates that second signal with the previous concatenation result to obtain an updated concatenation result. Illustratively, when the target circuit unit receives the i-th second signal, it concatenates the i-th second signal with the (i-1)-th concatenation result to obtain the i-th concatenation result. When i equals one, the (i-1)-th concatenation result is empty. When i equals two, the (i-1)-th concatenation result is the first second signal; when i equals the total number N of multiple second signals, the i-th concatenation result is the final concatenation result, i.e., the first signal.

[0122] In the above embodiments, the target circuit unit enters the splicing process as soon as it receives a second signal, which can save all the time used for splicing the second signal and speed up the transmission speed of the entire first signal.

[0123] In another embodiment, after the target circuit unit receives all the second signals, it splices multiple second signals to obtain the first signal. In this case, the target circuit unit can perform splicing only after all the second signals have passed the check, ensuring the correctness of the final splicing result and avoiding invalid splicing operations caused by starting splicing prematurely and ultimately failing to splice successfully.

[0124] In one embodiment, the target circuit unit includes a third register; the target circuit unit also stores the second signal to be spliced ​​among a plurality of second signals in the third register; the second signal to be spliced ​​is read from the third register, and the plurality of second signals are spliced ​​to obtain a first signal.

[0125] For example, after the target circuit unit receives the second signal, it will store the second signal in the third register. After the previous second signal is spliced, the target circuit unit will read the next second signal from the third register and splice the next second signal.

[0126] In one embodiment, as chip integration increases, the module area becomes larger, requiring more regislices for signals that pass through to improve signal quality. This increases the area significantly, and even if the signal doesn't flip, it also increases static power consumption. Furthermore, in current implementations, some signals are found to be slowly varying, changing only once every tens or even tens of thousands of frames, thus providing room for optimization.

[0127] For slowly varying signals, taking a 128-bit signal as an example, assuming the process involves passing through 5 intermediate circuit units (10 reslices in total), the number of registers used would be 10 * 128 = 1280. However, because the signal is slowly varying, for example, changing only once every 1024 clock cycles, the signal can be time-division multiplexed during transmission. That is, the signal is first reduced to 16 bits and transmitted 8 times, then reassembled at the target circuit unit, and finally restored to a 128-bit signal. This reduces the reslice resources required to 10 * 16 = 160 registers. Therefore, reducing the number of registers from 1280 to 160 reduces area resources by 87.5%, requiring only 7 more clock cycles to achieve this benefit.

[0128] This application can be implemented simply by adding bit-width conversion units within the transmitting and target circuit units. Specifically, a bit-width reduction unit is added within the transmitting circuit unit, and a bit-width restoration unit is added within the target circuit unit. The bit-width reduction unit reduces the bit-width of the time-division multiplexing based on the maximum bit-width of the input data. With the reduced bit-width, without affecting performance (e.g., adding one more cycle to 10240 cycles, an increase of only one ten-thousandth), a portion of the input data is transmitted first, and the remaining portion is buffered. The remaining portion is then transmitted in the next cycle, performing time-division multiplexing. Similarly, restoration follows a similar reverse process: the data received in the first cycle is temporarily stored, and after the data from the second cycle is received, the two cycles' data are merged and transmitted. For cases with significant bit-width variations, simply increasing the number of registers used for buffering data within the transmitting and target circuit units is sufficient for splitting and concatenating.

[0129] Figure 8 The diagram shows a structural block diagram of a signal passing-through device provided in an exemplary embodiment of this application. The device includes a transmitting module 810, an intermediate module 820, and a target module 830. A first register 821 is provided in the intermediate module 820.

[0130] The transmitting module 810 is used to split the first signal to be penetrated into multiple second signals, and send the multiple second signals to the intermediate module 820 in sequence;

[0131] The intermediate module 820 is used to write each second signal into the first register 821, and to read the second signal from the first register 821 and forward the second signal to the target module 830.

[0132] The size of the first signal is larger than the size of each of the second signals.

[0133] In an optional embodiment, the transmitting module 810 is configured to split the first signal into a plurality of second signals based on the first bit width of the first signal to be penetrated, wherein the second bit width of each of the plurality of second signals is smaller than the first bit width.

[0134] In an optional embodiment, the transmitting module 810 is configured to determine a target bit width and / or a target quantity based on a first bit width of the first signal to be penetrated; and to split the first signal into a plurality of second signals according to the target bit width and / or the target quantity, wherein the number of the plurality of second signals is the target quantity, and the second bit width of each of the plurality of second signals is the target bit width.

[0135] In an optional embodiment, the transmitting module 810 includes a second register 811; the transmitting module 810 is further configured to store a second signal to be transmitted among a plurality of second signals in the second register 811; and to read the second signal to be transmitted from the second register 811.

[0136] In an optional embodiment, the transmitting module 810 is configured to sequentially transmit a plurality of second signals to the intermediate module 820 over a plurality of clock cycles, wherein the plurality of clock cycles correspond one-to-one with the plurality of second signals.

[0137] In an optional embodiment, the first signal is a signal that needs to be transmitted to the target module 830 once every first duration, and the first duration satisfies the duration condition.

[0138] In an optional embodiment, the target module 830 is configured to receive a plurality of second signals in sequence and splice the plurality of second signals to obtain a first signal.

[0139] In an optional embodiment, the target module 830 includes a third register 831; the target module 830 is further configured to store the second signal to be spliced ​​among a plurality of second signals in the third register 831; and read the second signal to be spliced ​​from the third register 831.

[0140] In summary, this application embodiment splits the first signal to be passed through into multiple second signals, thereby transforming the task of passing through the first signal into the task of passing through multiple second signals. The signal passing through device sequentially passes through each second signal, allowing each second signal to reuse the first register on the intermediate module to enhance its driving capability. Therefore, the signal passing through device provided in this application does not require a large number of first registers on the intermediate module. If the first signal is directly passed through, due to its large size, the intermediate module needs to set up many first registers to temporarily store the first signal. However, this application embodiment splits the first signal into multiple second signals using time-division multiplexing, with each second signal smaller than the first signal. In this case, the intermediate module only needs to set up fewer first registers to temporarily store the second signals. This application effectively reduces the area occupied by the first registers on the intermediate module, thereby reducing the static power consumption caused by the first registers.

[0141] Figure 9 A structural block diagram of an electronic device 900 provided in an exemplary embodiment of this application is shown. Optionally, the electronic device 900 includes a through-circuit provided in an embodiment of this application.

[0142] Optionally, the electronic device can be a portable mobile terminal, such as a smartphone, tablet, MP3 player (Moving Picture Experts Group Audio Layer III), MP4 player (Moving Picture Experts Group Audio Layer IV), laptop, or desktop computer. The electronic device 900 may also be referred to as user equipment, portable terminal, laptop terminal, desktop terminal, or other names. Typically, the electronic device 900 includes a processor 901 and a memory 902.

[0143] Processor 901 may include one or more processing cores, such as a quad-core processor or an octa-core processor. Processor 901 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). Processor 901 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 901 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 901 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0144] The memory 902 may include one or more computer-readable storage media, which may be non-transitory. The memory 902 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices.

[0145] In some embodiments, the electronic device 900 may optionally include: a peripheral device interface 903 and at least one peripheral device. Those skilled in the art will understand that... Figure 9 The structure shown does not constitute a limitation on the electronic device 900, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0146] This application also provides a processor that includes a pass-through circuit as described in the above embodiments.

[0147] This application also provides a chip, which includes a processor, and the processor includes a pass-through circuit as described in the above embodiments.

[0148] This application also provides a graphics card that includes a pass-through circuit as described in the above embodiments.

[0149] This application also provides a server, which includes a pass-through circuit as described in the above embodiments.

[0150] Figure 10This illustration shows a schematic diagram of a server structure provided in an exemplary embodiment of this application. The server 1000 includes a plurality of graphics processors 1001, and at least one graphics processor 1001 integrates a pass-through circuit 1002 provided in this application. Figure 10 This illustrates a scenario where each of the multiple graphics processors 1001 integrates a pass-through circuit 1002.

[0151] The sequence numbers of the embodiments in this application are merely for descriptive purposes and do not represent the superiority or inferiority of the embodiments. Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware, or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk. The above descriptions are merely optional embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A through-circuit, characterized in that, The through-circuit includes a transmitting circuit unit, an intermediate circuit unit, and a target circuit unit, wherein a first register is provided in the intermediate circuit unit; The transmitting circuit unit is used to split the first signal that needs to be transmitted to the target circuit unit every first duration into multiple second signals, and sequentially transmit the multiple second signals to the intermediate circuit unit, wherein the first duration is greater than the interval duration threshold. The intermediate circuit unit is used to write each second signal into the first register, and to read the second signal from the first register and forward the second signal to the target circuit unit; The size of the first signal is larger than the size of each of the second signals.

2. The through-circuit according to claim 1, characterized in that, The transmitting circuit unit is configured to split the first signal into a plurality of second signals based on the first bit width of the first signal to be passed through, wherein the second bit width of each of the plurality of second signals is smaller than the first bit width.

3. The through-circuit according to claim 2, characterized in that, The transmitting circuit unit is configured to determine a target bit width based on the first bit width of the first signal to be passed through; and to split the first signal into the plurality of second signals according to the target bit width, wherein the second bit width of each of the plurality of second signals is the target bit width; or, The transmitting circuit unit is configured to determine a target quantity based on a first bit width of the first signal to be penetrated; and to split the first signal into a plurality of second signals according to the target quantity, wherein the number of the plurality of second signals is the target quantity. or, The transmitting circuit unit is configured to determine a target bit width and a target quantity based on the first bit width of the first signal to be penetrated; and to split the first signal into a plurality of second signals according to the target bit width and the target quantity, wherein the quantity of the plurality of second signals is the target quantity, and the second bit width of each of the plurality of second signals is the target bit width.

4. The through-circuit according to any one of claims 1 to 3, characterized in that, The transmitting circuit unit includes a second register; The transmitting circuit unit is further configured to store the second signal to be transmitted among the plurality of second signals in the second register; and to read the second signal to be transmitted from the second register.

5. The through-circuit according to any one of claims 1 to 3, characterized in that, The transmitting circuit unit is used to sequentially transmit the plurality of second signals to the intermediate circuit unit through multiple clock cycles, wherein the plurality of clock cycles correspond one-to-one with the plurality of second signals.

6. The through-circuit according to any one of claims 1 to 3, characterized in that, The target circuit unit is used to receive the plurality of second signals in sequence and splice the plurality of second signals to obtain the first signal.

7. The through-circuit according to claim 6, characterized in that, The target circuit unit includes a third register; The target circuit unit is further configured to store the second signal to be spliced ​​among the plurality of second signals in the third register; and to read the second signal to be spliced ​​from the third register.

8. A signal pass-through method, characterized in that, The method includes: The transmitting circuit unit splits the first signal, which needs to be passed through to the target circuit unit every first duration, into multiple second signals, and sequentially sends the multiple second signals to the intermediate circuit unit, wherein the first duration is greater than the interval duration threshold. The intermediate circuit unit writes each second signal into the first register, reads the second signal from the first register, and forwards the second signal to the target circuit unit; The size of the first signal is larger than the size of each of the second signals.

9. A signal penetration device, characterized in that, The device includes: The sending module is used to split the first signal that needs to be passed through to the target module every first duration into multiple second signals, and send the multiple second signals to the intermediate module in sequence, wherein the first duration is greater than the interval duration threshold. The intermediate module is used to write each second signal into the first register, and to read the second signal from the first register and forward the second signal to the target module; The size of the first signal is larger than the size of each of the second signals.

10. A processor, characterized in that, The processor includes a pass-through circuit as described in any one of claims 1 to 7.

11. A chip, characterized in that, The chip includes a processor, the processor including a pass-through circuit as described in any one of claims 1 to 7.

12. A server, characterized in that, The server includes a pass-through circuit as described in any one of claims 1 to 7.

13. An electronic device, characterized in that, The electronic device includes a processor, the processor including a pass-through circuit as described in any one of claims 1 to 7.

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