Method for generating circuit topology based on transfer function

Abstract

The invention discloses a method for generating circuit topology based on a transfer function, relates to the technical field of circuit design, and solves the technical problem that it is difficult to combine an artificial intelligence method in circuit design to improve the efficiency and reliability of analog circuit design. The method comprises the following steps: based on a graph theory, establishing a connected graph G under a given RLC circuit structure and element parameters; deriving the relationship between the transfer function and the impedance or admittance of the network nodes of the connected graph G based on the RLC circuit; searching and calculating a tree and a secondary tree required by the transfer function, and calculating to obtain a final expression of the transfer function; analyzing the order and the structure of the transfer function, and combining specification constraints and design specifications of circuit design to obtain a circuit design rule; and searching topology and parameters of the RLC circuit through genetic programming to obtain an optimal topological structure and an optimal element admittance value. According to the method, automatic search of genetic programming is guided by analyzing the hard constraint rule set, and the efficiency and reliability of circuit comprehensive design are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design, and in particular to a method for generating circuit topology based on a transfer function. Background Art

[0002] Designing the topology of a circuit is a complex and time-consuming process. Despite the availability of electronic design automation (EDA) tools, designers still need a deep understanding of circuit parameterization and topology variations to create high-quality designs.

[0003] In recent years, various types of artificial intelligence (AI) algorithms, such as evolutionary algorithms, machine learning, and reinforcement learning, have emerged by leveraging human-like learning and reasoning capabilities to effectively learn and optimize circuits, finding optimal circuit parameters that meet given specifications. Such algorithms typically require a target (fitness) function that describes the circuit's performance or quality and may include certain circuit design constraints. Fitness evaluation processes can be categorized into two types: equation-based evaluation, which uses mathematical equations to describe the circuit's behavior, and simulation-based evaluation, which requires Spice simulation software to analyze the circuit. However, the latter is often more difficult to implement and can be more time-consuming due to the interaction between the algorithm compiler and the simulation platform. While most machine learning-based methods offer excellent performance for optimizing analog circuits, they are typically computationally intensive and less flexible than traditional optimization methods. Furthermore, they often lack interpretability of the optimization process, making it difficult for users to understand how the circuit is optimized and the design choices made at each optimization step.

[0004] The transfer function is the ratio of the Laplace transform (or z-transform) of the response (i.e., output) of a linear system under zero initial conditions to the Laplace transform of the stimulus (i.e., input). It is an important mathematical model that describes the relationship between a circuit's input and output. In circuit design, transfer functions can be used to analyze circuit characteristics such as stability and frequency response. For specific circuits, such as filters, transfer functions can be used to calculate parameters such as cutoff frequency, passband attenuation, and stopband attenuation during the design process. Transfer functions can also be used to characterize circuit performance and certain functions. In actual chip design, due to limited chip area, the corresponding module circuit area is also limited. These area limitations are reflected at the schematic level as constraints on component size and number. Given these constraints on component number and size, there is an urgent need to use transfer functions, based on artificial intelligence algorithms, to search for circuit topology and component parameters to improve the efficiency of analog circuit design. Summary of the Invention

[0005] The present invention aims to provide a method for generating circuit topology based on transfer functions, addressing the existing technical problem of difficulty in incorporating artificial intelligence methods into circuit design to improve the efficiency and reliability of analog circuit design. The various technical effects achieved by the preferred technical solutions provided by the present invention are detailed below.

[0006] To achieve the above objectives, the present invention provides the following technical solutions: The present invention provides a method for generating circuit topology based on a transfer function, comprising the following steps: S100: based on graph theory, establishing a connectivity graph G based on the circuit topology under a given RLC circuit structure and component parameters; S200: deducing the relationship between the transfer function and the impedance or admittance of the network nodes of the connectivity graph G based on the RLC circuit; S300: searching for trees and secondary trees required for calculating the transfer function, and calculating and obtaining the final expression of the transfer function of the RLC circuit; S400: analyzing the order and structure of the transfer function based on the transfer function expression, combining the specification constraints and design specifications of the circuit design, obtaining the pre-requirements and constraints for designing heterogeneous circuits as circuit design rules; S500: using the circuit design rules as a hard constraint rule set for algorithmically searching for topology and parameters, searching the topology and parameters of the RLC circuit through genetic programming, and obtaining the optimal topology structure and the optimal component admittance value.

[0007] Preferably, the following steps are also included: S600: outputting the optimal topology structure and the optimal element admittance value, and comparing them with the Bode diagram of the target response H_target of the transfer function to verify the performance.

[0008] Preferably, in step S100, the RLC circuit is a two-port network including port 1 and port 2, forming five element branches: the first branch, the second branch, the third branch, the fourth branch, and the fifth branch; in the RLC circuit, the edges in the circuit are used as the edges of the connected graph G, the nodes in the circuit are used as the nodes of the connected graph G, and the sum of the admittances of all elements on each edge is the value of the edge in the connected graph G.

[0009] Preferably, in the step S200, Based on the parameter matrix Z, the first expression of the transfer function H corresponding to the circuit is obtained: , The parameter matrix Z is defined as: , in, Represent the port voltage of port 1 and port 2 and the port current of port 1 and port 2 respectively; represents the input impedance of port 1; is the first mutual impedance between port 1 and port 2, which indicates the effect of the current of port 2 on the voltage of port 1; is the second mutual impedance between port 1 and port 2, which indicates the effect of the current at port 1 on the voltage at port 2. represents the input impedance of port 2; If port 2 is open, , we get the second expression of the transfer function H: .

[0010] Preferably, the step S300 includes: analyzing the tree and the secondary tree involved in the node admittance based on the second expression of the transfer function H, and obtaining a third expression of the transfer function H based on the topological formula of the two-port network: , The topological formula of the two-port network is: in It represents the sum of the admittance products of all secondary trees in the connected graph G where points a and b are not together. It represents the sum of the admittances of all secondary trees in the connected graph G where ab and cd each form two groups and ab and cd are not together. is the sum of the admittance products of the branches of all trees; calculate the sum of the admittance products of the required tree and the secondary tree, and the admittances after Laplace transformation based on the resistance R, capacitance C and inductance L are respectively , the final expression of the transfer function is as follows, where s is a complex frequency variable: .

[0011] Preferably, in step S400, the order of the transfer function is the order of the highest-order term in the final expression of the transfer function, corresponding to the number of energy storage elements.

[0012] Preferably, in the step S400, the prerequisite requirements and constraints for designing heterogeneous circuits include: under high-frequency alternating current conditions where the complex frequency variable s tends to infinity, if the transfer function H(∞)=0, the circuit cannot have only resistance, and if the transfer function H(∞)≠0, the circuit does not contain series inductance on the main signal path or parallel capacitance to the ground; under direct current conditions, if the transfer function H(0)=0, the circuit is not a pure resistive network, nor is it a structure that allows direct current to pass through, and if the transfer function H(0)≠0, the circuit cannot contain series capacitance on the main signal path or parallel inductance to the ground.

[0013] Preferably, in step S500, searching the topology and parameters of the RLC circuit by genetic programming includes: S510: using the basic building blocks of the RLC circuit as the terminal set of genetic programming; S520: defining the objective function of genetic programming MinimizeCost=Error(H_actual, H_target)+Penalty, where Error represents the root mean square error between the actual response H_actual and the target response H_target of the transfer function calculated at multiple frequency points, and Penalty represents a penalty term for undesirable features; S530: Initialize the genetic population of genetic programming, randomly generate a batch of circuit individuals, each circuit individual is a tree structure including a function set and a terminal set, and remove circuit individuals that violate the hard constraint rule set; S540: Perform a fast local optimization search on the element admittance values ​​in the topological structure of each circuit individual to find the admittance value combination that minimizes its root mean square error Error, and calculate its fitness Cost value; S550: Generate new circuit individuals through crossover or mutation, and immediately verify them with the hard constraint rule set, and discard new circuit individuals that violate the hard constraint rule set; S560: Replace the circuit individuals in the population before S550 with the newly generated, compliant offspring to form a new generation population, and return to step S540 to repeat the entire process until the preset genetic generation is reached or the Cost value converges to within the preset threshold.

[0014] Preferably, the S550 step includes: S551: according to the cost value of the objective function, selecting the elite circuit individual with the lowest cost value to enter the next generation through roulette selection or tournament; S552: performing a reproduction operation on the selected elite circuit individuals to generate new child circuits; S553: ​​exchanging the subtrees of two parent circuits to generate a new circuit structure; S554: randomly changing a part of a circuit individual, or adding a new parallel branch at a node.

[0015] Preferably, the S600 step specifically includes: S610: outputting the circuit individual with the lowest cost value as the target circuit individual, including the complete topology structure and the optimal component admittance value; S620: simulating the target circuit individual in the circuit simulation software, drawing a Bode diagram, and comparing it with the Bode diagram of the target response H_target of the transfer function to verify the performance.

[0016] Implementing one of the above technical solutions of the present invention has the following advantages or beneficial effects: In this embodiment, a connectivity graph model of the circuit is established through graph theory, and based on this, a universal relationship between the circuit transfer function and the impedance / admittance of the network node is derived, thereby constructing a forward mapping from the circuit topology to the mathematical expression. Subsequently, the transfer function is deeply analyzed to extract its order and structure, and the circuit design rules are formed in combination with the specification constraints and design specifications of the circuit design. Based on the circuit design rules, the genetic programming algorithm is guided to conduct an effective search in the search space, avoiding the algorithm from blindly exploring areas that are physically infeasible or irrelevant to performance. The algorithm obtains the optimal topology and the optimal component admittance value by collaboratively optimizing the structure (topology) and parameters (component values) of the circuit, that is, obtaining a complete circuit design scheme including its topology and precise component values. This embodiment guides the automated search of genetic programming by analyzing a set of hard constraint rules, significantly improving the efficiency and reliability of circuit comprehensive design, and realizing the automated design of analog circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive work. In the drawings: Figure 1 is a flow chart of a method for generating a circuit topology based on a transfer function according to an embodiment of the present invention; Figure 2 This is a flow chart of step S500 of a method for generating a circuit topology based on a transfer function according to an embodiment of the present invention; Figure 3 This is a flow chart of step S550 of a method for generating a circuit topology based on a transfer function according to an embodiment of the present invention; Figure 4 This is a flow chart of step S600 of a method for generating a circuit topology based on a transfer function according to an embodiment of the present invention; Figure 5 is an RLC circuit diagram in a method for generating a circuit topology based on a transfer function according to an embodiment of the present invention; Figure 6 It is a connectivity graph G corresponding to the RLC circuit in a method for generating circuit topology based on a transfer function in an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to make the objects, technical solutions and advantages of the present invention clearer, the various exemplary embodiments to be described below will refer to the corresponding drawings, which constitute a part of the exemplary embodiments, in which various exemplary embodiments that may be used to implement the present invention are described. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation methods described in the following exemplary embodiments do not represent all implementation methods consistent with the present disclosure. It should be understood that they are only examples of processes, methods and devices that are consistent with some aspects of the present disclosure as detailed in the appended claims, and other embodiments may also be used, or structural and functional modifications may be made to the embodiments listed herein without departing from the scope and essence of the present invention.

[0019] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "transverse" and the like indicate the orientation or positional relationship based on the figures, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the elements referred to must have a specific orientation, be constructed and operated in a specific orientation. The terms "first", "second" and the like are only used for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. The term "multiple" means two or more. The terms "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, an integral connection, a mechanical connection, an electrical connection, a communication connection, a direct connection, an indirect connection through an intermediate medium, and can be the internal connection of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more related listed items. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0020] In order to illustrate the technical solution of the present invention, a specific embodiment is provided below, in which only the parts related to the embodiment of the present invention are shown.

[0021] Example: like Figure 1As shown, the present invention provides a method for generating circuit topology based on transfer function, comprising the following steps: S100: Based on graph theory, a connectivity graph G based on circuit topology is established under the structure and component parameters of a given RLC circuit, wherein any two points in the connectivity graph G are connected, intuitively representing the connection relationship between edges and nodes in the RLC circuit; a graph in graph theory is a figure composed of a number of given points and lines connecting two points, and such a figure is usually used to describe a certain specific relationship between certain things, using points to represent things and using a line connecting two points to represent that the corresponding two things have such a relationship. S200: Based on the RLC circuit, the relationship between the transfer function and the impedance or admittance of the network nodes of the connected graph G is derived; S300: The tree and secondary tree required for calculating the transfer function are searched, and the final expression of the transfer function of the RLC circuit is calculated; S400: Based on the transfer function expression (the transfer function is usually represented by H(s), and its essence is to describe the ratio between the Laplace transform of the output signal and the Laplace transform of the input signal, reflecting the close connection between the input signal and the output signal, and enabling a clearer understanding of the dynamic characteristics of the circuit; the transfer function can be used to predict and optimize the response of the circuit under different input signals), the order and structure of the transfer function are analyzed, and the design of heterogeneous circuits is obtained by combining the specification constraints and design specifications of the circuit design. Pre-requirements and constraints are used as circuit design rules; S500: the circuit design rules are used as a hard constraint rule set for the algorithm to search for topology and parameters. In this embodiment, the hard constraint rule set is as follows: ① The circuit must contain at least 3 energy storage elements; ② The circuit must have a structure that can make the transfer function H(0)=0 (such as a main circuit series capacitor or a main circuit series inductor); ③ The circuit prohibits any structure that can make the transfer function H(∞)=0 (such as a main circuit series capacitor or a main circuit series inductor); ④ The circuit prohibits any form of LC trap structure; ⑤ Due to the minimum phase, the ladder network topology is given priority; then the circuit topology and parameters are searched through genetic programming to obtain the optimal topology structure and the optimal component admittance value, that is, the complete circuit design solution.

[0022] In this embodiment, a connectivity graph model of the circuit is established through graph theory, and based on this, a universal relationship between the circuit transfer function and the impedance / admittance of the network node is derived, thereby constructing a forward mapping from the circuit topology to the mathematical expression. Subsequently, the transfer function is deeply analyzed to extract its order and structure, and the circuit design rules are formed in combination with the specification constraints and design specifications of the circuit design. Based on the circuit design rules, the genetic programming algorithm is guided to conduct an effective search in the search space, avoiding the algorithm from blindly exploring areas that are physically infeasible or irrelevant to performance. The algorithm obtains the optimal topology and the optimal component admittance value by collaboratively optimizing the structure (topology) and parameters (component values) of the circuit, that is, obtaining a complete circuit design scheme including its topology and precise component values. This embodiment guides the automatic search of genetic programming by analyzing the hard constraint rule set, significantly improving the efficiency and reliability of circuit comprehensive design, and realizing the automated design of analog circuits.

[0023] As an optional implementation, the following steps are also included: S600: output the optimal topology and the optimal component admittance value (admittance is the inverse of impedance, which is used to characterize the circuit's ability to conduct current. The component admittance value at this time is a combination of the admittance values ​​of resistance, inductance, and capacitance), and compare it with the Bode diagram of the target response H_target of the transfer function to verify the performance, thereby verifying through simulation that its frequency response is highly consistent with the target transfer function. The Bode diagram is an important tool for analyzing the frequency response of linear non-time-varying systems. It helps engineers evaluate system stability by depicting how the gain (amplitude) and phase of the transfer function change with frequency. Figure 4 As shown, it specifically includes: S610: outputting the circuit individual with the lowest Cost value as the target circuit individual, and the target circuit individual includes a complete topology structure and an optimal component admittance value; S620: simulating the target circuit individual in circuit simulation software (such as the SPICE simulator on the Android platform), drawing a Bode plot, and comparing it with the Bode plot of the target response H_target of the transfer function. For example, by utilizing the additivity of the Bode plot, the amplitude-frequency / phase-frequency curves of multiple systems are drawn in the same coordinate system, and the differences are directly observed. The performance can be verified by comparing the two Bode plots.

[0024] As an optional implementation, Figure 5 、 Figure 6 As shown, in step S100, the RLC circuit is a two-port network including port 1 (terminal 1-1') and port 2 (terminal 2-2'), forming a first branch ( Figure 6 Middle Branch 1), Second Branch ( Figure 6 Middle Branch Road 2), Third Branch Road ( Figure 6 Middle Branch Road 3), Fourth Branch Road ( Figure 6 Middle Branch Road 4), Fifth Branch Road ( Figure 6In the RLC circuit, the edges in the circuit are regarded as the edges of the connected graph G, and the nodes in the circuit are regarded as the nodes of the connected graph G. The sum of the admittances of all elements on each edge is the value of the edge in the connected graph G. Specifically, Figure 5 As shown, the RLC circuit includes resistors R1 and R2, capacitors C1 and C2, and an inductor L; the first plate of capacitor C1 is connected to terminal 1 and one end of resistor R1, and the second plate is connected to terminal 2, one end of resistor R2, and one end of inductor L; one end of resistor R1 is connected to terminal 1 and the first plate of capacitor C1, and the other end is connected to the first plate of capacitor C2 and one end of resistor R2; one end of resistor R2 is connected to the first plate of capacitor C2 and one end of resistor R1, and the other end is connected to the second plate of capacitor C1, resistor R2, and terminal 2; the first plate of capacitor C2 is connected to resistor R1, resistor R2, second plate terminal 1', terminal 2', and inductor L; one end of inductor L is connected to resistor R2, second plate terminal 2 of capacitor C1, and the other end is connected to the second plate of capacitor C2, terminal 1', and terminal 2'; wherein, , , , , .

[0025] As an optional implementation, in step S200, a first expression of the transfer function H corresponding to the circuit is obtained based on the parameter matrix Z: , The parameter matrix Z is defined as: , in, Represent the port voltage of port 1 and port 2 and the port current of port 1 and port 2 respectively; represents the input impedance of port 1; is the first mutual impedance between port 1 and port 2, which indicates the effect of the current of port 2 on the voltage of port 1; is the second mutual impedance between port 1 and port 2, which indicates the effect of the current at port 1 on the voltage at port 2. Indicates the input impedance of port 2; based on the open circuit of port 2 , we get the second expression of the transfer function H: .

[0026] As an optional implementation, step S300 includes: Based on the second expression of the transfer function H, the tree and the secondary tree involved in the node admittance are analyzed. The tree of the connected graph G corresponds to a subgraph of the connected graph G, and satisfies connectivity, contains all nodes and does not contain loops. The tree of the connected graph G is a secondary tree if any edge is removed. Based on the topological formula of the two-port network, the third expression of the transfer function H is obtained: , The topological formula of the two-port network is: in (a represents 1, b represents 1', The expression is used for convenience of expression) represents the sum of the admittance products of all secondary trees in the connected graph G where points a and b are not together. Indicates ab, cd in the connected graph G (ab represents 12, 12', cd represents 1'2, 1'2', The expression is for convenience of expression) The sum of the admittances of all secondary trees that form two groups and ab and cd are not together, is the sum of the branch admittance products of all trees; The sum of the admittance products of the required tree and the secondary tree is calculated. The specific calculation process of the tree required for calculating the transfer function and the secondary tree is: like Figure 6 As shown, The corresponding tree has the following branches: 12, 23, 34, 45, 14, 15, 25, 35, so we get: in is the admittance after Laplace transformation on branch a; The corresponding tree has the following branches: 12 branches, 23 branches, 15 branches, 25 branches, thus we get: There is no corresponding tree, so Thus we get: , The admittances after Laplace transformation based on resistance R, capacitance C and inductance L are , the final expression of the transfer function is as follows, where s is a complex frequency variable: .

[0027] As an optional implementation, in step S400, a new passive two-port network is designed based on the final expression of the transfer function, and has the same transfer function as the initial circuit network. The order of the transfer function is the order of the highest-order term in the final expression of the transfer function, which corresponds to the number of energy storage elements. Specifically, based on the analysis of the given transfer function, corresponding constraints are formulated: the poles and order of the transfer function are analyzed, and the pole analysis is performed using existing numerical methods. The order is taken from the order of the highest-order term in the final expression of the transfer function; the order of the transfer function corresponds to the number of energy storage elements (capacitors and inductors). The specific corresponding relationship is shown in Table 1. Among them, the cascade is a circuit structure formed by sequentially connecting several (two for a two-stage cascade, three for a three-stage cascade, and multiple for multiple cascades) identical resistor-capacitor (RC) low-pass filter units in series.

[0028] Table 1 The number of capacitor and inductor components corresponding to the order of the transfer function Furthermore, the poles in the circuit's denominator are implemented by resonant circuits formed by series inductors and capacitors. Ensure that the configuration of these components is consistent with the transfer function's denominator polynomial. Each pole is configured with an RLC branch, with the resistor adjusting damping and the inductor and capacitor collectively regulating the resonant frequency. Zeros can be implemented using specialized LC networks. If the transfer function's numerator is a high-order polynomial, multiple LC networks in parallel or series are required to ensure that the zero locations match the transfer function's numerator coefficients. The implementation of each zero must adhere to circuit symmetry and simplifying rules to minimize component count.

[0029] As an optional implementation, in the step S400, the pre-requirements and constraints for designing heterogeneous circuits include: under high-frequency alternating current conditions where the complex frequency variable s tends to infinity, in the RLC circuit, the complex frequency variable s is the core mathematical tool for describing the dynamic characteristics of the system, defined as s=σ+jω (σ is the attenuation coefficient, ω is the angular frequency, j is the imaginary unit, σ is the real part, ω is the imaginary part), which is used to convert the time domain differential equation into an algebraic equation in the complex frequency domain to simplify the circuit response analysis; if the transfer function H(∞)=0, that is, the final expression of the transfer function If the value corresponding to the formula is 0, then the circuit cannot contain only resistance. If the transfer function H(∞)≠0, that is, the value corresponding to the final expression of the transfer function is not 0, then the circuit does not contain a series inductor (high-frequency open circuit) or a shunt capacitor to ground (high-frequency short circuit) on the main signal path. Under DC conditions, the complex frequency variable s tends to 0. If the transfer function H(0)=0, then the circuit is not a pure resistive network, nor is it a structure that allows DC to pass through. If the transfer function H(0)≠0, then the circuit cannot contain a series capacitor on the main signal path or a shunt inductor to ground. In this embodiment, if the transfer function H(∞)≈1, that is, the value corresponding to the final expression of the transfer function is approximately equal to 1, then there cannot be a shunt capacitor to ground or a series inductor on the main signal path in the circuit. If the transfer function H(0)=0, then the circuit cannot be a pure resistive network, nor can it be a structure that allows DC to pass through (such as a series inductor in the main path or a shunt capacitor to ground). It also implies that there is a series capacitor or a shunt inductor in the circuit to block DC signals.

[0030] As an optional implementation, Figure 2As shown, in step S500, searching for the topology and parameters of the circuit through genetic programming includes: S510: using the basic building blocks of the RLC circuit as the terminal set of genetic programming, thereby defining the basic elements of genetic programming. The terminal set is the "basic element set" that constitutes the program tree structure in genetic programming. It serves as the "leaf node" of the program tree and is used to provide original input and limit the scope of the solution space. In this embodiment, the basic building blocks of the RLC circuit include: a resistor R, an inductor L, and a capacitor C (each element has a to-be-determined continuous admittance value); input / output ports Vin, Vout, and GND; a function set that combines the elements (a non-terminal symbol in genetic programming, used to define the operation mode or combination mode in the circuit structure); and a connector (a connector is a specific member of the function set, such as Series(A, B) indicates connecting elements A and B in series, Parallel(A, B) indicates connecting elements A and B in parallel, Shunt(A) indicates connecting A to ground, and Bridge(A, B) indicates creating a bridge connection). S520: Define the objective function of genetic programming (the objective function, also known as the fitness function, is used to quantitatively evaluate the quality of the program tree or expression generated by genetic programming and drives the direction of genetic programming evolution): Minimize Cost = Error(H_actual, H_target) + Penalty. Error represents the root mean square error between the actual transfer function response H_actual and the target response H_target calculated at multiple frequency points, and Penalty represents a penalty for undesirable features (such as too many components). The user can set this value based on actual needs. Therefore, minimizing the value of Error(H_actual, H_target) + Penalty on the right side of the expression drives the genetic programming process. S530: Initialize the genetic population for genetic programming and randomly generate a batch of individual circuits, i.e., multiple RLC circuits. Each individual circuit is a tree structure consisting of a function set (non-leaf nodes in the genetic programming tree structure) and a terminal set (leaf nodes in the genetic programming tree structure). Individual circuits that violate the hard constraint rule set are removed to ensure that the remaining individual circuits meet the hard constraint rule requirements, thereby improving the accuracy and efficiency of the genetic programming search. For example, if a circuit with a parallel capacitor is generated, violating the second rule of the hard constraint rule set, it is immediately discarded and regenerated until a compliant circuit individual is obtained, ensuring that the genetic programming search begins from a valid starting point. S540: Evaluate the fitness of each circuit individual in the population.A rapid local optimization search is performed on the admittance values ​​of the components in the topology of each individual circuit (e.g., using simple particle swarm optimization, which simulates the collaborative behavior of biological groups, such as birds foraging or fish schools, by sharing information between particles to find the optimal solution). The combination of admittance values ​​that minimizes the root mean square error (RMSE) is found, and its fitness cost is calculated. S550: Population evolution is performed to produce reliable circuit individuals. New circuit individuals are generated through crossover or mutation and immediately validated using a set of hard constraint rules. New circuit individuals that violate the hard constraint rules are discarded. Any offspring that violate the hard constraint rules are discarded to prevent invalid solutions from contaminating the population. S560: The circuit individuals in the population before S550 are replaced with the newly generated, compliant offspring to form a new population. The process then returns to step S540 and repeats until the preset number of generations is reached or the cost converges to within a preset threshold. Both the preset number of generations and the preset threshold can be set as needed.

[0031] As an optional implementation, Figure 3 As shown, step S550 includes: S551: Based on the cost value of the objective function, the elite circuit individuals with the lowest cost value are selected to enter the next generation through roulette selection (distributing probabilities according to fitness ratio, similar to randomly hitting individuals when a roulette wheel is turned) or tournament selection (randomly selecting two or more individuals and only retaining the ones with the highest fitness); S552: breeding the selected elite circuit individuals to generate new offspring circuits; S553: ​​exchanging the subtrees of the two parent circuits, which is the crossover operation in genetic programming, to generate a new circuit structure; S554: randomly changing a part of a circuit individual, such as changing the resistor R to the inductor L, or adding a new parallel branch at a node, which is the mutation operation in genetic programming.

[0032] The embodiment is only a special example and does not represent only one way of implementing the present invention.

[0033] The foregoing is merely a preferred embodiment of the present invention. Those skilled in the art will appreciate that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. Furthermore, under the guidance of the present invention, these features and embodiments may be modified to suit specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are intended to be within the scope of the present invention.

Claims

1. A method for generating circuit topology based on transfer function, characterized in that: The following steps are involved: S100: Based on graph theory, establish a connectivity graph G based on circuit topology under the given structure and component parameters of the RLC circuit; S200: Derivation of a relationship between a transfer function and an impedance or admittance of a network node of a connected graph G based on an RLC circuit; S300: searching for a tree and a secondary tree required for calculating a transfer function, and calculating and obtaining a final expression of the transfer function of the RLC circuit; S400: Analyzing the order and structure of the transfer function based on the transfer function expression, and combining the circuit design specification constraints and design specifications to obtain the pre-requirements and constraints for designing heterogeneous circuits as circuit design rules; S500: Using circuit design rules as a hard constraint rule set for algorithmic search of topology and parameters, searching the topology and parameters of the RLC circuit through genetic programming to obtain the optimal topology structure and the optimal component admittance value.

2. The method for generating a circuit topology based on a transfer function according to claim 1, characterized in that: The following steps are also included: S600: Outputs the optimal topology and the optimal component admittance value, and compares them with the Bode plot of the target response H_target of the transfer function to verify the performance.

3. The method for generating circuit topology based on transfer function according to claim 1, characterized in that: In step S100, the RLC circuit is a two-port network including port 1 and port 2, forming five element branches: a first branch, a second branch, a third branch, a fourth branch, and a fifth branch. In the RLC circuit, the edges in the circuit are used as the edges of the connected graph G, the nodes in the circuit are used as the nodes of the connected graph G, and the sum of the admittances of all elements on each edge is the value of the edge in the connected graph G.

4. The method for generating a circuit topology based on a transfer function according to claim 3, characterized in that: In the step S200, Based on the parameter matrix Z, the first expression of the transfer function H corresponding to the circuit is obtained: ， The parameter matrix Z is defined as: ， in, Represent the port voltage of port 1 and port 2 and the port current of port 1 and port 2 respectively; represents the input impedance of port 1; is the first mutual impedance between port 1 and port 2, which indicates the effect of the current of port 2 on the voltage of port 1; is the second mutual impedance between port 1 and port 2, which indicates the effect of the current at port 1 on the voltage at port 2. represents the input impedance of port 2; If port 2 is open, , we get the second expression of the transfer function H: 。 5. The method for generating circuit topology based on transfer function according to claim 4, characterized in that: The step S300 includes: Based on the second expression of the transfer function H, the tree and the secondary tree involved in the node admittance are analyzed, and the third expression of the transfer function H is obtained based on the topological formula of the two-port network: ， The topological formula of the two-port network is: in It represents the sum of the admittance products of all secondary trees in the connected graph G where points a and b are not together. It represents the sum of the admittances of all secondary trees in the connected graph G where ab and cd each form two groups and ab and cd are not together. is the sum of the branch admittance products of all trees; Calculate the sum of the admittance products of the required tree and the secondary tree, and the admittances after Laplace transformation based on the resistance R, capacitance C and inductance L are , the final expression of the transfer function is as follows, where s is a complex frequency variable: 。 6. The method for generating circuit topology based on transfer function according to claim 1, characterized in that: In step S400 , the order of the transfer function is the order of the highest-order term in the final expression of the transfer function, which corresponds to the number of energy storage elements.

7. The method for generating circuit topology based on transfer function according to claim 1, characterized in that: In the step S400, the prerequisite requirements and constraints for designing heterogeneous circuits include: under high-frequency alternating current conditions where the complex frequency variable s tends to infinity, if the transfer function H(∞)=0, then the circuit cannot have only resistance; if the transfer function H(∞)≠0, then the circuit does not contain series inductance on the main signal path or parallel capacitance to the ground; under direct current conditions, if the transfer function H(0)=0, then the circuit is not a pure resistive network, nor is it a structure that allows direct current to pass; if the transfer function H(0)≠0, then the circuit cannot contain series capacitance on the main signal path or parallel inductance to the ground.

8. The method for generating circuit topology based on transfer function according to claim 1, characterized in that: In step S500, searching the topology and parameters of the RLC circuit by genetic programming includes: S510: Using the basic building blocks of RLC circuits as terminal sets for genetic programming; S520: Define the objective function of genetic programming: Minimize Cost = Error (H_actual, H_target) + Penalty, where Error represents the root mean square error between the actual response H_actual and the target response H_target of the transfer function calculated at multiple frequency points, and Penalty represents a penalty term for undesirable features. S530: Initializing the genetic population of genetic programming, randomly generating a batch of circuit individuals, each circuit individual having a tree structure including a function set and a terminal set, and removing circuit individuals that violate the hard constraint rule set; S540: Perform a fast local optimization search on the admittance values ​​of the components in the topological structure of each individual circuit to find the admittance value combination that minimizes its root mean square error (Error), and calculate its fitness cost value; S550: Generate new circuit individuals through crossover or mutation, and immediately verify them using the hard constraint rule set, and discard new circuit individuals that violate the hard constraint rule set; S560: Replace the circuit individuals in the population before S550 with the newly generated, compliant offspring to form a new generation population, and return to step S540 to repeat the entire process until the preset genetic generation is reached or the cost value converges to within the preset threshold.

9. The method for generating a circuit topology based on a transfer function according to claim 8, characterized in that: The S550 step includes: S551: According to the cost value of the objective function, the elite circuit individual with the lowest cost value is selected through roulette wheel selection or tournament to enter the next generation; S552: Perform reproduction operations on the selected elite circuit individuals to generate new offspring circuits; S553: ​​swap the subtrees of the two parent circuits to generate a new circuit structure; S554: Randomly change a part of a circuit entity, or add a new parallel branch at a node.

10. The method for generating circuit topology based on transfer function according to claim 2, characterized in that: The step S600 specifically includes: S610: Outputting the circuit individual with the lowest cost value as the target circuit individual, including the complete topology structure and the optimal component admittance value; S620: Simulate the target circuit in circuit simulation software, draw a Bode plot, and compare it with the Bode plot of the target response H_target of the transfer function to verify the performance.

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