Verification method and device, electronic equipment, storage medium and program product

Abstract

The present disclosure relates to a verification method and device, electronic equipment, storage medium and program product, and relates to the field of chip verification. The method comprises: performing arbitration operation using a to-be-verified model, and outputting a first result; calling a target reference model, taking the arrangement order of the request channel numbers in the first queue of the target reference model as the polling order, simulating the arbitration behavior of the to-be-verified model through queue polling, and obtaining a second result; and comparing the first result with the second result to determine a verification result. The embodiments of the present disclosure avoid complex timing level modeling, the target reference model takes the arrangement order of the request channel numbers in the first queue as the polling order, simulates the arbitration behavior of the to-be-verified model through queue polling, is conducive to sufficient verification of the to-be-verified model, and greatly reduces the complexity and input cost of verification.

Description

Technical Field

[0001] This disclosure relates to the field of chip verification, and more particularly to a verification method and apparatus, electronic device, storage medium and program product. Background Technology

[0002] During the chip design process, verification is necessary to ensure the correctness of the design and guarantee that the manufactured chip meets the design objectives and expected functions. In chip verification, reference models of hardware modules can be built as needed to fully verify the chip design.

[0003] For chip designs integrating polling arbitrators, achieving a polling arbitrator model consistent with the hardware circuitry requires timing-level modeling. Without establishing a timing model of the polling arbitrator, relying solely on fuzzy comparisons of the final interface output makes it difficult to guarantee the correctness of the arbitration results, increasing the risk of future chip design issues. While timing-level modeling fully simulates the timing characteristics and logical relationships of the hardware circuitry, it demands enormous manpower and time investment in verification and development. Summary of the Invention

[0004] This disclosure presents a verification method and apparatus, electronic device, storage medium, and program product.

[0005] According to one aspect of this disclosure, a verification method is provided, comprising: using a model to be verified to perform an arbitration operation on at least one request signal and outputting a first result; invoking a target reference model and using the order of request channel numbers in a first queue of the target reference model as the polling order to simulate the arbitration behavior of the model to be verified on the at least one request signal through queue polling to obtain a second result; and comparing the first result with the second result to determine a verification result.

[0006] In one possible implementation, the method for constructing the target reference model includes: describing the behavior of the polling arbitrator in software using a hardware description language to obtain an initial reference model; setting a first queue and a second queue for the initial reference model to obtain the target reference model, wherein the second queue is used to store the interface sampling data of the model to be verified, and the first queue is used to store the request channel number of the model to be verified.

[0007] In one possible implementation, the method further includes: obtaining specification information of the model to be verified, the specification information indicating the maximum number of arbitrable request signals of the model to be verified each time; constructing a sampling interface for the model to be verified in a chip verification system according to the specification information, wherein the sampling interface is used to sample the model to be verified, and storing the sampled interface sampling data of the model to be verified into the second queue of the target reference model.

[0008] In one possible implementation, the interface sampling data includes N bits of data, a first identifier, and a second identifier. The N bits of data are used to indicate the validity of the request signals of the N request channels of the model to be verified. The first identifier is used to indicate whether at least one request channel has a valid request signal. The second identifier is used to indicate whether the model to be verified has successfully arbitrated. N is an integer greater than 1.

[0009] In one possible implementation, the step of invoking the target reference model, using the order of request channel numbers in the first queue of the target reference model as the polling order, simulates the arbitration behavior of the model to be verified against the at least one request signal through queue polling to obtain a second result, including: in response to the model to be verified completing the arbitration operation and outputting the first result, if the first identifier in the second queue is a first identifier value and the second identifier is a second identifier value, obtaining the second result according to the first queue and the second queue of the target reference model, wherein the first identifier value indicates that the request signal of at least one request channel is valid, and the second identifier value indicates that the arbitration of the model to be verified is successful.

[0010] In one possible implementation, obtaining the second result based on the first queue and the second queue of the target reference model includes: determining whether the request signal corresponding to the request channel number in the second queue is empty based on the request channel number stored at the head of the first queue; if the request signal corresponding to the request channel number in the second queue is not empty, taking the request signal corresponding to the request channel number as the second result, and arranging the request channel number stored at the head of the first queue to the tail of the first queue as the first queue corresponding to the next round of arbitration operation of the target reference model.

[0011] In one possible implementation, the method further includes: when the request signal corresponding to the request channel number in the second queue is empty, arranging the request channel number stored at the head of the first queue to the tail of the first queue to obtain an updated first queue; continuing to determine whether the request signal corresponding to the request channel number in the second queue is empty based on the request channel number stored at the head of the updated first queue, until the second result of the target reference model is obtained.

[0012] In one possible implementation, setting up a first queue and a second queue for the initial reference model to obtain the target reference model includes: obtaining specification information of the model to be verified, the specification information indicating the maximum number of arbitrable request signals for each time the model to be verified; setting up the first queue and the second queue for the initial reference model according to the specification information to obtain the target reference model, wherein the depth of the first queue and the second queue is determined by the specification information.

[0013] According to one aspect of this disclosure, a verification apparatus is provided, comprising: a first module for arbitrating at least one request signal using a model to be verified and outputting a first result; a second module for invoking a target reference model and simulating the arbitration behavior of the model to be verified on the at least one request signal by polling the queue in the order of the request channel numbers in a first queue of the target reference model, thereby obtaining a second result; and a comparison module for comparing the first result with the second result to determine a verification result.

[0014] In one possible implementation, the verification device further includes a construction module for constructing the target reference model, comprising: describing the behavior of the polling arbitrator in software using a hardware description language to obtain an initial reference model; setting a first queue and a second queue for the initial reference model to obtain the target reference model, wherein the second queue is used to store interface sampling data of the model to be verified, and the first queue is used to store the request channel number of the model to be verified.

[0015] In one possible implementation, the apparatus further includes a sampling interface construction module, configured to: acquire specification information of the model to be verified, the specification information indicating the maximum number of arbitrable request signals for each time the model to be verified; construct a sampling interface for the model to be verified in a chip verification system based on the specification information, wherein the sampling interface is used to sample the model to be verified, and store the sampled interface sampling data of the model to be verified into a second queue of the target reference model.

[0016] In one possible implementation, the interface sampling data includes N bits of data, a first identifier, and a second identifier. The N bits of data are used to indicate the validity of the request signals of the N request channels of the model to be verified. The first identifier is used to indicate whether at least one request channel has a valid request signal. The second identifier is used to indicate whether the model to be verified has successfully arbitrated. N is an integer greater than 1.

[0017] In one possible implementation, the second module is configured to: output the first result in response to the model to be verified completing the arbitration operation, and, if the first identifier in the second queue is a first identifier value and the second identifier is a second identifier value, obtain the second result according to the first queue and the second queue of the target reference model, wherein the first identifier value indicates that there is a valid request signal for at least one request channel, and the second identifier value indicates that the arbitration of the model to be verified is successful.

[0018] In one possible implementation, obtaining a second result based on the first queue and the second queue of the target reference model includes: determining whether the request signal corresponding to the request channel number in the second queue is empty based on the request channel number stored at the head of the first queue; if the request signal corresponding to the request channel number in the second queue is not empty, taking the request signal corresponding to the request channel number as the second result, and arranging the request channel number stored at the head of the first queue to the tail of the first queue as the first queue corresponding to the next round of arbitration operation of the target reference model.

[0019] In one possible implementation, the second module is further configured to: when the request signal corresponding to the request channel number in the second queue is empty, arrange the request channel number stored at the head of the first queue to the tail of the first queue to obtain an updated first queue; continue to determine whether the request signal corresponding to the request channel number in the second queue is empty based on the request channel number stored at the head of the updated first queue, until the second result of the target reference model is obtained.

[0020] In one possible implementation, setting a first queue and a second queue for the initial reference model to obtain a target reference model includes: obtaining specification information of the model to be verified, the specification information indicating the maximum number of arbitrable request signals for each time the model to be verified; setting the first queue and the second queue for the initial reference model according to the specification information to obtain the target reference model, wherein the depth of the first queue and the second queue is determined by the specification information.

[0021] According to one aspect of this disclosure, an electronic device is provided, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to perform the method described above.

[0022] According to one aspect of this disclosure, a computer-readable storage medium is provided that stores computer program instructions thereon, which, when executed by a processor, implement the above-described method.

[0023] According to one aspect of this disclosure, a computer program product is provided, including computer program instructions that, when executed by a processor, implement the above-described method.

[0024] In this embodiment of the disclosure, the model to be verified is used to arbitrate at least one request signal and output a first result; the target reference model is invoked, and the polling order is based on the order of the request channel numbers in the first queue of the target reference model. The arbitration behavior of the model to be verified on at least one request signal is simulated by the queue polling to obtain a second result; the first result and the second result are compared to determine the verification result.

[0025] In comparison with related technologies, chip verification work involves building reference models (e.g., software simulation models) for hardware modules (such as polling arbitrators) as needed. Modeling the polling arbitrator is particularly challenging. To achieve a reference model consistent with the hardware circuitry, timing-level modeling is required, fully simulating the timing and logic of the hardware circuitry. This ensures that the multi-factor inputs of the reference model are strictly consistent with the actual inputs of the model to be verified, and timing alignment is also essential. This places significant demands on the manpower and time required for verification development. Without establishing a timing model, relying solely on fuzzy comparisons of the final interface output makes it difficult to guarantee the correctness of the arbitration results, increasing the risk of future chip failures.

[0026] The verification method of this disclosure avoids complex time-series modeling by setting a first queue in the target reference model. The target reference model can use the order of request channel numbers in the first queue as the polling order to simulate the arbitration behavior of the model to be verified. This avoids complex time-series modeling. By setting a first queue, request channel numbers can be stored according to preset rules, abstracting the originally complex time-series relationship into a simple queue order relationship, greatly simplifying time-series processing. For example, an initial polling order can be set for the first queue. Then, whenever the model to be verified performs an arbitration operation, the target reference model can be called once. The target reference model updates the first queue according to preset rules each time it simulates arbitration behavior, so as to obtain the polling order for the next round of simulated arbitration behavior (i.e., the polling order used for the next call to the target reference model). This aligns the time-series of the target reference model and the model to be verified, facilitating thorough verification of the model to be verified and greatly reducing the complexity and cost of verification.

[0027] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0028] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0029] Figure 1 A flowchart illustrating a verification method according to an embodiment of this disclosure is shown.

[0030] Figure 2 A schematic diagram of a model to be verified according to an embodiment of this disclosure is shown.

[0031] Figure 3 A block diagram of a verification apparatus according to an embodiment of the present disclosure is shown.

[0032] Figure 4 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0033] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0034] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0035] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0036] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0037] Figure 1 A flowchart illustrating a verification method according to an embodiment of this disclosure is shown, such as... Figure 1 As shown, the verification method may include:

[0038] In step S11, the model to be verified is used to arbitrate at least one request signal, and a first result is output.

[0039] In step S12, the target reference model is invoked, and the polling order is based on the order of the request channel numbers in the first queue of the target reference model. The arbitration behavior of the model to be verified on at least one request signal is simulated by the queue polling to obtain the second result.

[0040] In step S13, the first result and the second result are compared to determine the verification result.

[0041] In one possible implementation, the verification method of this disclosure embodiment can be executed by an electronic device such as a terminal device or a server. The terminal device can be a user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, in-vehicle device, wearable device, etc. The verification method can be implemented by a processor calling computer-readable instructions stored in memory. Alternatively, the verification method can be executed by a server. A chip verification system, such as a Universal Verification Methodology (UVM) verification platform, can be deployed on the electronic device. This application does not limit the type of chip verification system.

[0042] In one possible implementation, in step S11, the model to be verified is a register transfer level model used in the chip verification system to simulate a polling arbitrator. The model to be verified in the chip verification system can be used to arbitrate at least one request signal and output a first result.

[0043] Arbitrators can be used to manage contentious access to shared resources (such as buses and memory) from multiple requesters (e.g., devices, interrupt sources), ensuring that resources are used by only one requester at a time and avoiding conflicts. A commonly used arbitrator is the round-robin arbitrator, whose main function is to receive request signals from multiple requesters and allocate resources in turn, ensuring that each requester has a fair opportunity to access the resource. In hardware circuits, round-robin arbitrators can be used to manage shared resources, ensuring efficient system operation and effectively improving system performance and fairness through a fair round-robin arbitration strategy.

[0044] The request signal from the model to be verified can originate from the driver of the chip verification system. The driver continuously applies different stimulus signals to the model as its request signal, thereby providing a simulated real-world input scenario for the model. The driver can set different request signals at different times based on user input commands. Alternatively, the driver can randomly generate different request signals at different times. The embodiments of this disclosure do not limit the specific method by which the driver generates the request signal.

[0045] It should be understood that in a chip verification system, since the driver can generate request signals that conform to various interface protocols, the driver can generate request signals with different functions according to different scenarios.

[0046] For example, in a scenario where multiple devices simultaneously initiate access requests to the memory, it's equivalent to multiple devices being upstream of the model to be verified and the memory being downstream. In this case, the request signal applied by the driver to the model to be verified is an access request signal. The model to be verified can be used to arbitrate at least one access request signal and output a first result.

[0047] For example, in a scenario where multiple peripherals (such as keyboards, mice, timers, etc.) simultaneously send interrupt requests to the processor, it's equivalent to the upstream of the model to be verified being multiple peripherals, and the downstream being the processor. In this case, the request signal applied by the driver to the model to be verified is an interrupt request signal. The model to be verified can be used to arbitrate at least one interrupt request signal and output a first result.

[0048] The request signals may include signals for various functions such as access requests, read requests, write requests, calculation requests, and interrupt requests. The embodiments of this disclosure do not specifically limit the functional categories of the request signals.

[0049] In one possible implementation, in step S12, whenever the model to be verified completes the arbitration operation and outputs a first result for at least one request signal input in the current round, the target reference model can be invoked to arbitrate the same at least one request signal in the order of the request channel numbers recorded in the first queue, and obtain a second result.

[0050] The arbitration rule of the target reference model is as follows: in each round, polling starts from the head of the first queue. If the request channel corresponding to a given request channel number does not have a request signal in the current round, that request channel number is skipped, and the polling continues to the next request channel number until a request channel with a request signal is found or the first queue has been traversed. After each round of arbitration, the selected request channel number is moved to the tail of the first queue. The updated order of the request channel numbers recorded in the first queue is then used as the polling order for the next round of arbitration in the target reference model.

[0051] In one possible implementation, in step S13, the first result of the arbitration output of the model to be verified and the second result of the arbitration output of the target reference model can be compared round by round to determine the verification result. If the first result and the second result differ in any round, an error message is output and the verification process restarts; if the first result of the arbitration output of the model to be verified and the second result of the arbitration output of the target reference model are the same in each round, the verification result indicates that the model to be verified has passed the verification.

[0052] In related technologies, reference models are built for hardware modules as needed during chip verification, with polling arbitrators being particularly challenging to model. To achieve a reference model consistent with the hardware circuitry, timing-level modeling is required, fully simulating the timing and logic of the hardware circuitry. This ensures that the multi-factor inputs of the reference model are strictly consistent with the actual inputs of the model to be verified, and timing alignment is also essential. This places significant demands on the manpower and time required for verification development. Without establishing a timing model, relying solely on fuzzy comparisons of the final interface output makes it difficult to guarantee the correctness of the arbitration results, increasing the risk of future chip failures.

[0053] The verification method of this disclosure avoids complex time-level modeling. A first queue is set up in the target reference model to store the request channel numbers of the model to be verified. The polling order is based on the arrangement of the request channel numbers in the first queue of the target reference model. The arbitration behavior of the model to be verified is simulated through queue polling. By setting up the first queue, it is easy to store the request channel numbers according to a preset rule, abstracting the originally complex time-series relationship into a simple queue order relationship, greatly simplifying the processing of time-series data. For example, an initial polling order can be set for the first queue. Then, whenever the model to be verified performs an arbitration operation, the target reference model can be called once. Each time the target reference model simulates arbitration behavior, the first queue is updated according to the preset rule to obtain the polling order for the next round of simulated arbitration behavior of the target reference model (i.e., the polling order used for the next call to the target reference model). This aligns the time-series of the target reference model and the model to be verified, facilitating thorough verification of the model to be verified and greatly reducing the complexity and cost of verification.

[0054] In one possible implementation, the method for constructing the target reference model includes: describing the behavior of the polling arbitrator in software using a hardware description language to obtain an initial reference model; setting a second queue and a first queue for the initial reference model to obtain the target reference model, wherein the second queue is used to store the interface sampling data of the model to be verified, and the first queue is used to store the request channel number of the model to be verified.

[0055] For example, the initial reference model is derived from the logic modeling corresponding to the arbitration behavior of a polling arbitrator based on a hardware description language. It should be understood that this initial reference model is not derived from timing-level modeling; it is a non-timing-level reference model, which significantly reduces development difficulty compared to timing-level reference models. In practical applications, although this initial reference model cannot simulate the timing logic of a polling arbitrator and cannot be directly synchronized with the polling arbitrator's timing, it can still be used to simulate the arbitration behavior logic of a polling arbitrator.

[0056] Hardware description languages ​​(HMRs) offer greater flexibility to developers due to their cross-platform nature—meaning the same initial reference model code can run on different simulation environments or hardware platforms—allowing them to fully utilize various resources. Examples of HMRs include System Verilog (SV), a high-level hardware description and verification language widely used in digital chip design and verification. For instance, a reference model for a polling arbiter can be built using SV. This disclosure does not limit the specific type of hardware description language used.

[0057] After obtaining the initial reference model, a first queue and a second queue can be set for the initial reference model to obtain the target reference model.

[0058] By setting up a first queue and a second queue for the initial reference model, the resulting target reference model can monitor each arbitration action of the model under test to align the timing and synchronize that timing to the target reference model. The model under test is a Register Transfer Level (RTL) model used in the chip verification system to simulate a polling arbitrator. It is an abstract model of synchronous digital circuits, determined based on the flow of digital signals between hardware registers, memories, combinational logic devices, and buses, as well as their logical algebraic operation.

[0059] In the verification environment of the chip verification system, the interface sampling data of the model to be verified can be transferred to the target reference model, and the interface sampling data obtained from each sampling can be stored in the second queue of the target reference model. In addition, a first queue with the same dimension as the number of request channels of the model to be verified is also created in the target reference model. The order of the request channel numbers in the first queue of the target reference model is used as the polling order to simulate a polling arbitrator in a queue polling manner.

[0060] For example, the input of the polling arbitrator simulated by the model to be verified includes N (N is an integer greater than 1) request channels, namely: request channel 1 to request channel N. The first queue can be initialized as 1, 2, 3, ..., N. The request channel number 1 stored at the head of the first queue indicates that request channel 1 has the highest priority, and the request channel number N stored at the tail of the first queue indicates that request channel N has the lowest priority.

[0061] The interface sampling data of the model to be verified can be monitored in real time. Assuming that in the first cycle (corresponding to the first arbitration operation), the excitation signal is applied to request channel 2 and request channel 3 of the model to be verified, by monitoring the interface sampling data of the model to be verified, the interface sampling data of the first cycle can be stored in the second queue. The second and third bits of the N bits of the interface sampling data are set to 1, and the other N-2 bits are set to 0, indicating that only request channel 2 and request channel 3 received the request signal, and the other N-2 request channels did not receive the request signal. The model to be verified can query whether the second bit of the N-bit data in the second queue (that is, the position indicated by the request channel number 2 stored at the head of the first queue) is 1. Since the second bit of the N-bit data included in the interface sampling data is found to be 1, it means that the request channel 2 has applied an excitation signal. The request signal from the request channel 2 can be used as the arbitration result, and the request channel number 2 stored at the head of the first queue is arranged to the tail of the first queue. The first queue is updated to 3, 4, ..., N, 1, 2, which indicates the next arbitration order. Among them, the request channel 3 has the highest priority and the request channel 2 has the lowest priority.

[0062] Assuming that in the second cycle (corresponding to the first arbitration operation), request channels 1 and 3 of the model to be verified applied excitation signals, the interface sampling data of the second cycle can be stored in the second queue by monitoring the interface sampling data of the model to be verified. The first and third bits of the N bits of this interface sampling data are set to 1, and the other N-2 bits are set to 0, indicating that only request channels 1 and 3 received the request signal, and the other N-2 request channels did not receive the request signal. The model to be verified can query whether the third bit of the N bits of data in the second queue (i.e., the position indicated by the request channel number 3 stored at the head of the first queue) is 1. Since the third bit of the N bits of data in the interface sampling data is found to be 1, it indicates that request channel 3 applied an excitation signal. The request signal from request channel 3 can be used as the arbitration result, and the request channel number 3 stored at the head of the first queue is moved to the tail of the first queue. The first queue is updated to 4, ..., N, 1, 2, 3, indicating the next arbitration order, where request channel 4 has the highest priority and request channel 3 has the lowest priority.

[0063] For example, suppose that in the second cycle (corresponding to the first arbitration operation), request channels 1 and 4 of the model to be verified apply excitation signals. By monitoring the interface sampling data of the model to be verified, the interface sampling data of the second cycle can be stored in the second queue. The first and fourth bits of the N bits of the interface sampling data are set to 1, and the other N-2 bits are set to 0, indicating that only request channels 1 and 4 received the request signal, and the other N-2 request channels did not receive the request signal. The model to be verified can query whether the 3rd bit in the N-bit data of the second queue (that is, the position indicated by the request channel number 3 stored at the current head of the first queue) is 1. Since the 3rd bit in the N-bit data of the interface sampling data is not 1, it means that the request channel 3 has not applied an excitation signal. The first queue is updated to 4, ..., N, 1, 2, 3. Then, the model continues to query whether the 4th bit in the N-bit data of the second queue (that is, the position indicated by the request channel number 4 stored at the current head of the first queue) is 1. Since the 4th bit in the N-bit data of the interface sampling data is 1, it means that the request channel 4 has applied an excitation signal. The request signal from the request channel 4 can be used as the arbitration result. The first queue is updated to 5, ..., N, 1, 2, 3, 4, indicating the next arbitration order. Among them, the request channel 5 has the highest priority and the request channel 4 has the lowest priority.

[0064] This continues until the driver stops applying excitation signals to the model to be verified. The embodiments of this disclosure do not impose specific limitations on the number of request channels and the number of arbitrations of the simulated polling arbitrator, and can be set according to the actual application scenario.

[0065] In step S12, a target reference model with a second queue and a first queue is obtained. In step S13, the model to be verified is verified based on the target reference model to obtain a verification result. For example, interface sampling data of the model to be verified can be sampled periodically and stored in the second queue of the target reference model. Based on the interface sampling data stored in the second queue and the arbitration order stored in the first queue, it is determined whether the behavior of the target reference model is consistent with the behavior of the model to be verified to obtain a verification result.

[0066] As can be seen, timing-level modeling of the polling arbitrator in hardware is highly complex and costly, and may result in insufficient verification. Therefore, the verification method of this disclosure avoids complex timing-level modeling. Instead, it sets up a first queue and a second queue in the target reference model. The second queue stores the interface sampling data of the model to be verified, and the first queue stores the request channel numbers of the model to be verified. The polling order is used as the order of the request channel numbers in the first queue of the target reference model to simulate the polling arbitrator. Since the second queue can store the interface sampling data of the model to be verified for each cycle in real time, whenever the second queue is updated (i.e., corresponding to one arbitration operation of the model to be verified), the first queue can be updated according to the second queue (for example, the number of request channel numbers to be inserted from the head of the first queue to the tail can be determined based on the N bits of data included in the interface sampling data in the second queue), thus obtaining the polling order of the target reference model for the next cycle. This aligns the timing of the target reference model and the model to be verified (each time the model to be verified arbitrates, the arbitration order of the target reference model can be updated synchronously using the first and second queues), which is beneficial for the full verification of the model to be verified and greatly reduces the complexity and cost of verification.

[0067] The verification method of the present disclosure embodiments will be described in detail below.

[0068] In practical applications, first clarify the implementation specifications of the register transfer level model (i.e. the model to be verified) used to simulate the polling arbitrator in the chip verification system, and clarify what specific multi-request objects the model to be verified contains.

[0069] In one possible implementation, the specification information of the model to be verified can be obtained, which indicates the maximum number of arbitrable request signals that the model to be verified can arbitrate each time, that is, the number of request channels of the polling arbitrator hardware simulated by the model to be verified.

[0070] Figure 2 A schematic diagram of a model to be verified according to an embodiment of this disclosure is shown. For example... Figure 2 As shown, the model to be verified is a register-transfer level model used in the chip verification system to simulate a polling arbiter. The inputs of this model include one control terminal, arb_en, which receives an enable signal, and four request channels (N=4): request channel pipe0, request channel pipe1, request channel pipe2, and request channel pipe3. The outputs of this model include two output interfaces: arb_out, which provides the arbitration result of the model (e.g., the selected request channel number), and arb_out_valid, which provides a valid output flag for the model.

[0071] Based on the specifications of the model to be verified, the behavior of the polling arbitrator is described in software using a hardware description language to obtain an initial reference model. According to the specifications, a first queue and a second queue can be set for the initial reference model to obtain the target reference model. The depths of the first queue and the second queue are determined by the specifications.

[0072] By setting the depth of the first and second queues using specification information, a target reference model that perfectly matches the behavior of the model to be verified can be constructed, which helps improve verification efficiency and accuracy. For example, assuming the specification information is N, indicating that the model to be verified has N request channels, the depth of the second queue can be set to N+2, and the depth of the first queue can be set to N.

[0073] In one possible implementation, based on specifications, a sampling interface is constructed for the model to be verified in the chip verification system. This sampling interface is used to sample the model to be verified, and the sampled interface sampling data is stored in a second queue of the target reference model. For example, multiple request channels of the model to be verified can be sampled in real time through the sampling interface in the verification environment, and the collected interface sampling data can be stored in the second queue.

[0074] Since the second queue can store the interface sampling data of each round of arbitration operation of the model to be verified in real time, whenever the second queue is updated (that is, the arbitration operation of the model to be verified is performed once), the first queue can be updated according to the second queue to obtain the polling order of the target reference model in the next round. This aligns the timing of the target reference model and the model to be verified, which is conducive to the full verification of the model to be verified and greatly reduces the complexity and cost of verification.

[0075] In one possible implementation, the interface sampling data may include N-bit data [0:N-1], a first identifier "valid", and a second identifier "enable". The N-bit data [0:N-1] is used to indicate the validity of the request signals of the N request channels of the model to be verified. The N-bit data [0:N-1] is data composed of the validity information of the request signals of the multiple request channels of the model to be verified, which is concatenated bit by bit. The first identifier "valid" is used to indicate whether there is a valid request signal of at least one request channel. The second identifier "enable" is used to indicate whether the arbitration of the model to be verified is successful. N is an integer greater than 1.

[0076] like Figure 2 As shown, based on the validity of each request signal in request channel pipe0, request channel pipe1, request channel pipe2, and request channel pipe3, the data can be spliced ​​from low to high to obtain the 4-bit data data[0:3] included in the interface sampling data.

[0077] For example, suppose that the request signals of the three request channels pipe0, pipe1 and pipe2 are valid, and the request channel pipe3 has not received a request signal, then data[0:3]=0111; where data[0]=1 indicates that the request channel pipe0 has received a request signal, data[1]=1 indicates that the request channel pipe1 has received a request signal, data[2]=1 indicates that the request channel pipe2 has received a request signal, and data[3]=0 indicates that the request channel pipe3 has not received a request signal.

[0078] By adjusting the value of N, the target reference model can be easily adapted to models of different sizes and complexities to be verified, thus enhancing the scalability of the verification method.

[0079] The first identifier is an identifier indicating that any request channel is valid; it can be represented as "valid", such as... Figure 2 As shown, if any of the four request channels receives a valid request signal, then the first identifier valid is valid, denoted as first identifier valid=1; if none of the four request channels receive a valid request signal, then the first identifier valid is invalid, denoted as first identifier valid=0.

[0080] The second identifier, enable, indicates that the arbitration of the model to be verified has been successful, such as... Figure 2 As shown, if the control terminal arb_en is enabled, the second flag enable is valid, enable=arb_en=1; if the control terminal arb_en input is empty or low, the second flag enable is invalid, enable=arb_en=0.

[0081] The first flag, "valid," quickly determines whether at least one request signal from any request channel in the current round of the model to be verified is valid. The second flag, "enable," quickly determines whether the arbitration operation of the current round of the model to be verified was successful. Using both flags improves the accuracy and effectiveness of the verification method. When both flags are true (e.g., first flag valid & second flag enabled = 1), the interface sampled data is valid; otherwise, when either flag is false (e.g., first flag valid & second flag enabled = 0), the interface sampled data is invalid and will mislead the verification results.

[0082] It should be understood that the embodiments disclosed herein are for illustrative purposes only. Figure 2 As an example, in practical applications, there is no limit to the number of request channels in the model to be verified.

[0083] In one possible implementation, the model to be verified can be verified based on a target reference model that includes a first queue and a second queue to obtain a verification result. For example, the model to be verified can be sampled through a sampling interface, and the interface sampling data of the model to be verified can be stored in a second queue; in response to the model to be verified completing the arbitration operation and outputting a first result, a second result can be generated based on the first queue and the second queue of the target reference model; the first result and the second result can be compared to obtain the verification result.

[0084] For example, the sampling interface can be a pre-written software interface used to sample the model to be verified, storing the interface sampling data of the model to be verified into a second queue. This sampling interface can use the valid_enable handshake protocol and simultaneously create an N-bit data field, corresponding to N bits of data[0:N-1]. The generation logic for the first identifier Valid is that the request signal of any of the N request channels is valid; the generation logic for the second identifier enable is that the control terminal arb_en is enabled.

[0085] In response to the model to be verified completing the arbitration operation, the first result is output, for example... Figure 2 The arb_out interface of the model to be verified outputs the selected request channel number. Since the second queue of the target reference model stores the interface sampling data of the model to be verified, and the first queue stores the arbitration order representing the priority, a second result can be generated based on the first and second queues of the target reference model.

[0086] In one possible implementation, in step S12, in response to the model to be verified completing the arbitration operation and outputting a first result, the target reference model can be invoked to generate a second result based on the first queue and the second queue of the target reference model.

[0087] For example, in response to the model to be verified completing the arbitration operation and outputting the first result, the target reference model can be called. If the first identifier in the second queue is the first identifier value and the second identifier is the second identifier value, the second result can be obtained according to the first queue and the second queue of the target reference model. Here, the first identifier value indicates that the request signal of at least one request channel is valid, and the second identifier value indicates that the arbitration of the model to be verified is successful.

[0088] In the example, the first identifier "valid" is an identifier indicating that any request channel is valid. If the first identifier "valid" = 1, that is, the first identifier "valid" is true, it means that at least one of the N request channels of the model to be verified has received a request signal. If the first identifier "valid" = 0, that is, the first identifier "valid" is false, it means that none of the request channels of the model to be verified have received a request signal.

[0089] The second flag, enable, indicates that the arbitration of the model to be verified was successful. If enable=1, that is, enable is true, it means that the model to be verified will perform the arbitration operation; if enable=0, that is, enable is false, it means that the model to be verified will not perform the arbitration operation.

[0090] If either the first identifier "valid" or the second identifier "enable" is false, it means that the interface sampling data of the model to be verified stored in the second queue is invalid, and the chip verification system can output an error and restart the verification process; if the first identifier "valid" is true and the second identifier "enable" is also true, it means that the interface sampling data of the model to be verified stored in the second queue is valid, and a second result can be generated based on the first and second queues of the target reference model.

[0091] Setting a first identifier and a second identifier can help improve the accuracy and effectiveness of the verification method.

[0092] In one possible implementation, the second result is obtained based on the first and second queues of the target reference model, including: determining whether the request signal corresponding to the request channel number in the second queue is empty based on the request channel number stored at the head of the first queue; if the request signal corresponding to the request channel number in the second queue is not empty, the request signal corresponding to the request channel number is taken as the second result, and the request channel number stored at the head of the first queue is moved to the tail of the first queue, serving as the first queue for the next round of arbitration operations of the target reference model. If the request signal corresponding to the request channel number in the second queue is empty, the request channel number stored at the head of the first queue is moved to the tail of the first queue, resulting in an updated first queue; the process continues to determine whether the request signal corresponding to the request channel number in the second queue is empty based on the request channel number stored at the head of the updated first queue, until the second result of the target reference model is obtained.

[0093] In this way, the target reference model can wait for the arbitration behavior of the model to be verified in real time. Whenever the model to be verified completes an arbitration operation, it obtains the interface sampling data corresponding to the current arbitration operation and stores it in the second queue of the target reference model.

[0094] For each round of arbitration operation of the target reference model, the request channel number stored in the head of the first queue of the target reference model can be obtained first, and it can be determined whether the request channel indicated by the request channel number has a request signal.

[0095] If the request channel is not empty, it means that the request channel has received a request signal in the current round. The request signal received at the request channel can be used as the request signal after arbitration in this round. At the same time, the request channel number at the head of the first queue is dequeued, the request channel numbers that were originally second and later in the order are moved forward in turn, and the request channel number corresponding to the request channel is placed at the tail of the first queue to obtain the updated first queue. The updated first queue is used as the first queue corresponding to the next round of arbitration operation of the target reference model.

[0096] If the request channel is empty, it means that the request channel did not receive a request signal in the current round and is invalid. In this case, the request channel number at the head of the first queue is dequeued, the request channel numbers that were originally second and later in the order are moved forward in turn, and the request channel number corresponding to the current request channel is placed at the tail of the first queue, resulting in the updated first queue.

[0097] Then, the same method can be used to check the request channel number stored in the head of the updated first queue, and determine whether the request channel indicated by the request channel number has a request signal, until it is determined that the request signal corresponding to the request channel number in the second queue is not empty based on the request channel number stored in the head of the updated first queue. The request signal received at the request channel can be used as the request signal after arbitration in this round, and the second result of the target reference model in this round can be obtained.

[0098] For example, suppose the model to be validated is as follows: Figure 2 The register transfer level model shown has four request channels, which can simulate the behavior of the polling arbiter in terms of timing through the first queue arb_4master_rr_q[0:3] with a depth of 4 in the target reference model. Here, arb_4master_rr_q[0] represents the head of the first queue arb_4master_rr_q[0:3], and arb_4master_rr_q[3] represents the tail of the first queue arb_4master_rr_q[0:3].

[0099] At the start of the simulation of the target reference model, the four request channel numbers from 0 to 3 can be sequentially sent into the first queue arb_4master_rr_q[0:3]= [3,2,1,0]. Among them, request channel number 0 is used to indicate request channel pipe0, and arb_4master_rr_q[0]=0 indicates that request channel pipe0 has the highest priority; request channel number 1 is used to indicate request channel pipe1, and arb_4master_rr_q[1]=1 indicates that request channel pipe1 has the second highest priority; request channel number 2 is used to indicate request channel pipe2, and arb_4master_rr_q[2]=2 indicates that request channel pipe2 has the third highest priority; request channel number 3 is used to indicate request channel pipe3, and arb_4master_rr_q[3]=3 indicates that request channel pipe3 has the lowest priority.

[0100] For the first round of arbitration operation of the target reference model, the request channel number 0 stored in the head of the first queue arb_4master_rr_q[0:3] of the target reference model can be obtained first, and it can be determined whether the request channel pipe0 indicated by the request channel number 0 has a request signal.

[0101] For example, if the request channel pipe0 is not empty, it means that the request channel pipe0 has received a request signal. The request signal received at the request channel pipe0 can be used as the request signal after this round of arbitration. At the same time, the request channel number 0 corresponding to the request channel pipe0 is placed at the end of the first queue arb_4master_rr_q[0:3] to obtain the updated first queue arb_4master_rr_q[0:3]. The updated first queue arb_4master_rr_q[0:3] is used as the first queue corresponding to the second round of arbitration operation of the target reference model, that is: the first queue arb_4master_rr_q[0:3] = [0,3,2,1].

[0102] For example, if the request channel pipe0 is empty, it means that the request channel pipe0 has not received a request signal and is invalid. Then, the request channel number 0 corresponding to the request channel pipe0 is placed at the end of the first queue arb_4master_rr_q[0:3], and the updated first queue arb_4master_rr_q[0:3] = [0,3,2,1]. Then, the same method can be used to check the request channel number 1 stored in the head of the updated first queue arb_4master_rr_q[0] in the first queue arb_4master_rr_q[0], and determine whether the request channel pipe1 indicated by the request channel number 1 has a request signal. If the request channel pipe1 is not empty, it means that the request channel pipe1 has received a request signal. The request signal received at the request channel pipe1 can be used as the request signal after the first round of arbitration. At the same time, the request channel number 1 corresponding to the request channel pipe1 is placed at the end of the first queue arb_4master_rr_q[0:3] to obtain the updated first queue arb_4master_rr_q[0:3]. The updated first queue arb_4master_rr_q[0:3] is used as the first queue corresponding to the second round of arbitration operation of the target reference model, that is: the first queue arb_4master_rr_q[0:3] = [1,0,3,2].

[0103] Similarly, in each round of arbitration, the first queue arb_4master_rr_q[0:3] can be checked according to the above method until the request signal at the request channel corresponding to the request channel number stored at the head of the updated first queue arb_4master_rr_q[0:3] is not empty. The request signal received at this request channel can be used as the request signal after this round of arbitration to obtain the second result of the target reference model for this round. Among them, since the model to be verified has undergone arbitration, a request channel number can be found from the first queue arb_4master_rr_q[0:3].

[0104] The verification result is obtained by performing a real-time comparison at the transmission level between the first result of the arbitration output of the model to be verified and the second result of the arbitration output of the target reference model. For example, the first result of the arbitration output of the model to be verified and the second result of the arbitration output of the target reference model can be compared round by round to see if they are the same. If they are different, an error message is output and the verification starts again. If the first result of the arbitration output of the model to be verified and the second result of the arbitration output of the target reference model are the same in each round, the verification result shows that the verification is successful. It should be understood that there are various specific comparison methods, and the embodiments of this disclosure do not impose specific limitations on them.

[0105] By setting up a first queue and a second queue, complex timing models can be avoided. The target reference model of the polling arbitrator can be developed through indirect timing synchronization, thereby fully verifying the model to be verified in the chip verification system.

[0106] In summary, the verification method of this embodiment sets up a first queue and a second queue in the target reference model. The second queue is used to store the interface sampling data of the model to be verified, and the first queue is used to simulate the arbitration order of the polling arbitrator. Based on the first queue and the second queue, it can be combined with the timing of the model to be verified to achieve full verification of the model to be verified. This avoids complex timing-level modeling (the development difficulty of the target reference model is much lower than that of the timing-level model). The target reference model does not need to be time-aligned with the model to be verified. It only needs to rely on the behavior of the model to be verified to fully verify the arbitration function, which greatly reduces the complexity and cost of verification.

[0107] It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0108] In addition, this disclosure also provides verification devices, electronic devices, computer-readable storage media, and programs, all of which can be used to implement any of the verification methods provided in this disclosure. The corresponding technical solutions and descriptions are described in the corresponding records in the method section and will not be repeated here.

[0109] Figure 3 A block diagram of a verification apparatus according to an embodiment of the present disclosure is shown, such as Figure 3 As shown, the verification device may include:

[0110] The first module 31 is used to arbitrate at least one request signal using the model to be verified and output a first result.

[0111] The second module 32 is used to call the target reference model, and use the order of the request channel numbers in the first queue of the target reference model as the polling order. The queue polling simulates the arbitration behavior of the model to be verified on at least one request signal to obtain a second result.

[0112] The comparison module 33 is used to compare the first result with the second result to determine the verification result.

[0113] In one possible implementation, the verification device further includes a construction module for constructing a target reference model, comprising: describing the behavior of the polling arbitrator in software using a hardware description language to obtain an initial reference model; setting a first queue and a second queue for the initial reference model to obtain the target reference model, wherein the second queue is used to store interface sampling data of the model to be verified, and the first queue is used to store the request channel number of the model to be verified.

[0114] In one possible implementation, the device further includes a sampling interface construction module for: acquiring specification information of the model to be verified, the specification information indicating the maximum number of arbitrable request signals for each time the model to be verified is; constructing a sampling interface for the model to be verified in the chip verification system according to the specification information, wherein the sampling interface is used to sample the model to be verified, and storing the sampled interface sampling data of the model to be verified into a second queue of the target reference model.

[0115] In one possible implementation, the interface sampling data includes N bits of data, a first identifier, and a second identifier. The N bits of data are used to indicate the validity of the request signals of the N request channels of the model to be verified. The first identifier is used to indicate whether the request signal of at least one request channel is valid. The second identifier is used to indicate whether the arbitration of the model to be verified is successful. N is an integer greater than 1.

[0116] In one possible implementation, the second module 32 is used to: in response to the model to be verified completing the arbitration operation and outputting a first result, and in the case that the first identifier in the second queue is a first identifier value and the second identifier is a second identifier value, obtain a second result according to the first queue and the second queue of the target reference model, wherein the first identifier value indicates that the request signal of at least one request channel is valid, and the second identifier value indicates that the arbitration of the model to be verified is successful.

[0117] In one possible implementation, the second result is obtained based on the first queue and the second queue of the target reference model, including: determining whether the request signal corresponding to the request channel number in the second queue is empty based on the request channel number stored at the head of the first queue; if the request signal corresponding to the request channel number in the second queue is not empty, the request signal corresponding to the request channel number is taken as the second result, and the request channel number stored at the head of the first queue is arranged to the tail of the first queue as the first queue corresponding to the next round of arbitration operation of the target reference model.

[0118] In one possible implementation, the second module 32 is further configured to: when the request signal corresponding to the request channel number in the second queue is empty, arrange the request channel number stored at the head of the first queue to the tail of the first queue to obtain the updated first queue; continue to determine whether the request signal corresponding to the request channel number in the second queue is empty based on the request channel number stored at the head of the updated first queue, until the second result of the target reference model is obtained.

[0119] In one possible implementation, setting up a first queue and a second queue for an initial reference model to obtain a target reference model includes: obtaining specification information of the model to be verified, the specification information indicating the maximum number of arbitrable request signals for each time the model to be verified is; setting up a first queue and a second queue for the initial reference model according to the specification information to obtain the target reference model, wherein the depth of the first queue and the second queue is determined by the specification information.

[0120] This method is specifically technically related to the internal structure of computer systems and can solve technical problems of how to improve hardware computing efficiency or execution performance (including reducing data storage, reducing data transmission, and increasing hardware processing speed), thereby achieving technical effects that improve the internal performance of computer systems in accordance with natural laws.

[0121] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0122] This disclosure also proposes a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the above-described method. The computer-readable storage medium can be volatile or non-volatile.

[0123] This disclosure also proposes an electronic device, including: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to execute the above-described method.

[0124] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-described method.

[0125] Electronic devices can be provided as terminals, servers, or other forms of devices.

[0126] Figure 4A block diagram of an electronic device 1900 according to an embodiment of the present disclosure is shown. For example, the electronic device 1900 may be provided as a server or a terminal device. (Refer to...) Figure 4 The electronic device 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0127] Electronic device 1900 may also include a power supply component 1926 configured to perform power management of electronic device 1900, a wired or wireless network interface 1950 configured to connect electronic device 1900 to a network, and an input / output interface 1958. Electronic device 1900 can operate on an operating system stored in memory 1932, such as a Microsoft Server operating system (Windows Server). TM Apple's graphical user interface-based operating system (Mac OS X) TM ), a multi-user, multi-process computer operating system (Unix) TM Linux is a free and open-source Unix-like operating system. TM ), an open-source Unix-like operating system (FreeBSD) TM (or similar.)

[0128] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of an electronic device 1900 to perform the above-described method.

[0129] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this disclosure.

[0130] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, (but not limited to) electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0131] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0132] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0133] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0134] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0135] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0136] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0137] The computer program product can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0138] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0139] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0140] If the technical solution of this application involves personal information, the product using this technical solution has clearly informed the user of the personal information processing rules and obtained the user's voluntary consent before processing the personal information. If the technical solution of this application involves sensitive personal information, the product using this technical solution has obtained the user's separate consent before processing the sensitive personal information, and also meets the requirement of "express consent". For example, at personal information collection devices such as cameras, clear and prominent signs are set up to inform users that they have entered the scope of personal information collection and that personal information will be collected. If an individual voluntarily enters the collection scope, it is deemed that they have agreed to the collection of their personal information; or on the personal information processing device, with clear signs / information informing users of the personal information processing rules, authorization is obtained from the individual through pop-up information or by asking the individual to upload their personal information; wherein, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the types of personal information processed.

[0141] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A verification method, characterized in that, The method includes: Arbitrate at least one request signal using the model to be verified, and output the first result. The target reference model is invoked, and the polling order is based on the order of the request channel numbers in the first queue of the target reference model. The arbitration behavior of the model to be verified on the at least one request signal is simulated by polling the queue to obtain a second result. The first queue is updated once for each time the target reference model simulates an arbitration behavior to obtain the polling order of the next simulated arbitration behavior of the target reference model. Compare the first result with the second result to determine the verification result.

2. The method according to claim 1, characterized in that, The method for constructing the target reference model includes: The behavior of the polling arbitrator is described in software using a hardware description language to obtain an initial reference model; A first queue and a second queue are set up for the initial reference model to obtain the target reference model, wherein the second queue is used to store the interface sampling data of the model to be verified, and the first queue is used to store the request channel number of the model to be verified.

3. The method according to claim 2, characterized in that, The method further includes: Obtain the specification information of the model to be verified, wherein the specification information is used to indicate the maximum number of arbitrable request signals of the model to be verified each time; Based on the specifications, a sampling interface is constructed for the model to be verified in the chip verification system. The sampling interface is used to sample the model to be verified, and the sampled interface sampling data of the model to be verified is stored in the second queue of the target reference model.

4. The method according to claim 2 or 3, characterized in that, The interface sampling data includes N bits of data, a first identifier, and a second identifier. The N bits of data are used to indicate the validity of the request signals of the N request channels of the model to be verified. The first identifier is used to indicate whether at least one request channel has a valid request signal. The second identifier is used to indicate whether the arbitration of the model to be verified was successful. N is an integer greater than 1.

5. The method according to claim 2, characterized in that, The invocation of the target reference model uses the order of request channel numbers in the first queue of the target reference model as the polling order. The polling simulates the arbitration behavior of the model to be verified on the at least one request signal, yielding a second result, including: In response to the model to be verified completing the arbitration operation and outputting the first result, if the first identifier in the second queue is the first identifier value and the second identifier is the second identifier value, the second result is obtained according to the first queue and the second queue of the target reference model, wherein the first identifier value indicates that the request signal of at least one request channel is valid, and the second identifier value indicates that the arbitration of the model to be verified is successful.

6. The method according to claim 5, characterized in that, The step of obtaining the second result based on the first queue and the second queue of the target reference model includes: Based on the request channel number stored at the head of the first queue, determine whether the request signal corresponding to the request channel number in the second queue is empty; If the request signal corresponding to the request channel number in the second queue is not empty, the request signal corresponding to the request channel number is taken as the second result, and the request channel number stored at the head of the first queue is arranged to the tail of the first queue, which is used as the first queue corresponding to the next round of arbitration operation of the target reference model.

7. The method according to claim 6, characterized in that, The method further includes: If the request signal corresponding to the request channel number in the second queue is empty, the request channel number stored at the head of the first queue is arranged to the tail of the first queue to obtain the updated first queue. Continue to determine whether the request signal corresponding to the request channel number in the second queue is empty based on the updated request channel number stored at the head of the first queue, until the second result of the target reference model is obtained.

8. The method according to claim 2, characterized in that, Setting up the first queue and the second queue for the initial reference model to obtain the target reference model includes: Obtain the specification information of the model to be verified, wherein the specification information is used to indicate the maximum number of arbitrable request signals of the model to be verified each time; Based on the specification information, a first queue and a second queue are set for the initial reference model to obtain the target reference model. The depths of the first queue and the second queue are determined by the specification information.

9. A verification device, characterized in that, include: The first module is used to arbitrate at least one request signal using the model to be verified and output a first result. The second module is used to call the target reference model, and use the order of the request channel numbers in the first queue of the target reference model as the polling order to simulate the arbitration behavior of the model to be verified on the at least one request signal through queue polling to obtain a second result; wherein, the target reference model updates the first queue once for each simulated arbitration behavior to obtain the polling order of the target reference model for the next simulated arbitration behavior; The comparison module is used to compare the first result with the second result to determine the verification result.

10. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to invoke instructions stored in the memory to execute the method according to any one of claims 1 to 8.

11. A computer-readable storage medium storing computer program instructions thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the method described in any one of claims 1 to 8.

12. A computer program product comprising computer program instructions, characterized in that, When the computer program instructions are executed by the processor, they implement the method described in any one of claims 1 to 8.

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