Method, device, equipment and medium for repairing failed memory cells in memory

Abstract

The memory failure storage unit repair method, device, equipment and medium provided by the embodiments of the present disclosure comprise: in response to receiving an activation operation submitted by a target object, obtaining a target row address corresponding to the activation operation; determining a target storage array to which a word line receiving the target row address belongs according to address information of a first address interval in the target row address; when the target row address is the same as a failure row address, determining a target redundant word line receiving the target row address according to the target storage array to which the word line receiving the target row address belongs. The use of the redundant word line of the storage array in which the failure word line is located to repair the failure storage unit is avoided, thereby increasing tRCD within the chip and affecting the read-write efficiency of the chip.

Description

Technical Field

[0001] The embodiments of this disclosure relate to the field of memory technology and related technical fields, and more specifically, to a method, apparatus, device, and medium suitable for repairing failed memory cells in a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM), also known as main memory, is an internal memory that directly exchanges data with the CPU. It features on-demand read / write capabilities and high speed, and is typically used as a temporary data storage medium for the operating system or other running programs.

[0003] A DRAM (Dynamic Random Access Memory) array consists of multiple memory cells. In the actual production process, some memory cells may fail. To replace these failed memory cells, the chip design includes redundant circuitry. The redundant circuitry is used to repair the failed memory cells, thereby improving the chip yield.

[0004] In the existing technology for repairing failed memory cells, the address of the failed memory cell is first obtained through a testing process, and then the row address of the failed memory cell is stored in a redundant circuit. During chip power-up, the row address of the failed cell is automatically loaded. When a row address is input during normal operation, it is compared with the row address stored in the redundant circuit. If they do not match, the row address input during normal operation continues to be used; if they match, the redundant word line is used.

[0005] Accessing a DRAM memory cell requires activating the row address (via an activation command) and then accessing the column address (via a write or read command). A certain forced wait time (tRCD) is required between these two operations to ensure that the row address signal is stable before the column address can be sent. However, when a failed word line and a repaired redundant word line are located in the same memory array, the tRCD inside the chip will be reduced, affecting the chip's read and write efficiency. Summary of the Invention

[0006] The embodiments described herein provide a method, apparatus, device, and medium for repairing failed memory cells in a memory, thereby improving chip read / write efficiency.

[0007] In a first aspect, according to the present disclosure, a method for repairing failed memory cells in a memory is provided. The memory includes multiple memory arrays, any one of which includes multiple memory cells arranged in an array. At least two of the multiple memory arrays include redundant word lines, including: In response to receiving an activation operation submitted by the target object, obtain the target row address corresponding to the activation operation; Based on the address information of the first address range in the target row address, determine the target memory array to which the word line receiving the target row address belongs; When the target row address is the same as the failed row address, the target redundant word line receiving the target row address is determined according to the target storage array to which the word line receiving the target row address belongs.

[0008] In some embodiments of this disclosure, determining the target redundant word line receiving the target row address based on the target storage array to which the word line receiving the target row address belongs includes: When the target memory array to which the word line receiving the target row address belongs does not include redundant word lines, a redundant word line is selected from any memory array that includes redundant word lines as the target redundant word line for receiving the target row address. When the target storage array to which the word line receiving the target row address belongs includes redundant word lines, a redundant word line is selected from a storage array outside the target storage array that includes redundant word lines as the target redundant word line for receiving the target row address.

[0009] In some embodiments of this disclosure, the storage array includes a first storage array, a second storage array, a third storage array, and a fourth storage array, wherein the second storage array includes a first redundant word line, and the third storage array includes a second redundant word line; The step of determining the target redundant word line receiving the target row address based on the target storage array to which the word line receiving the target row address belongs includes: When the target storage array to which the word line receiving the target row address belongs is the first storage array or the fourth storage array, a redundant word line is selected from the second storage array as the target redundant word line for receiving the target row address, or a redundant word line is selected from the third storage array as the target redundant word line for receiving the target row address. When the target storage array to which the word line receiving the target row address belongs is the second storage array, a redundant word line is selected from the third storage array as the target redundant word line for receiving the target row address. When the target storage array to which the word line receiving the target row address belongs is the third storage array, a redundant word line is selected from the second storage array as the target redundant word line for receiving the target row address.

[0010] In some embodiments of this disclosure, the storage array includes at least a first storage array group and a second storage array group, wherein the first storage array group and the second storage array group include a first storage array, a second storage array, a third storage array and a fourth storage array, the second storage array includes a first redundant word line, and the third storage array includes a second redundant word line; Before determining the target memory array to which the word line receiving the target row address belongs based on the address information of the first address range in the target row address, the method further includes: The third identification information is determined based on the address information of the second address range in the target row address; Based on the correspondence between the third identification information and the fourth identification information of the storage array group, the target storage array group to which the word line receiving the target row address belongs is determined.

[0011] In some embodiments of this disclosure, before determining the target redundant word line receiving the target row address based on the target storage array to which the word line receiving the target row address belongs, the method further includes: Acquire a selection signal, wherein the selection signal is used to select a repair method; The step of determining the target redundant word line receiving the target row address based on the target storage array to which the word line receiving the target row address belongs includes: The target redundant word line for receiving the target row address is determined based on the target storage array to which the word line receiving the target row address belongs and the selection signal.

[0012] In some embodiments of this disclosure, determining the target redundant word line receiving the target row address based on the target memory array to which the word line receiving the target row address belongs and the selection signal includes: When the target memory array to which the word line receiving the target row address belongs does not include redundant word lines and the selection signal is the first selection signal, a redundant word line is selected from any memory array that includes redundant word lines as the target redundant word line for receiving the target row address. When the target memory array to which the word line receiving the target row address belongs includes redundant word lines and the selection signal is the first selection signal, a redundant word line is selected from a memory array outside the target memory array that includes redundant word lines as the target redundant word line for receiving the target row address. When the selection signal is the second selection signal, a redundant word line is selected from any memory array including redundant word lines as the target redundant word line for receiving the target row address.

[0013] In some embodiments of this disclosure, determining the target memory array to which the word line receiving the target row address belongs, based on the address information of the first address range in the target row address, includes: The first identification information is determined based on the address information of the first address range in the target row address; Based on the correspondence between the first identification information and the second identification information of the storage array, the target storage array to which the word line receiving the target row address belongs is determined.

[0014] Secondly, according to the present disclosure, a device for repairing failed memory cells in a memory is provided. The memory includes multiple memory arrays, any one of which includes multiple memory cells arranged in an array. At least two of the multiple memory arrays include redundant word lines, including: The target row address acquisition module is used to acquire the target row address corresponding to the activation operation in response to receiving the activation operation submitted by the target object. The target storage array determination module is used to determine the target storage array to which the word line receiving the target row address belongs, based on the address information of the first address interval in the target row address; The target redundant word line determination module is used to determine the target redundant word line receiving the target row address based on the target storage array to which the word line receiving the target row address belongs when the target row address is the same as the failed row address.

[0015] Thirdly, according to the present disclosure, a computer device is provided, comprising: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any of the first aspects.

[0016] Fourthly, according to the present disclosure, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the methods described in any of the first aspects.

[0017] The method, apparatus, device, and medium for repairing failed memory cells in a memory provided in this disclosure first respond to receiving an activation operation submitted by a target object and obtain the target row address corresponding to the activation operation; then, based on the address information of the first address interval in the target row address, determine the target memory array to which the word line receiving the target row address belongs; finally, when the target row address is the same as the failed row address, determine the target redundant word line receiving the target row address based on the target memory array to which the word line receiving the target row address belongs. When the target memory array to which the word line receiving the target row address belongs does not include redundant word lines, a redundant word line is selected from any memory array that includes redundant word lines as the target redundant word line receiving the target row address; when the target memory array to which the word line receiving the target row address belongs includes redundant word lines, a redundant word line is selected from a memory array outside the target memory array that includes redundant word lines as the target redundant word line receiving the target row address. This avoids using redundant word lines from the memory array where the failed word line is located to repair failed memory cells, which increases the tRCD inside the chip and affects the chip's read / write efficiency. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein: Figure 1 This is a flowchart illustrating a method for repairing a failed memory cell in a memory according to an embodiment of this disclosure; Figure 2 This is a schematic diagram of the structure of a memory provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of another memory structure provided in an embodiment of this disclosure; Figure 4 This is a timing diagram of a memory provided in an embodiment of this disclosure; Figure 5A and Figure 5B This is a schematic diagram of the structure of the comparison circuit in the memory provided in the embodiments of this disclosure; Figure 6 This is a schematic diagram of a device for repairing a failed memory cell in a memory according to an embodiment of this disclosure; Figure 7 This is a schematic diagram of the structure of a computer device provided in an embodiment of this disclosure. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0020] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0021] In all embodiments of this disclosure, terms such as “first” and “second” are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0022] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0023] In view of the problems existing in the prior art, this disclosure provides a method for repairing failed memory cells in a memory, which is applied to a memory including multiple memory arrays. Any memory array includes multiple memory cells arranged in an array, and at least two of the multiple memory arrays include redundant word lines. Figure 1 This is a flowchart illustrating a method for repairing a failed memory cell in a memory according to an embodiment of this disclosure, as shown below. Figure 1 As shown, a method for repairing failed memory cells in a memory includes: S110. In response to receiving the activation operation submitted by the target object, obtain the target row address corresponding to the activation operation.

[0024] The memory includes multiple memory arrays, and a memory array includes multiple memory cells arranged in an array.

[0025] During the manufacturing process of memory chips, some word lines may become damaged. In this case, redundant word lines are needed to replace the damaged word lines. The row address is transmitted to the memory cell connected to the damaged word line through the redundant word lines. The process of replacing the damaged word line with a redundant word line is a process of address remapping, that is, the row address received by the redundant word line is the same as the row address received by the damaged word line.

[0026] After receiving the activation operation submitted by the target object, the memory obtains the target row address included in the activation operation, which is the row address RADT<12:3> carried by the activation command during a normal activation operation.

[0027] It should be noted that, in the above embodiments, the exemplary row address includes 10 bits. When there are many storage cells in the memory, the row address carried by the activation command during the activation operation can also be RADT<13:3> or RADT<14:3>, etc. This disclosure does not specifically limit this.

[0028] S120. Based on the address information of the first address range in the target row address, determine the target memory array to which the word line receiving the target row address belongs.

[0029] The address information in the first address range of the target row address refers to the address information in the eleventh to twelfth address range of the target row address, i.e., RADT<12:11>.

[0030] In a specific implementation, determining the target storage array to which the word line of the target row address belongs based on the address information of the first address interval in the target row address includes: determining first identification information based on the address information of the first address interval in the target row address; and determining the target storage array to which the word line of the target row address belongs based on the correspondence between the first identification information and the second identification information of the storage array.

[0031] As an example, such as Figure 2As shown, the memory includes four memory arrays: a first memory array, a second memory array, a third memory array, and a fourth memory array. The second identifier information corresponding to the first memory array is 00, the second identifier information corresponding to the second memory array is 01, the second identifier information corresponding to the third memory array is 10, and the second identifier information corresponding to the fourth memory array is 11. If the target row address RADT<12:3>=0000000000, and the address information of the first address interval in the target row address RADT<12:11>=00, then the determined first identifier information is 00. Through the correspondence between the first identifier information and the second identifier information of the memory arrays, it can be determined that the target memory array to which the word line receiving the target row address belongs is the first memory array. If the target row address RADT<12:3>=0100000000, and the address information of the first address interval in the target row address RADT<12:11>=01, then the determined first identifier information is 00. If the target row address is RADT<12:3>=1000000000, and the address information of the first address interval in the target row address is RADT<12:11>=10, then the determined first identifier is 10. Based on the correspondence between the first identifier and the second identifier of the storage array, the target storage array to which the word line of the received target row address belongs is the third storage array. If the target row address is RADT<12:3>=1100000000, and the address information of the first address interval in the target row address is RADT<12:11>=11, then the determined first identifier is 11. Based on the correspondence between the first identifier and the second identifier of the storage array, the target storage array to which the word line of the received target row address belongs is the fourth storage array.

[0032] As another example, such as Figure 3 As shown, the memory includes eight memory arrays, namely, the first memory array, the second memory array, the third memory array, and the fourth memory array of the first memory array group, and the first memory array, the second memory array, the third memory array, and the fourth memory array of the second memory array group. The second identification information corresponding to the first memory array of the first memory array group and the first memory array of the second memory array group is 00, the second identification information corresponding to the second memory array of the first memory array group and the second memory array of the second memory array group is 01, the second identification information corresponding to the third memory array of the first memory array group and the third memory array of the second memory array group is 10, and the second identification information corresponding to the fourth memory array of the first memory array group and the fourth memory array of the second memory array group is 11.

[0033] Since the second identification information of the first storage array in the first storage array group is the same as that of the first storage array in the second storage array group, the second identification information of the second storage array in the first storage array group is the same as that of the second storage array in the second storage array group, the second identification information of the third storage array in the first storage array group is the same as that of the third storage array in the second storage array group, and the second identification information of the fourth storage array in the first storage array group is the same as that of the fourth storage array in the second storage array group, in this implementation process, before executing step S120 to determine the target storage array to which the word line of the target row address belongs based on the address information of the first address interval in the target row address, the method further includes: determining the third identification information based on the address information of the second address interval in the target row address; and determining the target storage array group to which the word line of the target row address belongs based on the correspondence between the third identification information and the fourth identification information of the storage array group.

[0034] In this case, the number of memory cells is relatively large. During normal activation, the row address carried by the activation command can be RADT<13:3>, and the address information of the second address interval in the target row address is the address information of the thirteenth digit of the target row address, i.e., RADT. <13> .

[0035] At this time, the fourth identifier information corresponding to the first storage array group is 0, the fourth identifier information corresponding to the second storage array group is 1, the second identifier information corresponding to the first storage array is 00, the second identifier information corresponding to the second storage array is 01, the second identifier information corresponding to the third storage array is 10, and the second identifier information corresponding to the fourth storage array is 11. If the target row address RADT<13:3>=00000000000, the address information RADT in the second address range of the target row address... <13> =0, the address information RADT<12:11>=00 in the first address interval of the target row address, at this time, the determined third identification information is 0, and the first identification information is 00. Through the correspondence between the third identification information and the fourth identification information of the storage array group, and the correspondence between the first identification information and the second identification information of the storage array, it can be determined that the target storage array to which the word line receiving the target row address belongs is the first storage array of the first storage array group; if the target row address RADT<13:3>=001000000000, the address information RADT<12:11>=00 in the second address interval of the target row address <13> =0, the address information RADT<12:11>=01 in the first address interval of the target row address, at this time, the determined third identification information is 0, and the first identification information is 01. Through the correspondence between the third identification information and the fourth identification information of the storage array group, and the correspondence between the first identification information and the second identification information of the storage array, it can be determined that the target storage array to which the word line receiving the target row address belongs is the second storage array of the first storage array group; if the target row address RADT<13:3>=01000000000, the address information RADT<12:11> in the second address interval of the target row address is 0, the third identification information is 0, and the first identification information is 01. <13> =0, the address information RADT<12:11>=10 in the first address interval of the target row address, at this time, the determined third identifier is 0, the first identifier is 10, and through the correspondence between the third identifier and the fourth identifier of the storage array group, and the correspondence between the first identifier and the second identifier of the storage array, it can be determined that the target storage array to which the word line receiving the target row address belongs is the third storage array of the first storage array group; if the target row address RADT<13:3>=01100000000, the address information RADT<12:11>=10 in the second address interval of the target row address <13> =0, the address information RADT<12:11>=11 in the first address range of the target row address, at this time, the determined third identification information is 0, the first identification information is 11. Through the correspondence between the third identification information and the fourth identification information of the storage array group, and the correspondence between the first identification information and the second identification information of the storage array, it can be determined that the target storage array to which the word line of the receiving target row address belongs is the fourth storage array of the first storage array group.If the target row address RADT<13:3>=10000000000, the address information RADT in the second address range of the target row address... <13> =1, the address information RADT<12:11>=00 in the first address interval of the target row address. At this time, the determined third identifier is 1, and the first identifier is 00. Through the correspondence between the third identifier and the fourth identifier of the storage array group, and the correspondence between the first identifier and the second identifier of the storage array, it can be determined that the target storage array to which the word line receiving the target row address belongs is the first storage array of the second storage array group; if the target row address RADT<13:3>=101000000000, the address information RADT<12:11>=00 in the second address interval of the target row address. <13> =1, the address information RADT<12:11>=01 in the first address interval of the target row address. At this time, the determined third identifier is 1, and the first identifier is 01. Through the correspondence between the third identifier and the fourth identifier of the storage array group, and the correspondence between the first identifier and the second identifier of the storage array, it can be determined that the target storage array to which the word line receiving the target row address belongs is the second storage array of the second storage array group; if the target row address RADT<13:3>=11000000000, the address information RADT<12:11> in the second address interval of the target row address is 01. <13> =1, the address information RADT<12:11>=10 in the first address interval of the target row address, at this time, the determined third identifier is 1, the first identifier is 10, and through the correspondence between the third identifier and the fourth identifier of the storage array group, and the correspondence between the first identifier and the second identifier of the storage array, it can be determined that the target storage array to which the word line receiving the target row address belongs is the third storage array of the second storage array group; if the target row address RADT<13:3>=11100000000, the address information RADT<12:11>=10 in the second address interval of the target row address <13> =1, the address information RADT<12:11>=11 in the first address range of the target row address, at this time, the determined third identification information is 1, the first identification information is 11, through the correspondence between the third identification information and the fourth identification information of the storage array group, and the correspondence between the first identification information and the second identification information of the storage array, it can be determined that the target storage array to which the word line of the receiving target row address belongs is the fourth storage array of the second storage array group.

[0036] It should be noted that, Figure 2 and Figure 3 In this context, A<12:11> refers to the second identifier information corresponding to each storage array. <13> This refers to the fourth identification information corresponding to each storage array group, that is... Figure 2 and Figure 3In the first storage array, the second identification information is 00; the second identification information is 01; the second identification information is 10; the second identification information is 11; the fourth identification information is 0; and the fourth identification information is 1.

[0037] S130. When the target row address is the same as the failed row address, determine the target redundant word line for receiving the target row address based on the target storage array to which the word line of the receiving target row address belongs.

[0038] The address of the failed row is determined based on the memory testing process.

[0039] By comparing the target row address corresponding to the received activation operation with the failure row address, when the target row address corresponding to the activation operation is the same as the failure row address, the target redundant word line of the received target row address is determined according to the target storage array to which the word line of the received target row address belongs.

[0040] Specifically, if the target storage array to which the word line receiving the target row address belongs does not include redundant word lines, a redundant word line is selected from any storage array that includes redundant word lines as the target redundant word line for receiving the target row address; if the target storage array to which the word line receiving the target row address belongs includes redundant word lines, a redundant word line is selected from a storage array outside the target storage array that includes redundant word lines as the target redundant word line for receiving the target row address.

[0041] A specific example, see further. Figure 2 The storage array includes a first storage array, a second storage array, a third storage array, and a fourth storage array. The second storage array includes a first redundant word line, and the third storage array includes a second redundant word line. Figure 2 (The redundant word lines included in the second and third storage arrays are not shown). Based on the target storage array to which the word line of the target row address belongs, the target redundant word line for the target row address is determined, including: when the target storage array to which the word line of the target row address belongs is the first or fourth storage array, selecting a redundant word line from the second storage array as the target redundant word line for the target row address, or selecting a redundant word line from the third storage array as the target redundant word line for the target row address; when the target storage array to which the word line of the target row address belongs is the second storage array, selecting a redundant word line from the third storage array as the target redundant word line for the target row address; when the target storage array to which the word line of the target row address belongs is the third storage array, selecting a redundant word line from the second storage array as the target redundant word line for the target row address.

[0042] Another specific example, such as Figure 3 As shown, the storage array includes a first storage array group and a second storage array group. Both the first and second storage array groups include a first storage array, a second storage array, a third storage array, and a fourth storage array. The second storage array includes a first redundant word line, and the third storage array includes a second redundant word line. Figure 3 (Redundant word lines included in the second and third storage arrays are not shown). Determining the target redundant word line for receiving the target row address based on the target storage array to which the word line of the received target row address belongs includes: when the target storage array group to which the word line of the received target row address belongs is the first storage array group, and the target storage array is either the first storage array or the fourth storage array, then selecting a redundant word line from the second storage array of the first storage array group as the target redundant word line for receiving the target row address, or selecting a redundant word line from the third storage array of the first storage array group as the target redundant word line for receiving the target row address; when the target storage array group to which the word line of the received target row address belongs is the first storage array group, and the target storage array is the second storage array, then selecting a redundant word line from the third storage array of the first storage array group as the target redundant word line for receiving the target row address; when the target storage array group to which the word line of the received target row address belongs is the first storage array group, and the target storage array is the third storage array, then selecting a redundant word line from the second storage array of the first storage array group as the target redundant word line for receiving the target row address. When the target storage array group to which the word line receiving the target row address belongs is the second storage array group, and the target storage array is the first storage array or the fourth storage array, a redundant word line is selected from the second storage array of the second storage array group as the target redundant word line for receiving the target row address, or a redundant word line is selected from the third storage array of the second storage array group as the target redundant word line for receiving the target row address; when the target storage array group to which the word line receiving the target row address belongs is the second storage array group, and the target storage array is the second storage array, a redundant word line is selected from the third storage array of the second storage array group as the target redundant word line for receiving the target row address; when the target storage array group to which the word line receiving the target row address belongs is the second storage array group, and the target storage array is the third storage array, a redundant word line is selected from the second storage array of the second storage array group as the target redundant word line for receiving the target row address.

[0043] It should be noted that the above embodiments exemplify that the memory includes two sets of memory array groups. The memory may also include three or more sets of memory array groups. This disclosure does not specifically limit the number of memory array groups. When there are multiple sets of memory array groups, the row address carried by the activation command during normal activation operation can be RADT<14:3>. The address information of the second address interval in the target row address is the address information of the thirteenth to fourteenth address interval in the target row address, that is, RADT<14:13>.

[0044] Combination Figure 4 When the second and third storage arrays include redundant word lines, and the target storage array to which the word line receiving the target row address belongs is determined to be the second storage array based on the address information of the first address interval in the target row address, if the redundant word line in the second storage array is selected, the enable time of the redundant word line is t1. That is, the redundant word line of storage array 2 can only be enabled after the word line of the target row address is disabled. If the redundant word line in the third storage array is selected, since the word line of the target row address in the third storage array has not been disabled, the enable time of the redundant word line in the third storage array is t2. The enable time of the redundant word line in the third storage array is t1-t2 earlier than the enable time of the redundant word line in the second storage array. That is, the tRCD improvement time inside the chip is t1-t2, which reduces the tRCD inside the chip and improves the chip read and write efficiency.

[0045] The memory failure cell repair method provided in this disclosure first responds to receiving an activation operation submitted by a target object and obtains the target row address corresponding to the activation operation; then, based on the address information of the first address interval in the target row address, it determines the target memory array to which the word line receiving the target row address belongs; finally, when the target row address is the same as the failure row address, it determines the target redundant word line receiving the target row address based on the target memory array to which the word line receiving the target row address belongs. When the target memory array to which the word line receiving the target row address belongs does not include redundant word lines, a redundant word line is selected from any memory array that includes redundant word lines as the target redundant word line receiving the target row address; when the target memory array to which the word line receiving the target row address belongs includes redundant word lines, a redundant word line is selected from a memory array outside the target memory array that includes redundant word lines as the target redundant word line receiving the target row address. This avoids using the redundant word line of the memory array where the failure word line is located to repair the failure memory cell, which increases the tRCD inside the chip and affects the chip's read / write efficiency.

[0046] Based on the above embodiments, the method for repairing failed memory cells in a memory provided in this disclosure further includes: Obtain the selection signal, which is used to select the repair method.

[0047] at this time, Figure 2 The specific implementation process of step S130 includes: determining the target redundant word line for receiving the target row address based on the target storage array to which the word line of the target row address belongs and the selection signal.

[0048] Specifically, when the target storage array to which the word line receiving the target row address belongs does not include redundant word lines and the selection signal is the first selection signal, a redundant word line is selected from any storage array that includes redundant word lines as the target redundant word line for receiving the target row address; when the target storage array to which the word line receiving the target row address belongs includes redundant word lines and the selection signal is the first selection signal, a redundant word line is selected from a storage array outside the target storage array that includes redundant word lines as the target redundant word line for receiving the target row address; when the selection signal is the second selection signal, a redundant word line is selected from any storage array that includes redundant word lines as the target redundant word line for receiving the target row address.

[0049] In other words, in this implementation, by adding a selection signal, if the selection signal is the first selection signal, and if there are redundant word lines in the target memory array, then a redundant word line is selected from the memory array outside the target memory array that includes redundant word lines as the target redundant word line for receiving the target row address. If the selection signal is the second selection signal, if there are redundant word lines in the target memory array, either the redundant word line of the target memory array can be selected as the target redundant word line for receiving the target row address, or a redundant word line can be selected from the memory array outside the target memory array that includes redundant word lines as the target redundant word line for receiving the target row address. By adding a row address repair mode, the row address repair mode can be freely selected according to the actual performance of the memory, which can ensure the efficient use of redundant circuits and ensure that the chip performance is not reduced, thereby improving the product yield.

[0050] The following example illustrates this: different memory arrays are equipped with corresponding comparison circuits. These circuits compare the received target row address with the failed row address, and based on the comparison result, output a selection signal. This selection signal determines whether to use a normal word line or a redundant word line. Specifically, during testing, the memory stores the failed row address in the redundant circuit, such as... Figure 5AAs shown in 5B, RAXAFTL<12:3> is the address of the invalid line. <12> This refers to the twelfth bit of the invalid line address, ..., RAXAFTL <3> This refers to the third bit of the failed line address. Failed line addresses are loaded during memory power-on. RAF<12:3> is the loaded failed line address. <12> This refers to the address of the twelfth invalid line that was loaded, ..., RAF <3> This refers to the third bit of the loaded failed row address. The redundant circuit processes the failed row address to obtain the loaded failed row address. RADT<12:3> is the target row address carried by the activation command during normal activation operation. RRFAHIT<12:3> is the comparison signal, and RAXAFTL... <12> This refers to the twelfth bit comparison signal, ... RAXAFTL <3> This refers to the third comparison signal, while RRHITB is the enable signal for normal word line or redundant word line (RRHITB=0 selects redundant word line, RRHITB=1 selects normal word line), and SEL is the selection signal used to select the word line repair mode (SEL=0, that is, when the selection signal is the second selection signal, a redundant word line is selected from any memory array that includes redundant word lines as the target redundant word line for receiving the target row address; SEL=1, that is, when the selection signal is the first selection signal, when the target memory array to which the word line of the target row address belongs includes redundant word lines, a redundant word line is selected from a memory array outside the target memory array that includes redundant word lines as the target redundant word line for receiving the target row address).

[0051] Taking the second memory array as an example, if the failed row address A<12:3>=0100000000, meaning the failed row address is located in the second memory array, the failed row address needs to be input as RAXAFTL<12:3>=110000000000 during storage of the failed row address into the redundancy circuit. The failed row address loaded during power-on is RAF<12:3>=0011111111, and the row address input during normal operation is RADT<12:3>=0100000000. Figure 5A After the comparison circuit of the second memory array shown completes the comparison, the comparison signal RRFAHIT<12:3>=1111111111. If another selection signal SEL=0 is selected, the subsequent logic circuit processes the comparison signal to obtain the enable signal RRHITB=0. Redundant word lines can be selected to repair the failed word lines. The redundant word lines can be redundant word lines in the second memory array or redundant word lines in the third memory array.

[0052] If the failed row address A<12:3>=0100000000, meaning the failed row address is located in the second memory array, and if you want to use the redundant word lines in the second memory array for repair, then when transferring the failed row address to the redundant circuit, the required failed row address is RAXAFTL<12:3>=110000000000. The failed row address loaded during power-on is RAF<12:3>=0011111111, and the row address input during normal operation is RADT<12:3>=0100000000. Based on... Figure 5A After the comparison circuit of the second memory array is completed, the comparison signal RRFAHIT<12:3>=1111111111. If SEL=1, the subsequent logic circuit processes the comparison signal to obtain the enable signal RRHITB=1. At this time, the redundant word line in the second memory array is selected to repair the failed word line. Alternatively, the redundant word line in the third memory array can be selected to repair the failed word line in the second memory array.

[0053] The third storage array operates on the same principle as the second storage array, and this embodiment will not be described in detail.

[0054] Based on the above embodiments, this disclosure also provides a device for repairing failed memory cells in a memory. The memory includes multiple memory arrays, each memory array includes multiple memory cells arranged in an array, and at least two of the multiple memory arrays include redundant word lines, such as... Figure 6 As shown, the device for repairing failed memory cells in a memory includes: The target row address acquisition module 410 is used to acquire the target row address corresponding to the activation operation in response to receiving the activation operation submitted by the target object; The target storage array determination module 420 is used to determine the target storage array to which the word line receiving the target row address belongs based on the address information of the first address interval in the target row address; The target redundant word line determination module 430 is used to determine the target redundant word line receiving the target row address based on the target storage array to which the word line receiving the target row address belongs when the target row address is the same as the failed row address.

[0055] The memory failure cell repair apparatus provided in this disclosure first responds to receiving an activation operation submitted by a target object and obtains the target row address corresponding to the activation operation; then, based on the address information of the first address interval in the target row address, it determines the target memory array to which the word line receiving the target row address belongs; finally, when the target row address is the same as the failure row address, it determines the target redundant word line receiving the target row address based on the target memory array to which the word line receiving the target row address belongs. When the target memory array to which the word line receiving the target row address belongs does not include redundant word lines, a redundant word line is selected from any memory array that includes redundant word lines as the target redundant word line receiving the target row address; when the target memory array to which the word line receiving the target row address belongs includes redundant word lines, a redundant word line is selected from a memory array outside the target memory array that includes redundant word lines as the target redundant word line receiving the target row address. This avoids using redundant word lines from the memory array where the failure word line is located to repair the failure memory cell, which increases the tRCD inside the chip and affects the chip's read / write efficiency.

[0056] In some embodiments of this disclosure, determining the target redundant word line receiving the target row address based on the target storage array to which the word line receiving the target row address belongs includes: When the target memory array to which the word line receiving the target row address belongs does not include redundant word lines, a redundant word line is selected from any memory array that includes redundant word lines as the target redundant word line for receiving the target row address. When the target storage array to which the word line receiving the target row address belongs includes redundant word lines, a redundant word line is selected from a storage array outside the target storage array that includes redundant word lines as the target redundant word line for receiving the target row address.

[0057] In some embodiments of this disclosure, the storage array includes a first storage array, a second storage array, a third storage array, and a fourth storage array, wherein the second storage array includes a first redundant word line, and the third storage array includes a second redundant word line; The step of determining the target redundant word line receiving the target row address based on the target storage array to which the word line receiving the target row address belongs includes: When the target storage array to which the word line receiving the target row address belongs is the first storage array or the fourth storage array, a redundant word line is selected from the second storage array as the target redundant word line for receiving the target row address, or a redundant word line is selected from the third storage array as the target redundant word line for receiving the target row address. When the target storage array to which the word line receiving the target row address belongs is the second storage array, a redundant word line is selected from the third storage array as the target redundant word line for receiving the target row address. When the target storage array to which the word line receiving the target row address belongs is the third storage array, a redundant word line is selected from the second storage array as the target redundant word line for receiving the target row address.

[0058] In some embodiments of this disclosure, the storage array includes at least a first storage array group and a second storage array group, wherein the first storage array group and the second storage array group include a first storage array, a second storage array, a third storage array and a fourth storage array, the second storage array includes a first redundant word line, and the third storage array includes a second redundant word line; Before determining the target memory array to which the word line receiving the target row address belongs based on the address information of the first address range in the target row address, the method further includes: The third identification information is determined based on the address information of the second address range in the target row address; Based on the correspondence between the third identification information and the fourth identification information of the storage array group, the target storage array group to which the word line receiving the target row address belongs is determined.

[0059] In some embodiments of this disclosure, before determining the target redundant word line receiving the target row address based on the target storage array to which the word line receiving the target row address belongs, the method further includes: Acquire a selection signal, wherein the selection signal is used to select a repair method; The step of determining the target redundant word line receiving the target row address based on the target storage array to which the word line receiving the target row address belongs includes: The target redundant word line for receiving the target row address is determined based on the target storage array to which the word line receiving the target row address belongs and the selection signal.

[0060] In some embodiments of this disclosure, determining the target redundant word line receiving the target row address based on the target memory array to which the word line receiving the target row address belongs and the selection signal includes: When the target memory array to which the word line receiving the target row address belongs does not include redundant word lines and the selection signal is the first selection signal, a redundant word line is selected from any memory array that includes redundant word lines as the target redundant word line for receiving the target row address. When the target memory array to which the word line receiving the target row address belongs includes redundant word lines and the selection signal is the first selection signal, a redundant word line is selected from a memory array outside the target memory array that includes redundant word lines as the target redundant word line for receiving the target row address. When the selection signal is the second selection signal, a redundant word line is selected from any memory array including redundant word lines as the target redundant word line for receiving the target row address.

[0061] In some embodiments of this disclosure, determining the target memory array to which the word line receiving the target row address belongs, based on the address information of the first address range in the target row address, includes: The first identification information is determined based on the address information of the first address range in the target row address; Based on the correspondence between the first identification information and the second identification information of the storage array, the target storage array to which the word line receiving the target row address belongs is determined.

[0062] Based on the above embodiments, this application also provides a computer device, please refer to the following for details. Figure 7 , Figure 7 This is a basic structural block diagram of the computer device in this embodiment.

[0063] The computer device includes a memory 510 and a processor 520 that are interconnected via a system bus. It should be noted that only a computer device with components 510-520 is shown in the figure; however, it should be understood that it is not required to implement all the shown components, and more or fewer components may be implemented alternatively. Those skilled in the art will understand that the computer device described herein is a device capable of automatically performing numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes, but is not limited to, microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), embedded devices, etc.

[0064] Computer devices can include desktop computers, laptops, handheld computers, and cloud servers. These devices allow for human-computer interaction with users through methods such as keyboards, mice, remote controls, touchpads, or voice-activated devices.

[0065] The memory 510 includes at least one type of readable storage medium, including non-volatile memory or volatile memory, such as flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. RAM may include static RAM or dynamic RAM. In some embodiments, the memory 510 may be an internal storage unit of a computer device, such as the hard disk or memory of the computer device. In other embodiments, the memory 510 may also be an external storage device of the computer device, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, or flash card equipped on the computer device. Of course, the memory 510 may include both internal storage units and external storage devices of the computer device. In this embodiment, the memory 510 is typically used to store the operating system and various application software installed on the computer device, such as the program code of the method described above. In addition, the memory 510 may also be used to temporarily store various types of data that have been output or will be output.

[0066] The processor 520 is typically used to perform the overall operation of a computer device. In this embodiment, the memory 510 is used to store program code or instructions, including computer operation instructions. The processor 520 is used to execute the program code or instructions stored in the memory 510 or to process data, such as program code that runs the methods described above.

[0067] In this article, the bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. This bus system can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0068] Another embodiment of this application also provides a computer-readable medium, which may be a computer-readable signal medium or a computer-readable medium. A processor in a computer reads computer-readable program code stored in the computer-readable medium, enabling the processor to execute the functional actions specified in each step or combination of steps in the above method; and to generate means for implementing the functional actions specified in each block or combination of blocks in the block diagram.

[0069] Computer-readable media include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared memory or semiconductor systems, devices or apparatuses, or any suitable combination thereof, wherein the memory is used to store program code or instructions, the program code including computer operation instructions, and the processor is used to execute the program code or instructions of the above-described methods stored in the memory.

[0070] The definitions of memory and processor can be found in the description of the foregoing computer device embodiments, and will not be repeated here.

[0071] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0072] In the various embodiments of this application, the functional units or modules can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0073] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0074] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0075] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0076] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A method for repairing failed memory cells in a memory, the memory comprising multiple memory arrays, any one memory array comprising multiple memory cells arranged in an array, wherein at least two of the multiple memory arrays include redundant word lines, characterized in that, include: In response to receiving an activation operation submitted by the target object, obtain the target row address corresponding to the activation operation; Based on the address information of the first address range in the target row address, determine the target memory array to which the word line receiving the target row address belongs; When the target row address is the same as the failed row address, the target redundant word line receiving the target row address is determined according to the target storage array to which the word line receiving the target row address belongs; The step of determining the target redundant word line receiving the target row address based on the target storage array to which the word line receiving the target row address belongs includes: When the target memory array to which the word line receiving the target row address belongs does not include redundant word lines, a redundant word line is selected from any memory array that includes redundant word lines as the target redundant word line for receiving the target row address. When the target storage array to which the word line receiving the target row address belongs includes redundant word lines, a redundant word line is selected from a storage array outside the target storage array that includes redundant word lines as the target redundant word line for receiving the target row address.

2. The method according to claim 1, characterized in that, The storage array includes a first storage array, a second storage array, a third storage array, and a fourth storage array. The second storage array includes a first redundant word line, and the third storage array includes a second redundant word line. The step of determining the target redundant word line receiving the target row address based on the target storage array to which the word line receiving the target row address belongs includes: When the target storage array to which the word line receiving the target row address belongs is the first storage array or the fourth storage array, a redundant word line is selected from the second storage array as the target redundant word line for receiving the target row address, or a redundant word line is selected from the third storage array as the target redundant word line for receiving the target row address. When the target storage array to which the word line receiving the target row address belongs is the second storage array, a redundant word line is selected from the third storage array as the target redundant word line for receiving the target row address. When the target storage array to which the word line receiving the target row address belongs is the third storage array, a redundant word line is selected from the second storage array as the target redundant word line for receiving the target row address.

3. The method according to claim 1, characterized in that, The storage array includes at least a first storage array group and a second storage array group. The first storage array group and the second storage array group include a first storage array, a second storage array, a third storage array and a fourth storage array. The second storage array includes a first redundant word line and the third storage array includes a second redundant word line. Before determining the target memory array to which the word line receiving the target row address belongs based on the address information of the first address range in the target row address, the method further includes: The third identification information is determined based on the address information of the second address range in the target row address; Based on the correspondence between the third identification information and the fourth identification information of the storage array group, the target storage array group to which the word line receiving the target row address belongs is determined.

4. The method according to claim 1, characterized in that, Before determining the target redundant word line receiving the target row address based on the target storage array to which the word line receiving the target row address belongs, the method further includes: Acquire a selection signal, wherein the selection signal is used to select a repair method; The step of determining the target redundant word line receiving the target row address based on the target storage array to which the word line receiving the target row address belongs includes: The target redundant word line for receiving the target row address is determined based on the target storage array to which the word line receiving the target row address belongs and the selection signal.

5. The method according to claim 4, characterized in that, The step of determining the target redundant word line receiving the target row address based on the target storage array to which the word line receiving the target row address belongs and the selection signal includes: When the target memory array to which the word line receiving the target row address belongs does not include redundant word lines and the selection signal is the first selection signal, a redundant word line is selected from any memory array that includes redundant word lines as the target redundant word line for receiving the target row address. When the target memory array to which the word line receiving the target row address belongs includes redundant word lines and the selection signal is the first selection signal, a redundant word line is selected from a memory array outside the target memory array that includes redundant word lines as the target redundant word line for receiving the target row address. When the selection signal is the second selection signal, a redundant word line is selected from any memory array including redundant word lines as the target redundant word line for receiving the target row address.

6. The method according to claim 1, characterized in that, The step of determining the target memory array to which the word line receiving the target row address belongs, based on the address information of the first address range in the target row address, includes: The first identification information is determined based on the address information of the first address range in the target row address; Based on the correspondence between the first identification information and the second identification information of the storage array, the target storage array to which the word line receiving the target row address belongs is determined.

7. A device for repairing failed memory cells in a memory, the memory comprising multiple memory arrays, each memory array comprising multiple memory cells arranged in an array, wherein at least two of the multiple memory arrays include redundant word lines, characterized in that, include: The target row address acquisition module is used to acquire the target row address corresponding to the activation operation in response to receiving the activation operation submitted by the target object. The target storage array determination module is used to determine the target storage array to which the word line receiving the target row address belongs, based on the address information of the first address interval in the target row address; The target redundant word line determination module is used to determine the target redundant word line receiving the target row address based on the target storage array to which the word line receiving the target row address belongs when the target row address is the same as the failed row address. The step of determining the target redundant word line receiving the target row address based on the target storage array to which the word line receiving the target row address belongs includes: When the target memory array to which the word line receiving the target row address belongs does not include redundant word lines, a redundant word line is selected from any memory array that includes redundant word lines as the target redundant word line for receiving the target row address. When the target storage array to which the word line receiving the target row address belongs includes redundant word lines, a redundant word line is selected from a storage array outside the target storage array that includes redundant word lines as the target redundant word line for receiving the target row address.

8. A computer device, characterized in that, include: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1 to 6.

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