Centrally embedded package substrate and manufacturing method thereof

Abstract

The invention provides a centrally embedded package substrate and a manufacturing method thereof. Specifically, the manufacturing method comprises the following steps: firstly, embedding a frame substrate into a second dielectric layer, and filling and leveling up an opening of the frame substrate by the second dielectric layer; attaching a component to the surface of the second dielectric layer in the opening; and finally, pressing the component into the second dielectric layer in the opening. According to the technical scheme, the influence of glue overflow and poor bottom flatness on the surface mounting of the component under the condition that the opening is not filled and leveled up can be effectively avoided.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging technology, and in particular to a centrally embedded packaging substrate and a manufacturing method thereof. Background Art

[0002] Embedded substrate (ES) is an advanced packaging technology that embeds passive components (such as capacitors, resistors, and inductors) or active components (such as chips) directly into the package substrate. Through high-density interconnection and three-dimensional integration, it helps achieve miniaturization of electronic devices. Summary of the Invention

[0003] In view of this, the present disclosure aims to provide a centrally embedded packaging substrate and a manufacturing method thereof.

[0004] Based on the above objectives, in a first aspect, the present disclosure provides a method for manufacturing a centrally embedded packaging substrate, comprising:

[0005] (a) providing a frame substrate; wherein the frame substrate comprises a first surface and a second surface disposed opposite to each other; the frame substrate comprises openings and through-hole columns penetrating the first surface and the second surface;

[0006] (b) attaching a second dielectric layer to the first surface of the frame substrate; wherein the second dielectric layer is an adhesive dielectric layer;

[0007] (c) extruding the frame substrate into the second dielectric layer so that the second dielectric layer is squeezed into the opening, wherein the second dielectric layer fills the opening;

[0008] (d) adhering components to the surface of the second dielectric layer in the opening on the second surface of the frame substrate;

[0009] (e) pressing the component into the second dielectric layer in the opening;

[0010] (f) laminating a third dielectric layer on the second surface of the frame substrate, and curing the second dielectric layer and the third dielectric layer;

[0011] (g) forming a first circuit layer on the surface of the second dielectric layer; and forming a second circuit layer on the surface of the third dielectric layer; wherein,

[0012] The through-hole column is conductively connected to the first circuit layer and the second circuit layer; at least one of the first circuit layer and the second circuit layer is conductively connected to the terminal of the component.

[0013] In some embodiments, before step (c), the method further comprises: covering the second surface with a first film layer;

[0014] Before step (d), the method further includes: removing the first film layer.

[0015] In some embodiments, the first film layer includes a polyethylene terephthalate film.

[0016] In some embodiments, step (d) further includes: pre-baking the second dielectric layer after attaching the components.

[0017] In some embodiments, the pre-baking temperature is selected from 60 to 200° C., and the baking time is selected from 10 to 120 minutes.

[0018] In some embodiments, step (a) comprises:

[0019] (a1) providing a carrier plate, and forming a through-hole column and a sacrificial column on the carrier plate;

[0020] (a2) forming a first dielectric layer on the carrier board, embedding the through-hole pillar and the sacrificial pillar, wherein the first dielectric layer exposes end surfaces of the through-hole pillar and the sacrificial pillar;

[0021] (a3) removing the carrier plate;

[0022] (a4) Etching and removing the sacrificial post, so that the first dielectric layer surrounded by the sacrificial post falls off to form the opening.

[0023] In some embodiments, the second dielectric layer and the third dielectric layer are made of the same or different materials; and / or

[0024] The second dielectric layer and the third dielectric layer are made of resin material without glass fiber.

[0025] In some embodiments, the process of step (c) is vacuum hot pressing; and / or

[0026] The process of step (e) is vacuum hot pressing.

[0027] In some embodiments, step (g) comprises:

[0028] (g1) forming a first blind hole exposing a terminal of the component and a second blind hole exposing an end surface of the through-hole column;

[0029] (g2) forming a first circuit layer on the surface of the second dielectric layer by hole-filling electroplating, and forming a second circuit layer on the surface of the third dielectric layer.

[0030] In some embodiments, the frame substrate further includes a target.

[0031] In some embodiments, the component includes a first terminal proximate to the first surface and a second terminal proximate to the second surface;

[0032] The first circuit layer is conductively connected to the first terminal; the second circuit layer is conductively connected to the second terminal.

[0033] In a second aspect, the present disclosure discloses a centrally embedded packaging substrate, which includes a first dielectric layer, a second dielectric layer, a third dielectric layer, components, a first circuit layer, and a second circuit layer; wherein the first dielectric layer includes a through-hole column and an opening embedded therein, wherein the component is embedded in the opening; the second dielectric layer is on the first surface of the first dielectric layer, and the third dielectric layer is on the second surface of the first dielectric layer, wherein the gap between the component and the opening is filled by the second dielectric layer; the first circuit layer is formed on the surface of the second dielectric layer; the second circuit layer is formed on the surface of the third dielectric layer; the through-hole column is conductively connected to the first circuit layer and the second circuit layer; at least one of the first circuit layer and the second circuit layer is conductively connected to the terminal of the component.

[0034] In some embodiments, the component includes a first terminal close to the second dielectric layer and a second terminal close to the third dielectric layer; the first circuit layer is conductively connected to the first terminal; and the second circuit layer is conductively connected to the second terminal.

[0035] As can be seen from the above, the present disclosure provides a centrally embedded packaging substrate and its manufacturing method. First, the frame substrate is embedded in the second dielectric layer, and the second dielectric layer fills the opening of the frame substrate; then, the components are attached to the surface of the second dielectric layer in the opening; and finally, the components are pressed into the second dielectric layer in the opening. In conventional technology, the components are first adhered to the opening and then the filler is injected into the opening, which often easily causes technical problems such as component displacement and incomplete filling. The technical solution of the present application not only effectively avoids the above-mentioned technical problems in conventional technology, but also effectively avoids the impact of component placement due to glue overflow and poor bottom flatness when the opening is not filled. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the present disclosure or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] FIG1( a ) is a schematic diagram showing a process of manufacturing a packaging substrate provided by related art in an ideal state;

[0038] FIG1( b ) shows a schematic diagram of a process of manufacturing a packaging substrate provided by the related art in an actual state;

[0039] Figure 2(a) to Figure 2(h) A schematic cross-sectional view showing the intermediate structure of each step of a method for manufacturing a centrally embedded packaging substrate provided by an embodiment of the present disclosure;

[0040] Figure 3 A schematic structural diagram of a centrally embedded packaging substrate provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0041] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0042] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative position relationships. When the absolute position of the described object changes, the relative position relationship may also change accordingly.

[0043] In the drawings, the thickness and shapes of some layers and regions may be exaggerated for better understanding and ease of description.

[0044] Figure 1(a) illustrates a schematic diagram of an ideal process for fabricating a package substrate according to related art; Figure 1(b) illustrates a schematic diagram of an actual process for fabricating a package substrate according to related art. As shown in Figure 1(a), in an ideal state, carrier film 101 is attached to frame 102, and the interface between the two is smooth and free of adhesive overflow. In this case, component 103 can be properly attached to carrier film 101 at the bottom of the opening of frame 102. Unfortunately, this is not the case in reality. As shown in Figure 1(b), carrier film 101 is a permanent resin film that needs to be heated to a certain melt viscosity before being attached to frame 102. This is often done under vacuum. Both of these factors can cause the permanent resin film 101 to overflow around the opening of frame 102, or even onto its surface. This reduces the size of the opening and degrades the flatness of the film at the bottom of the opening, ultimately preventing component 103 from being properly attached to carrier film 101 at the bottom of the opening. In addition, considering that the fluidity of the permanent resin film 101 during the vacuum hot pressing process is unavoidable, when the component 103 and the permanent resin film 101 are pressed together by vacuum hot pressing, the fluidity of the permanent resin film 101 will cause the component 103 to move, resulting in a positional offset of the component 103, making it difficult to align the subsequent wiring layers.

[0045] In light of this, the present disclosure provides a centrally embedded package substrate and its manufacturing method. First, a frame substrate is embedded in a second dielectric layer, which then fills the opening in the frame substrate. Components are then attached to the surface of the second dielectric layer within the opening. Finally, the components are pressed into the second dielectric layer within the opening. This technical solution effectively prevents component placement issues caused by adhesive overflow and poor bottom flatness when the opening is not filled.

[0046] Figure 2(a) to Figure 2(h) A schematic cross-sectional view of the intermediate structure of each step of a method for manufacturing a centrally embedded package substrate provided by an embodiment of the present disclosure is shown. The manufacturing method specifically includes:

[0047] First, a frame substrate 201 is provided—step (a), as shown in FIG. 2( a ).

[0048] Optionally, the frame substrate 201 includes a first surface A and a second surface B that are opposite to each other; the frame substrate 201 includes an opening 2013 passing through the first surface A and the second surface B, a through-hole column 2012 and a target 2014 .

[0049] The present disclosure exemplarily describes the method for manufacturing the frame substrate 201 as follows:

[0050] (a1) A carrier plate is provided, and a through-hole column 2012 and a sacrificial column are formed on the carrier plate. It should be noted that the specific process for forming the through-hole column 2012 and the sacrificial column on the carrier plate can be formed by electroplating after forming a corresponding pattern using photoresist, which is not described in detail in this disclosure.

[0051] (a2) forming a first dielectric layer 2011 on the carrier plate; the first dielectric layer 2011 exposes end surfaces of the through-hole pillars 2012 and the sacrificial pillars;

[0052] (a3) removing the carrier plate;

[0053] (a4) The sacrificial pillars are etched away, so that the first dielectric layer 2011 surrounded by the sacrificial pillars falls off to form openings 2013. Here, the number of openings 2013 can be set as needed, and this disclosure does not limit this.

[0054] In addition, the size of the opening 2013 is larger than the size of the component 204 to be embedded subsequently, so as to ensure that the component 204 can be embedded in the opening 2013 .

[0055] Here, the target 2014 can be formed simultaneously with the through-hole column 2012, which can effectively reduce the manufacturing process and lower the preparation cost.

[0056] It should be noted that the above method of manufacturing the frame substrate 201 is only an example and not a limitation. Any method capable of forming the frame substrate 201 with the opening 2013 and the through-hole column 2012 is applicable to the embodiments of the present disclosure and will not be described in detail.

[0057] Next, the second dielectric layer 202 is attached to the first surface A, and the first film layer 203 is covered on the second surface B—step (b), as shown in FIG2(b).

[0058] Optionally, the second dielectric layer 202 is a bonding dielectric layer. Generally, the bonding dielectric layer is sticky at room temperature or under heating, and can bond the frame substrate 201 .

[0059] In some embodiments, the material of the second dielectric layer 202 may be a resin material that does not contain glass fiber, such as one selected from the group consisting of liquid crystal polymer, BT (bismaleimide triazine) resin, semi-cured prepreg, ABF (Ajinomoto Build-up) film, epoxy resin, and polyimide resin, but the present disclosure is not limited thereto.

[0060] Alternatively, the first film layer 203 may include a polyethylene terephthalate film (PET).

[0061] Then, the frame substrate 201 is embedded in the second dielectric layer 202 , and the second dielectric layer 202 fills the opening 2013 —step (c), as shown in FIG. 2( c ).

[0062] Optionally, the process of step (c) may be vacuum hot pressing.

[0063] It should be understood that precisely controlling the thickness and embedding speed of the second dielectric layer 202 can also ensure that the second dielectric layer 202 fills the opening 2013 evenly without the first film layer 203. The first film layer 203 can prevent the second dielectric layer 202 from overflowing beyond the second surface B, thereby ensuring that the second dielectric layer 202 fills the opening 2013 evenly.

[0064] If the first film layer 203 is covered on the second surface B, the first film layer 203 can be removed after completing step (c). If the first film layer 203 is not covered on the second surface B, the step of removing the first film layer 203 can be omitted.

[0065] Next, components 204 are attached to the surface of the second dielectric layer 202 in the opening 2013—step (d), as shown in FIG. 2( d ).

[0066] Here, attaching the components 204 on the surface of the second dielectric layer 202 can avoid the problems of glue overflow and poor bottom flatness affecting normal component placement when the second dielectric layer 202 is not fully filled in the related technical solutions.

[0067] The component 204 can be an active component (such as a transistor, an IC chip, a logic circuit component, a power amplifier), a passive component (a capacitor, an inductor, a resistor), or a combination thereof. The number of components 204 is not limited to one, and can be multiple.

[0068] In some embodiments, step (d) further includes: pre-baking the second dielectric layer 202 after attaching the component 204 .

[0069] Pre-baking can increase the curing degree of the second dielectric layer 202 without completely curing the second dielectric layer 202 , thereby helping to reduce the positional movement of the components 204 caused by excessive flow of the second dielectric layer 202 during the subsequent vacuum hot pressing process.

[0070] Optionally, the pre-baking temperature is selected from 60° C. to 200° C., such as 80° C., 90° C., 100° C., 120° C., 150° C., 180° C., 200° C., etc. The baking time is selected from 10 to 120 minutes, such as 10 minutes, 20 minutes, 50 minutes, 80 minutes, 100 minutes, 110 minutes, etc. It should be noted that the specific pre-baking temperature and baking time can be determined for different materials of the second dielectric layer 202 while ensuring that the second dielectric layer 202 is not completely cured, and this disclosure does not limit this.

[0071] Then, the component 204 is pressed into the second dielectric layer 202 in the opening—step (e), as shown in Figure 2(e). Optionally, the process of step (e) can be vacuum hot pressing.

[0072] Next, the third dielectric layer 205 is laminated on the second surface, and the second dielectric layer 202 and the third dielectric layer 205 are cured—step (f), as shown in FIG. 2( f ).

[0073] In some embodiments, the material of the third dielectric layer 205 may be a resin material without glass fiber. The resin material without glass fiber is as described above and will not be described in detail.

[0074] It should be noted that the materials of the second dielectric layer 202 and the third dielectric layer 205 may be the same or different. In other words, the materials of the second dielectric layer 202 and the third dielectric layer 205 may be exactly the same, for example, both ABF films. Alternatively, the materials of the second dielectric layer 202 and the third dielectric layer 205 may be completely different, for example, the second dielectric layer 202 may be ABF film, and the third dielectric layer 205 may be PP film.

[0075] Finally, a first circuit layer 208 is formed on the surface of the second dielectric layer 202; a second circuit layer 209 is formed on the surface of the third dielectric layer 205 - step (g), as shown in FIG. Figure 2(g) to Figure 2(h) shown.

[0076] Here, the through-hole column 2012 is conductively connected to the first circuit layer 208 and the second circuit layer 209 ; at least one of the first circuit layer 208 and the second circuit layer 209 is conductively connected to the terminal of the component 204 .

[0077] In Figure 2(h), both first circuit layer 208 and second circuit layer 209 are conductively connected to terminals of component 204. For example, component 204 includes a first terminal near the first surface and a second terminal near the second surface; first circuit layer 208 is conductively connected to the first terminal; and second circuit layer 209 is conductively connected to the second terminal.

[0078] A second dielectric layer 202 and a third dielectric layer 205 are respectively provided on both sides of the frame substrate 201; a first circuit layer 208 is formed on the surface of the second dielectric layer 202; a second circuit layer 209 is formed on the surface of the third dielectric layer 205, so that the component 204 is located in the center of the package substrate.

[0079] In addition, since the first circuit layer 208 and the second circuit layer 209 are both prepared after the components 204 are embedded, the wiring flexibility of the first circuit layer 208 and the second circuit layer 209 can be increased.

[0080] In some embodiments, step (g) comprises:

[0081] As shown in FIG2(g), step (g1): forming a first blind hole 206 exposing the terminal of the component and a second blind hole 207 exposing the end surface of the through-hole column 2012. Here, the first blind hole 206 and the second blind hole 207 can be formed by laser drilling.

[0082] As shown in FIG. 2( h ), step ( g2 ): forming a first circuit layer 208 on the surface of the second dielectric layer 202 by hole-filling electroplating, and forming a second circuit layer 209 on the surface of the third dielectric layer 209 .

[0083] Here, step (g2) can be achieved by preparing a metal seed layer and combining it with electroplating and pattern transfer, which is not limited in the present disclosure.

[0084] As can be seen, the above-described manufacturing method, in which the second dielectric layer 202 is attached to the frame substrate 201, eliminates the need for a semi-finished substrate, thus reducing alignment difficulties. Furthermore, the pre-fabricated through-hole posts 2012 on the frame substrate 201 are used to connect the first circuit layer 208 and the second circuit layer 209, eliminating the need for post-production interlayer vias. Only the first blind vias 206 and the second blind vias 207 need to be filled with electroplating, thus reducing the difficulty and cost of electroplating.

[0085] Based on the same inventive concept, an embodiment of the present disclosure also provides a centrally embedded packaging substrate. Figure 3 FIG. 1 shows a schematic structural diagram of a centrally embedded package substrate provided by an embodiment of the present disclosure. Figure 3 As shown,

[0086] The packaging substrate includes a first dielectric layer 2011, a second dielectric layer 202, a third dielectric layer 203, components 204, a first circuit layer 208, and a second circuit layer 209; wherein the first dielectric layer 2011 includes a through-hole column 2012 and an opening; the component 204 is arranged in the opening; the second dielectric layer 202 and the third dielectric layer 203 are respectively located on two surfaces of the first dielectric layer 2011, and the component 204 is embedded in the second dielectric layer 202; the first circuit layer 208 is located on the surface of the second dielectric layer 202; the second circuit layer 209 is located on the surface of the third dielectric layer 203; the through-hole column 2012 is conductively connected to the first circuit layer 208 and the second circuit layer 209; at least one of the first circuit layer 208 and the second circuit layer 209 is conductively connected to the terminal of the component 204.

[0087] In some embodiments, the component 204 includes a first terminal close to the second dielectric layer 202 and a second terminal close to the third dielectric layer 203 ; the first circuit layer 208 is conductively connected to the first terminal; and the second circuit layer 209 is conductively connected to the second terminal.

[0088] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Within the scope of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0089] The embodiments of the present disclosure are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A method for manufacturing a centrally embedded package substrate, characterized in that: include: (a) providing a frame substrate; wherein the frame substrate comprises a first surface and a second surface disposed opposite to each other; the frame substrate comprises openings and through-hole columns penetrating the first surface and the second surface; (b) attaching a second dielectric layer to the first surface of the frame substrate; wherein the second dielectric layer is an adhesive dielectric layer; (c) extruding the frame substrate into the second dielectric layer so that the second dielectric layer is squeezed into the opening, wherein the second dielectric layer fills the opening; (d) adhering components to the surface of the second dielectric layer in the opening on the second surface of the frame substrate; (e) pressing the component into the second dielectric layer in the opening; (f) laminating a third dielectric layer on the second surface of the frame substrate, and curing the second dielectric layer and the third dielectric layer; (g) forming a first circuit layer on the surface of the second dielectric layer; and forming a second circuit layer on the surface of the third dielectric layer; wherein, The through-hole column is conductively connected to the first circuit layer and the second circuit layer; at least one of the first circuit layer and the second circuit layer is conductively connected to the terminal of the component.

2. The production method according to claim 1, characterized in that Before step (c), the method further includes: covering the second surface with a first film layer; Before step (d), the method further includes: removing the first film layer.

3. The production method according to claim 2, characterized in that: The first film layer includes a polyethylene terephthalate film.

4. The production method according to claim 1, characterized in that Step (d) further includes: pre-baking the second dielectric layer after attaching the components.

5. The production method according to claim 1, characterized in that: The pre-baking temperature is selected from 60 to 200° C., and the baking time is selected from 10 to 120 minutes.

6. The production method according to claim 1, characterized in that: Step (a) further comprises: (a1) providing a carrier plate, and forming a through-hole post and a sacrificial post on the carrier plate; (a2) forming a first dielectric layer on the carrier board, embedding the through-hole pillar and the sacrificial pillar, wherein the first dielectric layer exposes end surfaces of the through-hole pillar and the sacrificial pillar; (a3) removing the carrier plate; (a4) Etching and removing the sacrificial post, so that the first dielectric layer surrounded by the sacrificial post falls off to form the opening.

7. The production method according to claim 1, characterized in that: The materials of the second dielectric layer and the third dielectric layer are the same or different; and / or The second dielectric layer and the third dielectric layer are made of resin material without glass fiber.

8. The production method according to claim 1, characterized in that: The process of step (c) is vacuum hot pressing; and / or The process of step (e) is vacuum hot pressing.

9. The production method according to claim 1, characterized in that: Step (g) comprises: (g1) forming a first blind hole exposing a terminal of the component and a second blind hole exposing an end surface of the through-hole column; (g2) forming a first circuit layer on the surface of the second dielectric layer by hole-filling electroplating, and forming a second circuit layer on the surface of the third dielectric layer.

10. The manufacturing method according to claim 1, characterized in that: The frame substrate further includes a target.

11. The production method according to claim 1, characterized in that: The component comprises a first terminal close to the first surface and a second terminal close to the second surface; The first circuit layer is conductively connected to the first terminal; the second circuit layer is conductively connected to the second terminal.

12. A centrally embedded packaging substrate, characterized in that: The packaging substrate includes a first dielectric layer, a second dielectric layer, a third dielectric layer, components, a first circuit layer, and a second circuit layer; wherein the first dielectric layer includes embedded through-hole columns and openings, wherein the components are embedded in the openings; the second dielectric layer is on the first surface of the first dielectric layer, and the third dielectric layer is on the second surface of the first dielectric layer, wherein the gaps within the openings of the components are filled by the second dielectric layer; the first circuit layer is formed on the surface of the second dielectric layer; the second circuit layer is formed on the surface of the third dielectric layer; the through-hole columns are conductively connected to the first circuit layer and the second circuit layer; and at least one of the first circuit layer and the second circuit layer is conductively connected to the terminals of the components.

13. The packaging substrate according to claim 12, wherein: The component includes a first terminal close to the second dielectric layer and a second terminal close to the third dielectric layer; the first circuit layer is conductively connected to the first terminal; and the second circuit layer is conductively connected to the second terminal.

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