Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof. The first dielectric layer and the second dielectric layer with different etching selectivity are sequentially formed on the substrate with steps, and the step height and the step low are exposed in turns. In the exposure in turns, the contact hole pattern is transferred in turns in different areas by using the etching selectivity difference between the second dielectric layer and the first dielectric layer. Thus, the photoresist thickness is not limited by the step height, and the contact hole line width can be 0.15 μm or below.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] ESD (Electro-Static discharge) structure can release the static electricity generated by electronic components instantaneously, and can effectively protect MOSFET (Metal Oxide Semiconductor Field Effect Transistor) components from damage caused by static electricity. The ESD structure forms a step greater than 6000 angstroms on the surface of the substrate. In subsequent formation of a contact hole by photolithography, in order to avoid the fact that the photoresist cannot cover the step after reflow of the photoresist, the thickness of the photoresist must be greater than the height of the step by 2000-4000 angstroms. In this case, the thickness of the photoresist is usually more than 8000 angstroms to 10000 angstroms.

[0003] For a MOSFET device with a small line width, the ratio of the thickness of the photoresist to the line width is less than 1:5, otherwise the aspect ratio of the photoresist after development is too large, which is prone to cause collapse of the photoresist and cause photolithography failure. Therefore, the MOSFET device with the ESD structure is limited by the thickness of the photoresist, and it is difficult to make the line width of the contact hole less than 0.15 microns. SUMMARY

[0004] The present application aims to provide a semiconductor structure and a manufacturing method thereof, to solve the problem that it is difficult to make the line width of the contact hole of the MOSFET device less than 0.15 microns in the prior art.

[0005] To solve the above problems, the present application provides a manufacturing method of a semiconductor structure, comprising:

[0006] providing a substrate, the substrate having a first surface and a second surface, the second surface and the first surface being different in height so as to have a step therebetween;

[0007] forming a first dielectric layer and a second dielectric layer in sequence, the first dielectric layer covering the first surface and the second surface, the second dielectric layer covering the first dielectric layer, the second dielectric layer and the first dielectric layer having different etching selectivities;

[0008] forming a patterned first photoresist layer on the second dielectric layer above the first surface, etching the second dielectric layer with the patterned first photoresist layer as a mask to transfer a first pattern to the second dielectric layer above the first surface, and removing the second dielectric layer above the second surface to obtain a patterned second dielectric layer;

[0009] forming a patterned second photoresist layer on the second surface, and etching the first dielectric layer with the patterned second photoresist layer and the patterned second dielectric layer as masks to transfer a second pattern and the first pattern to the first dielectric layer above the second surface and the first dielectric layer above the first surface respectively, to obtain a patterned first dielectric layer; and

[0010] etching the substrate with the patterned first dielectric layer as a mask to form a contact hole in the substrate.

[0011] Optionally, in the method for manufacturing the semiconductor structure, the first surface is higher than the second surface, or the second surface is higher than the first surface.

[0012] Optionally, in the method for manufacturing the semiconductor structure, when the photoresist layer is formed above the one of the first surface and the second surface with a lower height, the thickness of the photoresist layer is not greater than the step height.

[0013] Optionally, in the method for manufacturing the semiconductor structure, the method for forming the patterned first photoresist layer comprises:

[0014] forming a first initial photoresist layer by spin coating, the first initial photoresist layer covering the first surface and the second dielectric layer above the second surface;

[0015] removing the first initial photoresist layer above the second surface by exposure and development, and patterning the first initial photoresist layer above the first surface to obtain the patterned first photoresist layer.

[0016] Optionally, in the method for manufacturing the semiconductor structure, the method for forming the patterned second photoresist layer comprises:

[0017] forming a second initial photoresist layer by spin coating, the second initial photoresist layer covering the first dielectric layer above the second surface and covering the patterned second dielectric layer;

[0018] removing the second initial photoresist layer covering the patterned second dielectric layer by exposure and development, and patterning the second initial photoresist layer above the second surface to obtain the patterned second photoresist layer.

[0019] Optionally, in the method for manufacturing the semiconductor structure, the material of the first dielectric layer comprises silicon dioxide.

[0020] Optionally, in the method for manufacturing the semiconductor structure, the material of the second dielectric layer includes one or more of amorphous carbon, silicon nitride, silicon oxynitride, and polycrystalline silicon.

[0021] Optionally, in the method for manufacturing the semiconductor structure, the substrate includes a substrate and a functional structure film layer;

[0022] The substrate includes a first region and a second region, the functional structure film layer covers the second region, the surface of the first region constitutes one of the first surface and the second surface, and the surface of the functional structure film layer constitutes the other of the first surface and the second surface.

[0023] Optionally, in the semiconductor structure manufacturing method, the functional structure film is an ESD structure film, which includes a protective layer, a buffer layer, and a conductive layer stacked sequentially from bottom to top.

[0024] The present invention also provides a semiconductor structure manufactured using the manufacturing method described in any of the preceding claims.

[0025] In summary, the semiconductor structure and its manufacturing method provided by the present invention sequentially form a first dielectric layer and a second dielectric layer with different etching selectivity ratios on a substrate with steps, and expose the substrate at the high and low points of the steps in stages. During the staged exposure, the difference in etching selectivity between the second dielectric layer and the first dielectric layer is used to transfer the contact hole pattern in different regions. In this way, the photoresist thickness is not limited by the step height, and the contact hole linewidth can be 0.15 μm or less. Attached Figure Description

[0026] Figure 1 A flowchart of a semiconductor structure manufacturing method provided in Embodiment 1 of the present invention;

[0027] Figures 2-6 For this Figure 1 Schematic diagrams of the device structures corresponding to each step in the process;

[0028] Figure 7 A flowchart of a semiconductor structure manufacturing method provided in Embodiment 2 of the present invention;

[0029] Figures 8-11 For this Figure 7 Schematic diagrams of the device structures corresponding to each step in the process;

[0030] The labels in the attached figures are explained as follows:

[0031] 10 - Substrate; 20 - First dielectric layer; 30 - Second dielectric layer; 40 - First photoresist layer; 50 - Second photoresist layer;

[0032] 101 - Substrate; 102 - Protective layer; 103 - Buffer layer; 104 - Conductive layer;

[0033] 601 - First contact hole; 602 - Second contact hole;

[0034] A - First surface; B - Second surface. Detailed Implementation

[0035] The semiconductor structure and its manufacturing method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise scales, used only to facilitate and clarify the illustration of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different figures may have different emphases and sometimes use different scales. It should be understood that relative terms such as "above," "below," "top," and "bottom" shown in the drawings can be used to describe the relationships between various elements. These relative terms are intended to cover different orientations of elements other than those depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, an element described as "above" another element will now be below that element. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish various components, elements, steps, etc., in the specification, and are not used to indicate logical or sequential relationships between various components, elements, steps, etc.

[0036] Example 1

[0037] like Figure 1 As shown, this embodiment provides a method for manufacturing a semiconductor structure, including the following steps:

[0038] S11, providing a substrate having a first surface and a second surface, the first surface being lower than the second surface such that there is a step between them;

[0039] S12, a first dielectric layer and a second dielectric layer are formed sequentially. The first dielectric layer covers the first surface and the second surface, and the second dielectric layer covers the first dielectric layer. The second dielectric layer and the first dielectric layer have different etching selectivity.

[0040] S13, a patterned first photoresist layer is formed on the second dielectric layer above the first surface, and the second dielectric layer is etched using the patterned first photoresist layer as a mask to transfer the first pattern to the second dielectric layer above the first surface, and the second dielectric layer located above the second surface is removed to obtain the patterned second dielectric layer.

[0041] S14, a patterned second photoresist layer is formed on the second surface; the first dielectric layer is etched using the patterned second photoresist layer and the patterned second dielectric layer as masks, to transfer the second pattern and the first pattern to the first dielectric layer above the second surface and the first dielectric layer above the first surface, respectively, to obtain a patterned first dielectric layer; and,

[0042] S15, using the patterned first dielectric layer as a mask, the substrate is etched to form contact holes within the substrate.

[0043] The manufacturing method provided in this embodiment involves multiple exposures on the step (the first surface at a higher position) and below the step (the second surface at a lower position). The photoresist thickness is not limited by the step height, and the contact hole linewidth can be 0.15μm or less.

[0044] The following combination Figures 2-6 The manufacturing method provided in this embodiment will be further described.

[0045] First, such as Figure 2 As shown, steps S1 and S2 are performed to provide a substrate 10, and a first dielectric layer 20 and a second dielectric layer 30 are sequentially formed on the substrate 10. Since the substrate 10 has steps, the surface of the second dielectric layer 30 still has steps after the first dielectric layer 20 and the second dielectric layer 30 are sequentially formed.

[0046] As an example, the steps of the substrate 10 are formed by forming a functional structure layer on the substrate. Specifically, the substrate 10 includes a substrate 101 and a functional structure film layer. The substrate 101 includes a first region and a second region. The functional structure film layer covers the second region. The surface of the first region constitutes one of the first surface and the second surface. The surface of the functional structure film layer constitutes the other of the first surface and the second surface.

[0047] Further, in the embodiment, the functional structure film layer can be the ESD structure film layer as described above, which includes a protection layer 102, a buffer layer 103 and a conductive layer 104 stacked in sequence from bottom to top. The specific forming process of the ESD structure film layer includes: depositing the protection layer 102, which is used to protect the underlying substrate 101 from subsequent processes (such as ion implantation or high-temperature annealing); depositing the buffer layer 103, which can relieve the stress between the protection layer 102 and the conductive layer 104; and depositing the conductive layer 104, which forms a PN junction with the substrate 101 and is used to discharge static electricity. As an example, the material of the substrate 101 in the embodiment can be silicon, the material of the protection layer 102 can be silicon nitride, the material of the buffer layer 103 can be silicon dioxide, and the material of the conductive layer 104 can be polysilicon. The specific process method for forming the ESD structure film layer is well known to those skilled in the art, and will not be described here.

[0048] In some other embodiments, the step of the step can also be generated by other processes, not necessarily by the ESD structure film layer.

[0049] In the embodiment, the height of the first surface A is less than the height of the second surface B, and accordingly, the height of the second dielectric layer 30 above the first surface A is less than the height of the second dielectric layer 30 above the second surface B.

[0050] The second dielectric layer 30 and the first dielectric layer 20 have different etching selectivity ratios. The first dielectric layer 20 can continue to remain as an interlayer dielectric layer in subsequent processes, and therefore, the first dielectric layer 20 preferably uses a low dielectric constant material. As an example, in the embodiment, the material of the first dielectric layer 20 uses silicon dioxide, and in some other examples, the material of the first dielectric layer 20 can also use fluorine silicate glass (FSG) and the like. Accordingly, the material of the second dielectric layer 30 can use one or more of amorphous carbon, silicon nitride, silicon oxynitride, and polysilicon. When the second dielectric layer 30 is patterned, a suitable etching liquid can be selected to etch and remove the second dielectric layer 30 in a specific area and stop on the first dielectric layer 20. When the first dielectric layer 20 is patterned, a suitable etching liquid can also be selected to etch and remove the first dielectric layer 20 in a specific area, and the previously formed patterned second dielectric layer 30 can act as a protection layer / mask layer in this etching step to protect the underlying first dielectric layer 20 from being etched.

[0051] For example, if the material of the first dielectric layer 20 is silicon dioxide and the material of the second dielectric layer 30 is amorphous carbon, when the target etching object is the second dielectric layer 30, nitric acid can be used for etching, and when the target etching object is the first dielectric layer 20, O2 / H2 / N2 plasma can be used for etching.

[0052] Secondly, step S13 is performed, as shown in the figure, a patterned first photoresist layer 40 is formed on the second dielectric layer 30 above the first surface A, and then, as shown in the figure, an etching process is performed with the patterned first photoresist layer 40 as a mask, at this time, the second dielectric layer 30 above the first surface A is patterned, and the second dielectric layer 30 above the second surface B is etched and removed without photoresist shielding, and finally the second dielectric layer 30 that is left constitutes a patterned second dielectric layer 30. Figure 3 Figure 4

[0053] The method for forming the patterned first photoresist layer 40 can include: forming a first initial photoresist layer by spin coating, the first initial photoresist layer covering the second dielectric layer 30 above the first surface A and the second surface B; removing the first initial photoresist layer above the second surface B by exposure and development, and patterning the first initial photoresist layer above the first surface A to obtain the patterned first photoresist layer 40.

[0054] Because the wafer area is small, generally, the whole surface is spin-coated for coating, therefore, when forming a photoresist layer above the first surface A, first, photoresist coating is needed on the second surface B, because of the manufacturing method provided by the embodiment, this step only needs to use the photoresist formed above the first surface A for first image transfer, and the thickness of the photoresist above the second surface B is not required, therefore, the overall thickness of the photoresist does not need to be greater than the step height 2000-4000 Å, and finally the photoresist layer of the second dielectric layer 30 above the first surface A can have a smaller thickness, even less than 200 Å.

[0055] Next, step S14 is performed, as shown in the figure, Figure 5 ​​As shown, a patterned second photoresist layer 50 is formed on the first dielectric layer 20 above the second surface B, and then an etching process is performed with the patterned second photoresist layer 50 and the patterned second dielectric layer 30 in step S12 as masks, and a second pattern is transferred to the first dielectric layer 20 above the second surface B through the patterned second photoresist layer 50. The second dielectric layer 30 remaining after step S12 also acts as a mask layer in this step, and can also be understood as a protective layer, and the first pattern is transferred to the first dielectric layer 20 above the first surface A. After this step is completed, the first dielectric layer 20 has a first pattern and a second pattern, the first pattern is located in the area above the first surface A, and the second pattern is located in the area above the second surface B. For a MOSEET device, the first pattern formed in the first dielectric layer 20 is a pattern of a first contact hole formed in the substrate 101, and the second pattern formed in the first dielectric layer 20 is a pattern of a second contact hole formed in the conductive layer 104 of the ESD structure film layer.

[0056] The method for forming the patterned second photoresist layer 50 includes: forming a second initial photoresist layer by spin coating, the second initial photoresist layer covering the first dielectric layer 20 above the second surface B and covering the patterned second dielectric layer 30; removing the second initial photoresist layer covering the patterned second dielectric layer 30 by exposure and development, and patterning the second initial photoresist layer above the second surface B to obtain the patterned second photoresist layer 50.

[0057] Finally, step S15 is performed, as shown, the substrate 10 is etched with the patterned first dielectric layer 20 as a mask to form a contact hole in the substrate 10. Figure 6

[0058] Specifically, a first contact hole 601 is formed in the substrate 10 corresponding to the first pattern, and a second contact hole 602 is formed in the substrate 10 corresponding to the second pattern. For a MOSEET device, through this step, a first contact hole 601 is formed in the first region of the substrate 101, and a second contact hole 602 is formed in the conductive layer 104 of the ESD structure film layer.

[0059] The embodiment also provides a semiconductor structure manufactured by the manufacturing method provided by the embodiment. Therefore, the semiconductor structure provided by the embodiment can have a line width of the first contact hole 601 and the second contact hole 602 of 0.15 μm or less.

[0060]

Embodiment Two

[0061] As shown in FIG. 7, the embodiment provides a manufacturing method of a semiconductor structure, comprising:

[0062] S21, providing a substrate 10, the substrate 10 having a first surface A and a second surface B, the first surface A being higher than the second surface B so as to have a step therebetween;

[0063] S22, sequentially forming a first dielectric layer 20 and a second dielectric layer 30, the first dielectric layer 20 covering the first surface A and the second surface B, the second dielectric layer 30 covering the first dielectric layer 20, the second dielectric layer 30 having a different etching selectivity ratio from the first dielectric layer 20;

[0064] S23, forming a patterned first photoresist layer 40 on the second dielectric layer 30 above the first surface A, etching the second dielectric layer 30 with the patterned first photoresist layer 40 as a mask to transfer a first pattern to the second dielectric layer 30 above the first surface A, and removing the second dielectric layer 30 above the second surface to obtain a patterned second dielectric layer 30;

[0065] S24, forming a patterned second photoresist layer 50 on the second surface B, etching the first dielectric layer 20 with the patterned second photoresist layer 50 and the patterned second dielectric layer 30 as masks to transfer a second pattern and the first pattern to the first dielectric layer 20 above the second surface B and the first dielectric layer 20 above the first surface A respectively, to obtain a patterned first dielectric layer 20; and,

[0066] S25, etching the substrate 10 with the patterned first dielectric layer 20 as a mask to form a contact hole in the substrate 10.

[0067] As can be seen, in the embodiment one, the first surface A is the low step, and the second surface B is the high step, while in the embodiment, the first surface A is the high step, and the second surface B is the low step. In the embodiment one, the pattern is transferred at the low step first, while in the embodiment, the pattern is transferred at the high step first.

[0068] The following will be described in combination with Figures 8-11 The manufacturing method provided by the embodiment will be further described.

[0069] Firstly, the step S21 and the step S22 are executed, as shown in FIG. 1, a substrate 10 is provided, the substrate 10 having a first surface A and a second surface B, the first surface A being higher than the second surface B so as to have a step therebetween. Figure 8As shown, a substrate 10 is provided, and a first dielectric layer 20 and a second dielectric layer 30 are formed on the substrate 10 in sequence. Since the substrate 10 has a step, after the first dielectric layer 20 and the second dielectric layer 30 are formed in sequence, the surface of the second dielectric layer 30 still has a step.

[0070] Secondly, step S22 is performed, as shown in the figure, a patterned first photoresist layer 40 is formed on the second dielectric layer 30 above the first surface A, and then an etching process is performed with the patterned first photoresist layer 40 as a mask. At this time, the second dielectric layer 30 above the first surface A is patterned, and the second dielectric layer 30 above the second surface B is etched and removed because it is not blocked by the photoresist. The second dielectric layer 30 finally retained constitutes a patterned second dielectric layer 30. Figure 9 Next, step S23 is performed, as shown in the figure, a patterned second photoresist layer 50 is formed on the first dielectric layer 20 above the second surface B, and then an etching process is performed with the patterned second photoresist layer 50 and the patterned second dielectric layer 30 in step S12 as masks. The second pattern is transferred to the first dielectric layer 20 above the second surface B through the patterned second photoresist layer 50. The second dielectric layer 30 retained after step S12 also acts as a mask layer in this step, which can also be understood as a protection layer 102, and the first pattern is transferred to the first dielectric layer 20 above the first surface A. After this step is completed, the first dielectric layer 20 has a first pattern and a second pattern, the area where the first pattern is located is above the first surface A, and the area where the second pattern is located is above the second surface B.

[0071] Figure 10 Finally, step S24 is performed, as shown in the figure, the substrate 10 is etched with the patterned first dielectric layer 20 as a mask to form a contact hole in the substrate 10.

[0072] Figure 11

[0073] Further comparison between steps S21-S24 of the present embodiment and S11-S14 of Embodiment 1 shows that whether starting from the high or low step for patterning, similar operation processes are performed. In the multiple exposure, the etching selectivity difference between the second dielectric layer 30 and the first dielectric layer 20 is utilized to transfer the contact hole pattern in different regions. In this way, the thickness of the photoresist is not limited by the step height, and the contact hole line width can be as small as 0.15 μm or below.

[0074] ​​​The specific process method or material selection in each step in this embodiment is consistent with that in Embodiment 1, and the related content can be referred to Embodiment 1. It needs to be distinguished that, since the positions of the first surface A and the second surface B described in Embodiment 1 and this embodiment are opposite, the positions corresponding to the first pattern and the second pattern in Embodiment 1 and this embodiment are opposite. In Embodiment 1, the first pattern is used to form a contact hole in the substrate 101, and the second pattern is used to form a contact hole in the conductive layer 104 of the ESD structure. In this embodiment, the first pattern is used to form a contact hole in the conductive layer 104 of the ESD structure, and the second pattern is used to form a contact hole in the substrate 101.

[0075] This embodiment also provides a semiconductor structure manufactured by the manufacturing method provided in this embodiment. Therefore, the line width of the first contact hole 601 and the second contact hole 602 in the semiconductor structure provided in this embodiment can be less than 0.15 μm.

[0076] In summary, the semiconductor structure and the manufacturing method thereof provided in the embodiments of the present application can form a first dielectric layer and a second dielectric layer with different etching selectivity on a substrate with a step in sequence, and perform exposure in sections at the high part of the step and the low part of the step. In the exposure in sections, the contact hole pattern is transferred in sections in different regions by using the difference in etching selectivity between the second dielectric layer and the first dielectric layer. In this way, the thickness of the photoresist is not limited by the height of the step, and the line width of the contact hole can be less than 0.15 μm.

[0077] It needs to be noted that, in this specification, each embodiment is described in a progressive manner, and each embodiment mainly describes the difference from other embodiments. The same or similar parts in each embodiment can be referred to each other. In addition, the different parts in each embodiment can also be used in combination with each other, and the present application is not limited in this respect.

[0078] In addition, it needs to be noted that, although the present application has been disclosed with the above preferred embodiments, the above embodiments are not used to limit the present application. For any skilled person in the art, many possible changes, modifications and modifications, or equivalent embodiments with equivalent changes can be made to the technical solution of the present application without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical solution of the present application, still belongs to the protection scope of the technical solution of the present application.

Claims

1. A method of manufacturing a semiconductor structure, characterized by, The method comprises: providing a substrate having a first surface and a second surface, the second surface and the first surface being different in height so as to have a step therebetween; forming a first dielectric layer and a second dielectric layer in sequence, the first dielectric layer covering the first surface and the second surface, the second dielectric layer covering the first dielectric layer, the second dielectric layer having a different etching selectivity ratio from the first dielectric layer; forming a patterned first photoresist layer on the second dielectric layer above the first surface, etching the second dielectric layer as a mask of the patterned first photoresist layer to transfer a first pattern to the second dielectric layer above the first surface, and removing the second dielectric layer above the second surface to obtain a patterned second dielectric layer; forming a patterned second photoresist layer on the second surface, etching the first dielectric layer as a mask of the patterned second photoresist layer and the patterned second dielectric layer to transfer a second pattern and the first pattern to the first dielectric layer above the second surface and the first dielectric layer above the first surface respectively, and obtaining a patterned first dielectric layer; and, etching the substrate as a mask of the patterned first dielectric layer to form a contact hole in the substrate.

2. The method of manufacturing a semiconductor structure according to claim 1, wherein The first surface is higher than the second surface, or the second surface is higher than the first surface.

3. The method of manufacturing a semiconductor structure according to claim 1, wherein When forming a photoresist layer above the one of the first surface and the second surface that has a lower height, the thickness of the photoresist layer is not greater than the height of the step.

4. The method of manufacturing a semiconductor structure according to claim 1, wherein The method for forming the patterned first photoresist layer comprises: forming a first initial photoresist layer above the first surface and the second surface by spin coating, the first initial photoresist layer covering the second dielectric layer; removing the first initial photoresist layer above the second surface by exposure and development, and patterning the first initial photoresist layer above the first surface to obtain the patterned first photoresist layer.

5. The method of manufacturing a semiconductor structure according to claim 4, wherein The method for forming the patterned second photoresist layer comprises: forming a second initial photoresist layer above the second surface by spin coating, the second initial photoresist layer covering the first dielectric layer and covering the patterned second dielectric layer; removing the second initial photoresist layer covering the patterned second dielectric layer by exposure and development, and patterning the second initial photoresist layer above the second surface to obtain the patterned second photoresist layer.

6. The method of manufacturing a semiconductor structure according to claim 1, wherein The material of the first dielectric layer comprises silicon dioxide.

7. The method of manufacturing a semiconductor structure according to claim 6, wherein The material of the second dielectric layer comprises one or more of amorphous carbon, silicon nitride, silicon oxynitride, and polycrystalline silicon.

8. The method of manufacturing a semiconductor structure according to claim 1, wherein The substrate comprises a substrate and a functional structure film layer. The substrate comprises a first region and a second region, the functional structure film layer covering the second region, a surface of the first region constituting one of the first surface and the second surface, and a surface of the functional structure film layer constituting the other of the first surface and the second surface.

9. The method of manufacturing a semiconductor structure according to claim 8, wherein The functional structure film layer is an ESD structure film layer, and the ESD structure film layer comprises, from bottom to top, a protective layer, a buffer layer and a conductive layer.

10. A semiconductor structure, characterized by The semiconductor structure is manufactured by the manufacturing method according to any one of claims 1-9.

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