Multi-birth chip, wafer and wafer cutting method

Abstract

The invention discloses a multi-birth chip, a wafer and a wafer cutting method, and is applied to the technical field of chip preparation. A plurality of functional areas located on the surface of one side of the substrate; the functional areas are separated by non-functional areas, and reference patterns are arranged in the non-functional areas; the reference patterns are used for identifying the test units and generating an electronic Map when the chip is subjected to an electrical test, so that the contour line of the multiple-birth chip corresponds to the test units in the electronic Map, and the reference patterns which can be identified in the wafer correspond to the test units in the electronic Map one by one. The reference patterns are arranged in the multiple-birth chip, and the recognizable reference patterns in the wafer are in one-to-one correspondence with the test units in the electronic Map, so that the multiple-birth chip can be recognized based on the reference patterns in one-to-one correspondence during cutting recognition, the fixation of the cutting position of the multiple-birth chip is ensured, and the cutting accuracy of the multiple-birth chip is improved. And the chip layout after cutting is matched with the electronic Map, so that the product yield is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of chip preparation, and in particular to a multiple-chip, a wafer and a wafer cutting method. Background Art

[0002] A multiple chip is a chip structure required for chip electrical testing (CP) before wafer sawing. A multiple chip usually has the functional structures of multiple chips.

[0003] In the existing technology, there is a mismatch between the chip layout of multiple chips after wafer cutting and the electronic map (chip test layout diagram) generated by the chip electrical test. This will cause the electronic map to be unable to be used correctly during the chip welding process (Dieattach), resulting in the absorption of electrically failed chips during welding, ultimately affecting the product yield.

[0004] Therefore, how to provide a method that can ensure that the positions of wafer cutting during the preparation of multiple chips match the electronic map during the chip electrical testing is an urgent problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] An object of the present invention is to provide a multiple chip, which can ensure that the position of wafer cutting when preparing multiple chips matches the electronic map during chip electrical testing; another object of the present invention is to provide a wafer and a wafer cutting method, which can ensure that the position of wafer cutting when preparing multiple chips matches the electronic map during chip electrical testing.

[0006] In order to solve the above technical problems, the present invention provides a multiple birth chip, comprising:

[0007] substrate;

[0008] Multiple functional areas are located on the surface of one side of the substrate; the functional areas are separated by non-functional areas, and reference patterns are set in the non-functional areas; the reference patterns are used to identify test units and generate electronic maps when the chips are electrically tested, so that the outlines of the multiple chips correspond to the test units in the electronic map, and the reference patterns that can be identified in the wafer correspond one-to-one to each test unit in the electronic map.

[0009] Optionally, the reference graphic is a reference point formed by a single graphic.

[0010] Optionally, an even number of the functional areas are provided on one surface of the substrate, and the reference point is located at the center of the multiple chips.

[0011] Optionally, the shapes of the reference points on the wafer surface are the same.

[0012] Optionally, the width of the reference point is no greater than two-thirds of the width of the non-functional area, and the depth of the reference point is no greater than 5 μm.

[0013] Optionally, the reference graphic is a combined graphic composed of multiple reference points.

[0014] Optionally, different reference points in the same reference graph have different graphs.

[0015] Optionally, the reference pattern is made of metal material or silicon layer material.

[0016] The present invention also provides a wafer comprising a substrate and a plurality of functional areas located on a surface of one side of the substrate, wherein the functional areas are arranged in an array and separated by non-functional areas; a plurality of the functional areas are combined to form a multiple chip, the non-functional areas between the multiple chips form cutting paths, and the non-functional areas within the multiple chips are provided with reference patterns;

[0017] The reference pattern is used to identify the test unit and generate an electronic map when the chip is electrically tested, so that the wafer includes multiple chips corresponding to the test units in the electronic map, and the reference pattern identifiable in the wafer corresponds one-to-one to each test unit in the electronic map.

[0018] The present invention also provides a wafer cutting method, comprising:

[0019] Obtaining a wafer; the wafer includes a substrate and a plurality of functional areas located on a surface of one side of the substrate, the functional areas being arranged in an array and separated by non-functional areas; the plurality of functional areas being combined to form a multiplex chip, the non-functional areas between the multiplex chips forming dicing lanes, and the non-functional areas within the multiplex chips being provided with reference patterns;

[0020] Identifying the reference pattern, identifying the test unit when the chip is electrically tested and generating an electronic map; the position of the test unit corresponds to the position of the reference pattern;

[0021] Based on the recognition of the reference pattern position, the wafer is cut according to the electronic map to obtain the multiple chips.

[0022] The present invention provides a multiple chip, comprising: a substrate; multiple functional areas located on a surface of one side of the substrate; the functional areas are separated by non-functional areas, and reference patterns are provided in the non-functional areas; the reference patterns are used to identify test units and generate an electronic map when the chip is electrically tested, so that the outlines of the multiple chips correspond to the test units in the electronic map, and the reference patterns identifiable in the wafer correspond one-to-one with each test unit in the electronic map.

[0023] By setting reference patterns in the multiple chips and ensuring that the identifiable reference patterns in the wafer correspond one-to-one to each test unit in the electronic map, the multiple chips can be identified based on the one-to-one corresponding reference patterns during cutting and identification, thereby ensuring that the cutting position of the multiple chips is fixed, ensuring that the chip layout after cutting matches the electronic map, and thus ensuring the product yield.

[0024] The present invention also provides a wafer and a wafer cutting method, which also have the above-mentioned beneficial effects and will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 The schematic diagram of the prior art shows that the layout of the chip after cutting is inconsistent with the layout in the electronic map;

[0027] Figure 2 A schematic structural diagram of a multiple-birth chip provided by an embodiment of the present invention;

[0028] Figure 3 An electronic map provided by an embodiment of the present invention;

[0029] Figure 4 A schematic diagram of cutting for preparing multiple-baby chips provided by an embodiment of the present invention;

[0030] Figure 5 A schematic structural diagram of a wafer provided by an embodiment of the present invention;

[0031] Figure 6 The present invention provides a flow chart of a wafer cutting method.

[0032] In the figure: 1. Functional area, 2. Reference graphics, 3. Test unit. DETAILED DESCRIPTION

[0033] The core of the present invention is to provide a fetus chip. Figure 1 , Figure 1 The schematic diagram of the chip layout after cutting in the prior art is inconsistent with the layout in the electronic map. Figure 1 In the existing technology, the chip cutting process requires that the chip layout after cutting is consistent with the layout in the electronic map. However, at the current stage, there is a situation where the chip layout of multiple chips after wafer cutting does not match the electronic map generated by the chip electrical test. This is because at the current stage, wafer cutting is based on a certain chip as a reference, and the appearance of the chips is the same. This will result in the inability to identify the multiple chips on a fixed chip inside the multiple chips during cutting and identification, which will lead to an unstable identification position. The unstable identification position will lead to an unstable cutting position, that is, the unstable identification chip will lead to an unstable cutting position of the multiple chips. The chip layout after cutting does not match the electronic map, which will make the chip welding process unable to capture the chip according to the electronic map, ultimately affecting the product yield.

[0034] The present invention provides a multiple-chip, comprising: a substrate; a plurality of functional areas located on a surface of one side of the substrate; the functional areas are separated by non-functional areas, and reference patterns are provided in the non-functional areas; the reference patterns are used to identify test units and generate an electronic map when the chip is electrically tested, so that the outline of the multiple-chip corresponds to the test units in the electronic map, and the reference patterns identifiable in the wafer correspond one-to-one to each test unit in the electronic map.

[0035] By setting reference patterns in the multiple chips and ensuring that the identifiable reference patterns in the wafer correspond one-to-one to each test unit in the electronic map, the multiple chips can be identified based on the one-to-one corresponding reference patterns during cutting and identification, thereby ensuring that the cutting position of the multiple chips is fixed, ensuring that the chip layout after cutting matches the electronic map, and thus ensuring the product yield.

[0036] In order to enable those skilled in the art to better understand the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0037] Example 1

[0038] Please refer to Figures 2 to 4 , Figure 2 A schematic structural diagram of a multiple-birth chip provided by an embodiment of the present invention; Figure 3An electronic map provided by an embodiment of the present invention; Figure 4 A schematic diagram of cutting for preparing multiple chips provided by an embodiment of the present invention.

[0039] See also Figure 2 In an embodiment of the present invention, a multiple-chip comprises: a substrate; a plurality of functional areas 1 located on a surface of one side of the substrate; the functional areas 1 are separated by non-functional areas, and the non-functional areas are provided with reference patterns 2; the reference patterns 2 are used to identify test units 3 and generate an electronic map when the chip is electrically tested, so that the outline of the multiple-chip corresponds to the test units 3 in the electronic map, and the reference patterns 2 identifiable in the wafer correspond one-to-one to each test unit 3 in the electronic map.

[0040] The substrate serves as the base for the multiple chips. Multiple functional regions 1 are typically located on the substrate surface, each representing the functional structure of a chip. The specific structure of each functional region 1 depends on the specific function of the chip and is not specifically defined here. The substrate is typically a silicon substrate, although other materials can also be used in this embodiment. The specific material of the substrate is also not specifically defined in this embodiment.

[0041] A multi-chip typically has multiple functional regions 1, separated by non-functional regions. These non-functional regions serve as cutting paths for the multi-chip, and are cut along these non-functional regions. These non-functional regions are typically located between two adjacent functional regions 1 in the multi-chip, and between a single functional region 1 and the edge of the multi-chip.

[0042] In this embodiment, the aforementioned non-functional area is provided with a reference pattern 2, which is used for positioning when dicing the wafer to form multiple chips. In this embodiment, after receiving the incoming wafer, each functional area 1 within the wafer must first undergo chip electrical testing. This chip electrical testing is typically performed based on test cells 3 in the electronic map, which typically cover multiple functional areas 1. During the subsequent wafer dicing process, multiple chips conforming to the outlines of the test cells 3 must be cut, thereby aligning each functional area 1 within the multiple chips with the test results from the chip electrical testing.

[0043] See also Figure 3 as well as Figure 4The electronic map described above is equivalent to the layout diagram of the multiple chips within the wafer required for chip electrical testing. The test cells 3 are the unit structures of the electronic map, corresponding to the corresponding multiple chips. In this embodiment, the outlines of the multiple chips must correspond to the test cells 3 in the electronic map, ensuring that the chip layout of the multiple chips matches the electronic map after wafer dicing. In this embodiment, the reference patterns 2 identifiable within the wafer correspond one-to-one with each test cell 3 in the electronic map. Therefore, each test cell 3 in the electronic map can be located within the wafer based on the identified reference patterns 2. The electronic map includes a correspondence between the position information of each identified reference point 2 and the position information of each test cell 3. Furthermore, after dicing the wafer based on the positioning of the reference points 2, the chip layout of the multiple chips matches the electronic map. Typically, in this embodiment, each reference pattern 2 is located at the same position as the corresponding test cell 3, making it easier to locate the position of the corresponding test cell 3 based on the reference pattern 2. It should be noted that the outline of the above-mentioned test unit 3 may exceed the outline of the wafer, which will not affect the corresponding relationship between the reference pattern 2 and the test unit 3, including their positional correspondence.

[0044] In this embodiment, the reference pattern 2 is used to identify test cells 3 and generate an electronic map during electrical testing of the chip. Specifically, the electronic map of this embodiment is generated during electrical testing. When generating the electronic map, corresponding test cells 3 are generated based on the identified positions of the reference pattern 2. This ensures that the positions of the test cells 3 correspond to the positions of the reference pattern 2. This ensures that when the wafer is cut based on the positions of the reference pattern 2, the outlines of the resulting multiple chips correspond to the test cells 3.

[0045] Two specific types of reference graphics 2 will be provided below. The first is that the reference graphics 2 is a reference point formed by a single graphic. At this time, a plurality of reference points will be provided in the wafer of this embodiment, wherein each reference point corresponds one-to-one to each test unit 3 in the electronic map. Since the above-mentioned test units 3 are specifically distributed in an array, the corresponding reference points will also be distributed in an array on the surface of the wafer. At this time, only one reference point will be provided in the area corresponding to each test unit 3 on the surface of the wafer. And because the reference points are usually located at the same position of the corresponding test unit 3, the reference points will be distributed in an array on the surface of the wafer, and the spacing between adjacent reference points is usually the same.

[0046] In this embodiment, an even number of functional regions 1 are provided on one side of the substrate surface. In this case, the reference point is typically located at the center of the multiple chip, corresponding to the center of the test unit 3. This facilitates determining the location of the test unit 3, and therefore the wafer dicing position, based on the reference point during the identification process. For example, a multiple chip consisting of four functional regions 1 arranged in a 2×2 pattern will form a cross-shaped non-functional region within the multiple chip. In this case, the reference point will be located at the intersection of these cross-shaped non-functional regions, i.e., at the center of the multiple chip. On the wafer surface before dicing, the reference point will be located at the focal point of the non-functional region, with adjacent reference points separated by a non-functional region.

[0047] If a multi-chip has an odd number of functional areas 1 on one side, for example, nine functional areas 1 arranged in a 3×3 pattern, non-functional areas will be formed in a tic-tac-toe pattern within the multi-chip. In this case, the reference point can be set at any intersection of the tic-tac-toe non-functional areas, such as the intersection at the upper left corner. In this case, on the wafer surface before dicing, adjacent reference points will be separated by two non-functional areas.

[0048] In order to facilitate identification, in this embodiment, the reference points set on the wafer surface have the same shape, so that the machine can easily identify the reference points and then perform positioning based on the reference points.

[0049] In this embodiment, the width of the reference point is usually not more than two-thirds of the width of the non-functional area, and the depth of the reference point is usually not more than 5μm, so as to avoid the influence of the setting of the reference point on the functional area 1. The above parameters can be designed according to the magnification of the chip positioning device, and are not specifically limited here. When setting the reference points in this embodiment, it is necessary to make each reference point visible in the microscope and the device lens under direct and oblique light conditions, and the corresponding shapes of the above reference points can be circles, triangles, letters, numbers, etc. In this embodiment, the material of the above reference figure 2 is metal material or silicon layer material, that is, the material of the above reference point can be metal material or silicon layer material and other materials that are easy to cut. Of course, in this embodiment, there is no specific limitation on the material of the reference point, and it depends on the specific situation.

[0050] The second type of reference pattern 2 is a composite pattern composed of multiple reference points. By locating the multiple reference points in this composite pattern, more precise positioning of the test unit 3 in the electronic map is achieved, ensuring that the chip layout after dicing matches the electronic map. In this embodiment, to ensure accurate identification of each reference point, different reference points within the same reference pattern 2 typically have different patterns. The specific details of each reference point can be found in the first type of reference pattern 2 in this embodiment. For a reference pattern 2 composed of multiple reference points, the multiple reference points within the same reference pattern 2 are typically located adjacent to each other, and the specific details regarding the size, material, and morphology of each reference point are not specifically limited herein.

[0051] A multiple chip provided in this embodiment sets a reference pattern 2 in the multiple chip and ensures that the identifiable reference pattern 2 in the wafer corresponds one-to-one to each test unit 3 in the electronic map, so that when the multiple chip is cut and identified, it can be identified based on the one-to-one corresponding reference pattern 2, thereby ensuring that the cutting position of the multiple chip is fixed, ensuring that the chip layout after cutting matches the electronic map, and further ensuring the product yield.

[0052] Example 2

[0053] Different from the above-mentioned embodiment of the invention, the embodiment of the present invention further introduces a wafer based on the above-mentioned embodiment of the invention. The specific structure of the wafer can be referenced to the structure of the above-mentioned multiple chips.

[0054] Please refer to Figure 5 , Figure 5 A schematic structural diagram of a wafer provided by an embodiment of the present invention.

[0055] See also Figure 5 In an embodiment of the present invention, a wafer includes a substrate and a plurality of functional areas 1 located on one surface of the substrate, wherein the functional areas 1 are distributed in an array and separated by non-functional areas; a plurality of the functional areas 1 are combined to form a multiplex chip, wherein the non-functional areas between the multiplex chips form cutting paths, and the non-functional areas within the multiplex chips are provided with reference patterns 2; the wafer includes a plurality of multiplex chips corresponding to test units 3 in an electronic map, and the reference patterns 2 identifiable in the wafer correspond one-to-one to each test unit 3 in the electronic map.

[0056] The specific structure of a single multiple chip has been described in detail in the above-mentioned embodiments of the invention and will not be repeated here. The wafer provided in this embodiment can be made into multiple multiple chips after cutting, and correspondingly, multiple reference patterns 2 are set on one side of the wafer surface. In addition, based on the preparation of multiple chips, the non-functional area between the multiple chips in this embodiment is a cutting path. When cutting the wafer to prepare multiple chips, the wafer polarity will be cut along the cutting path. The above-mentioned reference pattern 2 is specifically set in the non-functional area inside the multiple chip, and the non-functional area inside the multiple chip will only be used as a cutting path when the multiple chip is divided into single chips.

[0057] The details of the reference pattern 2 can be found in the above embodiment and will not be further elaborated here. Each reference pattern 2 must correspond one-to-one with each test cell 3 in the electronic map, and the position of each reference pattern 2 within the corresponding test cell 3 is typically fixed. This ensures that positioning based on the reference pattern 2 during cutting ensures that the cutting position of multiple chips is fixed, ensuring that the chip layout after cutting matches the electronic map, thereby ensuring product yield.

[0058] Example 3

[0059] Different from the above-mentioned embodiment of the invention, the embodiment of the present invention further introduces a wafer cutting method based on the above-mentioned embodiment of the invention. The specific content of the wafer cutting method can be referred to in correspondence with the structure of the above-mentioned wafer.

[0060] Please refer to Figure 6 , Figure 6 The present invention provides a flow chart of a wafer cutting method.

[0061] See also Figure 6 In an embodiment of the present invention, a wafer cutting method includes:

[0062] S101: Obtain a wafer.

[0063] In this embodiment, the wafer includes a substrate and multiple functional regions 1 located on one surface of the substrate. The functional regions 1 are arranged in an array and separated by non-functional regions. Multiple functional regions 1 are combined to form a multiple chip. The non-functional regions between the multiple chips form dicing streets. Reference patterns 2 are provided in the non-functional regions within the multiple chips. The specific structure of the wafer has been described in detail in the above embodiments and will not be repeated here.

[0064] S102: Identify the reference pattern, identify the test unit when the chip is electrically tested, and generate an electronic map.

[0065] In this embodiment, the positions of the test units 3 correspond to the positions of the reference patterns 2. In this embodiment, the reference patterns 2 pre-set in the wafer to be cut are first identified to determine the position information of the reference patterns 2 within the wafer. In this step, the test units 3 corresponding to the wafer during electrical testing are identified based on the position information of the reference patterns 2, and an electronic map formed by the multiple test units 3 is generated. Obviously, the positions of the individual test units 3 in this electronic map correspond to the positions of the reference patterns 2 within the wafer, meaning that the positions of the test units 3 correspond to the positions of the reference patterns 2.

[0066] In this embodiment, the wafer includes multiple chips corresponding to the test cells 3 in the electronic map. Clearly, the positions of these chips within the wafer also correspond to the positions of the reference pattern 2. The reference pattern 2, identifiable within the wafer, corresponds one-to-one with each test cell 3 in the electronic map, thereby ensuring a one-to-one correspondence between each chip and each test cell 3. The specific details of reference pattern 2 have been detailed in the above embodiment and will not be repeated here.

[0067] In this step, the above-mentioned reference figure 2 needs to be identified to generate a corresponding electronic map based on the position of the reference figure 2, that is, the position of the corresponding test unit 3 in the electronic map in the wafer is determined based on the position of the reference figure 2, and then the contour position of the multiple chip is determined. Obviously, the contour position of the multiple chip and the contour of the test unit 3 can correspond to each other.

[0068] S103: Based on the recognition of the reference pattern position, the wafer is cut according to the electronic map to obtain multiple chips.

[0069] This step, based on identifying the position of the reference pattern 2 on the wafer, locates the corresponding position of each test unit 3 in the electronic map on the wafer. After the wafer is cut according to the electronic map, the resulting multiple chips will correspond one-to-one with the test units 3, ensuring that the layout of the multiple chips after cutting matches the electronic map, thereby ensuring product yield. For the specific cutting process, please refer to the existing technology and will not be described in detail here.

[0070] A wafer cutting method provided in this embodiment sets a reference pattern 2 in a multiple chip and ensures that the identifiable reference pattern 2 in the wafer corresponds one-to-one to each test unit 3 in the electronic map, so that when the multiple chips are cut and identified, they can be identified based on the one-to-one corresponding reference pattern 2, thereby ensuring that the cutting position of the multiple chips is fixed, ensuring that the chip layout after cutting matches the electronic map, and thus ensuring the product yield.

[0071] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0072] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0073] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0074] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0075] The above is a detailed introduction to a multiple-chip, wafer, and wafer cutting method provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A multiple birth chip, characterized in that: include: substrate; A plurality of functional areas are located on one surface of the substrate; the functional areas are separated by non-functional areas, and reference patterns are provided in the non-functional areas; The reference pattern is used to identify the test unit and generate an electronic map when the chip is electrically tested, so that the outline of the multiple chips corresponds to the test unit in the electronic map, and the reference pattern identifiable in the wafer corresponds one-to-one to each test unit in the electronic map.

2. The multiple birth chip according to claim 1, characterized in that: The reference pattern is a reference point formed by a single pattern.

3. The multiple birth chip according to claim 2, characterized in that: An even number of the functional areas are provided on one surface of the substrate, and the reference point is located at the center of the multiple chips.

4. The multiple birth chip according to claim 2, characterized in that: The shapes of the reference points on the wafer surface are the same.

5. The multiple birth chip according to claim 4, characterized in that: The width of the reference point is no greater than two-thirds of the width of the non-functional area, and the depth of the reference point is no greater than 5 μm.

6. The multiple birth chip according to claim 1, characterized in that: The reference pattern is a combined pattern composed of multiple reference points.

7. The multiple birth chip according to claim 6, characterized in that: Different reference points in the same reference pattern have different patterns.

8. The multiple birth chip according to claim 1, characterized in that: The reference pattern is made of metal material or silicon layer material.

9. A wafer, characterized in that: The present invention comprises a substrate and a plurality of functional areas located on a surface of one side of the substrate, wherein the functional areas are arranged in an array and separated by non-functional areas; the plurality of functional areas are combined to form a multiple chip, the non-functional areas between the multiple chips form cutting streets, and the non-functional areas within the multiple chips are provided with reference patterns; The reference pattern is used to identify the test unit and generate an electronic map when the chip is electrically tested, so that the wafer includes multiple chips corresponding to the test units in the electronic map, and the reference pattern identifiable in the wafer corresponds one-to-one to each test unit in the electronic map.

10. A wafer cutting method, characterized in that: include: Obtain wafers; The wafer includes a substrate and a plurality of functional areas located on a surface of one side of the substrate, wherein the functional areas are distributed in an array and separated by non-functional areas; A plurality of the functional areas are combined to form a multiple chip, the non-functional areas between the multiple chips form cutting lanes, and the non-functional areas within the multiple chips are provided with reference patterns; Identifying the reference pattern, identifying the test unit when the chip is electrically tested and generating an electronic map; the position of the test unit corresponds to the position of the reference pattern; Based on the recognition of the reference pattern position, the wafer is cut according to the electronic map to obtain the multiple chips.

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