A semiconductor structure and a method of fabricating the same

Abstract

The application discloses a semiconductor structure and a preparation method thereof, which comprises a substrate, a device area on the substrate, the device area comprising at least one semiconductor device, the semiconductor device comprising at least an electrode area, a first dielectric layer on the device area, the first dielectric layer being provided with a slot, and a projection position of the slot on the substrate being at least partially misaligned with the semiconductor device, a high-resistance structure filled in the slot, a first metal layer penetrating through the first dielectric layer and being in contact with at least one electrode area of the semiconductor device, the first metal layer being flush with the surface of the first dielectric layer, a second dielectric layer on the first dielectric layer, a second metal layer penetrating through the second dielectric layer, part of the second metal layer being in contact with the first metal layer to form an electrode lead-out part, and part of the second metal layer being in contact with the high-resistance structure to electrically connect the high-resistance structure to the semiconductor device. The application improves the stability of the semiconductor device through the position and structure design of the high resistance.

Description

Technical Field

[0001] This application relates to the field of semiconductor device fabrication technology, and in particular to a semiconductor structure with a high resistance structure and its fabrication method. Background Technology

[0002] In current advanced semiconductor manufacturing processes, a separate high-resistivity (HIR) structure is introduced. This high resistor is connected to the conductive electrodes of the semiconductor device via tungsten (W) metal pillars to achieve voltage division, current limiting, and leakage current prevention. Fabricating this high resistor typically requires first creating a high-resistivity layer, followed by etching to form the resistive structure. However, in current processes, after the semiconductor device body is completed, a high-resistivity layer is created within a dielectric layer and etched to form the high-resistivity structure. Because subsequent metal layers need to be isolated, an additional dielectric layer is required, increasing the dielectric layer thickness and the complexity of subsequent processes. A first metal layer is then created above the high resistor, connected to the high resistor and the semiconductor device via tungsten metal pillars. The high resistivity of tungsten results in a slow response speed, leading to poor overall device performance. Summary of the Invention

[0003] In summary, this application addresses the structural defect in existing processes where high resistance is located between the semiconductor device body and the first metal layer. It proposes a novel semiconductor structure that improves the connection performance between the metal layer and the high-resistance structure by designing the location and structure of the high resistance, thereby enhancing the stability of the semiconductor device. At the same time, it simplifies the fabrication process and reduces costs.

[0004] A semiconductor structure provided according to the purpose of this application includes: a substrate; a device region located on the substrate, the device region including at least one semiconductor device, the semiconductor device including at least one electrode region; a first dielectric layer located on the device region, the first dielectric layer having a slot, and the projection position of the slot on the substrate being at least partially offset from the semiconductor device; a high-resistivity structure filling the slot; a first metal layer penetrating the first dielectric layer and contacting at least one electrode region of the semiconductor device, the first metal layer being flush with the surface of the first dielectric layer and the high-resistivity structure; a second dielectric layer located on the first dielectric layer; a second metal layer penetrating the second dielectric layer, a portion of the second metal layer contacting the first metal layer to form an electrode lead-out, and a portion of the second metal layer contacting the high-resistivity structure for electrically connecting the high-resistivity structure to the semiconductor device.

[0005] Preferably, the high-resistivity structure comprises a multilayer film, at least a portion of which is formed by a hard mask in the metal layer fabrication process.

[0006] Furthermore, the hard mask layer includes a barrier layer, an oxide layer, and a high-resistivity material layer.

[0007] Optionally, the volume of the slot is related to the design resistance of the high-resistance structure, and the width of the slot does not exceed twice the thickness of the hard mask layer.

[0008] Preferably, the high-resistivity material layer is titanium nitride or a modified material thereof.

[0009] This application also provides a method for fabricating a semiconductor structure, comprising: providing a substrate having a device region comprising a semiconductor device on its surface; forming a first dielectric layer on the device region and etching a trench on the dielectric layer, wherein the projection position of the trench on the substrate is at least partially offset from the semiconductor device; depositing a hard mask layer of a multilayer film structure on the first dielectric layer, such that the multilayer film structure forms a high-resistivity structure within the trench; etching a mask pattern on the hard mask layer and depositing a first metal layer on the first dielectric layer based on the mask pattern, such that the first metal layer is adjacent to the electrode region of the semiconductor device. Contact; remove excess portions of the first metal layer and the hard mask layer until the first dielectric layer is exposed, such that the first metal layer and the high-resistivity structure are flush with the surface of the first dielectric layer; fabricate a second dielectric layer on the first dielectric layer, and create a window in the second dielectric layer to expose the high-resistivity structure and at least a portion of the first metal layer; fabricate a second metal layer on the second dielectric layer, wherein the second metal layer partially contacts the first metal layer through the window in the second dielectric layer to form an electrode lead, and partially contacts the high-resistivity structure for electrically connecting the high-resistivity structure to the semiconductor device.

[0010] Preferably, the hard mask layer includes a barrier layer, an oxide layer, and a high-resistivity material layer, and the width of the slot does not exceed twice the thickness of the hard mask layer.

[0011] Preferably, the method for fabricating the hard mask layer includes:

[0012] A barrier layer is formed on the sidewalls and bottom of the slot and on the first medium layer;

[0013] An oxide layer is formed on the barrier layer;

[0014] A high-resistivity material layer is formed on the oxide layer, and the high-resistivity material layer fills the groove.

[0015] Furthermore, the high-resistivity material layer is titanium nitride, and the material further includes oxygen ion implantation modification of the titanium nitride.

[0016] Preferably, the second metal layer is copper, and the second metal layer electrically connects the high-resistivity structure to the semiconductor device through the first metal layer.

[0017] As described above, this application provides a semiconductor structure and its fabrication method. By fabricating a first metal layer and a high-resistivity structure at the same dielectric layer height, making them flush with the surface of the first dielectric layer, and then fabricating a second metal layer on top, the high-resistivity structure and the first metal layer are connected using the redistribution structure of the second metal layer. An unexpected effect is that, compared to existing solutions where the high-resistivity structure is located below the first metal layer, a thicker dielectric layer is unnecessary, reducing device fabrication difficulty and improving fabrication efficiency. Furthermore, the high-resistivity structure exhibits a higher response speed, adapting to more advanced processes. During the fabrication of the high-resistivity structure, a hard mask from metal fabrication processes is used as the co-layer material, saving process steps, increasing film utilization, and reducing device fabrication costs. The two metal layers can be directly deposited through windows in the dielectric layer to form a copper metal contact structure, saving tungsten metal studs. The copper metal contact structure also enables the high-resistivity structure to have a faster response speed, improving device stability and performance. By injecting oxygen atoms into the high-resistivity structure, the resistance value of the high-resistivity structure can be adjusted to achieve a higher and controllable resistance value. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of this application;

[0019] Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application;

[0020] Figure 3 This is a schematic diagram of the first dielectric layer according to an embodiment of this application;

[0021] Figure 4 This is a schematic diagram of the slot location in the first dielectric layer according to an embodiment of this application;

[0022] Figure 5 This is a schematic diagram of a high-resistivity structure according to an embodiment of this application;

[0023] Figure 6 This is a schematic diagram of the first recess in one embodiment of this application;

[0024] Figure 7 This is a schematic diagram of the first metal layer according to an embodiment of this application;

[0025] Figure 8 This is a schematic diagram of the first metal layer after planarization according to an embodiment of this application;

[0026] Figure 9 This is a schematic diagram of the second dielectric layer according to an embodiment of this application;

[0027] Figure 10 This is a schematic diagram of a metal mask layer according to an embodiment of this application;

[0028] Figure 11 This is a schematic diagram of the second recess in one embodiment of this application;

[0029] Figure 12 This is a schematic diagram of the second metal layer according to an embodiment of this application.

[0030] Label Explanation:

[0031] 10 Substrate; 11 Device region; 111 Semiconductor device; 12 First dielectric layer; 121 Groove; 13 High-resistivity structure; 131 Barrier layer; 132 Oxide layer; 133 High-resistivity material layer; 14 First metal layer; 15 Second dielectric layer; 16 Second metal layer; 17 Etch stop layer; 18 Passivation layer; 19 First recess; 20 Dielectric capping layer; 21 Sacrificial layer; 22 Metal hard mask layer; 23 Second recess. Detailed Implementation

[0032] The present application will be described in detail below with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present application. Any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the protection scope of the present application.

[0033] The present application will be further described in detail below with reference to the accompanying drawings, so that those skilled in the art can better understand and implement the present application, but the embodiments described are not intended to limit the present application.

[0034] Example 1

[0035] like Figure 1 As shown, Figure 1 A semiconductor structure according to a first embodiment of the present invention is provided. The semiconductor structure includes a substrate 10, a device region 11, a first dielectric layer 12, a high-resistivity structure 13, a first metal layer 14, a second dielectric layer 15, and a second metal layer 16.

[0036] The device region 11 is located on the substrate 10, and the device region 11 includes at least one semiconductor device 111. The embodiments of this application do not limit the type or number of semiconductor devices 111. Semiconductor devices 111 include, for example, field-effect transistors (FETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, insulated-gate bipolar transistors (IGBTs), fast recovery diodes (FRDs), high-efficiency diodes (HEDs), constant voltage diodes, high-frequency diodes, light-emitting diodes (LEDs), gate-turn-off thyristors (GTOs), light-triggered thyristors (LTTs), thyristors, charge-coupled devices (CCD image sensors), digital signal processors (DSPs), photorelays, or microprocessors. An integration of one or more semiconductor devices such as a processor, which can be fabricated according to the specific requirements of semiconductor integrated device fabrication. For example, a semiconductor device is a CMOS transistor.

[0037] Those skilled in the art should understand that, within the existing semiconductor device process technology framework, any application scenario requiring the connection of a high-resistivity structure can be considered a semiconductor device as claimed in this application, and no specific limitations are made here. This semiconductor device includes at least one electrode region. Taking a CMOS device as an example, in a CMOS integrated circuit, the electrode structure of a semiconductor device mainly includes a gate, a source, a drain, and a body / bulk. These electrodes are electrically connected through metal interconnect layers. For example, at the top of the gate, a metal (such as tungsten or copper) via is used to connect to the upper metal wiring to achieve signal input; in the silicide layer of the source / drain region, a contact hole is used to connect to the underlying metal (such as the M1 layer), and then the vias are used to lead out layer by layer to the electrode pads. The metal stack layers used for interconnection with each electrode can be constructed using back-end processes (BEOL) to create multiple layers of metal wiring (such as M1-Mx), then isolated by a dielectric layer (such as SiO2), with each layer vertically interconnected vias. Other devices may have Schottky contacts between metal and semiconductor layers, which can also be applied under the concept of this invention, and are not limited here.

[0038] In some embodiments, a first dielectric layer 12 is located on the device region 11. This first dielectric layer 12 is preferably an ultra-low k dielectric, which reduces the parasitic capacitance between the metal layer and the device. In this invention, the thickness of the first dielectric layer 12 satisfies two conditions: first, it is sufficient to fabricate a high-resistivity structure; second, it allows for windowing and deposition of the subsequent first metal layer 14. Figure 3 and Figure 6 As shown, the first dielectric layer 12 has a slot 121, and the projection position of the slot 121 on the substrate is at least partially offset from the semiconductor device 111. The slot 121 is used to deposit a high-resistivity structure 13. The position of the slot 121 needs to meet the following conditions: firstly, it needs to facilitate the redistribution of the metal layer to connect the high resistance to the device; secondly, it needs to leave enough space for the first metal layer.

[0039] In some embodiments, such as Figure 6As shown, a high-resistivity structure 13 is filled in the trench, and the high-resistivity structure 13 includes a multilayer film. At least a portion of the multilayer film is composed of a hard mask layer in the metal layer fabrication process. Specifically, the high-resistivity structure 13 (hard mask layer) includes a barrier layer 131, an oxide layer 132, and a high-resistivity material layer 133. Preferably, the volume of the trench 121 is related to the design resistance value of the high-resistivity structure 13, and the width of the trench 121 does not exceed twice the thickness of the hard mask layer. This ensures that the high-resistivity structure 13 has sufficient resistance, effectively reduces parasitic capacitance, and improves the performance of the semiconductor device. In a preferred embodiment, the high-resistivity material layer is titanium nitride (TiN) or a modified material thereof. Titanium nitride has good high-resistivity characteristics and stability, which can meet the requirements for high-resistivity materials in semiconductor structures.

[0040] In some embodiments, the first metal layer 14 extends through the first dielectric layer 12 and contacts at least one electrode region of the semiconductor device 111. The first metal layer 14 is flush with the surface of the first dielectric layer 12 along with the high-resistivity structure 13. The first metal layer 14 may be made of a metal material with good conductivity, such as copper, aluminum, or their alloys, and forms an electrical connection through contact with the electrode region of the semiconductor device. In a preferred embodiment, the first metal layer 14 is made of copper.

[0041] In some embodiments, the second dielectric layer 15 is located on the first dielectric layer 12 and serves to provide electrical isolation and protection. The second dielectric layer 15 may be made of silicon oxide, silicon nitride, or a low dielectric constant material to reduce parasitic capacitance.

[0042] In some embodiments, a second metal layer 16 extends through the second dielectric layer 15. A portion of the second metal layer 16 contacts the first metal layer 14 to form an electrode lead-out, and another portion of the second metal layer 16 contacts the high-resistivity structure 13 for electrically connecting the high-resistivity structure 13 to the semiconductor device 111. The second metal layer 16 may be made of the same or a different conductive material as the first metal layer 14. Through contact with the first metal layer 14 and the high-resistivity structure 13, it enables the conduction of electrical signals and the electrical connection function of the high-resistivity structure. In a preferred embodiment, the second metal layer 16 is made of copper.

[0043] In this embodiment, the semiconductor structure effectively adjusts the electrical characteristics of the semiconductor device, reduces parasitic capacitance, and improves device performance by setting a high-resistance structure 13 in the first dielectric layer 12 and electrically connecting the high-resistance structure 13 to the semiconductor device through the second metal layer 16. Simultaneously, the high-resistance structure 13 employs a multilayer film design, utilizing a hard mask from the metal layer fabrication process to form part of the film layer, simplifying the manufacturing process and improving production efficiency.

[0044] Example 2

[0045] This embodiment provides a method for fabricating a semiconductor structure, which can be used to manufacture the semiconductor structure described in Embodiment 1. For example... Figure 2 As shown, the preparation method includes the following steps:

[0046] S201, a substrate is provided, on which a device region 11 is provided, and the device region 11 includes at least one semiconductor device 111. The semiconductor device includes at least one electrode region for subsequent electrical connection.

[0047] In step S202, a first dielectric layer 12 is formed on the device region 11, and a trench 121 is etched on the first dielectric layer 12. The projection position of the trench 121 on the substrate 10 is at least partially misaligned with the semiconductor device 111. This misalignment design helps to reduce parasitic capacitance and improve device performance. The first dielectric layer 12 can be made of an ultra-low k dielectric material to further reduce parasitic capacitance.

[0048] S203, a hard mask layer is fabricated on the first dielectric layer 12. This hard mask layer is a multilayer film structure, and the multilayer film structure is deposited in the trench 121 to form a high-resistivity structure 13. Specifically, the high-resistivity structure 13 includes a barrier layer 131, an oxide layer 132, and a high-resistivity material layer 133, and the high-resistivity material layer 133 occupies more than half of the trench width. The high-resistivity material layer uses titanium nitride material, and the titanium nitride is modified by oxygen ion implantation so that the resistance of the high-resistivity structure 13 meets the design requirements.

[0049] S204, a mask pattern is etched on the hard mask layer, and a window is opened on the first dielectric layer 12 using the mask pattern and a first metal layer 14 is deposited, so that the first metal layer 14, under the definition of the mask pattern, makes contact with at least one electrode region of the semiconductor device 111 to form an electrical connection.

[0050] S205, remove excess portions from the surface of the first metal layer 14 and the hard mask layer until the first dielectric layer 12 is exposed, so that the first metal layer 14 and the high-resistivity structure 13 are flush with the surface of the first dielectric layer 12. This planarization process facilitates subsequent processes and ensures the stability of the structure.

[0051] S206, a second dielectric layer 15 is fabricated on the first dielectric layer 12, and a window is made in the second dielectric layer 15 to expose the high-resistivity structure 13 and at least a portion of the first metal layer 14. The second dielectric layer may also be made of an ultra-low-k dielectric material, and may be the same as or different from the first dielectric layer 12.

[0052] S207, a second metal layer 16 is fabricated on the second dielectric layer 15. The second metal layer 16 is made of copper. Through openings in the second dielectric layer 15, it partially contacts the first metal layer 14 to form an electrode lead-out portion, and partially contacts the high-resistivity structure 13, for electrically connecting the high-resistivity structure 13 to the semiconductor device 111. The second metal layer 16 achieves electrical connection of the high-resistivity structure 13 to the semiconductor device 111 through the first metal layer 14.

[0053] The following is for reference. Figures 3 to 12 The method for fabricating the semiconductor structure according to the embodiments of this application will be described in detail, wherein, Figures 3 to 12 A schematic cross-sectional view of a semiconductor structure obtained by performing each step of a method for fabricating a semiconductor structure according to an embodiment of this application is shown. It is worth noting that, to avoid repetition, only brief descriptions are given for components and structures identical to those in Embodiment 1 above; detailed explanations and descriptions can be found in the description of Embodiment 1.

[0054] Please see Figure 3 In some embodiments, a device is fabricated on the substrate 10 to form a device region 11, which includes at least one semiconductor device 111. The substrate 10 can be any material suitable for forming a semiconductor device, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafers, or other III / V compound semiconductor materials, and also includes a stacked structure composed of these semiconductor materials, or silicon-on-insulator, silicon-on-insulator, silicon-germanium-on-insulator, and germanium-on-insulator, etc.

[0055] Please see Figure 3 In some embodiments, an etch stop layer 17, a passivation layer 18, and a first dielectric layer 12 are formed on the device region 11. The etch stop layer 17 is disposed on the device region 11, the passivation layer 18 is disposed on the etch stop layer 17, and the first dielectric layer 12 is disposed on the passivation layer 18. The etch stop layer 17 is made of materials such as silicon carbide (SiCN) or silicon carbide (SiC) to prevent metal ions in the metal layer from diffusing into the device region 11. It also helps to stop the etching process in a timely and accurate manner during the subsequent etching process to form the first metal layer 14, without damaging the underlying semiconductor device. The etch stop layer 17 can be deposited by methods such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The passivation layer 18 can be silicon dioxide (SiO2). 2）The passivation layer 18, etc., can be prepared by chemical vapor deposition. It possesses high strength to increase the stress resistance of the first dielectric layer 12 during fabrication and reduce cracking. For example, the passivation layer 18 is prepared using a tetraethoxysilane (TEOS) process. TEOS is a common silicon source in chemical vapor deposition processes and can be used to generate a SiO2 film. Silica is deposited on the surface of the etch stop layer 17, forming a silica film (passivation layer 18). The first dielectric layer 12 can be prepared from low-k materials such as silicon fluoride (SiF), silicon oxycarbide (SiOC), or silicon oxyfluoride (SiOF), or from ultra-low-k materials such as silica aerogel, to reduce parasitic capacitance between the metal layer and the device. The first dielectric layer 12 can be deposited using methods such as chemical vapor deposition or low-pressure chemical vapor deposition (LPCVD). The thicknesses of the etch stop layer 17, passivation layer 18, and first dielectric layer 12 can be selected according to the fabrication requirements of the semiconductor device. In this embodiment, the thickness of the first dielectric layer 12 satisfies the following conditions: first, it is sufficient to fabricate a high-resistivity structure 13; second, it allows for windowing and deposition of the subsequent first metal layer 14.

[0056] Please see Figure 4 In some embodiments, a patterned photoresist layer (not shown) is formed on the first dielectric layer 12 to locate the position of the groove 121. Using the patterned photoresist layer as a mask, the first dielectric layer 12 is etched to form the groove 121. After the groove 121 is formed, the patterned photoresist layer is removed by wet etching or ashing. For example, the groove 121 is formed by a dry etching process, and the etching gas can be one or a combination of several gases such as trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), or nitrogen (N2), or a mixture of them and oxygen (O2).

[0057] Please see Figure 5As shown, after forming the trench 121, a hard mask layer is formed on the first dielectric layer 12 and within the trench 121. This hard mask layer is a multilayer film structure, and the multilayer film structure is deposited in the trench 121 to form a high-resistivity structure 13, including a barrier layer 131, an oxide layer 132, and a high-resistivity material layer 133. The barrier layer 131 is formed on the sidewalls and bottom of the trench 121 and on the first dielectric layer 12, i.e., the barrier layer 131 is located within the trench 121 and the first dielectric layer 12. The barrier layer 131 can be deposited by methods such as chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD), and the barrier layer 131 is, for example, silicon carbide (SiCN) or silicon nitride. An oxide layer 132 is formed on the barrier layer 131. The oxide layer 132 can be silicon dioxide (SiO2) or the like, and can be prepared by chemical vapor deposition. Then, a high-resistivity material layer 133 is formed on the oxide layer 132, which can be deposited by physical vapor deposition or the like. For example, silicon carbide nitride is deposited on the bottom and walls of the trench 121 and on the first dielectric layer 12 by chemical vapor deposition to form a barrier layer 131, providing good insulation properties to prevent titanium nitride from diffusing into the dielectric layer. Next, tetraethoxysilane is deposited on the barrier layer 131 by chemical vapor deposition to form an oxide layer 132, providing stress support for the structure and ensuring the stability of the high-resistivity structure. Then, titanium nitride is deposited on the oxide layer 132 by physical vapor deposition to fill the trench 121, ensuring complete filling, to form a high-resistivity material layer 133. Titanium nitride serves as the high-resistivity material for the resistive structure, thus forming a structure with high-resistivity characteristics. By depositing the barrier layer 131, oxide layer 132, and high-resistivity material layer 133 within the trench 121, a high-resistivity structure 13 is formed. In this embodiment, while forming a hard mask layer in the trench 121 using a deposition process, a hard mask layer covering the first dielectric layer 12 is also formed. The hard mask layer is used to form the high-resistivity structure 13 on the one hand, and provides a hard mask layer for the subsequent formation of the first metal layer 14 on the other hand. This saves process steps, increases the utilization rate of the hard mask layer, and reduces the cost of device fabrication.

[0058] Please see Figure 6As shown, in some embodiments, a patterned photoresist layer (not shown) is formed on the high-resistivity material layer 133. The patterned photoresist layer forms multiple openings to define the positions of the first metal layer 14 to be formed later. Using the patterned photoresist layer as a mask, etching is performed towards the substrate 10, etching the high-resistivity material layer 133, oxide layer 132, barrier layer 131, first dielectric layer 12, passivation layer 18, and etch stop layer 17 until the etch stop layer 17, forming multiple first recesses 19. The first recesses 19 expose a portion of the device region 11. The barrier layer 131 prevents metal ions in the metal layer from diffusing into the dielectric layer, preventing electromigration and improving the electrical performance of the semiconductor integrated device. The barrier layer 131 and oxide layer 132 are used to ensure complete contact and surface flatness of the metal layer during the formation of the first metal layer 14. The high-resistivity material layer 133, as a mask structure for subsequent metal layer processes, plays a role in pattern transfer and can control the morphology and quality of the metal layer openings. For example, the first recess 19 can be formed by a dry etching process, and the etching gas can be one or a combination of several gases selected from the following: trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), nitrogen (N2), or oxygen (O2). In other embodiments, the recess can be formed using a combination of dry and wet etching processes or a wet etching process.

[0059] Please see Figure 7 In some embodiments, after the first recess 19 is formed, the patterned photoresist layer is removed by wet etching or ashing, and a first metal layer 14 is deposited in the first recess 19 until the first metal layer 14 completely fills the first recess 19. The first metal layer 14 can be one or a combination of copper, aluminum, or tungsten. For example, the first metal layer 14 is a copper layer, which can be formed by physical vapor deposition or electroplating, and fills the first recess 19 until it covers the high-resistivity material layer 133. When forming the first metal layer 14, to ensure that the first recess 19 is completely filled, some metal material may overflow, thereby forming a metal material cover layer on the surface of the high-resistivity material layer 133. In one embodiment, before depositing the first metal layer 14, a barrier layer (not shown) can be formed on the sidewalls and bottom of the first recess 19. The barrier layer is formed, for example, by physical vapor deposition. The barrier layer can be a material with good adhesion, such as tantalum (Ta) or tantalum nitride (TaN). The thickness of the barrier layer is, for example, 2 nm to 5 nm, to enhance the adhesion between the first metal layer 14 and the sidewalls of the first recess 19, prevent electromigration, and improve the electrical performance of the semiconductor integrated device.

[0060] Please see Figure 8As shown, in some embodiments, the first metal layer 14 undergoes a planarization process, for example, a chemical mechanical polishing (CMP) process, to remove excess capping layers, high-resistivity material layers 133, oxide layers 132, and barrier layers 131 of the metal material located on the first dielectric layer 12, leaving only the first metal layer 14 and the high-resistivity structure 13, so that the surfaces of the first metal layer 14 and the high-resistivity material layer 133 are flush with the first dielectric layers 12 on both sides. The first metal layer 14 penetrates the first dielectric layer 12 and contacts at least one electrode region of the semiconductor device 111. The first metal layer 14 and the high-resistivity structure 13 are flush with the surface of the first dielectric layer 12. It should be noted that in this embodiment, the first metal layer 14 is disposed on the device region 11, that is, the first metal layer 14 is the first metal layer. In this embodiment, the first metal layer 14 and the high-resistivity structure 13 are fabricated at the same dielectric layer height, making them flush with the surface of the first dielectric layer 12. Then, a second metal layer 16 is fabricated on top, and the high-resistivity structure and the first metal layer 14 are connected by the redistribution structure of the second metal layer 16. Compared with the existing solution where the high-resistivity structure 13 is located below the first metal layer 14, a thicker dielectric layer is not required, which reduces the difficulty of device fabrication and improves the fabrication efficiency, and also makes the high-resistivity structure have a higher response speed.

[0061] In some embodiments, after planarizing the first metal layer 14, the high-resistivity structure 13 region is subjected to localized light irradiation, and oxygen atoms are implanted into the high-resistivity material layer 133 using ion implantation to adjust the resistance value of the high-resistivity structure so that the resistance of the high-resistivity structure meets a design requirement. In this embodiment, by implanting oxygen atoms into the high-resistivity structure 13, the resistance value of the high-resistivity structure 13 can be adjusted to achieve a higher and more controllable resistance value.

[0062] Please see Figure 9 As shown, in some embodiments, a second dielectric layer 15 is formed on the first dielectric layer 12, the first metal layer 14, and the resistive structure 15, covering the first metal layer 14, the resistive structure 15, and a portion of the first dielectric layer 12. The second dielectric layer 15 can be prepared from a low-k material such as silicon fluoride (SiF), silicon oxycarbide (SiOC), or silicon oxyfluoride (SiOF), or from an ultra-low dielectric material (ELK) such as silica aerogel, to reduce parasitic capacitance between the metal layer and the device. The second dielectric layer 15 can be deposited using methods such as chemical vapor deposition or low-pressure chemical vapor deposition. The thicknesses of the second dielectric layer 15 and the first dielectric layer 12 can be selected according to the device type or fabrication requirements. For example, the thicknesses of the second dielectric layer 15 and the first dielectric layer 12 are equal.

[0063] Please see Figure 10As shown, in some embodiments, a dielectric capping layer 20, a sacrificial layer 21, and a metal hard mask layer 22 are sequentially deposited on the second dielectric layer 15. Exemplarily, silicon carbide is deposited on the second dielectric layer 15 via chemical vapor deposition to form the dielectric capping layer 20, providing good insulation properties to prevent the diffusion of metal ions in the metal layer, prevent electromigration, and improve the electrical performance of the semiconductor integrated device. Next, tetraethoxysilane is deposited on the dielectric capping layer 20 via chemical vapor deposition to form the sacrificial layer 21. Then, titanium nitride is deposited on the sacrificial layer 21 via physical vapor deposition to form the metal hard mask layer 22. The sacrificial layer 21 and the metal hard mask layer 22 ensure complete contact and surface flatness of the metal layer during the formation of the second metal layer 16. The metal hard mask layer 22 serves as a mask structure for subsequent metal layer processes, acting as a pattern transfer mechanism and controlling the morphology and quality of the metal layer openings.

[0064] Please see Figure 11 As shown, in some embodiments, a patterned photoresist layer (not shown) is formed on the metal hard mask layer 22. The patterned photoresist layer is exposed and developed to form multiple second openings, which define the positions of the second metal layer 16 to be formed later. Using the patterned photoresist layer as a mask, the metal hard mask layer 22, sacrificial layer 21, dielectric capping layer 20, and second dielectric layer 15 are etched down to the first dielectric layer 12, exposing the first metal layer 14 within the first dielectric layer 12, forming the second recess 23. Exemplarily, the second recess 23 can be formed by a dry etching process, and the etching gas can be, for example, one or a combination of several gases selected from trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), nitrogen (N2), or oxygen (O2). In other embodiments, a combination of dry etching and wet etching processes or a wet etching process can be used to form the recess.

[0065] Please see Figure 12As shown, in some embodiments, after the second recess 23 is formed, the patterned photoresist layer is removed by wet etching or ashing, and a second metal layer 16 is deposited in the second recess 23 until the second metal layer 16 completely fills the second recess 23. The second metal layer 16 can be one or a combination of copper, aluminum, or tungsten layers. The second metal layer 16 penetrates the second dielectric layer 15, and a portion of the second metal layer 16 contacts the first metal layer 14 and a portion of the second metal layer 16 contacts the high-resistivity structure 13, for electrically connecting the high-resistivity structure 13 to the semiconductor device 111, thereby realizing the electrical connection of the high-resistivity structure 13 to the semiconductor device 111. In this embodiment, the second metal layer 16 is a copper layer, and the second metal layer 16 can be formed by physical vapor deposition or electroplating, and the second metal layer 16 fills the second recess 23 until it covers the metal hard mask layer 22. In one embodiment, before depositing the second metal layer 16, a barrier layer (not shown) can be formed on the sidewalls and bottom of the second recess 23. The barrier layer is formed, for example, by physical vapor deposition. The barrier layer can be a material with good adhesion, such as tantalum (Ta) or tantalum nitride (TaN). The thickness of the barrier layer is, for example, 2 nm to 5 nm, to enhance the adhesion between the second metal layer 16 and the sidewalls of the second recess 23, prevent electromigration, and improve the electrical performance of the semiconductor integrated device.

[0066] In some embodiments, after removing a portion of the second metal layer 16, a planarization process is performed on the second metal layer 16, for example, by chemical mechanical polishing (CMP) to remove the metal hard mask layer 22, the sacrificial layer 21, and the dielectric overlay layer 20. Figure 1 As shown. Planarization facilitates subsequent processes and ensures the stability of the semiconductor structure. In this embodiment, the two metal layers can be deposited directly in the dielectric layer through windows to form a copper metal contact structure, saving the need for tungsten metal studs.

[0067] In summary, this application improves the semiconductor structure and its fabrication method by fabricating the first metal layer and the high-resistivity structure at the same dielectric layer height, making them flush with the surface of the first dielectric layer. A second metal layer is then fabricated on top, and its redistribution structure connects the high-resistivity structure and the first metal layer. An unexpected benefit is that, compared to existing schemes where the high-resistivity structure is located below the first metal layer, a thicker dielectric layer is unnecessary, reducing device fabrication difficulty and improving efficiency. Furthermore, the high-resistivity structure exhibits a higher response speed, adapting to more advanced processes. The high-resistivity structure fabrication utilizes a hard mask from metal fabrication processes as a co-layer material, saving process steps, increasing film utilization, and reducing device fabrication costs. The two metal layers can be directly deposited through windows in the dielectric layer to form a copper metal contact structure, saving tungsten metal studs. This copper metal contact structure also enables the high-resistivity structure to have a faster response speed, improving device stability and performance. By injecting oxygen atoms into the high-resistivity structure, its resistance can be adjusted to achieve a higher and more controllable resistance value.

[0068] The above are all preferred embodiments of this application and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

[0069] Although preferred embodiments of the present application have been disclosed for illustrative purposes, those skilled in the art will recognize that various modifications, additions, and substitutions are possible without departing from the scope and spirit of the present application as disclosed in the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A device region located on the substrate, the device region including at least one semiconductor device, the semiconductor device including at least one electrode region; A first dielectric layer is located on the device region, the first dielectric layer having a slot, and the projection position of the slot on the substrate is at least partially offset from the semiconductor device; A high-resistance structure is filled in the slot; A first metal layer extends through the first dielectric layer and contacts at least one electrode region of the semiconductor device. The first metal layer is flush with the surface of the first dielectric layer along with the high-resistivity structure. The second dielectric layer is located on the first dielectric layer; A second metal layer extends through the second dielectric layer. A portion of the second metal layer contacts the first metal layer to form an electrode lead-out portion. A portion of the second metal layer contacts the high-resistivity structure for electrically connecting the high-resistivity structure to the semiconductor device. The high-resistivity structure includes a multilayer film, at least a portion of which is composed of a hard mask layer in the metal layer fabrication process. The hard mask layer includes a barrier layer, an oxide layer, and a high-resistivity material layer stacked sequentially from bottom to top. The volume of the slot is related to the design resistance value of the high-resistivity structure, and the width of the slot does not exceed twice the thickness of the hard mask layer.

2. The semiconductor structure according to claim 1, characterized in that: The high-resistivity material layer is titanium nitride or a modified version thereof.

3. A method for preparing a semiconductor structure as described in any one of claims 1-2, characterized in that, include: A substrate is provided, the surface of which is provided with a device region containing semiconductor devices; A first dielectric layer is formed on the device region, and a trench is etched on the first dielectric layer, wherein the projection position of the trench on the substrate is at least partially offset from the semiconductor device; A hard mask layer of a multilayer film structure is deposited on the first dielectric layer, so that the multilayer film structure forms a high-resistivity structure within the slot; A mask pattern is etched on the hard mask layer, and a first metal layer is deposited on the first dielectric layer based on the mask pattern, so that the first metal layer contacts the electrode region of the semiconductor device; Remove excess portions of the first metal layer and the hard mask layer until the first dielectric layer is exposed, so that the first metal layer and the high-resistivity structure are flush with the surface of the first dielectric layer. A second dielectric layer is fabricated on the first dielectric layer, and a window is made in the second dielectric layer to expose the high-resistivity structure and at least a portion of the first metal layer; A second metal layer is fabricated on the second dielectric layer. The second metal layer partially contacts the first metal layer through an opening in the second dielectric layer to form an electrode lead-out portion, and partially contacts the high-resistivity structure for electrically connecting the high-resistivity structure to the semiconductor device. The hard mask layer includes a barrier layer, an oxide layer, and a high-resistivity material layer stacked sequentially from bottom to top, and the width of the opening does not exceed twice the thickness of the hard mask layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The method for fabricating the hard mask layer includes: A barrier layer is formed on the sidewalls and bottom of the slot and on the first medium layer; An oxide layer is formed on the barrier layer; A high-resistivity material layer is formed on the oxide layer, and the high-resistivity material layer fills the groove.

5. The method for preparing a semiconductor structure according to claim 3, characterized in that: The high-resistivity material layer is titanium nitride, and the material further includes oxygen ion implantation modification of the titanium nitride.

6. The method for preparing a semiconductor structure according to claim 3, characterized in that: The second metal layer is copper, and the second metal layer electrically connects the high-resistivity structure to the semiconductor device through the first metal layer.

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