Arc suppression circuit, charging interface and charging cable

Abstract

The embodiment of the invention discloses an arc suppression circuit. The arc suppression circuit comprises a driving circuit, a charging circuit, a discharging circuit and a charging control circuit, the driving circuit is used for outputting a first driving signal in response to the fact that the charging interface is inserted into external equipment, or outputting a second driving signal in response to the fact that the external equipment is pulled out of the charging interface, and the external equipment is configured to transmit bus voltage to the bus through the charging interface. And the charging control circuit is used for responding to the first driving signal and controlling the charging circuit to receive the bus voltage for charging, or responding to the second driving signal and controlling the charging circuit to stop charging and controlling the charging circuit to discharge to the bus through the discharging circuit so as to improve the bus voltage of the bus. According to the embodiment of the invention, the electric arc suppression circuit is arranged at the power receiving end, the electric arc energy of the charging interface is suppressed by increasing the voltage of the power receiving end during plugging, and compared with a method of reducing the voltage of the power supply end during plugging, the method of increasing the voltage of the power receiving end is relatively rapid and has universality.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of power supply technology, and specifically to an arc suppression circuit, a charging interface, and a charging cable. Background Art

[0002] Existing fast-charging devices can output voltages up to 48V or 60V. These devices are prone to arcing during hot-plugging. The arc energy generated by a 48V voltage difference is very high, far exceeding the energy of an arc generated by a conventional 5-20V voltage difference. This arc can easily corrode the charging port of the fast-charging device, shortening its lifespan. Summary of the Invention

[0003] In order to solve the above technical problems, the embodiments of the present application provide an arc suppression circuit, a charging interface and a charging cable to improve the situation where the energy of the arc generated by the charging interface is relatively large.

[0004] In a first aspect, an embodiment of the present application provides an arc suppression circuit, which is applied to a charging interface, wherein the charging interface is provided with a busbar, and the busbar is used to transmit a bus voltage. The arc suppression circuit includes: a drive circuit, electrically connected to the busbar, and configured to output a first drive signal in response to the charging interface being inserted into an external device, or output a second drive signal in response to the external device being unplugged from the charging interface, wherein the external device is configured to transmit the bus voltage to the busbar through the charging interface; a charging circuit, electrically connected to the drive circuit; a discharge circuit, electrically connected to the busbar and to the charging circuit; a charging control circuit, electrically connected to the drive circuit and the charging circuit, respectively, and configured to control the charging circuit to receive the bus voltage for charging in response to the first drive signal, or to control the charging circuit to stop charging in response to the second drive signal, and to control the charging circuit to discharge to the busbar through the discharge circuit to increase the bus voltage of the busbar.

[0005] Optionally, the drive circuit includes a voltage hysteresis variation circuit, which is electrically connected to the bus and also electrically connected to the charging circuit, and is configured to output a first drive signal in response to the charging interface being inserted into an external device and the bus voltage being greater than a positive threshold, or to output a second drive signal in response to the charging interface being unplugged from an external device and the bus voltage being less than a negative threshold, wherein the positive threshold is greater than the charging voltage of the charging circuit, and the negative threshold is less than the charging voltage of the charging circuit.

[0006] Optionally, the voltage hysteresis variation circuit is a Schmitt trigger, which includes a first operational amplifier, a first resistor, and a second resistor. The inverting input terminal of the first operational amplifier is electrically connected to the bus, the non-inverting input terminal of the first operational amplifier is electrically connected to the first end of the first resistor and the first end of the second resistor, respectively. The second end of the first resistor is electrically connected to the charging circuit, and the second end of the second resistor is electrically connected to the output terminal of the first operational amplifier and the charging control circuit, respectively. The first operational amplifier is configured to output a first drive signal in response to the charging interface being inserted into an external device and the bus voltage being greater than a positive threshold, or to output a second drive signal in response to the charging interface being unplugged from an external device and the bus voltage being less than a negative threshold.

[0007] Optionally, the charging control circuit includes: a first switching circuit, electrically connected to the voltage hysteresis change circuit, and configured to respond to the first drive signal to enter a cut-off state to output a first control signal, or, respond to the second drive signal, enter a conductive state to output a second control signal; a second switching circuit, electrically connected to the bus and also electrically connected to the first switching circuit and the charging circuit, respectively, and configured to respond to the first control signal to enter a conductive state to transmit the bus voltage to the charging circuit through the second switching circuit, so that when the charging voltage of the charging circuit reaches a preset voltage, the first switching circuit is triggered to enter a cut-off state, or, respond to the second control signal, enter a cut-off state to disconnect the loop for transmitting the bus voltage to the charging circuit.

[0008] Optionally, when the charging circuit discharges to the busbar through the discharging circuit, the electric energy output by the charging circuit is discharged through the first switching circuit in the on state.

[0009] Optionally, the discharge circuit includes an isolation circuit and a voltage follower circuit; the isolation circuit is electrically connected to the bus and is configured to prevent the bus voltage from flowing back into the charging circuit through the voltage follower circuit; the voltage follower circuit is electrically connected to the isolation circuit and the charging circuit, respectively, and is configured to apply the charging voltage of the charging circuit to the bus through the isolation circuit when the external device is unplugged from the charging interface.

[0010] Optionally, the isolation circuit includes a diode, the positive pole of the diode is electrically connected to the output end of the voltage follower circuit, and the negative pole of the diode is electrically connected to the bus, and the diode is configured to block the bus voltage from flowing back into the charging circuit through the voltage follower circuit.

[0011] Optionally, the voltage follower circuit includes a second operational amplifier, the non-inverting input terminal of the second operational amplifier is electrically connected to the charging circuit, the inverting input terminal of the second operational amplifier is electrically connected to the output terminal of the second operational amplifier, and the output terminal of the second operational amplifier is electrically connected to the isolation circuit.

[0012] In a second aspect, an embodiment of the present application provides a charging interface, comprising the above-mentioned arc suppression circuit.

[0013] In a third aspect, an embodiment of the present application provides a charging cable comprising the above-mentioned arc suppression circuit.

[0014] The beneficial effects of the arc suppression circuit provided in the embodiment of the present application are as follows: the embodiment of the present application sets an arc suppression circuit at the receiving end, and suppresses the energy of the arc at the charging interface by increasing the voltage at the receiving end during plugging and unplugging. Compared with the method of reducing the voltage at the power supply end during plugging and unplugging, the method of increasing the voltage at the receiving end is faster and more universal. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0016] Figure 1 A schematic diagram of an application scenario of an arc suppression circuit provided in an embodiment of the present application; Figure 2 A schematic diagram of the circuit structure of an arc suppression circuit provided in an embodiment of the present application; Figure 3 A schematic diagram of the circuit structure of an arc suppression circuit provided in another embodiment of the present application; Figure 4 This is a schematic diagram of the circuit structure of an arc suppression circuit provided in yet another embodiment of the present application; Figure 5 This is a schematic diagram of the circuit structure of an arc suppression circuit provided in yet another embodiment of the present application; Figure 6 This is a schematic diagram of the circuit structure of an arc suppression circuit provided in yet another embodiment of the present application; Figure 7 This is a schematic diagram of the circuit structure of an arc suppression circuit provided in yet another embodiment of the present application; Figure 8 This is a schematic diagram of the circuit structure of an arc suppression circuit provided in yet another embodiment of the present application; Figure 9 This is a schematic diagram of the circuit structure of an arc suppression circuit provided in yet another embodiment of the present application; Figure 10 This is a schematic diagram of the circuit structure of an arc suppression circuit provided in yet another embodiment of the present application; Figure 11 This is a schematic diagram of the circuit structure of an arc suppression circuit provided in yet another embodiment of the present application; Figure 12 This is a schematic diagram of the circuit structure of an arc suppression circuit provided in yet another embodiment of the present application; Figure 13 This is a schematic diagram of the circuit structure of an arc suppression circuit provided in yet another embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to facilitate the understanding of the present application, the present application is described in more detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or there can be one or more centered elements therebetween. When an element is described as being "electrically connected" to another element, it can be directly connected to the other element, or there can be one or more centered elements therebetween. The terms "upper", "lower", "inner", "outer", "bottom" and the like used in this specification indicate an orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" and the like are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0018] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" used in this specification includes any and all combinations of one or more of the related listed items. In addition, the technical features involved in the different embodiments of this application described below may be combined with each other as long as they do not conflict with each other.

[0019] To meet the growing demand for high power, the USB Association's PD3.1 protocol supports voltages up to 48V. The UFCS protocol launched in China extends power output voltages up to 60V. Hot-plugging chargers is prone to arcing. Reducing the voltage difference across the charging port can suppress arcing. Arcing can be suppressed in two ways: 1. Reducing the voltage on the power supply side during plugging and unplugging; 2. Raising the voltage on the power receiving side during plugging and unplugging.

[0020] The first method requires detecting whether the load is unplugged from the charging port through changes in the CC line or load current. When the load is unplugged from the charging port, the fast charging device quickly reduces the output voltage to reduce the energy of the arc. This method has high requirements for the power management chip, which requires the power management chip to have high-precision ADC detection capabilities to detect subtle changes in current and then quickly reduce the output voltage. However, the power supply end of the power management chip is equipped with a capacitor. Due to the voltage hysteresis change of the capacitor, it takes milliseconds to reduce the output voltage, resulting in the first method being less than ideal for suppressing arcs.

[0021] The second method requires setting up a large capacitor, which slowly discharges the battery at the charging port, reducing the voltage difference at the charging port and thus reducing the energy of the arc. However, the cost of the large capacitor is high, and the large capacitor will draw current from the receiving end, causing the current transmitted from the power supply equipment to the receiving end to fluctuate easily.

[0022] In the embodiment of the present application, an arc suppression circuit is provided at the receiving end. By increasing the voltage at the receiving end during plugging and unplugging, the energy of the arc at the charging interface is suppressed. Compared with the method of reducing the voltage at the power supply end during plugging and unplugging, increasing the voltage at the receiving end is faster and more universal, and is applicable to both the Type-A interface connected to the adapter and the Type-C interface connected to the receiving end.

[0023] See also Figure 1 The arc suppression circuit 100 is applied to a charging interface 200 , which is provided with a busbar 21 for transmitting a busbar voltage. The charging interface 200 is electrically connected to an external device 300 .

[0024] The external device 300 transmits power to the charging port 200, which then transmits the power to the load 400 via the bus 21 in the form of a bus voltage, thereby driving the load 400. When the external device 300 is unplugged from the charging port 200, the arc suppression circuit 100 raises the bus voltage of the bus 21, thereby reducing the voltage difference between the voltage output by the external device 300 and the bus voltage of the charging port 200, thereby reducing the energy of the arc.

[0025] In some embodiments, the arc suppression circuit 100 is provided on the charging interface 200, which is provided on the load 400. The charging interface may be a Type-A interface or a Type-C interface, and correspondingly, the external device 300 may be an electronic device having a Type-A interface or a Type-C interface. The external device 300 charges the load 400 through the charging interface 200. When the external device 300 is unplugged from the charging interface 200 of the load 400, the arc suppression circuit 100 raises the bus voltage of the bus 21, which is equivalent to raising the voltage of the charging interface 200, thereby reducing the voltage difference between the voltage output by the external device 300 and the voltage of the charging interface 200, thereby reducing the energy of the arc.

[0026] In other embodiments, the arc suppression circuit 100 is provided on a charging cable. Specifically, the charging cable comprises a cable body and first and second charging interfaces disposed at both ends of the cable body. The arc suppression circuit 100 can be provided on the first charging interface, the second charging interface, or the cable body. The interface type of the first charging interface and the interface type of the second charging interface can be the same or different. The first and second charging interfaces can be either Type-A or Type-C.

[0027] The first charging port of the charging cable is electrically connected to the external device 300, and the second charging port of the charging cable is electrically connected to the load 400. The external device 300 provides power to the load 400 via the charging cable. When the external device 300 is unplugged from the first charging port of the charging cable, the arc suppression circuit 100 raises the bus voltage of the bus 21, which is equivalent to raising the voltage of the first charging port. This reduces the voltage difference between the voltage output by the external device 300 and the voltage of the first charging port, thereby reducing the energy of the arc.

[0028] See also Figure 2 The arc suppression circuit 100 includes a driving circuit 11 , a charging circuit 12 , a discharging circuit 13 and a charging control circuit 14 .

[0029] The drive circuit 11 is electrically connected to the bus 21 and is configured to output a first drive signal in response to the charging interface 200 being inserted into the external device 300, or to output a second drive signal in response to the external device 300 being removed from the charging interface 200. The external device 300 is configured to transmit the bus voltage to the bus 21 via the charging interface 200. The level type of the first drive signal and the level type of the second drive signal are opposite. In some embodiments, the first drive signal is a low level and the second drive signal is a high level. In other embodiments, the first drive signal is a high level and the second drive signal is a low level.

[0030] The charging circuit 12 is electrically connected to the driving circuit 11 , and the discharging circuit 13 is electrically connected to the bus bar 21 and is also electrically connected to the charging circuit 12 .

[0031] The charging control circuit 14 is electrically connected to the drive circuit 11 and the charging circuit 12, respectively, and is used to respond to the first drive signal to control the charging circuit 12 to receive the bus voltage for charging, or, respond to the second drive signal, control the charging circuit 12 to stop charging, and control the charging circuit 12 to discharge to the bus 21 through the discharge circuit 13 to increase the bus voltage of the bus 21. This is equivalent to raising the voltage of the charging interface 200, thereby reducing the voltage difference between the voltage output by the external device 300 and the voltage of the charging interface 200, and reducing the energy of the arc.

[0032] In some embodiments, the driving circuit 11 is a microprocessor, which is electrically connected to the bus 21 and also electrically connected to the charging circuit 12. The microprocessor detects that the charging interface 200 is inserted into the external device 300 and outputs a first driving signal, or detects that the external device 300 is unplugged from the charging interface 200 and outputs a second driving signal.

[0033] In some other embodiments, the driving circuit 11 includes a voltage hysteresis circuit 110, see Figure 3 The voltage hysteresis change circuit 110 is electrically connected to the bus 21 and is also electrically connected to the charging circuit 12. It is used to respond to the charging interface being plugged into an external device and the bus voltage being greater than the positive threshold, and output a first drive signal. The charging control circuit 14 responds to the first drive signal and controls the charging circuit 12 to receive the bus voltage for charging.

[0034] The voltage hysteresis change circuit 110 is also used to: output a second drive signal in response to the external device being unplugged from the charging interface and the bus voltage being less than a negative threshold. The charging control circuit 14 responds to the second drive signal to control the charging circuit 12 to stop charging, and controls the charging circuit 12 to discharge to the bus 21 through the discharge circuit 13 to increase the bus voltage of the bus 21.

[0035] For the receiving end, the load can regulate the bus voltage, causing the bus voltage to change. The voltage hysteresis variation circuit delays the change in the bus voltage, which can resist the jitter interference of the bus voltage. When the bus voltage changes between the positive threshold and the negative threshold, the drive signal output by the voltage hysteresis variation circuit does not change. The drive signal output by the voltage hysteresis variation circuit can only change when the bus voltage is greater than the positive threshold or when the bus voltage is less than the negative threshold. The voltage hysteresis variation circuit provides a wide variation range for the bus voltage change, reliably eliminating the jitter interference of the bus voltage.

[0036] The positive threshold is greater than the charging voltage of the charging circuit 12, and the negative threshold is less than the charging voltage of the charging circuit 12. The positive threshold provided in the embodiment of the present application is linked to the charging voltage, and the negative threshold is also linked to the charging voltage. This can help the charging circuit 12 quickly enter the charging state when the external device 300 is inserted into the charging interface 200, and quickly enter the discharging state to increase the bus voltage when the external device 300 is unplugged from the charging interface 200. This realizes the rapid switching of the charging circuit 12 between the charging state and the discharging state during hot plugging, so as to reliably increase the bus voltage and suppress the energy of the arc.

[0037] See also Figure 4 The voltage hysteresis variation circuit 110 is a Schmitt trigger, which includes a first operational amplifier U1, a first resistor R1, and a second resistor R2. The inverting input terminal of the first operational amplifier U1 is electrically connected to the bus 21, and the non-inverting input terminal of the first operational amplifier U1 is electrically connected to the first end of the first resistor R1 and the first end of the second resistor R2, respectively. The second end of the first resistor R1 is electrically connected to the charging circuit 12, and the second end of the second resistor R2 is electrically connected to the output terminal of the first operational amplifier U1 and the charging control circuit 14, respectively.

[0038] The first operational amplifier U1 is used to output a first drive signal in response to the charging interface 200 being plugged into the external device 300 and the bus voltage being greater than the positive threshold. The charging control circuit 14 responds to the first drive signal and controls the charging circuit 12 to receive the bus voltage for charging.

[0039] The first operational amplifier U1 is further configured to output a second drive signal in response to the external device 300 being unplugged from the charging interface 200 and the bus voltage being less than a negative threshold. The charging control circuit 14 controls the charging circuit 12 to stop charging in response to the second drive signal, and controls the charging circuit 12 to discharge to the bus 21 through the discharge circuit 13 to increase the bus voltage of the bus 21.

[0040] Positive threshold V TH and the negative threshold V TL The expression is as follows:

[0041] and They are the positive power supply voltage and negative power supply voltage of the first operational amplifier U1 respectively.

[0042] The embodiment of the present application adopts a Schmitt trigger as the voltage hysteresis change circuit 110, and utilizes the characteristics of voltage hysteresis change to suppress the jitter interference of the bus voltage and improve working reliability.

[0043] See also Figure 5The charging circuit 12 includes a capacitor C1, a first end of the capacitor C1 is electrically connected to the second end of the first resistor R1, the charging control circuit 14 and the discharge circuit 13, and a second end of the capacitor C1 is grounded.

[0044] When the charging port 200 is plugged into an external device 300, the bus voltage gradually increases. When the bus voltage exceeds the positive threshold, the first operational amplifier U1 outputs a low-level first drive signal. In response to the first drive signal, the charging control circuit 14 controls the charging circuit 12 to receive the bus voltage for charging.

[0045] When the external device 300 is unplugged from the charging port 200, the bus voltage drops rapidly. When the bus voltage falls below the negative threshold, the first op amp U1 outputs a high-level second drive signal. In response to the second drive signal, the charging control circuit 14 controls the charging circuit 12 to stop charging and discharge the battery to the bus 21 via the discharge circuit 13, thereby increasing the bus voltage of the bus 21.

[0046] See also Figure 6 The charging control circuit 14 includes a first switching circuit 141 and a second switching circuit 142. The first switching circuit 141 is electrically connected to the voltage hysteresis change circuit 110, and is used to respond to the first drive signal and enter the cut-off state to output the first control signal, or respond to the second drive signal and enter the conduction state to output the second control signal.

[0047] The second switch circuit 142 is electrically connected to the bus 21 and is also electrically connected to the first switch circuit 141 and the charging circuit 12. It is configured to respond to a first control signal and enter an on state to transmit the bus voltage to the charging circuit 12 through the second switch circuit 142. When the charging voltage of the charging circuit 12 reaches a preset voltage, the first switch circuit 141 is triggered to enter an off state. Alternatively, in response to a second control signal, the second switch circuit 142 is configured to enter an off state to disconnect the bus voltage from the charging circuit 12. The first control signal and the second control signal have opposite levels. In some embodiments, the first control signal is low and the second control signal is high. In other embodiments, the first control signal is high and the second control signal is low.

[0048] When the charging circuit 12 discharges energy to the bus 21 through the discharge circuit 13, the energy output by the charging circuit 12 is discharged through the first switch circuit 141, which is in the on state. When the external device 300 is unplugged from the charging port 200, the receiving end easily shuts off the charging path that supplies energy to the load. However, the energy from the charging circuit 12 can be discharged through the first switch circuit 141, which is in the on state, while simultaneously raising the bus voltage. When the external device 300 is next plugged into the charging port 200, the charging circuit 12, having discharged energy, can quickly enter the charging state to store energy, and reliably raise the bus voltage when in the discharge state.

[0049] See also Figure 7 The first switching circuit 141 includes a first switching tube, which is electrically connected to the voltage hysteresis change circuit 110 and the second switching circuit 142 respectively, and is used to respond to the first drive signal and enter the cut-off state to output the first control signal, or respond to the second drive signal and enter the on state to output the second control signal.

[0050] See also Figure 8 The first switching transistor is a first NMOS transistor Q1. The gate of the first NMOS transistor Q1 is electrically connected to the voltage hysteresis variation circuit 110. The drain of the first NMOS transistor Q1 is electrically connected to the second switching circuit 142. The source of the first NMOS transistor Q1 is grounded. The first NMOS transistor Q1 is configured to respond to a low level and enter a cut-off state to output a high level through the drain, or respond to a high level and enter a conduction state to output a low level through the drain. The first drive signal and the second control signal are both low levels, and the second drive signal and the first control signal are both high levels.

[0051] Please continue reading Figure 8 The first switch circuit 141 further includes a third resistor R3, a first end of which is electrically connected to the busbar 21, and a second end of which is electrically connected to the drain of the first NMOS transistor Q1. When the charging circuit 12 discharges to the busbar 21 via the discharge circuit 13, the electrical energy output by the charging circuit 12 is discharged through the first NMOS transistor Q1 and the third resistor R3, which are both in the conductive state.

[0052] See also Figure 9 The second switching circuit 142 includes a second switching tube, which is electrically connected to the bus 21 and the first switching circuit 141, and is used to respond to the first control signal and enter the on state to allow the bus voltage to be transmitted to the charging circuit 12 through the second switching tube, or, respond to the second control signal, enter the off state to disconnect the loop for transmitting the bus voltage to the charging circuit 12.

[0053] See also Figure 10The second switch tube is a second NMOS tube Q2. The drain of the second NMOS tube Q2 is electrically connected to the bus 21. The second end of the third resistor R3 is electrically connected to the gate of the second NMOS tube Q2. The source of the second NMOS tube Q2 is electrically connected to the charging circuit 12. The second NMOS tube Q2 is used to respond to a high level and enter a conductive state to transmit the bus voltage to the charging circuit 12 through the second NMOS tube Q2. When the charging voltage of the charging circuit 12 reaches a preset voltage, the first switch circuit 141 is triggered to enter a cut-off state, or respond to a low level and enter a cut-off state to disconnect the loop for transmitting the bus voltage to the charging circuit 12. The first control signal is a high level, and the second control signal is a low level.

[0054] The working principles of the first switch circuit 141 and the second switch circuit 142 are as follows: When an external device 300 is plugged into charging port 200, the bus voltage gradually increases. When the bus voltage exceeds the positive threshold, first op amp U1 outputs a low-level first drive signal. In response to the low-level first drive signal, first NMOS transistor Q1 enters a cutoff state, raising the voltage at the drain of first NMOS transistor Q1 and thereby outputting a high-level first control signal. Second NMOS transistor Q2, in response to the high-level first control signal, enters a conductive state, transmitting the bus voltage through second NMOS transistor Q2 to capacitor C1. Capacitor C1 receives electrical energy and enters a charging state, with the charged voltage of capacitor C1 gradually increasing.

[0055] When the voltage drop between the gate voltage of the first NMOS transistor Q1 and the charging voltage fails to meet the conduction condition of the first NMOS transistor Q1, the first NMOS transistor Q1 enters the cutoff state, and the bus voltage cannot be transmitted to the capacitor C1 through the second NMOS transistor Q2. Therefore, the capacitor C1 stops charging. When charging, the capacitor C1 only needs to draw a small amount of current and gradually releases the stored energy when discharging. During other time periods, it is isolated from the bus voltage and does not affect the load's demand for the bus voltage.

[0056] When the external device 300 is unplugged from the charging port 200, the bus voltage drops rapidly. When the bus voltage is less than the negative threshold, the first op amp U1 outputs a high-level second drive signal. In response to the high-level second drive signal, the first NMOS transistor Q1 enters the on-state, pulling down the voltage at the drain of the first NMOS transistor Q1 and outputting a low-level second control signal. The second NMOS transistor Q2 responds to the low-level second control signal and enters the off-state, preventing the bus voltage from being transmitted to the capacitor C1 through the second NMOS transistor Q2. At the same time, the capacitor C1 discharges to the bus 21 through the discharge circuit 13, thereby increasing the bus voltage of the bus 21.

[0057] The bus voltage and the voltage across the capacitor are relatively high, for example, 48V or 60V, and the voltage across the capacitor is 20V. The voltage output by the voltage hysteresis variation circuit 110 to the first NMOS transistor Q1 is relatively small. The embodiment of the present application uses a two-stage switching circuit as the charging control circuit 14 to achieve the effect of a small voltage controlling a large voltage. Specifically, the first NMOS transistor Q1 is controlled by the voltage hysteresis variation circuit 110. When the first NMOS transistor Q1 enters the cut-off state, the bus voltage acts on the gate of the second NMOS transistor Q2. Even if the voltage across the capacitor acts on the source of the second NMOS transistor Q2, although the bus voltage and the voltage across the capacitor are relatively high, the bus capacitance is still greater than the voltage across the capacitor. The second NMOS transistor Q2 still enters the on-state, and the bus voltage is transmitted to the capacitor C1 through the second NMOS transistor Q2. In this way, even when the voltage across the capacitor is relatively large, the small voltage output by the voltage hysteresis variation circuit 110 can be used to control the second NMOS transistor Q2 to enter the on-state with the help of the larger bus voltage, achieving the effect of a small voltage controlling a large voltage.

[0058] See also Figure 11 The discharge circuit 13 includes an isolation circuit 131 and a voltage follower circuit 132 .

[0059] The isolation circuit 131 is electrically connected to the busbar 21 and is used to prevent the busbar voltage from flowing back into the charging circuit 12 through the voltage follower circuit 132. The voltage follower circuit 132 is electrically connected to the isolation circuit 131 and the charging circuit 12, respectively, and is used to apply the charging voltage of the charging circuit 12 to the busbar 21 through the isolation circuit 131 when the external device 300 is unplugged from the charging interface 200.

[0060] The input impedance of the voltage follower circuit 132 is relatively high, preventing the power of the charging circuit 12 from being rapidly depleted. Therefore, the discharge rate of the charging circuit 12 to the bus 21 via the voltage follower circuit 132 is scientifically controllable, preventing the complete release of power from the charging circuit 12 before an arc forms, thereby reliably suppressing arc energy. Furthermore, the embodiment of the present application also adjusts the discharge rate by adjusting the resistance of the third resistor R3, ensuring that the voltage at the receiving end does not drop too low at the moment of unplugging, and that the power is fully discharged after unplugging, without affecting the next plug-in.

[0061] See also Figure 12 The isolation circuit 131 includes a diode D1, the anode of the diode D1 is electrically connected to the output end of the voltage follower circuit 132, and the cathode of the diode D1 is electrically connected to the bus 21. The diode D1 is used to prevent the bus voltage from flowing back to the charging circuit 12 through the voltage follower circuit 132.

[0062] When the bus voltage is greater than the charging voltage, without diode D1, the bus voltage flows back through the voltage follower circuit 132 to the charging circuit 12, potentially affecting the load's current draw. However, diode D1 prevents the bus voltage from flowing back through the voltage follower circuit 132 to the charging circuit 12, improving load reliability.

[0063] See also Figure 13 The voltage follower circuit 132 includes a second operational amplifier U2. The non-inverting input terminal of the second operational amplifier U2 is electrically connected to the charging circuit 12, the inverting input terminal of the second operational amplifier U2 is electrically connected to the output terminal of the second operational amplifier U2, and the output terminal of the second operational amplifier U2 is electrically connected to the isolation circuit 131. The second operational amplifier U2 can output the charging voltage following the charging circuit 12, and the charging voltage is then transmitted to the bus 21 through the diode D1.

[0064] In order to elaborate on the working principle of the arc suppression circuit 100 provided in the embodiment of the present application, the embodiment of the present application combines Figure 13 The details are as follows: ① When the charging port 200 is plugged into an external device 300, the voltage Vc1 across capacitor C1 is zero, and the bus voltage gradually increases. When the bus voltage exceeds the positive threshold, the Schmitt trigger outputs a low-level first drive signal. In response to the low-level first drive signal, the first NMOS transistor Q1 enters a cutoff state, raising the voltage at the drain of the first NMOS transistor Q1 and thereby outputting a high-level first control signal. In response to the high-level first control signal, the second NMOS transistor Q2 enters a conductive state, transmitting the bus voltage through the second NMOS transistor Q2 to capacitor C1. Capacitor C1 receives electrical energy and enters a charging state, with the charged voltage of capacitor C1 gradually increasing.

[0065] When the charging voltage of capacitor C1 rises to a level slightly lower than the bus voltage, the voltage drop between the gate voltage of the first NMOS transistor Q1 and the charging voltage is less than the turn-on threshold of the first NMOS transistor Q1. The first NMOS transistor Q1 enters the cut-off state, and the bus voltage cannot be transmitted to capacitor C1 through the second NMOS transistor Q2. Therefore, capacitor C1 stops charging.

[0066] The equivalent impedance RL of load 400 receives the bus voltage through bus 21 and is driven by the bus voltage to operate. At this time, diode D1 blocks the bus voltage from flowing back into capacitor C1 through voltage follower circuit 132, preventing capacitor C1 from being forced to charge. This isolates capacitor C1 from bus 21 and prevents the load from being affected by capacitor C1.

[0067] When the external device 300 is unplugged from the charging port 200, the bus voltage drops rapidly. When the bus voltage is less than the negative threshold, the first op amp U1 outputs a high-level second drive signal. In response to the high-level second drive signal, the first NMOS transistor Q1 enters the on-state, pulling down the voltage at the drain of the first NMOS transistor Q1 and thereby outputting a low-level second control signal. The second NMOS transistor Q2, in response to the low-level second control signal, enters the off-state, preventing the bus voltage from being transmitted to the capacitor C1 through the second NMOS transistor Q2. At the same time, capacitor C1 discharges to the bus 21 through the voltage follower circuit 132, increasing the bus voltage of the bus 21. This reduces the voltage difference between the voltage output by the external device 300 and the voltage of the first charging port, thereby reducing the energy of the arc.

[0068] When the receiving end closes the charging path for providing power to the load, the power in capacitor C1 is discharged through the voltage follower circuit 132 and the third resistor R3. When the external device 300 is plugged into the charging port 200 again, the capacitor C1, which has discharged energy, can quickly enter the charging state to store energy and reliably raise the bus voltage in the discharging state.

[0069] In summary, the arc suppression circuit 100 provided in the embodiment of the present application has at least the following technical effects: 1) An arc suppression circuit is installed at the receiving end. By increasing the voltage at the receiving end during plugging and unplugging, the energy of the arc at the charging interface is suppressed. Compared with reducing the voltage at the supply end during plugging and unplugging, increasing the voltage at the receiving end is faster and more universal.

[0070] 2) The circuit structure of the arc suppression circuit 100 is relatively simple and reliable, applicable to all fast charging interfaces, and does not occupy resources of the original circuit.

[0071] 3) The circuit's response speed is optimized. When the bus voltage is being regulated, rather than when an external device is unplugged from the charging port, the circuit's response is delayed due to the hysteresis of the Schmitt trigger, resulting in slow capacitor charging and discharging. When the external device is unplugged from the charging port, the bus voltage quickly drops to zero, allowing the arc suppression circuit to take over within nanoseconds.

[0072] 4) The arc suppression circuit 100 has little interference with the charging circuit. It only draws a small amount of electricity during the charging phase of the capacitor and gradually releases the stored electricity during the discharging phase. It is isolated from the busbar at other times and does not affect the normal charging process.

[0073] 5) Due to the presence of the voltage follower, the receiving end cannot immediately drain the capacitor. By adjusting the resistance of the third resistor R3 to adjust the discharge rate, the voltage at the receiving end is not too low when the device is unplugged. After the device is unplugged, the power is completely discharged without affecting the next insertion.

[0074] 6) The Schmitt trigger can resist the jitter of the bus voltage and avoid frequent control of the charging control circuit.

[0075] 7) The embodiment of the present application uses a two-stage switching circuit as the charging control circuit 14 to achieve the effect of controlling a large voltage with a small voltage.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Based on the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the present application as described above. For the sake of simplicity, they are not provided in detail. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An arc suppression circuit, applied to a charging interface, wherein the charging interface is provided with a busbar, the busbar being used to transmit busbar voltage, characterized in that: The arc suppression circuit comprises: a drive circuit electrically connected to the bus and configured to output a first drive signal in response to an external device being inserted into the charging interface, or to output a second drive signal in response to an external device being unplugged from the charging interface, wherein the external device is configured to transmit a bus voltage to the bus through the charging interface; a charging circuit, electrically connected to the driving circuit; a discharge circuit, electrically connected to the busbar and to the charging circuit; The charging control circuit is electrically connected to the drive circuit and the charging circuit, respectively, and is configured to respond to the first drive signal to control the charging circuit to receive the bus voltage for charging, or respond to the second drive signal to control the charging circuit to stop charging and control the charging circuit to discharge to the bus through the discharge circuit to increase the bus voltage of the bus.

2. The arc suppression circuit according to claim 1, characterized in that: The drive circuit includes a voltage hysteresis variation circuit, which is electrically connected to the bus and also electrically connected to the charging circuit. The circuit is configured to output a first drive signal in response to the charging interface being plugged into an external device and the bus voltage being greater than a positive threshold, or to output a second drive signal in response to the charging interface being unplugged from an external device and the bus voltage being less than a negative threshold, wherein the positive threshold is greater than the charging voltage of the charging circuit, and the negative threshold is less than the charging voltage of the charging circuit.

3. The arc suppression circuit according to claim 2, characterized in that: The voltage hysteresis variation circuit is a Schmitt trigger, which includes a first operational amplifier, a first resistor, and a second resistor. The inverting input terminal of the first operational amplifier is electrically connected to the bus, the non-inverting input terminal of the first operational amplifier is electrically connected to the first end of the first resistor and the first end of the second resistor, respectively. The second end of the first resistor is electrically connected to the charging circuit, and the second end of the second resistor is electrically connected to the output terminal of the first operational amplifier and the charging control circuit, respectively. The first operational amplifier is configured to output a first drive signal in response to the charging interface being inserted into an external device and the bus voltage being greater than a positive threshold, or to output a second drive signal in response to the charging interface being unplugged from an external device and the bus voltage being less than a negative threshold.

4. The arc suppression circuit according to claim 2, wherein: The charging control circuit includes: a first switch circuit, electrically connected to the voltage hysteresis variation circuit, and configured to enter a cutoff state to output a first control signal in response to the first drive signal, or enter a conduction state to output a second control signal in response to the second drive signal; The second switch circuit is electrically connected to the bus and is also electrically connected to the first switch circuit and the charging circuit, and is configured to respond to the first control signal, enter an on state to transmit the bus voltage to the charging circuit through the second switch circuit, so that when the charging voltage of the charging circuit reaches a preset voltage, the first switch circuit is triggered to enter an off state, or, respond to the second control signal, enter an off state to disconnect the loop for transmitting the bus voltage to the charging circuit.

5. The arc suppression circuit according to claim 4, characterized in that: When the charging circuit discharges to the busbar through the discharging circuit, the electric energy output by the charging circuit is discharged through the first switch circuit in the on state.

6. The arc suppression circuit according to any one of claims 1 to 5, characterized in that: The discharge circuit includes an isolation circuit and a voltage follower circuit; The isolation circuit is electrically connected to the bus and configured to prevent the bus voltage from flowing back to the charging circuit through the voltage follower circuit; The voltage follower circuit is electrically connected to the isolation circuit and the charging circuit respectively, and is configured to apply the charging voltage of the charging circuit to the busbar through the isolation circuit when the external device is unplugged from the charging interface.

7. The arc suppression circuit according to claim 6, characterized in that: The isolation circuit includes a diode, the positive electrode of the diode is electrically connected to the output end of the voltage follower circuit, and the negative electrode of the diode is electrically connected to the bus. The diode is configured to prevent the bus voltage from flowing back to the charging circuit through the voltage follower circuit.

8. The arc suppression circuit according to claim 6, characterized in that: The voltage follower circuit includes a second operational amplifier, a non-inverting input terminal of the second operational amplifier is electrically connected to the charging circuit, an inverting input terminal of the second operational amplifier is electrically connected to the output terminal of the second operational amplifier, and the output terminal of the second operational amplifier is electrically connected to the isolation circuit.

9. A charging interface, characterized in that: The arc suppression circuit comprises the arc suppression circuit according to any one of claims 1 to 8.

10. A charging cable, characterized in that: The arc suppression circuit comprises the arc suppression circuit according to any one of claims 1 to 8.

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