Resonant gate drive circuit with reconfigurable dead time control

Abstract

The application discloses a resonant gate drive circuit with reconfigurable dead-time control, and belongs to the field of integrated circuits, comprising a reconfigurable dead-time control circuit and a resonant drive circuit. The reconfigurable dead-time control circuit is composed of three cascaded stages of a pulse wave generation circuit, a shift register circuit and a logic operation circuit, and an input end is connected with an external control signal; the resonant drive circuit is composed of six transistors, two inductors and one capacitor, and an output end is connected with a driven circuit; the pulse wave generation circuit comprises six groups of D flip-flops, output signals pass through the shift register circuit and reach the logic operation circuit to form six independent control signals, directly drive the switching states of the six transistors of the resonant drive circuit, generate resonance through the inductors and the load capacitor of the driven circuit, realize drive energy recovery, and realize frequency conversion and duty cycle conversion output by changing the pulse length of part of the input signals. The circuit only relies on one external control signal, and can flexibly control key parameters.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a resonant gate drive circuit with reconfigurable dead-time control. Background Technology

[0002] Driven by the ongoing demand for miniaturization in portable devices, achieving high efficiency and miniaturization of switching power supplies has become a key development direction in this technology field. Increasing the switching frequency is an effective way to reduce the size and weight of switching power supplies; however, this also leads to a significant increase in the losses of power switching transistors, with gate drive losses being particularly prominent.

[0003] Traditional gate drive losses are typically proportional to the switching frequency. At high switching frequencies, these high drive losses become a major bottleneck restricting further increases in frequency and power density of power converters. Specifically, in a typical peripheral circuit configuration, a single half-bridge driver chip can only drive a pair of half-bridge power transistors, and its drive losses increase linearly with frequency, severely limiting further increases in the converter's switching frequency. Furthermore, some converter topologies have a large number of power MOSFETs. Using the traditional half-bridge driver chip solution would lead to a series of problems, including a large number of required driver chips, a dramatic increase in drive losses, an exceptionally complex auxiliary power supply structure, and an excessively large space occupied by the drive system, ultimately reducing the overall power density of the system.

[0004] To effectively reduce system drive losses, high-frequency resonant gate drive technology has emerged. This technology utilizes the LC resonance principle of inductance and capacitance to recover energy from the gate capacitor, significantly reducing drive losses and demonstrating clear advantages in high-frequency applications. In recent years, various resonant gate drive circuit structures have been proposed. However, existing solutions generally suffer from the following drawbacks: excessive circuit footprint, low drive energy recovery efficiency, complex control signals, insufficient drive capability, difficulty in flexibly adjusting duty cycle and dead time, and timing deviations easily generated by multi-signal control. These shortcomings limit the widespread application of resonant gate drive technology in high-efficiency, high-frequency, and high-power-density power supply systems. Summary of the Invention

[0005] Technical Problem: Addressing the issues of large footprint, low energy recovery efficiency, poor flexibility in duty cycle and dead time adjustment, and timing deviations easily generated by multi-signal control in existing resonant gate drive circuits, this invention proposes a resonant gate drive circuit with reconfigurable dead time control. Relying on only one external control signal, it can flexibly adjust key parameters, significantly reducing PAD resource usage and control logic complexity during drive circuit integration. It eliminates the need for an external dead time IC and complex decoupling algorithms, while also eliminating the risk of duty cycle drift and soft-switching failure caused by multi-signal synchronization timing deviations. This results in high drive energy recovery efficiency, and the duty cycle and dead time of the output signal are flexibly adjustable.

[0006] Technical solution: The present invention adopts the following technical solution: a resonant gate drive circuit with reconfigurable dead time control, comprising: a reconfigurable dead time control circuit and a resonant drive circuit.

[0007] The reconfigurable dead-time control circuit includes a pulse wave generation circuit, a shift register circuit, and a logic operation circuit. The resonant drive circuit consists of six metal-oxide-semiconductor field-effect transistors (MOSFETs) S1, S2, S3, S4, S5, and S6, two inductors L1 and L2, and a capacitor Ce. The output terminals Vgsr1 and Vgsr2 are connected to the driven circuit.

[0008] The pulse wave generating circuit includes six sets of D flip-flops DFF1~DFF6, and output signals Q1~Q6 to the shift register circuit. The shift register circuit includes ten sets of cascaded D flip-flops DFF7~DFF16 and NAND gate units. The output signals Q7~Q16 are input to the logic operation circuit after being logically operated by the NAND gate units, forming six independent control signals G1~G6, which are output to the resonant drive circuit to directly drive the switching state of transistors S1~S6.

[0009] The resonant drive circuit resonates with the load capacitors Cgsr1 and Cgsr2 of the driven circuit through inductors L1 and L2 to achieve drive energy recovery, and achieves variable frequency and variable duty cycle output by changing part of the pulse duration of the input signal PWM1.

[0010] Preferably, the reconfigurable dead-time control circuit consists of a pulse wave generation circuit, a shift register circuit, and a logic operation circuit cascaded together.

[0011] The input control signal PWM1 is connected in parallel to the data terminals (D terminals) of the six D flip-flops DFF1~DFF6 of the pulse wave generation circuit. The output signals Q1~Q6 are fed back to the reset terminal (Reset) of this stage through the inverter delay chain, forming a self-limiting pulse sequence.

[0012] In the shift register circuit, the output signals Q1~Q6 of the previous stage pulse wave generation circuit are connected to the clock terminal (CLK) of the D flip-flops DFF7~DFF16 in this stage. The output signals Q7~Q16 are sent to the data terminal (D terminal) of the next D flip-flop after being logically operated by the NAND gate unit, so as to realize the signal delay with adjustable phase step Δt.

[0013] The logic operation circuit receives the output signals Q7~Q16 from the shift register circuit, synthesizes them into six independent control signals G1~G6 through combinational logic, and outputs them to directly drive the gate timing of transistors S1~S6 in the resonant drive circuit.

[0014] Preferably, the resonant drive circuit includes a power switch network, a resonant energy recovery network, and a drive interface unit.

[0015] Transistors S1 and S2 are PMOS transistors, and transistors S3, S4, S5, and S6 are NMOS transistors. The connection definitions for each transistor are as follows:

[0016] The gate of transistor S1 is connected to the control signal G1 output by the logic operation circuit, the source is connected to VCC, and the drain is connected to inductor L1, the drain of transistor S3, and the output terminal Vgsr1.

[0017] The gate of transistor S2 is connected to the control signal G2 output by the logic operation circuit, the source is connected to VCC, and the drain is connected to inductor L2, the drain of transistor S4, and the output terminal Vgsr2.

[0018] The gates of transistors S3 and S4 are connected to the control signals G3 and G4 output from the logic operation circuit, respectively, and their sources are grounded.

[0019] The gates of transistors S5 and S6 are connected to the control signals G5 and G6 output from the logic operation circuit, respectively. Their drains are connected to inductors L1 and L2, respectively. Their sources are connected to the same node of capacitor Ce, and the other end of Ce is connected to ground GND.

[0020] In the drive interface unit, one end of the load capacitors Cgsr1 and Cgsr2 is connected to the two output terminals Vgsr1 and Vgsr2 of the resonant drive circuit, respectively, and the other end is grounded to GND.

[0021] Preferably, the input terminal of the reconfigurable dead time control circuit is connected to the control signal PWM1 generated by the DSP chip, which generates drive signals G1~G6 to control the switching state of transistors S1~S6, so as to realize the resonance between inductors L1 and L2 and the gate capacitors Cgsr1 and Cgsr2 of the driven circuit, thereby realizing the recovery of drive energy. Furthermore, the variable frequency and variable duty cycle output can be achieved by changing part of the pulse duration of the input signal PWM1.

[0022] Depending on the different input control signals G1~G6, the resonant gate drive circuit operates in different working modes. By utilizing the resonance effect between inductors L1 and L2 and the load capacitors Cgsr1 and Cgsr2 of the driven circuit, an energy recovery path is constructed to realize the recovery of the main power topology gate drive energy.

[0023] Preferably, there are eight different operating modes, and the single cycle of the input signal PWM1 is divided into timing phases T1 to T8. Among them, T4 and T8 directly regulate the dead time between the output signals Vgsr1 and Vgsr2, and T2 and T6 independently control the duty cycle of the output signals Vgsr1 and Vgsr2. By independently adjusting the phase difference through the DSP, the required dead time and duty cycle can be flexibly set to achieve single-channel PWM1 input collaborative reconstruction of dual parameters.

[0024] Compared with the prior art, the present invention, employing the above technical solution, has the following technical effects:

[0025] 1. The resonant gate drive circuit of this invention relies on only one external control signal to flexibly adjust key parameters, reducing the PAD area and drive signal timing error by 83% during integration, eliminating the need for an external dead-time IC and complex decoupling algorithm, and significantly reducing drive loss at high frequencies.

[0026] 2. The single-signal control circuit of this invention can eliminate the risk of duty cycle drift and soft switching failure caused by multi-signal synchronization timing deviation, achieve high drive energy recovery efficiency, significantly reduce drive loss, and the duty cycle and dead time of the output signal are flexibly adjustable.

[0027] 3. The circuit control of this invention is simple, and it can realize soft switching and dual output of MOS transistors, drive a large number of transistors. The components used are small in size, easy to integrate, and have low power consumption, saving cost and space, and have a wide range of applications. Attached Figure Description

[0028] Figure 1 This is the converter circuit topology diagram used in this invention;

[0029] Figure 2 This is a structural diagram of the resonant gate driving circuit of the present invention;

[0030] Figure 3 This is the reconfigurable dead-time control circuit diagram of the present invention;

[0031] Figure 4 This is a diagram of the resonant drive circuit of the present invention;

[0032] Figure 5 This is a diagram of the control signal module of the present invention;

[0033] Figure 6This is a key waveform timing diagram of an embodiment of the present invention;

[0034] Figure 7 These are schematic diagrams of current loops under different modes in embodiments of the present invention;

[0035] Figure 8 This is a key waveform timing diagram after dead time reconstruction according to an embodiment of the present invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the application will be further described in detail below with reference to the accompanying drawings. The described embodiments are only a part of the embodiments involved in this invention. All non-innovative embodiments based on this invention by other researchers in the art are within the protection scope of this invention.

[0037] In a preferred embodiment of the present invention, such as Figure 1 As shown, the resonant gate drive circuit with reconfigurable dead-time control is suitable for driving the secondary-side synchronous rectifier transistors SR1, SR2, SR3 and SR4 in an LLC-DCX converter.

[0038] Among them, the gates of transistors SR1 and SR3 are connected to the output terminal Vgsr1 of the resonant gate drive circuit, and the gates of transistors SR2 and SR4 are connected to the output terminal Vgsr2 of the resonant gate drive circuit.

[0039] The resonant gate drive circuit in this embodiment, such as Figure 2 As shown, it consists of a reconfigurable dead-time control circuit and a resonant drive circuit. The input signal of the reconfigurable dead-time control circuit is the PWM1 signal, and the output signals are G1~G6. The input signals of the resonant drive circuit are connected to G1-G6, and the output terminal is connected to the driven circuit.

[0040] Specifically, a reconfigurable dead-time control circuit, such as Figure 3 As shown, it consists of three cascaded stages: a pulse wave generation circuit, a shift register circuit, and a logic operation circuit.

[0041] The pulse wave generation circuit uses six isomorphic D flip-flop units (DFF1-DFF6). The D terminals of the six D flip-flops are connected to the PWM1 signal. The output signals Q1~Q6 are fed back to the Reset terminal through an inverter delay chain to generate a self-limiting pulse with programmable pulse width.

[0042] The shift register circuit contains ten cascaded D flip-flops (DFF7-DFF16) and NAND gate units. The CLK terminal of the cascaded unit is connected to Q1~Q6, and the outputs Q7~Q16 are fed into the next stage D terminal through NAND gate logic to achieve an adjustable phase step Δt delay.

[0043] The logic operation circuit, based on Q7~Q16, performs combinational logic decoding and outputs six gate drive signals G1~G6 to the power transistors S1~S6 of the resonant gate drive circuit.

[0044] The resonant drive circuit in this embodiment, such as Figure 4 As shown, it consists of three parts: a power switching network, a resonant energy recovery network, and a drive interface.

[0045] In the power switching network, the gates of PMOS transistors S1 and S2 are connected to control signals G1 and G2, respectively, and their sources are connected to the power supply VCC; the gates of NMOS transistors S3 and S4 are connected to G3 and G4, respectively, and their sources are grounded. The drains of S1 and S3, along with inductor L1, are connected to the first output terminal Vgsr1, and the drains of S2 and S4, along with inductor L2, are connected to the second output terminal Vgsr2.

[0046] In the resonant energy recovery network, the gates of MOSFETs S5 and S6 are connected to G5 and G6, respectively, and their drains are connected to the non-output terminals of L1 and L2, respectively. The source is connected to the resonant capacitor Ce through node N1, and the other end of Ce is grounded.

[0047] In the driver interface, Figure 4 It also includes the driven circuit, which can be equivalent to load capacitors Cgsr1 and Cgsr2. One end of the equivalent load capacitors Cgsr1 and Cgsr2 is connected to the two output terminals Vgsr1 and Vgsr2 of the resonant gate drive circuit, respectively, and the other end of both is grounded to GND.

[0048] Furthermore, in this embodiment, the resonant gate drive circuit control signal input module, such as... Figure 5 As shown, the input module can use a digital signal processor (DSP) chip to generate a pulse width modulation (PWM) control signal. The period of this PWM1 signal is set to the target high-frequency operating frequency (typically 1MHz to 2MHz), and an appropriate amplitude and duty cycle are configured. A single cycle of PWM1 is divided into timing phases T1 to T8, where T4 and T8 directly control the dead time between output signals Vgsr1 and Vgsr2, and T2 and T6 independently control their duty cycles. By modifying the phase parameters through the DSP, the two target values ​​can be reconstructed collaboratively without the need for additional external control pins.

[0049] like Figure 6 As shown, this embodiment controls the turn-on or turn-off of transistors S1-S6 by controlling the logic state of the input signal PWM1. The time period between t3 and t4 is the dead time TD1, and the time period between t7 and t8 is the dead time TD2.

[0050] Inductor current i L1 i L2These represent the currents flowing through inductors L1 and L2, respectively, and the driving voltage Vgsr is the voltage at the two output terminals Vgsr1 and Vgsr2 of the resonant drive circuit. By precisely setting the logic state of the input signal PWM1, the output signals Vgsr1, Vgsr2, and the inductor current i can be controlled. L1 i L2 Precise regulation.

[0051] As a preferred embodiment, the dual-output non-isolated resonant gate drive circuit proposed in this embodiment can be divided into eight modes in one operating cycle, such as... Figure 7 As shown, the red part represents the current path in this mode, and the arrows indicate the direction of the current.

[0052] Combination Figure 6 and Figure 7 It allows for a detailed analysis of the circuit operation under eight modes:

[0053] like Figure 7 As shown in (a), in operating mode 1 (t0-t1): at time t0, transistor S5 is turned on, and inductor L1 resonates with load capacitor Cgsr1 and capacitor Ce, resonating and charging the load capacitor. The voltage Vgsr1 gradually increases, and the inductor current i L1 It is sinusoidal and flows into the load capacitor Cgsr1.

[0054] During this period, the inductor current i L1 This can be described using the following formula:

[0055] ;

[0056] in, This indicates the voltage value of Vgsr1. This indicates the capacitance value of Cgsr1.

[0057] like Figure 7 As shown in (b), operating mode 2 (t1-t2): at time t1, the voltage Vgsr1 rises to Vcc, that is, the source-drain voltage difference of transistor S1 is zero, and the resonant current i L1 The voltage is 0. At this time, control transistor S1 is turned on and S5 is turned off, thus achieving zero-voltage turn-on of S1 and zero-current turn-off of S5. Afterwards, the output voltage Vgsr1 is clamped to Vcc, and no current flows through inductors L1 and L2.

[0058] like Figure 7 As shown in (c), operating mode 3 (t2-t3): At time t2, transistor S1 is turned off and S5 is turned on. Inductor L1 resonates with load capacitor Cgsr1 and capacitor Ce, causing resonant discharge of the load capacitor. The gate drive energy is recovered into capacitor Ce. The voltage at the output terminal Vgsr1 gradually decreases, and the inductor current iL1 It is sinusoidal, and the current flow direction is opposite to that in working mode 1.

[0059] like Figure 7 As shown in (d), operating mode 4 (t3-t4): at time t3, the output voltage Vgsr1 drops to 0, that is, the source-drain voltage difference of transistor S3 is zero, and the resonant current i L1 The voltage is 0. At this time, control transistor S3 is turned on and S5 is turned off, thus achieving zero-voltage turn-on of S3 and zero-current turn-off of S5. After that, the output voltages Vgsr1 and Vgsr2 are both 0, and no current flows through inductors L1 and L2. This period is the dead time TD1.

[0060] like Figure 7 As shown in (e), operating mode 5 (t4-t5): At time t4, transistor S6 is turned on, and inductor L2 resonates with load capacitor Cgsr2 and capacitor Ce, resonating and charging the load capacitor. The voltage at the output terminal Vgsr2 gradually increases, and the inductor current i L2 It is sinusoidal and flows into the load capacitor Cgsr2.

[0061] During this period, the inductor current i L2 This can be described using the following formula:

[0062] ;

[0063] in, This represents the Vgsr2 voltage value. This indicates the capacitance value of Cgsr2.

[0064] like Figure 7 As shown in (f), operating mode 6 (t5-t6): at time t5, the output voltage Vgsr2 rises to Vcc, that is, the source-drain voltage difference of transistor S2 is zero, and the resonant current i L2 The voltage is 0. At this time, control transistor S2 is turned on and S6 is turned off, thus achieving zero-voltage turn-on of S2 and zero-current turn-off of S6. Afterwards, the output voltage Vgsr2 is clamped to Vcc, and no current flows through inductors L1 and L2.

[0065] like Figure 7 As shown in (g), operating mode 7 (t6-t7): At time t6, transistor S2 is turned off and S6 is turned on. Inductor L2 resonates with load capacitor Cgsr2 and capacitor Ce, causing resonant discharge to the load capacitor. The gate drive energy is recovered into capacitor Ce. The output voltage Vgsr2 gradually decreases, and the inductor current i L2 It is sinusoidal, and the current flow direction is opposite to that in working mode 5.

[0066] like Figure 7As shown in (h), operating mode 8 (t7-t8): at time t7, the output voltage Vgsr2 drops to 0, that is, the source-drain voltage difference of transistor S4 is zero, and the resonant current i L2 The voltage is 0. At this time, control transistor S4 is turned on and S6 is turned off, thus achieving zero-voltage turn-on of S4 and zero-current turn-off of S6. After that, the output voltages Vgsr1 and Vgsr2 are both 0, and no current flows through inductors L1 and L2. This period is the dead time TD2.

[0067] Furthermore, such as Figure 8 As shown, the reconfigurable dead-time dual-output non-isolated resonant gate drive circuit proposed in this invention can achieve reconfigurable dead time by precisely adjusting the timing control of the input signal PWM1.

[0068] As a preferred embodiment, in this case, it is manifested as follows:

[0069] Increase the time interval T4 of the PWM1 signal to increase the dead time DT1;

[0070] Reduce the T8 time period of the PWM1 signal to reduce the dead time DT2.

[0071] Therefore, by adjusting the timing state of the single input signal PWM1, the dead times DT1 and DT2 can be independently reconstructed.

[0072] In summary, the reconfigurable dead-time dual-output non-isolated resonant gate drive circuit proposed in this embodiment controls the state of MOSFET switches (S1-S6) by precisely regulating the timing state of the input signal PWM1, thereby achieving resonance between inductors L1 and L2 and the equivalent gate capacitances Cgsr1 and Cgsr1 of the driven circuit. This efficiently recovers gate drive energy, reduces drive losses by 85%, and improves power system efficiency by more than 1 percentage point.

[0073] Meanwhile, the circuit boasts a simplified structure and easy control, allowing for flexible adjustment of the duty cycle and independent, precise adjustment of dead times DT1 and DT2, thus expanding its application scenarios. Furthermore, this drive system requires only one external control signal, saving 83% of PAD area compared to traditional multi-channel drive control schemes and eliminating multi-channel signal adaptation errors. Based on these characteristics, the circuit of this invention can be widely applied to advanced power systems such as AI servers and data center power supplies.

[0074] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A resonant gate drive circuit with reconfigurable dead-time control, characterized in that, include: Reconfigurable dead-time control circuit and resonant drive circuit; The reconfigurable dead time control circuit consists of a pulse wave generation circuit, a shift register circuit, and a logic operation circuit cascaded together, with its input terminal connected to the control signal PWM1 generated by the DSP chip. The resonant driving circuit consists of six metal oxide semiconductor field-effect transistors S1~S6, two inductors L1 and L2, and a capacitor Ce. The output terminals Vgsr1 and Vgsr2 are connected to the driven circuit. The pulse wave generating circuit includes six sets of isomorphic D flip-flops DFF1~DFF6, and outputs signals Q1~Q6 to the shift register circuit; the shift register circuit includes ten sets of cascaded D flip-flops DFF7~DFF16 and NAND gate units, and the output signals Q7~Q16 are input to the logic operation circuit after being logically operated by the NAND gate units, forming six independent control signals G1~G6, which are output to the resonant drive circuit to directly drive the switching state of transistors S1~S6; The resonant drive circuit resonates with the load capacitors Cgsr1 and Cgsr2 of the driven circuit through inductors L1 and L2 to achieve drive energy recovery, and achieves variable frequency and variable duty cycle output by changing part of the pulse duration of the input signal PWM1. The resonant drive circuit includes a power switch network, a resonant energy recovery network, and a drive interface unit. Transistors S1 and S2 are PMOS, and transistors S3, S4, S5, and S6 are NMOS. In the power switch network, the gate of transistor S1 is connected to the control signal G1 output by the logic operation circuit, the source is connected to VCC, and the drain is connected to inductor L1, the drain of transistor S3 and the output terminal Vgsr1. The gate of transistor S2 is connected to the control signal G2 output by the logic operation circuit, the source is connected to VCC, and the drain is connected to inductor L2, the drain of transistor S4, and the output terminal Vgsr2. The gates of transistors S3 and S4 are connected to the control signals G3 and G4 output from the logic operation circuit, respectively, and their sources are grounded. In the resonant energy recovery network, the gates of transistors S5 and S6 are respectively connected to the control signals G5 and G6 output by the logic operation circuit, the drains are respectively connected to inductors L1 and L2, the source is connected to the same node of capacitor Ce, and the other end of capacitor Ce is connected to ground GND. In the drive interface unit, one end of the load capacitors Cgsr1 and Cgsr2 are connected to the two output terminals Vgsr1 and Vgsr2 of the resonant drive circuit, respectively, and the other end is grounded to GND. In the pulse wave generation circuit, the input control signal PWM1 is connected in parallel to the data terminals of six D flip-flops DFF1~DFF6, and the output signals Q1~Q6 are fed back to the reset terminal of this stage through the inverter delay chain, forming a self-limiting pulse sequence. In the shift register circuit, the output signals Q1~Q6 of the previous stage pulse wave generation circuit are connected to the clock terminals of the D flip-flops DFF7~DFF16 of this stage. The output signals Q7~Q16 are sent to the data terminals of the next D flip-flop after being logically operated by the NAND gate unit, so as to realize the signal delay with adjustable phase step Δt. The logic operation circuit receives the output signals Q7~Q16 from the shift register circuit, synthesizes them into six independent control signals G1~G6 through combinational logic, and outputs them to directly drive the gate timing of transistors S1~S6 in the resonant drive circuit.

2. The resonant gate drive circuit with reconfigurable dead-time control according to claim 1, characterized in that, Depending on the different input control signals G1~G6, the resonant gate drive circuit operates in different working modes. By utilizing the resonance effect between the inductors L1 and L2 and the load capacitors Cgsr1 and Cgsr2 of the driven circuit, an energy recovery path is constructed to realize the recovery of the main power topology gate drive energy.

3. The resonant gate drive circuit with reconfigurable dead-time control according to claim 2, characterized in that, The resonant gate drive circuit has eight operating modes, and the operation of the resonant gate drive circuit in each operating mode is as follows: Operating Mode 1: At time t0, transistor S5 is turned on, and inductor L1 resonates with load capacitor Cgsr1 and capacitor Ce, resonating and charging load capacitor Cgsr1. The voltage at the output terminal Vgsr1 gradually increases, and the current i flowing through inductor L1... L1 It is sinusoidal and flows into the load capacitor Cgsr1; Operating Mode 2: At time t1, the output voltage Vgsr1 rises to the power supply voltage Vcc, the source-drain voltage difference of transistor S1 is zero, and the current i flowing through inductor L1... L1 The value is 0; control transistor S1 to turn on and transistor S5 to turn off, the voltage at the output terminal Vgsr1 is clamped to Vcc, and no current flows through inductors L1 and L2. Operating Mode 3: At time t2, transistor S1 is off and transistor S5 is on. Inductor L1 resonates with the load capacitor Cgsr1 and capacitor Ce, causing resonant discharge on the load capacitor Cgsr1. The gate drive energy is recovered into capacitor Ce, and the voltage at the output terminal Vgsr1 gradually decreases. The current i flowing through inductor L1... L1 It exhibits a sinusoidal shape, and the current flow direction is opposite to that of operating mode 1; Operating mode 4: At time t3, the output voltage Vgsr1 drops to 0, the source-drain voltage difference of transistor S3 is zero, and the resonant current i L1 The voltage is 0; control transistor S3 is turned on and transistor S5 is turned off, the output voltages Vgsr1 and Vgsr2 are both 0, no current flows through the inductor output voltages L1 and L2, and the dead time TD1 is during the working mode 4. Operating mode 5: At time t4, transistor S6 is turned on, and inductor L2 resonates with load capacitor Cgsr2 and capacitor Ce, resonating and charging load capacitor Cgsr2. The voltage at the output terminal Vgsr2 gradually increases, and the current i flowing through inductor L2... L2 It is sinusoidal and flows into the load capacitor Cgsr2; Operating mode 6: At time t5, the output voltage Vgsr2 rises to Vcc, the source-drain voltage difference of transistor S2 is zero, and the resonant current i L2 The value is 0; control transistor S2 to turn on and transistor S6 to turn off, the voltage at the output terminal Vgsr2 is clamped to Vcc, and no current flows through inductors L1 and L2. Operating Mode 7: At time t6, transistor S2 is off and transistor S6 is on. Inductor L2 resonates with the load capacitor Cgsr2 and capacitor Ce, causing resonant discharge on the load capacitor Cgsr2. The gate drive energy is recovered into capacitor Ce, and the voltage at the output terminal Vgsr2 gradually decreases. The current i flowing through inductor L2... L2 It exhibits a sinusoidal shape, and the current flow direction is opposite to that of operating mode 5; Operating mode 8: At time t7, the output voltage Vgsr2 drops to 0, the source-drain voltage difference of transistor S4 is zero, and the resonant current i L2 The voltage is 0; control transistor S4 is turned on and transistor S6 is turned off, the output voltages Vgsr1 and Vgsr2 are both 0, no current flows through inductors L1 and L2, and the dead time TD2 is during the operation of mode 8.

4. The resonant gate drive circuit with reconfigurable dead-time control according to claim 3, characterized in that, The single cycle of the input signal PWM1 is divided into timing phases T1 to T8. T4 and T8 directly regulate the dead time TD1 and TD2 between the output signals Vgsr1 and Vgsr2. T2 and T6 independently control the duty cycle of the output signals Vgsr1 and Vgsr2. The phase parameters are adjusted independently by the DSP to set the required dead time and duty cycle, thereby realizing the dual-parameter collaborative reconstruction of the single-channel PWM1 input.

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