Fault-tolerant control methods, devices, circuits, electrical equipment, media, and products for inverters.

Abstract

This disclosure provides a fault-tolerant control method, apparatus, circuit, electrical equipment, medium, and product for an inverter. The fault-tolerant control method includes: in the event of a fault in the third bridge arm, disconnecting the third bridge arm and connecting its output terminal to the midpoint of the DC bus; after disconnecting the third bridge arm, determining the vector synthesis order of the reference voltage vector based on the space vector sector where the reference voltage vector is located, wherein the vector synthesis order is the implementation order of multiple basic vectors used to synthesize the reference voltage vector, and the basic vectors are space vectors determined based on the switching states of the switching devices of the first bridge arm and the second bridge arm; determining the action time of each of the multiple basic vectors based on the reference voltage vector, the multiple basic vectors, and a predetermined control period; and obtaining and outputting control signals for controlling the first and second bridge arms based on the action times of each basic vector and the vector synthesis order.

Description

Technical Field

[0001] This disclosure relates to the field of inverter technology, and in particular to a fault-tolerant control method, apparatus, circuit, electrical equipment, medium and product for inverters. Background Technology

[0002] Three-phase two-level inverters have significant advantages in terms of size, manufacturing cost, maintenance cost, and control complexity, and are widely used in motor frequency conversion drives and photovoltaic grid-connected control. In some critical applications, inverters need to have continuous operation capability. However, in related technologies, faults such as bridge arm short circuits or open circuits may occur during the operation of three-phase two-level inverters, causing them to lose continuous and stable operation. Summary of the Invention

[0003] One technical problem addressed by this disclosure is that, in related technologies, a single-phase bridge arm fault may occur during the operation of an inverter, causing the inverter to be unable to operate continuously and stably.

[0004] According to one aspect of this disclosure, a fault-tolerant control method for an inverter is provided, wherein the inverter includes a first bridge arm, a second bridge arm, and a third bridge arm, the fault-tolerant control method comprising: in the event of a fault in the third bridge arm, disconnecting the third bridge arm and connecting the output terminal of the third bridge arm to the midpoint of a DC bus; after disconnecting the third bridge arm, determining the vector synthesis order of the reference voltage vector based on the space vector sector where the reference voltage vector is located, wherein the vector synthesis order is the implementation order of a plurality of basic vectors for synthesizing the reference voltage vector, the basic vectors being space vectors determined based on the switching states of the switching devices of the first bridge arm and the switching states of the switching devices of the second bridge arm; determining the action time of each of the plurality of basic vectors based on the reference voltage vector, the plurality of basic vectors, and a predetermined control period; and obtaining and outputting control signals for controlling the first bridge arm and the second bridge arm based on the action times of the various basic vectors and the vector synthesis order.

[0005] In some embodiments, the fault-tolerant control method further includes: determining the space vector sector in which the reference voltage vector is located before determining the vector synthesis order of the reference voltage vector, wherein the space vector sector includes a first space vector sector and a second space vector sector, the first space vector sector and the second space vector sector are respectively determined by a plurality of corresponding basic vectors, and the first space vector sector is different from the second space vector sector.

[0006] In some embodiments, determining the spatial vector sector in which the reference voltage vector is located includes: decomposing the reference voltage vector in the αβ axis coordinate system to obtain a first decomposed vector on the α axis and a second decomposed vector on the β axis; and based on the first decomposed vector and the second decomposed vector, determining which spatial vector sector, the first spatial vector sector and the second spatial vector sector, the reference voltage vector is located in.

[0007] In some embodiments, the vector synthesis order includes a first vector synthesis order and a second vector synthesis order, wherein the first vector synthesis order is different from the second vector synthesis order; determining the vector synthesis order of the reference voltage vector based on the spatial vector sector where the reference voltage vector is located includes: determining the vector synthesis order of the reference voltage vector as the first vector synthesis order when the reference voltage vector is located in the first spatial vector sector; and determining the vector synthesis order of the reference voltage vector as the second vector synthesis order when the reference voltage vector is located in the second spatial vector sector.

[0008] In some embodiments, the basic vector determined by the switching states of the switching devices of the first bridge arm and the second bridge arm includes a first basic vector, a second basic vector, a third basic vector, and a fourth basic vector, wherein the first basic vector and the third basic vector are equal in magnitude and opposite in direction, the second basic vector and the fourth basic vector are equal in magnitude and opposite in direction, and the first basic vector is perpendicular to the second basic vector.

[0009] In some embodiments, the magnitudes of the first fundamental vector and the third fundamental vector are respectively... The magnitudes of the second fundamental vector and the fourth fundamental vector are respectively ,in, The bus voltage of the DC bus connected to the inverter; in the αβ axis coordinate system, the spatial vector angle of the first basic vector is... The spatial vector angle of the second fundamental vector is The spatial vector angle of the third basic vector is The spatial vector angle of the fourth basic vector is .

[0010] In some embodiments, determining the action time of each of the plurality of basic vectors based on the reference voltage vector, the plurality of basic vectors, and a predetermined control period includes: constructing a spatial rectangular coordinate system with the line containing the first basic vector as the first coordinate axis and the line containing the second basic vector as the second coordinate axis; decomposing the reference voltage vector and the plurality of basic vectors on the first coordinate axis and the second coordinate axis, respectively, to obtain a plurality of decomposed vectors corresponding to the reference voltage vector and the plurality of basic vectors; and calculating the action time of each of the plurality of basic vectors based on the plurality of decomposed vectors and the control period, and using the volt-second balance equation.

[0011] In some embodiments, the vector synthesis order adopts a symmetrical vector order; the basic vector at the center of the vector synthesis order takes the required action time, and the basic vectors on both sides of the center of the vector synthesis order each take half of the required action time.

[0012] In some embodiments, cutting off the third bridge arm and connecting the output terminal of the third bridge arm to the midpoint of the DC bus includes: controlling all switching devices on the third bridge arm to turn off; and controlling the bidirectional thyristor connected between the output terminal of the third bridge arm and the midpoint of the DC bus to turn on.

[0013] According to another aspect of this disclosure, a fault-tolerant control device for an inverter is provided, wherein the inverter includes a first bridge arm, a second bridge arm, and a third bridge arm, and the fault-tolerant control device includes: a fault handling unit, configured to disconnect the third bridge arm and connect its output terminal to the midpoint of a DC bus in the event of a fault in the third bridge arm; a first determining unit, configured to determine the vector synthesis order of the reference voltage vector based on the space vector sector where the reference voltage vector is located after disconnecting the third bridge arm, wherein the vector synthesis order is the implementation order of multiple basic vectors for synthesizing the reference voltage vector, and the basic vectors are space vectors determined based on the switching states of the switching devices of the first bridge arm and the switching states of the switching devices of the second bridge arm; a second determining unit, configured to determine the action time of each of the multiple basic vectors based on the reference voltage vector, the multiple basic vectors, and a predetermined control period; and an output unit, configured to obtain and output control signals for controlling the first bridge arm and the second bridge arm based on the action times of the various basic vectors and the vector synthesis order.

[0014] According to another aspect of this disclosure, a fault-tolerant control device for an inverter is provided, comprising: a memory; and a processor coupled to the memory, the processor being configured to execute the fault-tolerant control method as described above based on instructions stored in the memory.

[0015] According to another aspect of this disclosure, a fault-tolerant circuit is provided, comprising: the fault-tolerant control device as described above.

[0016] In some embodiments, the fault-tolerant circuit further includes: an inverter, comprising a first bridge arm, a second bridge arm, and a third bridge arm, wherein the first bridge arm, the second bridge arm, and the third bridge arm are respectively connected in parallel between a first conductor and a second conductor of the DC bus; wherein the first bridge arm includes a first switching device, a first fuse, a second switching device, and a second fuse connected in series between the first conductor and the second conductor of the DC bus; the second bridge arm includes a third switching device, a third fuse, a fourth switching device, and a fourth fuse connected in series between the first conductor and the second conductor of the DC bus; the third bridge arm includes a fifth switching device, a fifth fuse, a sixth switching device, and a sixth fuse connected in series between the first conductor and the second conductor of the DC bus; wherein the fault-tolerant control device is electrically connected to the control terminals of the first switching device, the second switching device, the third switching device, the fourth switching device, the fifth switching device, and the sixth switching device, respectively.

[0017] In some embodiments, the fault-tolerant circuit further includes: a first capacitor and a second capacitor, wherein a first terminal of the first capacitor is electrically connected to a first conductor of the DC bus, a second terminal of the first capacitor is electrically connected to a first terminal of the second capacitor, and a second terminal of the second capacitor is electrically connected to a second conductor of the DC bus; a first bidirectional thyristor electrically connected between the output terminal of the first bridge arm and the second terminal of the first capacitor; a second bidirectional thyristor electrically connected between the output terminal of the second bridge arm and the second terminal of the first capacitor; and a third bidirectional thyristor electrically connected between the output terminal of the third bridge arm and the second terminal of the first capacitor; wherein the fault-tolerant control device is electrically connected to the control terminals of the first bidirectional thyristor, the second bidirectional thyristor, and the third bidirectional thyristor, respectively.

[0018] In some embodiments, the fault-tolerant circuit further includes: a voltage equalization circuit, electrically connected between the first conductor and the second conductor of the DC bus, for equalizing the voltage at the midpoint of the DC bus.

[0019] In some embodiments, the voltage equalization circuit includes: a first resistor, a first end of which is electrically connected to a first end of a first capacitor, and a second end of which is electrically connected to a second end of the first capacitor; a second resistor, a first end of which is electrically connected to a first end of the second capacitor, and a second end of which is electrically connected to a second end of the second capacitor; a seventh switching device, a first end of which is electrically connected to the first end of the first resistor; a third resistor, a first end of which is electrically connected to the second end of the seventh switching device, and a second end of which is electrically connected to the second end of the first resistor; an eighth switching device, a first end of which is electrically connected to the first end of the second resistor; and a fourth resistor, a first end of which is electrically connected to the second end of the eighth switching device, and a second end of which is electrically connected to the second end of the second resistor.

[0020] In some embodiments, the fault-tolerant circuit further includes: a potential equalization control circuit, configured to obtain a first voltage of the first capacitor and a second voltage of the second capacitor, and control the switching state of the seventh switching device and the switching state of the eighth switching device based on the first voltage and the second voltage, so as to achieve potential equalization at the midpoint of the DC bus, wherein the potential at the midpoint of the DC bus is the potential at the second end of the first capacitor.

[0021] In some embodiments, the potential equalization control circuit includes: a comparator for receiving a first voltage and a second voltage, comparing the first voltage and the second voltage, and outputting a comparison result; a trigger for receiving the comparison result and outputting a trigger signal when the comparison result exceeds a predetermined range; and a drive circuit for receiving the trigger signal, and based on the trigger signal, outputting a first drive signal to the seventh switching device and a second drive signal to the eighth switching device to control the switching state of the seventh switching device and the switching state of the eighth switching device.

[0022] In some embodiments, the driving circuit includes: a NOT gate circuit and a driving chip, wherein the output terminal of the flip-flop is directly connected to the first input terminal of the driving chip, and the output terminal of the flip-flop is connected to the second input terminal of the driving chip through the NOT gate circuit; the driving chip is used to output the first driving signal based on the trigger signal received at the first input terminal, and to output the second driving signal based on the inverted signal of the trigger signal received at the second input terminal.

[0023] In some embodiments, the capacitance of the first capacitor is equal to the capacitance of the second capacitor; the resistance of the first resistor is equal to the resistance of the second resistor; and the resistance of the third resistor is equal to the resistance of the fourth resistor.

[0024] According to another aspect of this disclosure, an electrical device is provided, comprising: a fault-tolerant circuit as described above.

[0025] According to another aspect of this disclosure, a computer-readable storage medium is provided having computer instructions stored thereon that, when executed by a processor, implement the fault-tolerant control method as described above.

[0026] According to another aspect of this disclosure, a computer program product is provided, comprising a computer program or instructions that, when executed by a processor, implement the fault-tolerant control method as described above.

[0027] In the aforementioned fault-tolerant control method, when a fault occurs in the third bridge arm, the third bridge arm is disconnected, and its output terminal is connected to the midpoint of the DC bus. After disconnecting the third bridge arm, the vector synthesis order of the reference voltage vector is determined based on the space vector sector where the reference voltage vector is located. This vector synthesis order refers to the implementation sequence of multiple basic vectors used to synthesize the reference voltage vector. The basic vectors are space vectors determined based on the switching states of the switching devices in the first and second bridge arms. Based on the reference voltage vector, multiple basic vectors, and a predetermined control cycle, the duration of each basic vector is determined. Finally, based on the duration of each basic vector and the vector synthesis order, control signals for controlling the first and second bridge arms are obtained and output. Thus, after a single-phase bridge arm fault occurs in the inverter, the faulty bridge arm is disconnected through topology reconfiguration, and combined with this fault-tolerant control method, the inverter continues to operate stably, improving the stability of inverter operation.

[0028] Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0029] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0030] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0031] Figure 1 This is a schematic diagram illustrating the circuit structure of a fault-tolerant circuit according to some embodiments of the present disclosure;

[0032] Figure 2 This is a circuit diagram illustrating the inverter cutting off a faulty bridge arm in a fault-tolerant circuit according to some embodiments of the present disclosure;

[0033] Figure 3 This is a flowchart illustrating a fault-tolerant control method for an inverter according to some embodiments of the present disclosure;

[0034] Figure 4 This is a fault-tolerant topology space vector diagram showing an inverter according to some embodiments of the present disclosure before a fault occurs in the C-phase bridge arm;

[0035] Figure 5 This is a fault-tolerant topology space vector diagram showing the C-phase bridge arm of an inverter according to some embodiments of the present disclosure after a failure;

[0036] Figure 6 This is a schematic diagram of the load corresponding to the space vector PPO after a fault occurs in the C-phase arm of an inverter according to some embodiments of the present disclosure;

[0037] Figure 7 This is a schematic diagram showing the direction and magnitude of the space vector PPO in the ABC coordinate system.

[0038] Figure 8 This is a schematic diagram showing the decomposition of the coordinate information of a spatial vector from the αβ axis to the KT axis;

[0039] Figure 9 This is a schematic diagram showing the decomposition of the reference voltage vector Vref on the KT axis;

[0040] Figure 10 This is a schematic block diagram illustrating a fault-tolerant control device for an inverter according to some embodiments of the present disclosure;

[0041] Figure 11 This is a schematic block diagram illustrating a fault-tolerant control device for an inverter according to other embodiments of the present disclosure;

[0042] Figure 12 This is a schematic block diagram illustrating a fault-tolerant control device for an inverter according to some embodiments of the present disclosure;

[0043] Figure 13 This is a schematic diagram illustrating a fault-tolerant control device for an inverter according to some embodiments of the present disclosure;

[0044] Figure 14 This is a schematic diagram illustrating the circuit structure of a fault-tolerant circuit according to other embodiments of the present disclosure;

[0045] Figure 15 This is a schematic diagram illustrating the circuit structure of a potential equalization control circuit according to some embodiments of the present disclosure. Detailed Implementation

[0046] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0047] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0048] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0049] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0050] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0051] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0052] Figure 1 This is a schematic diagram illustrating the circuit structure of a fault-tolerant circuit according to some embodiments of the present disclosure.

[0053] like Figure 1 As shown, the fault-tolerant circuit includes an inverter 10. The inverter 10 includes a first bridge arm 11, a second bridge arm 12, and a third bridge arm 13. The first bridge arm 11, second bridge arm 12, and third bridge arm 13 are connected in parallel between the first conductor 71 and the second conductor 72 of the DC bus 70. For example, the first bridge arm 11 is the A-phase bridge arm, the second bridge arm 12 is the B-phase bridge arm, and the third bridge arm 13 is the C-phase bridge arm. It should be noted that the first bridge arm 11, second bridge arm 12, and third bridge arm 13 do not necessarily have a one-to-one correspondence with the A-phase, B-phase, and C-phase bridge arms. For example, the first bridge arm 11 could also be the C-phase bridge arm, the second bridge arm 12 could be the A-phase bridge arm, and the third bridge arm 13 could be the B-phase bridge arm; or, for example, the first bridge arm 11 could be the C-phase bridge arm, the second bridge arm 12 could be the B-phase bridge arm, and the third bridge arm 13 could be the A-phase bridge arm, and so on. These are not exhaustive examples.

[0054] like Figure 1As shown, the first bridge arm 11 may include a first switching device S connected in series between the first conductor 71 and the second conductor 72 of the DC bus. a1 First fuse FU1, second switching device S a2 And the second fuse FU2. The second bridge arm 12 may include a third switching device S connected in series between the first conductor 71 and the second conductor 72 of the DC bus. b1 Third fuse FU3, fourth switching device S b2 and the fourth fuse FU4. The third bridge arm 13 may include a fifth switching device S connected in series between the first conductor 71 and the second conductor 72 of the DC bus. c1 Fifth fuse FU5, sixth switching device S c2 And the sixth fuse FU6.

[0055] like Figure 1 As shown, the fault-tolerant circuit may further include a first capacitor C1 and a second capacitor C2. The first terminal of the first capacitor C1 is electrically connected to the first conductor 71 of the DC bus, the second terminal of the first capacitor C1 is electrically connected to the first terminal of the second capacitor C2, and the second terminal of the second capacitor C2 is electrically connected to the second conductor 72 of the DC bus. The connection point between the first capacitor C1 and the second capacitor C2 (i.e., the second terminal of the first capacitor C1 or the first terminal of the second capacitor C2) serves as the midpoint O of the DC bus.

[0056] like Figure 1 As shown, the fault-tolerant circuit may further include a first bidirectional thyristor T1, a second bidirectional thyristor T2, and a third bidirectional thyristor T3. The first bidirectional thyristor T1 is electrically connected between the output terminal of the first bridge arm 11 (e.g., point A) and the second terminal of the first capacitor C1 (i.e., the midpoint of the DC bus). The second bidirectional thyristor T2 is electrically connected between the output terminal of the second bridge arm 12 (e.g., point B) and the second terminal of the first capacitor C1. The third bidirectional thyristor T3 is electrically connected between the output terminal of the third bridge arm 13 (e.g., point C) and the second terminal of the first capacitor C1.

[0057] like Figure 1 As shown, the fault-tolerant circuit may further include a voltage equalization circuit 20. The voltage equalization circuit 20 is electrically connected between the first conductor 71 and the second conductor 72 of the DC bus 70. The voltage equalization circuit 20 is used to equalize the voltage at the midpoint of the DC bus.

[0058] In some embodiments, such as Figure 1As shown, the voltage equalization circuit 20 may include a first resistor R1 and a second resistor R2. The first terminal of the first resistor R1 is electrically connected to the first terminal of the first capacitor C1, and the second terminal of the first resistor R1 is electrically connected to the second terminal of the first capacitor C1. That is, the first resistor R1 is connected in parallel with the first capacitor C1. The first terminal of the second resistor R2 is electrically connected to the first terminal of the second capacitor C2, and the second terminal of the second resistor R2 is electrically connected to the second terminal of the second capacitor C2. That is, the second resistor R2 is connected in parallel with the second capacitor C2.

[0059] like Figure 1 As shown, the voltage equalization circuit 20 may further include a seventh switching device S1, a third resistor R3, an eighth switching device S2, and a fourth resistor R4. The first terminal of the seventh switching device S1 is electrically connected to the first terminal of the first resistor R1. The first terminal of the third resistor R3 is electrically connected to the second terminal of the seventh switching device S1, and the second terminal of the third resistor R3 is electrically connected to the second terminal of the first resistor R1. That is, the seventh switching device S1 and the third resistor R3 are connected in series, and then in parallel with the first resistor R1. The first terminal of the eighth switching device S2 is electrically connected to the first terminal of the second resistor R2. The first terminal of the fourth resistor R4 is electrically connected to the second terminal of the eighth switching device S2, and the second terminal of the fourth resistor R4 is electrically connected to the second terminal of the second resistor R2. That is, the eighth switching device S2 and the fourth resistor R4 are connected in series, and then in parallel with the second resistor R2.

[0060] The foregoing has described fault-tolerant circuits according to some embodiments of the present disclosure. In conjunction with these fault-tolerant circuits, fault-tolerant control methods for inverters according to some embodiments of the present disclosure can be described.

[0061] Figure 3 This is a flowchart illustrating a fault-tolerant control method for an inverter according to some embodiments of the present disclosure. The inverter includes a first arm, a second arm, and a third arm. The fault-tolerant control method can be executed by a fault-tolerant control device. Figure 3 As shown, the fault-tolerant control method includes steps S302 to S308.

[0062] In step S302, if the third bridge arm fails, the third bridge arm is disconnected and its output terminal is connected to the midpoint of the DC bus.

[0063] In some embodiments, step S302 may include: controlling all switching devices on the third bridge arm to turn off; and controlling the bidirectional thyristor connected between the output terminal of the third bridge arm and the midpoint of the DC bus to turn on. Here, turning off all switching devices on the third bridge arm can effectively disconnect the third bridge arm, reducing the adverse effects of the faulty bridge arm. By controlling the bidirectional thyristor to turn on, the output terminal of the third bridge arm can be connected to the midpoint of the DC bus, which can maintain the current output of the faulty phase, for example, it can maintain motor drive control or grid-connected control.

[0064] For example, the following explanation can be based on the C-phase bridge arm as the third bridge arm.

[0065] like Figure 1 As shown, before the bridge arm fails, the bidirectional thyristors T1, T2 and T3 are not conducting, and the topology is a normal three-phase two-level inverter drive mode.

[0066] Fault-tolerant control devices (such as controllers) can receive the output current i from all three bridge arms. a i b and i c When the fault-tolerant control device detects current i a i b and i c If a certain current in the bridge exhibits an abnormal change, it can be determined that the bridge arm that outputs that current has malfunctioned.

[0067] For example, if a current abnormally increases, it may be due to a short-circuit fault in the arm that outputs that current. The fault-tolerant control device can output a control signal to the control terminal of the switching devices on the faulty arm, causing all switching devices on the faulty arm to turn off, thus disconnecting the faulty arm. Alternatively, in the event of a short-circuit fault on a single-phase arm of the inverter, the fast-acting fuse on the corresponding faulty phase will trip, effectively disconnecting the faulty arm and reducing the adverse effects of the short circuit on the circuit.

[0068] For example, if a current suddenly drops, such as to 0, it may be due to an open circuit fault in the bridge arm that outputs the current. The fault-tolerant control device can output a control signal to the control terminal of the switching device on the faulty bridge arm, so that all the switching devices on the faulty bridge arm are turned off, thus cutting off the faulty bridge arm.

[0069] In the event of a fault in the third bridge arm, in addition to disconnecting the faulty bridge arm, the bidirectional thyristor T of the faulty phase can also be turned on. x Where x is 1, 2 or 3, the inverter fault phase output is directly connected to the midpoint of the DC bus, for example, directly connected to the second terminal (e.g., negative terminal) of the first capacitor C1 and the first terminal (e.g., positive terminal) of the second capacitor C2 of the DC bus, to complete the fault-tolerant topology reconfiguration.

[0070] Because of the three-phase symmetry, we analyze the fault in phase C. When phase C fails, the corresponding bidirectional thyristor T3 conducts, and the fifth fuse FU5 and the sixth fuse FU6 on phase C disconnect. The reconstructed topology after the fault is as follows: Figure 2 As shown. From Figure 2 It can be seen that after topology reconfiguration, the faulty phase output draws power directly from the DC bus midpoint O. At this time, the current i at point C... c The current i equal to the midpoint O of the DC bus O .

[0071] In addition, in some embodiments, the voltage equalization circuit 20 in the front stage of the inverter can be activated to equalize the potential at the midpoint O of the DC bus, thereby improving the frequency conversion control accuracy.

[0072] In step S304, after cutting out the third bridge arm, the vector synthesis order of the reference voltage vector is determined based on the spatial vector sector where the reference voltage vector is located. The vector synthesis order is the implementation order of multiple basic vectors used to synthesize the reference voltage vector. The basic vectors are spatial vectors determined based on the switching states of the switching devices of the first bridge arm and the switching states of the switching devices of the second bridge arm.

[0073] Here, the reference voltage vector is the reference voltage vector calculated by the controller. Inverters are usually used in grid-connected, motor control and other scenarios, which involve current closed-loop control. The output of the PI (Proportional Integral) controller in the current closed-loop control is the reference voltage vector Vref. Therefore, the reference voltage vector is the voltage value that the inverter needs to output to meet the application requirements.

[0074] To maintain the inverter's drive function after topology reconfiguration, a space vector pulse width modulation algorithm can be designed for the inverter after a fault. First, the changes in space vector distribution before and after the fault are analyzed, and the switching sequence of space vector modulation is redefined:

[0075] Define the switching function of the inverter as follows:

[0076] (1)

[0077] As can be seen from equation (1), before the fault, the three-phase two-level inverter can output 8 switching states, corresponding to 8 space voltage vectors, such as Figure 4 As shown, PNN, PPN, NPN, NPP, NNP, PNP, PPP, and NNN (where PPP and NNN are zero vectors, representing the origin of the ABC three-phase space vector coordinate system). These eight space voltage vectors are distributed across six sectors, I to VI.

[0078] In a four-switch three-phase inverter following a single-phase fault, for example, if the C-phase bridge arm (as the third bridge arm) fails, its output side, connected to the midpoint of the DC bus, can only output V. dc / 2 (here, V) dc (This refers to the DC bus voltage). Setting this output state to 0 reduces the number of normal switching states to four: PPO, NNO, PNO, and NPO. By observing the topology vector diagram of the four-switch three-phase inverter after a C-phase bridge arm fault (e.g., ...), Figure 5 As shown in the figure, the reconstructed topological spatial vector diagram has two spatial vector sectors, namely sector I and sector II, as shown in the figure. Figure 5 As shown, its overall spatial vector distribution satisfies the reference voltage vector synthesis condition.

[0079] In some embodiments, the fault-tolerant control method described above may further include: determining the space vector sector in which the reference voltage vector resides before determining the vector synthesis order of the reference voltage vector. That is, determining which space vector sector the reference voltage vector is located in. Figure 5 As shown, the space vector sector includes a first space vector sector I and a second space vector sector II. The first space vector sector I and the second space vector sector II are each determined by a corresponding set of basic vectors, and the first space vector sector is different from the second space vector sector. For example, the first space vector sector I is determined by a corresponding set of basic vectors PPO, NPO, and NNO, and the second space vector sector is determined by a corresponding set of basic vectors PPO, PNO, and NNO. In this embodiment, by determining the space vector sector where the reference voltage vector is located, it is convenient to determine the corresponding vector synthesis order based on which space vector sector the reference voltage vector is in, and then execute the corresponding fault-tolerant control, so that the output current after the inverter fault is as consistent as possible with the output current before the fault, thereby improving the stability of the inverter operation.

[0080] In some embodiments, determining the spatial vector sector in which the reference voltage vector resides includes: decomposing the reference voltage vector in the αβ-axis coordinate system to obtain a first decomposed vector on the α-axis and a second decomposed vector on the β-axis; and based on the first and second decomposed vectors, determining which spatial vector sector, either the first or second spatial vector sector, the reference voltage vector resides in. Here, the αβ-axis coordinate system is a coordinate system known to those skilled in the art. For example, the α-axis coincides with the axis of the A-phase winding in the ABC coordinate system, the β-axis is perpendicular (or orthogonal) to the α-axis, and satisfies the "right-hand rule" (if the α-axis is horizontal to the right, the β-axis is vertically upward), and the origin of the coordinate system may coincide with the geometric center of the motor stator or the neutral point of the three-phase winding.

[0081] In the above embodiments, by decomposing the reference voltage vector in the αβ axis coordinate system, it is possible to conveniently determine which spatial vector sector the reference voltage vector is located in based on the decomposed vector.

[0082] For example, when the reference voltage vector Vref is located in sector I, it is synthesized from space vectors NNO, NPO, and PPO. When the reference voltage vector Vref is located in sector II, it is synthesized from space vectors NNO, PNO, and PPO. Therefore, by decomposing the reference voltage vector in the αβ axis coordinate system, the sector location of the reference voltage vector Vref can be obtained through calculation.

[0083] , (2)

[0084] in, It is the component of the reference voltage vector Vref on the α axis. is the component of the reference voltage vector Vref on the β axis, and M is the position of the reference voltage vector Vref in the spatial vector distribution diagram.

[0085] Here, the reference voltage vector Vref is decomposed in the αβ axis coordinate system, as follows: Figure 5 As shown, based on geometric relationships, the sector determination formula (3) can be listed as follows:

[0086] (3)

[0087] Formula (2) can be derived from formula (3).

[0088] According to formula (2), the spatial vector sector in which the reference voltage vector is located can be determined. For example, if the component of the reference voltage vector Vref on the α axis... and components on the β axis Meet the conditions Then the reference voltage vector is determined to be located in the second space vector sector II; if the components of the reference voltage vector Vref on the α axis and components on the β axis Meet the conditions If the reference voltage vector is located in sector I of the first spatial vector, then the sector location of the reference voltage vector Vref can be determined based on formula (2).

[0089] In some embodiments, the vector synthesis order includes a first vector synthesis order and a second vector synthesis order, wherein the first vector synthesis order and the second vector synthesis order are different. Step S304 may include: determining the vector synthesis order of the reference voltage vector as the first vector synthesis order when the reference voltage vector is located in a first spatial vector sector; and determining the vector synthesis order of the reference voltage vector as the second vector synthesis order when the reference voltage vector is located in a second spatial vector sector. In this embodiment, different vector synthesis orders of the reference voltage vector are determined based on the different spatial vector sectors in which the reference voltage vector is located. Thus, a suitable vector synthesis order can accurately synthesize the reference voltage vector, thereby ensuring that the current output after an inverter fault is as consistent as possible with the current output before the fault, thereby improving the stability of inverter operation.

[0090] Comparing the spatial vector diagrams before and after the inverter fault reveals significant changes in both length and direction. Therefore, the reference voltage synthesis rules need to be redesigned. For example, the sequence of reference voltage vector synthesis is shown in Table 1.

[0091] Table 1. Reference Voltage Vector Synthesis Order

[0092]

[0093] Where M represents a sector in the basic voltage vector diagram.

[0094] The above process determines the synthesis order of the reference voltage for the four-switch three-phase inverter topology after a failure of the third arm (e.g., the C-phase arm).

[0095] Taking the reference voltage vector located in the first spatial vector sector I as an example, Table 1 shows that the vector synthesis order is: NNO, NPO, PPO, NPO and NNO, that is, the reference voltage vector is synthesized in the order of NNO, NPO, PPO, NPO and NNO.

[0096] In step S306, the action time of each of the multiple basic vectors is determined based on the reference voltage vector, multiple basic vectors and a predetermined control period.

[0097] Taking the third bridge arm as the C-phase bridge arm as an example, by analyzing the operation mode of the four-switch three-phase inverter after a C-phase bridge arm fault, the inverter output voltage can be obtained as follows:

[0098] , (4)

[0099] Among them, u ao u bo u co These are the A, B, and C phase output voltages of the inverter, respectively. This refers to the bus voltage of the DC bus connected to the inverter.

[0100] Define n as the three-phase neutral point. For example, if the load is a motor, then n is the neutral point of the motor stator winding, and u an The voltage u is the voltage between the output terminal of phase A of the inverter and the center point n of the stator winding. bn The voltage u is the voltage between the output terminal of phase B of the inverter and the center point n of the stator winding. cn This refers to the voltage between the C-phase output terminal of the inverter and the center point n of the stator winding. For example, if the load is a power grid, then n is the neutral point n of a three-phase four-wire power grid, and u... an The voltage u is the voltage between the output terminal of phase A of the inverter and the neutral point n of the power grid. bn The voltage u is the voltage between the output terminal of phase B of the inverter and the neutral point n of the power grid. cn This is the voltage between the C-phase output terminal of the inverter and the neutral point n of the power grid.

[0101] When the switch state is PNO(u1), the first switching device S of phase A bridge arm a1 The second switching device S of phase A bridge arm is turned on. a2 The third switching device S of the B-phase bridge arm is turned off. b1 The fourth switching device S of the B-phase bridge arm is turned off. b2 If it is conducting, then

[0102] ,

[0103] ,

[0104] .

[0105] Conversely, when the switching state is NPO(u3), that is, when the switching state is NPO(u3), the first switching device S of phase A bridge arm... a1 The second switching device S of phase A bridge arm is turned off. a2 The third switching device S of phase B bridge arm is conducting. b1 The fourth switching device S of the B-phase bridge arm is conducting. b2 Turn off, then

[0106] ,

[0107] ,

[0108] .

[0109] When the switching state is PPO(u2), the first switching device S of phase A bridge arm a1 The second switching device S of phase A bridge arm is turned on. a2The third switching device S of the B-phase bridge arm is turned off. b1 The fourth switching device S of the B-phase bridge arm is conducting. b2 Turn off, see reference Figure 6 The load diagram corresponding to the space vector PPO shown is illustrated (it can be assumed that the load of phase a = the load of phase b = the load of phase c).

[0110] ,

[0111] ,

[0112] .

[0113] Conversely, when the switching state is NNO(u4), the first switching device S of phase A bridge arm... a1 The second switching device S of phase A bridge arm is turned off. a2 The third switching device S of phase B bridge arm is conducting. b1 The fourth switching device S of the B-phase bridge arm is turned off. b2 If it is conducting, then

[0114] ,

[0115] ,

[0116] .

[0117] In summary, the amplitudes of PNO(u1), PPO(u2), NPO(u3), and NNO(u4) are:

[0118] , (5)

[0119] The spatial vector angles of PNO(u1), PPO(u2), NPO(u3), and NNO(u4) are (with the αβ axis coordinate system as the reference coordinate system):

[0120] (6)

[0121] Here, we can take the spatial vector PPO as an example for explanation, such as... Figure 7 As shown, Figure 7 The diagram shows the ABC spatial coordinate system, combined with the aforementioned voltage division of phases A and B as follows: C-phase load voltage division , will u an u bn u cn By performing vector synthesis, the direction and magnitude of vector PPO can be obtained.

[0122] Therefore, in the embodiments of this disclosure, the basic vectors determined by the switching states of the switching devices of the first bridge arm and the second bridge arm include a first basic vector, a second basic vector, a third basic vector, and a fourth basic vector (i.e., there are four basic vectors in total). For example, the first basic vector is vector PNO, the second basic vector is vector PPO, the third basic vector is vector NPO, and the fourth basic vector is vector NNO. The first basic vector and the third basic vector have equal magnitudes and opposite directions, the second basic vector and the fourth basic vector have equal magnitudes and opposite directions, and the first basic vector is perpendicular to the second basic vector. By determining these four basic vectors, a reference voltage vector can be easily and accurately synthesized, thereby ensuring that the current output after an inverter fault is as consistent as possible with the current output before the fault, thus improving the stability of inverter operation.

[0123] As mentioned above, the magnitudes of the first and third fundamental vectors are respectively The magnitudes of the second and fourth fundamental vectors are respectively ,in, This represents the bus voltage of the DC bus connected to the inverter. In the αβ-axis coordinate system, the spatial vector angle of the first fundamental vector is... The spatial vector angle of the second fundamental vector is The spatial vector angle of the third fundamental vector is The spatial vector angle of the fourth fundamental vector is This yields four accurate basic vectors, allowing for convenient and accurate synthesis of the reference voltage vector.

[0124] In some embodiments, determining the action time of each of the multiple basic vectors based on a reference voltage vector, multiple basic vectors, and a predetermined control cycle includes: constructing a spatial rectangular coordinate system with the line containing the first basic vector as the first coordinate axis and the line containing the second basic vector as the second coordinate axis; decomposing the reference voltage vector and the multiple basic vectors on the first and second coordinate axes respectively to obtain multiple decomposed vectors corresponding to the reference voltage vector and the multiple basic vectors respectively; and calculating the action time of each of the multiple basic vectors based on the multiple decomposed vectors and the control cycle, using the volt-second balance equation. In this embodiment, by constructing a new spatial rectangular coordinate system (which can be called a KT coordinate system) based on the lines containing two mutually perpendicular basic vectors, it is convenient to perform calculations after decomposing the reference voltage vector and the multiple basic vectors on the coordinate axes of this coordinate system, thereby obtaining the action time of each basic vector. This facilitates the acquisition of corresponding control signals for controlling the first and second bridge arms, ensuring that the output current after an inverter fault is as consistent as possible with the output current before the fault, thereby improving the stability of inverter operation.

[0125] For example, such as Figure 5 As shown, a spatial rectangular coordinate system, namely the KT coordinate system, is constructed using the line containing the first basic vector PNO as the first coordinate axis and the line containing the second basic vector PPO as the second coordinate axis. For example, in this coordinate system, the direction of the first coordinate axis (T-axis) is opposite to the direction of the first basic vector PNO, and the direction of the second coordinate axis (K-axis) is consistent with the direction of the second basic vector PPO. Of course, those skilled in the art will understand that the directions of the first coordinate axis (T-axis) and the second coordinate axis (K-axis) are not limited to this example and can be other directions, such as the first coordinate axis (T-axis) being consistent with the direction of the first basic vector PNO, the second coordinate axis (K-axis) being consistent with the direction of the second basic vector PPO, and so on. Therefore, the scope of this disclosure is not limited to this.

[0126] To reduce computational load, the coordinate information of the basic vectors PNO(u1), PPO(u2), NPO(u3), NNO(u4) and the reference voltage vector Vref can be decomposed from the αβ axis onto the KT axis.

[0127] For example, such as Figure 8 As shown, a spatial vector V can be decomposed into the K-axis and T-axis, through methods such as... Figure 8 The geometric relationship shown indicates that the vector V is decomposed into components U on the K-axis. K and the component U decomposed onto the T-axis T for:

[0128] , (7)

[0129] in, Let V be the component of a spatial vector V along the α-axis. Let V be the component of a certain space vector V on the β axis.

[0130] In this way, the reference voltage vector and multiple basic vectors can be decomposed on the first and second coordinate axes respectively to obtain multiple decomposed vectors corresponding to the reference voltage vector and multiple basic vectors respectively.

[0131] Next, based on the obtained multiple decomposed vectors and the predetermined control period, and using the volt-second balance equation, the action time of each of the multiple basic vectors is calculated.

[0132] For example, let's take the case where the reference voltage vector Vref is located in the first space vector sector I as an example. Figure 9 As shown, by decomposing the reference voltage vector Vref along the K-axis and T-axis, the components of Vref along the K-axis can be obtained. UKref and the components of Vref on the T-axis U Tref Then, according to the volt-second balance equation, V S ×T S =V1×T1+V2×T2+V3×T3 (The fundamental principle of volt-second balance is the principle of area equivalence, where T...) S Voltage V S The durations of action are T1 (where T1 is the duration of action of voltage V1), T2 (where T2 is the duration of action of voltage V2), and T3 (where T3 is the duration of action of voltage V3). Therefore, by decomposing the basic vectors NPO, PPO, and NNO on the K-axis and T-axis, we can obtain the components of the basic vector NPO on the K-axis. U KNPO 、 Components of the basic vector PPO on the K-axis U KPPO 、 Components of the basic vector NNO on the K-axis U KNNO 、 Components of the basic vector NPO on the T-axis U TNPO 、 Components of the basic vector PPO on the T-axis U TPPO 、 Components of the basic vector NNO on the T-axis U TNNO For example, the components of the basic vector PPO on the K-axis are: V dc / 2. The component on the T-axis is 0, therefore U KPPO =V dc / 2 , U TPPO =0 The same principle applies to other vectors. Then, write the volt-second balance principle on the K-axis and T-axis respectively:

[0133] U Kref ×T S =U KNPO ×T NPO +U KPPO ×T PPO +U KNNO ×T NNO ,

[0134] U Tref ×T S =U TNPO ×T NPO +U TPPO ×TPPO +U TNNO ×T NNO ,

[0135] Moreover, there is T S =T NPO +T PPO +T NNO Here, T S For the predetermined control period, T NPO T is the duration of action of the basic vector NPO(u3). NNO T is the duration of action of the fundamental vector NNO(u4). PPO The duration of action of the basic vector PPO(u2).

[0136] Therefore, time T can be calculated. NPO T NNO T PPO ,as follows:

[0137] ,

[0138] ,

[0139] .

[0140] Similarly, when the reference voltage vector Vref is located in the second space vector sector II, the duration T of the fundamental vector PNO(u1) is calculated. PNO The duration T of the basic vector NNO(u4) NNO The duration T of the basic vector PPO(u2) PPO They are as follows:

[0141] ,

[0142] ,

[0143] .

[0144] In this way, the duration of action of each basic vector used to synthesize the reference voltage vector was calculated.

[0145] In summary, the synthesis rule for the reference voltage vector after inverter fault reconfiguration can be obtained.

[0146] In step S308, based on the action time of each basic vector and the order of vector synthesis, control signals for controlling the first bridge arm and the second bridge arm are obtained and output.

[0147] Here, the control signals used to control the first bridge arm and the second bridge arm are the same control signals used to control the switching states of all switching devices in the first bridge arm and the second bridge arm. In other words, they are the topology space vector pulse width modulation (SVPWM) signals after a bridge arm failure.

[0148] Since each basic vector reflects the switching state (i.e., on or off) of each switching device in the first and second bridge arms, the control signal for controlling the first and second bridge arms, i.e., the SVPWM signal, can be obtained based on the action time and vector synthesis order of each basic vector. In other words, after obtaining the synthesis rules of the reference voltage vector after inverter fault reconfiguration, the fault-tolerant space vector pulse width modulation algorithm for the reconfigured topology can be completed according to the vector synthesis order shown in Table 1.

[0149] For example, taking the reference voltage vector Vref in sector I as an example, according to Table 1, the vector synthesis order of the reference voltage vector is: NNO, NPO, PPO, NPO, NNO.

[0150] In some cases, the reference voltage vector Vref is synthesized using the above sequence, and a five-segment output is used. This is achieved by controlling the switching device to activate the lower bridge of phase A (i.e., the second switching device S). a2 (Conduction), the lower bridge of phase B is turned on (i.e., the fourth switching device S) b2 (Conduction), and the corresponding control signal for other vectors (similarly), causes NNO to act first on T. NNO / 2 time, then NPO acts on T NPO / 2 time, then PPO acts on T PPO The time, then the NPO acts on T. NPO / 2 time, and then NNO acts again T NNO In half the time, one control cycle T is completed. S Synthesis of Vref.

[0151] Therefore, in some embodiments, the vector synthesis sequence can adopt a symmetrical vector sequence. For example, in Table 1, when the reference voltage vector Vref is in sector I, the vector sequence on both sides of PPO is symmetrical with PPO as the center. Similarly, when the reference voltage vector Vref is in sector II, the vector sequence on both sides of PPO is also symmetrical with PPO as the center. Moreover, as described in the examples above, for this symmetrical vector sequence, the basic vector at the center of the vector synthesis sequence uses the required action time, while the basic vectors on both sides of the center can each use half the required action time. This results in smaller voltage fluctuations in the final synthesized reference voltage vector, improving the stability of inverter operation.

[0152] This provides a fault-tolerant control method for an inverter according to some embodiments of the present disclosure. The inverter includes a first bridge arm, a second bridge arm, and a third bridge arm. The fault-tolerant control method includes: disconnecting the third bridge arm in the event of a fault, and connecting the output terminal of the third bridge arm to the midpoint of the DC bus; after disconnecting the third bridge arm, determining the vector synthesis order of the reference voltage vector based on the space vector sector where the reference voltage vector is located, wherein the vector synthesis order is the implementation order of multiple basic vectors used to synthesize the reference voltage vector, and the basic vectors are space vectors determined based on the switching states of the switching devices of the first bridge arm and the second bridge arm; determining the action time of each of the multiple basic vectors based on the reference voltage vector, the multiple basic vectors, and a predetermined control cycle; and obtaining and outputting control signals for controlling the first and second bridge arms based on the action time of each basic vector and the vector synthesis order. In this embodiment, after a single-phase bridge arm fault occurs in the inverter, the faulty bridge arm is disconnected through topology reconstruction, and combined with this fault-tolerant control method, the inverter continues to operate stably, improving the stability of inverter operation. Correspondingly, motor drive control or grid-connected control can also be maintained.

[0153] Figure 10 This is a schematic block diagram illustrating a fault-tolerant control device for an inverter according to some embodiments of the present disclosure. For example, the fault-tolerant control device is a controller (e.g., a microprocessor). The inverter includes a first arm, a second arm, and a third arm.

[0154] like Figure 10 As shown, the fault-tolerant control device includes a fault processing unit 41, a first determination unit 42, a second determination unit 43, and an output unit 44.

[0155] The fault handling unit 41 is used to disconnect the third bridge arm and connect the output terminal of the third bridge arm to the midpoint of the DC bus in the event of a fault in the third bridge arm.

[0156] The first determining unit 42 is used to determine the vector synthesis order of the reference voltage vector based on the spatial vector sector where the reference voltage vector is located after the third bridge arm is cut off. The vector synthesis order is the implementation order of multiple basic vectors used to synthesize the reference voltage vector. The basic vectors are spatial vectors determined based on the switching state of the switching device of the first bridge arm and the switching state of the switching device of the second bridge arm.

[0157] The second determining unit 43 is used to determine the action time of each of the multiple basic vectors based on the reference voltage vector, multiple basic vectors and a predetermined control cycle.

[0158] The output unit 44 is used to obtain and output control signals for controlling the first bridge arm and the second bridge arm based on the action time of each basic vector and the order of vector synthesis.

[0159] Thus, a fault-tolerant control device for an inverter according to some embodiments of the present disclosure is provided. In this fault-tolerant control device, when a fault occurs in the third bridge arm, the fault handling unit disconnects the third bridge arm and connects its output terminal to the midpoint of the DC bus; after disconnecting the third bridge arm, the first determining unit determines the vector synthesis order of the reference voltage vector based on the space vector sector where the reference voltage vector is located; the second determining unit determines the action time of each of the multiple basic vectors based on the reference voltage vector, multiple basic vectors, and a predetermined control cycle; the output unit obtains and outputs control signals for controlling the first and second bridge arms based on the action time of each basic vector and the vector synthesis order. In this way, after a single-phase bridge arm fault occurs in the inverter, the faulty bridge arm is disconnected through topology reconstruction, and the inverter can continue to operate stably, improving the stability of inverter operation.

[0160] In some embodiments, the first determining unit 42 may also be used to determine the space vector sector where the reference voltage vector is located before determining the vector synthesis order of the reference voltage vector, wherein the space vector sector includes a first space vector sector and a second space vector sector, the first space vector sector and the second space vector sector are respectively determined by a certain number of basic vectors, and the first space vector sector is different from the second space vector sector.

[0161] In some embodiments, the first determining unit 42 is used to decompose the reference voltage vector in the αβ axis coordinate system to obtain a first decomposed vector on the α axis and a second decomposed vector on the β axis, and based on the first decomposed vector and the second decomposed vector, determine which spatial vector sector the reference voltage vector is located in the first spatial vector sector and the second spatial vector sector.

[0162] In some embodiments, the vector synthesis order includes a first vector synthesis order and a second vector synthesis order, wherein the first vector synthesis order and the second vector synthesis order are different. The first determining unit 42 can be used to determine the vector synthesis order of the reference voltage vector as the first vector synthesis order when the reference voltage vector is located in a first spatial vector sector, and to determine the vector synthesis order of the reference voltage vector as the second vector synthesis order when the reference voltage vector is located in a second spatial vector sector.

[0163] In some embodiments, the basic vector determined by the switching state of the switching device of the first bridge arm and the switching state of the switching device of the second bridge arm includes a first basic vector, a second basic vector, a third basic vector, and a fourth basic vector, wherein the first basic vector and the third basic vector are equal in magnitude and opposite in direction, the second basic vector and the fourth basic vector are equal in magnitude and opposite in direction, and the first basic vector is perpendicular to the second basic vector.

[0164] In some embodiments, the magnitudes of the first fundamental vector and the third fundamental vector are respectively... The magnitudes of the second and fourth fundamental vectors are respectively ,in, The bus voltage of the DC bus connected to the inverter; in the αβ axis coordinate system, the spatial vector angle of the first fundamental vector is... The spatial vector angle of the second fundamental vector is The spatial vector angle of the third fundamental vector is The spatial vector angle of the fourth fundamental vector is .

[0165] In some embodiments, the second determining unit 43 may be used to: construct a spatial rectangular coordinate system with the straight line where the first basic vector is located as the first coordinate axis and the straight line where the second basic vector is located as the second coordinate axis; decompose the reference voltage vector and the multiple basic vectors on the first coordinate axis and the second coordinate axis respectively to obtain multiple decomposed vectors corresponding to the reference voltage vector and the multiple basic vectors respectively; and calculate the action time of each basic vector among the multiple basic vectors based on the multiple decomposed vectors and the control period, and using the volt-second balance equation.

[0166] In some embodiments, the vector composition order adopts a symmetrical vector order; the basic vector at the center of the vector composition order uses the required action time, and the basic vectors on both sides of the center of the vector composition order each use half of the required action time.

[0167] In some embodiments, the fault handling unit 41 is used to control all switching devices on the third bridge arm to turn off, and to control the bidirectional thyristor connected between the output terminal of the third bridge arm and the midpoint of the DC bus to turn on.

[0168] Figure 11 This is a schematic block diagram illustrating a fault-tolerant control device for an inverter according to other embodiments of the present disclosure. The fault-tolerant control device includes a memory 510 and a processor 520. Wherein:

[0169] The memory 510 can be a disk, flash memory, or any other non-volatile storage medium. The memory is used for storage. Figure 3 The instructions in the corresponding embodiment.

[0170] The processor 520 is coupled to the memory 510 and can be implemented as one or more integrated circuits, such as a microprocessor or microcontroller. The processor 520 is used to execute instructions stored in the memory, and after a single-phase bridge arm fault occurs in the inverter, it switches off the faulty bridge arm through topology reconfiguration, enabling the inverter to continue to operate stably and improving the stability of inverter operation.

[0171] In some embodiments, it may also be as follows Figure 12 As shown, the fault-tolerant control device 30 includes a memory 510 and a processor 520. The processor 520 is coupled to the memory 510 via a BUS bus 530. The fault-tolerant control device 30 can also be connected to an external storage device 550 via a storage interface 540 to access external data, and can also be connected to a network or another computer system (not shown) via a network interface 560, which will not be described in detail here.

[0172] In this embodiment, data instructions are stored in the memory and then processed by the processor. After a single-phase bridge arm fault occurs in the inverter, the faulty bridge arm is disconnected through topology reconstruction, and the inverter can continue to operate stably, thus improving the stability of inverter operation.

[0173] Figure 13 This is a schematic diagram illustrating a fault-tolerant control device for an inverter according to some embodiments of the present disclosure.

[0174] like Figure 13 As shown, the fault-tolerant control device 30 can be used to receive the three-phase current i from the inverter. a i b and i c In the three-phase current i a i b and i c If any current in the bridge changes abnormally, it can be determined that the arm that outputs that current has failed.

[0175] The fault-tolerant control device 30 can also be used to output multiple control signals for controlling the bridge arm (e.g., control signal S). Sa1 S Sa2 S Sb1 S Sb2 S Sc1 and S Sc2 At least some of the control signals are sent to the multiple switching devices of the corresponding multiple bridge arms to control the on and off of the multiple switching devices respectively.

[0176] The fault-tolerant control device 30 can also be used to output multiple control signals for controlling the bidirectional thyristor (e.g., control signal S). T1 S T2 and S T3 ( ) to the corresponding multiple bidirectional thyristors, so as to control the conduction and turn-off of the multiple bidirectional thyristors respectively.

[0177] In some embodiments of this disclosure, a fault-tolerant circuit is also provided, which includes the fault-tolerant control device as described above, for example, such as... Figure 13 The fault-tolerant control device shown is as follows. Figure 13 The fault-tolerant control device shown can be adopted as follows: Figure 10 , Figure 11 or Figure 12 The fault-tolerant control device shown.

[0178] Figure 14 This is a schematic diagram illustrating the circuit structure of a fault-tolerant circuit according to other embodiments of the present disclosure.

[0179] For example, such as Figure 14 As shown, the fault-tolerant circuit includes an inverter 10. The inverter 10 includes a first bridge arm 11, a second bridge arm 12, and a third bridge arm 13. The first bridge arm 11, second bridge arm 12, and third bridge arm 13 are connected in parallel between the first conductor 71 and the second conductor 72 of the DC bus 70. For example, the first bridge arm 11 is the A-phase bridge arm, the second bridge arm 12 is the B-phase bridge arm, and the third bridge arm 13 is the C-phase bridge arm. It should be noted that the first bridge arm 11, second bridge arm 12, and third bridge arm 13 do not necessarily have a one-to-one correspondence with the A-phase, B-phase, and C-phase bridge arms. For example, the first bridge arm 11 could also be the C-phase bridge arm, the second bridge arm 12 could be the A-phase bridge arm, and the third bridge arm 13 could be the B-phase bridge arm; or, for example, the first bridge arm 11 could be the C-phase bridge arm, the second bridge arm 12 could be the B-phase bridge arm, and the third bridge arm 13 could be the A-phase bridge arm, and so on. These are not exhaustive examples.

[0180] like Figure 14 As shown, the first bridge arm 11 may include a first switching device S connected in series between the first conductor 71 and the second conductor 72 of the DC bus. a1First fuse FU1, second switching device S a2 And a second fuse FU2. For example, the first terminal of the first fuse FU1 is electrically connected to the first conductor 71 (e.g., node 71P of the first conductor 71), and the second terminal of the first fuse FU1 is electrically connected to the first switching device S. a1 The first terminal, the first switching device S a1 The second terminal is electrically connected to the second switching device S. a2 The first terminal, the second switching device S a2 The second end is electrically connected to the first end of the second fuse FU2, and the second end of the second fuse FU2 is electrically connected to the second conductor 72 (e.g., the 72N node of the second conductor 72).

[0181] The second bridge arm 12 may include a third switching device S connected in series between the first conductor 71 and the second conductor 72 of the DC bus. b1 Third fuse FU3, fourth switching device S b2 and the fourth fuse FU4. For example, the first terminal of the third fuse FU3 is electrically connected to the first conductor 71 (e.g., node 71P of the first conductor 71), and the second terminal of the third fuse FU3 is electrically connected to the third switching device S. b1 The first terminal, the third switching device S b1 The second terminal is electrically connected to the fourth switching device S. b2 The first terminal, the fourth switching device S b2 The second end is electrically connected to the first end of the fourth fuse FU4, and the second end of the fourth fuse FU4 is electrically connected to the second conductor 72 (e.g., the 72N node of the second conductor 72).

[0182] The third bridge arm 13 may include a fifth switching device S connected in series between the first conductor 71 and the second conductor 72 of the DC bus. c1 Fifth fuse FU5, sixth switching device S c2 And the sixth fuse FU6. For example, the first terminal of the fifth fuse FU5 is electrically connected to the first conductor 71 (e.g., node 71P of the first conductor 71), and the second terminal of the fifth fuse FU5 is electrically connected to the fifth switching device S. c1 The first terminal, the fifth switching device S c1 The second terminal is electrically connected to the sixth switching device S. c2 The first terminal, the sixth switching device S c2 The second end is electrically connected to the first end of the sixth fuse FU6, and the second end of the sixth fuse FU6 is electrically connected to the second conductor 72 (e.g., the 72N node of the second conductor 72).

[0183] Fault-tolerant control device ( Figure 14(Not shown in the image) are electrically connected to the first switching device S respectively. a1 Control terminal, second switching device S a2 Control terminal, third switching device S b1 Control terminal, fourth switching device S b2 Control terminal, fifth switching device S c1 Control terminal and sixth switching device S c2 The control terminal. In this way, the fault-tolerant control device can output multiple control signals to the multiple switching devices of the corresponding multiple bridge arms, so as to control the conduction and cutoff of the multiple switching devices respectively.

[0184] In this way, after the fault-tolerant control device determines that a certain bridge arm of the inverter is faulty, it can control the shutdown of all the switching devices of that bridge arm, thereby cutting off the faulty bridge arm. In addition, combined with the fault-tolerant control method described above (such as through SVPWM), it controls the conduction and shutdown of the switching devices of other bridge arms that are not faulty, so that the inverter continues to operate stably and improves the stability of inverter operation.

[0185] In some embodiments, the first fuse FU1, the second fuse FU2, the third fuse FU3, the fourth fuse FU4, the fifth fuse FU5, and the sixth fuse FU6 are fast-acting fuses.

[0186] like Figure 14 As shown, the fault-tolerant circuit may further include a first capacitor C1 and a second capacitor C2. The first terminal of the first capacitor C1 is electrically connected to the first conductor 71 of the DC bus, the second terminal of the first capacitor C1 is electrically connected to the first terminal of the second capacitor C2, and the second terminal of the second capacitor C2 is electrically connected to the second conductor 72 of the DC bus. The connection point between the first capacitor C1 and the second capacitor C2 (i.e., the second terminal of the first capacitor C1 or the first terminal of the second capacitor C2) serves as the midpoint O of the DC bus.

[0187] In some embodiments, the capacitance of the first capacitor C1 is equal to the capacitance of the second capacitor C2. This helps to balance the potential at the midpoint of the DC bus as much as possible.

[0188] For example, the capacitance values ​​of the first capacitor C1 and the second capacitor C2 can be 680 μF (microfarads). Of course, those skilled in the art will understand that the scope of this disclosure is not limited to the specific capacitance values ​​of the first capacitor C1 and the second capacitor C2, and the capacitance values ​​of the first capacitor C1 and the second capacitor C2 can be set according to actual needs or actual circumstances.

[0189] like Figure 14As shown, the fault-tolerant circuit may further include a first bidirectional thyristor T1, a second bidirectional thyristor T2, and a third bidirectional thyristor T3. The first bidirectional thyristor T1 is electrically connected between the output terminal of the first bridge arm 11 (e.g., point A) and the second terminal of the first capacitor C1 (i.e., the midpoint O of the DC bus). The second bidirectional thyristor T2 is electrically connected between the output terminal of the second bridge arm 12 (e.g., point B) and the second terminal of the first capacitor C1 (i.e., the midpoint O of the DC bus). The third bidirectional thyristor T3 is electrically connected between the output terminal of the third bridge arm 13 (e.g., point C) and the second terminal of the first capacitor T1 (i.e., the midpoint O of the DC bus).

[0190] Fault-tolerant control device ( Figure 14 (Not shown) are electrically connected to the control terminals of the first bidirectional thyristor T1, the second bidirectional thyristor T2, and the third bidirectional thyristor T3, respectively. In this way, the fault-tolerant control device can output multiple control signals for controlling the bidirectional thyristors to the corresponding bidirectional thyristors, so as to control the conduction and turn-off of the multiple bidirectional thyristors respectively.

[0191] In this way, after a fault occurs in one of the bridge arms of the inverter, after the bridge arm is disconnected, a control signal is sent to the corresponding bidirectional thyristor through the fault-tolerant control device to turn on the bidirectional thyristor. This makes it easy for the inverter to continue to operate and improves the stability of the inverter operation.

[0192] like Figure 14 As shown, the fault-tolerant circuit may further include a voltage equalization circuit 20. The voltage equalization circuit 20 is electrically connected between the first conductor 71 and the second conductor 72 of the DC bus 70. The voltage equalization circuit 20 is used to equalize the voltage at the midpoint of the DC bus. Through this voltage equalization circuit, the potential at the midpoint of the DC bus can be made as equal as possible, improving the frequency converter control accuracy.

[0193] In some embodiments, such as Figure 14 As shown, the voltage equalization circuit 20 may include a first resistor R1 and a second resistor R2. The first terminal of the first resistor R1 is electrically connected to the first terminal of the first capacitor C1, and the second terminal of the first resistor R1 is electrically connected to the second terminal of the first capacitor C1. That is, the first resistor R1 is connected in parallel with the first capacitor C1. The first terminal of the second resistor R2 is electrically connected to the first terminal of the second capacitor C2, and the second terminal of the second resistor R2 is electrically connected to the second terminal of the second capacitor C2. That is, the second resistor R2 is connected in parallel with the second capacitor C2.

[0194] In some embodiments, the resistance value of the first resistor R1 is equal to the resistance value of the second resistor R2. This facilitates the potential equalization at the midpoint of the DC bus.

[0195] For example, the resistance values ​​of the first resistor R1 and the second resistor R2 can both be 27 kΩ (kiloohms). Of course, those skilled in the art will understand that the scope of this disclosure is not limited to the specific resistance values ​​of the first resistor R1 and the second resistor R2, and the specific resistance values ​​of the first resistor R1 and the second resistor R2 can be set according to actual needs or actual circumstances.

[0196] like Figure 14 As shown, the voltage equalization circuit 20 may further include a seventh switching device S1, a third resistor R3, an eighth switching device S2, and a fourth resistor R4. The first terminal of the seventh switching device S1 is electrically connected to the first terminal of the first resistor R1. The first terminal of the third resistor R3 is electrically connected to the second terminal of the seventh switching device S1, and the second terminal of the third resistor R3 is electrically connected to the second terminal of the first resistor R1. That is, the seventh switching device S1 and the third resistor R3 are connected in series, and then in parallel with the first resistor R1. The first terminal of the eighth switching device S2 is electrically connected to the first terminal of the second resistor R2. The first terminal of the fourth resistor R4 is electrically connected to the second terminal of the eighth switching device S2, and the second terminal of the fourth resistor R4 is electrically connected to the second terminal of the second resistor R2. That is, the eighth switching device S2 and the fourth resistor R4 are connected in series, and then in parallel with the second resistor R2.

[0197] In the voltage equalization circuit of the above embodiment, the seventh switching device is connected in series with the third resistor and then in parallel with the first resistor, and the eighth switching device is connected in series with the fourth resistor and then in parallel with the second resistor. In this way, by controlling the on and off of the seventh and eighth switching devices, it is possible to control whether the third resistor and the first resistor are connected in parallel, and whether the fourth resistor and the second resistor are connected in parallel, thereby adjusting the potential of the DC bus midpoint O, so as to make the potential of the DC bus midpoint as balanced as possible and improve the frequency conversion control accuracy.

[0198] In some embodiments, the resistance value of the third resistor R3 is equal to the resistance value of the fourth resistor R4. This facilitates the potential equalization at the midpoint of the DC bus.

[0199] For example, the resistance values ​​of the third resistor R3 and the fourth resistor R4 can both be 27 kΩ (kiloohms). Of course, those skilled in the art will understand that the scope of this disclosure is not limited to the specific resistance values ​​of the third resistor R3 and the fourth resistor R4, and the specific resistance values ​​of the third resistor R3 and the fourth resistor R4 can be set according to actual needs or actual circumstances.

[0200] The connection of the third resistor R3 and the fourth resistor R4 is controlled by the seventh switch device S1 and the eighth switch device S2, thereby changing the total voltage equalization resistance value. For example, when the seventh switch device S1 is on and the eighth switch device S2 is off, the first resistor R1 and the third resistor R3 are connected in parallel and then connected in series with the second resistor R2 to achieve voltage equalization. Since the resistance of the first resistor R1 and the third resistor R3 decreases after being connected in parallel, the voltage drop decreases, and thus the voltage u on the first capacitor C1 decreases. p The voltage decreases, and the voltage u across the second capacitor C2 decreases. n As the voltage increases, this voltage equalization circuit can regulate the voltage.

[0201] like Figure 14 As shown, the fault-tolerant circuit may further include a potential equalization control circuit 60. The equalization control circuit 60 is used to obtain the first voltage u of the first capacitor C1. p The second voltage u of the second capacitor C2 n And based on the first voltage u p Second voltage u n The switching states of the seventh switching device S1 and the eighth switching device S2 are controlled to balance the potential at the midpoint O of the DC bus. Here, the potential at the midpoint O of the DC bus is the potential of the second terminal of the first capacitor C1 (and also the potential of the first terminal of the second capacitor C2).

[0202] For example, the first voltage u of the first capacitor C1 can be detected by a voltage detection device. p The second voltage u of the second capacitor C2 n The first voltage and the second voltage are transmitted to the potential equalization control circuit so that the potential equalization control circuit can perform voltage equalization based on the comparison result of the first voltage and the second voltage.

[0203] In the above embodiments, by setting a potential equalization control circuit, the conduction and cutoff of the seventh switching device and the conduction and cutoff of the eighth switching device can be controlled based on the detected first voltage of the first capacitor and the second voltage of the second capacitor, thereby maximizing the potential equalization of the DC bus midpoint, which can improve the frequency conversion control accuracy.

[0204] In the embodiments of this disclosure, the above-mentioned fault-tolerant control scheme can be implemented to address faults such as bridge arm short circuits or open circuits that may occur during the operation of a three-phase two-level inverter. Through redundancy design and reconfiguration, the inverter can still operate normally in the event of a fault, thereby improving the reliability and safety of the system. This fault-tolerant control scheme not only effectively extends the service life of the equipment but also ensures stable system operation, possessing significant engineering application value.

[0205] Figure 15This is a schematic diagram illustrating the circuit structure of a potential equalization control circuit according to some embodiments of the present disclosure. For example... Figure 15 As shown, the potential equalization control circuit may include a comparator 610, a trigger 620, and a drive circuit 630.

[0206] Comparator 610 is used to receive the first voltage u p Second voltage u n It compares a first voltage and a second voltage and outputs the comparison result. For example, the comparator can output a voltage value between -3V and +3V as the comparison result. Here, comparator 610 is a voltage comparator.

[0207] Trigger 620 is used to receive the comparison result and output a trigger signal if the comparison result exceeds a predetermined range. Here, if the comparison result exceeds the predetermined range, it indicates that the potential at the midpoint of the DC bus deviates from the theoretical potential value (e.g., V0). dc / 2) If the fluctuation is too large, for example, exceeding the upper or lower threshold, it indicates that the DC bus midpoint potential fluctuation exceeds the allowable range. In this case, a trigger signal is output to the drive circuit, causing the drive circuit to control the on / off state of the seventh and eighth switching devices. For example, the trigger is a Schmitt trigger. This trigger can provide hysteresis control on the comparator output to prevent frequent adjustments.

[0208] For example, the predetermined range can be -1V to +1V. Of course, the above predetermined range can be set according to actual needs or circumstances; for example, it can be obtained through testing or experimentation. The scope of this disclosure is not limited to the specific range of this predetermined range.

[0209] For example, the DC bus voltage difference (u) can be obtained through a voltage comparator. p u n (Voltage difference), then the Schmitt trigger can set upper and lower thresholds, for example, assuming the voltage deviates from V. dc Twenty percent of 2 is considered large. Taking a DC bus voltage of 540V as an example, this deviation from the DC bus voltage of 54V is considered large. The threshold value of the Schmitt trigger's peripheral circuit corresponding to 54V can be changed (for example, the corresponding upper threshold value is 1V, and the corresponding lower threshold value is -1V). When the comparator output exceeds the upper threshold value or the lower threshold value set by the Schmitt trigger, the level of the Schmitt trigger will jump, causing the Schmitt trigger to output a trigger signal, which will then control the seventh switching device S1 and the eighth switching device S2 through the drive circuit.

[0210] The drive circuit 630 receives a trigger signal and, based on the trigger signal, outputs a first drive signal to the seventh switching device and a second drive signal to the eighth switching device to control the switching states of the seventh and eighth switching devices. That is, the drive circuit 630 controls the on / off state of the seventh switching device and the eighth switching device based on the trigger signal.

[0211] In the above embodiments, a comparator, a flip-flop, and a drive circuit are set in the potential equalization control circuit. By operating the comparator, flip-flop, and drive circuit together, the situation of adjusting the DC bus midpoint potential too frequently can be reduced.

[0212] In some embodiments, such as Figure 15 As shown, the driving circuit 630 may include a NOT gate 631 and a driving chip 632. The output of the flip-flop 620 is directly connected to the first input of the driving chip 632, and the output of the flip-flop 620 is connected to the second input of the driving chip 632 through the NOT gate 631. The driving chip 632 is used to output a first driving signal g1 based on the trigger signal received at the first input, and to output a second driving signal g2 based on the inverted signal of the trigger signal received at the second input. Figure 14 As shown, the first drive signal g1 is input to the control terminal of the seventh switch device S1 to control the seventh switch device S1 to turn on and off, and the second drive signal g2 is input to the control terminal of the eighth switch device S2 to control the eighth switch device S2 to turn on and off.

[0213] In the above embodiments, by setting the NOT gate circuit and the driver chip, the first drive signal and the second drive signal can be reversed. This allows the seventh switch device and the eighth switch device to not be turned on at the same time, nor to be turned off at the same time. That is, one of the seventh switch device and the eighth switch device is turned on while the other is turned off. This can achieve the purpose of adjusting the potential of the DC bus midpoint, thereby making the potential of the DC bus midpoint as balanced as possible.

[0214] In embodiments of this disclosure, by Figure 2 It can be seen that in the reconstructed inverter topology, the faulty phase output is directly powered from the DC bus midpoint, and under ideal conditions, the DC bus midpoint potential is V. dc / 2, however, capacitor manufacturing issues and faulty phase power supply can cause fluctuations in the midpoint potential of the DC bus capacitor, deviating from V. dc / 2, in addition to increasing the capacitance of the DC bus, the voltage equalization control circuit can also be used to balance the potential at the midpoint of the DC bus. For example... Figure 1 , Figure 2 or Figure 14As shown, equalizing resistors R1 and R2 are connected in parallel with capacitors C1 and C2 on the DC bus to reduce the potential deviation at the midpoint of the DC bus caused by the different capacitance values ​​of C1 and C2 due to capacitor manufacturing processes. Additionally, equalizing resistors R3 and R4 are connected in parallel with R1 and R2. The connection of equalizing resistors R3 and R4 is controlled by fully controllable switching devices S1 and S2 (e.g., IGBTs (Insulated Gate Bipolar Transistors)). The voltage u of capacitors C1 and C2 on the DC side is sampled. p u n The sampled voltage value is input to a voltage comparator, and the output value of the voltage comparator is connected to a Schmitt trigger for hysteresis control. When the potential at the midpoint of the DC bus deviates from V... dc When / 2 is relatively large, adjustment is performed to prevent excessively rapid adjustment, as this may cause the switching devices S1 and S2 to overheat due to excessively high switching frequency. Then, the output of the Schmitt trigger is connected to a logic NOT gate to output two complementary signals to the driver chip, thereby obtaining the drive signals g1 and g2 for the switching devices S1 and S2, which are used for equalization control of the DC bus midpoint potential.

[0215] In some embodiments of this disclosure, the first to eighth switching devices may be IGBT devices with diodes.

[0216] In the control flow of some embodiments of this disclosure, firstly, the three-phase two-level inverter operates normally; next, it is determined whether a single-phase bridge arm is faulty. If so, the faulty phase bridge arm is switched off and the corresponding bidirectional thyristor is turned on, completing the inverter topology and reconfiguring. If the bridge arm is not faulty, the inverter continues to operate normally. After the faulty phase bridge arm is switched off and the corresponding bidirectional thyristor is turned on, the midpoint potential balancing control circuit is executed; next, the three-phase two-level inverter fault-tolerant control is implemented. The fault-tolerant control is as described above and will not be repeated here.

[0217] In the embodiments of this disclosure, a fault-tolerant topology for a three-phase two-level inverter is designed based on the related technology. When a short circuit or open circuit fault occurs in a single phase arm of the inverter, the faulty phase arm is first cut off by a fast fuse, and the bidirectional thyristor at the output terminal of the faulty phase is turned on to realize inverter reconfiguration. Then, the DC bus midpoint voltage of the reconfigured inverter is controlled by the voltage equalization control circuit in the front stage to make the DC bus midpoint potential equal. Based on the reconfigured inverter topology and the fault-tolerant control SVPWM algorithm, the three-phase two-level inverter can continue to operate after a fault occurs.

[0218] After a single-phase bridge arm short-circuit or open-circuit fault occurs in a three-phase two-level inverter, the faulty bridge arm is disconnected through topology reconfiguration. Combined with a fault-tolerant control algorithm, motor drive control or grid-connected control can be maintained. A voltage equalization control circuit is designed in the front stage of the inverter to ensure that the inverter's midpoint potential is balanced after topology reconfiguration, improving the frequency conversion control accuracy. The fault-tolerant control method for a three-phase two-level inverter disclosed in this embodiment can ensure that the inverter still has a certain driving capability after a single-phase bridge arm short-circuit or open-circuit fault, enabling the inverter to still achieve motor drive or grid connection after a fault, meeting the needs of some critical applications.

[0219] In some embodiments of this disclosure, an electrical device is also provided, which includes the fault-tolerant circuit as described above.

[0220] In some embodiments, this disclosure also provides a computer-readable storage medium (e.g., a non-transitory computer-readable storage medium) having stored thereon computer program instructions that are implemented when executed by a processor. Figure 3 The steps of the method in the corresponding embodiments are described. Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, apparatus, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable non-transitory storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0221] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0222] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0223] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0224] In some embodiments of this disclosure, a computer program product is also provided, which includes a computer program or instructions that, when executed by a processor, implement the fault-tolerant control method as described above.

[0225] In some embodiments of this disclosure, a computer program is also provided, comprising: instructions that, when executed by a processor, cause the processor to perform the fault-tolerant control method as described above.

[0226] This concludes the detailed description of the present disclosure. To avoid obscuring the concept of the disclosure, some details known in the art have not been described. Those skilled in the art will fully understand how to implement the technical solutions disclosed herein based on the above description.

[0227] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A fault-tolerant control method for an inverter, wherein, The inverter includes a first bridge arm, a second bridge arm, and a third bridge arm, and the fault-tolerant control method includes: In the event of a failure in the third bridge arm, disconnect the third bridge arm and connect the output terminal of the third bridge arm to the midpoint of the DC bus; After cutting out the third bridge arm, the vector synthesis order of the reference voltage vector is determined based on the spatial vector sector where the reference voltage vector is located. The vector synthesis order is the implementation order of multiple basic vectors used to synthesize the reference voltage vector. The basic vector is a spatial vector determined based on the switching state of the switching device of the first bridge arm and the switching state of the switching device of the second bridge arm. Based on the reference voltage vector, the plurality of basic vectors, and a predetermined control cycle, the application time of each of the plurality of basic vectors is determined; and Based on the action time of each basic vector and the order of vector synthesis, control signals for controlling the first bridge arm and the second bridge arm are obtained and output. The fault-tolerant control method further includes: determining the spatial vector sector where the reference voltage vector is located before determining the vector synthesis order of the reference voltage vector, wherein the spatial vector sector includes a first spatial vector sector and a second spatial vector sector, the first spatial vector sector and the second spatial vector sector are respectively determined by a number of corresponding basic vectors, and the first spatial vector sector is different from the second spatial vector sector; The basic vector determined by the switching states of the switching devices of the first bridge arm and the second bridge arm includes a first basic vector, a second basic vector, a third basic vector, and a fourth basic vector. The first basic vector and the third basic vector are equal in magnitude and opposite in direction, the second basic vector and the fourth basic vector are equal in magnitude and opposite in direction, and the first basic vector is perpendicular to the second basic vector.

2. The fault-tolerant control method according to claim 1, wherein, Determining the space vector sector where the reference voltage vector is located includes: The reference voltage vector is decomposed in the αβ axis coordinate system to obtain a first decomposed vector on the α axis and a second decomposed vector on the β axis; and Based on the first decomposition vector and the second decomposition vector, determine which space vector sector, the first space vector sector or the second space vector sector, the reference voltage vector is located in.

3. The fault-tolerant control method according to claim 1, wherein: The vector synthesis order includes a first vector synthesis order and a second vector synthesis order, wherein the first vector synthesis order is different from the second vector synthesis order; Based on the spatial vector sector where the reference voltage vector is located, the vector composition order of the reference voltage vector is determined, including: When the reference voltage vector is located within the first space vector sector, the vector synthesis order of the reference voltage vector is determined to be the first vector synthesis order; and When the reference voltage vector is located in the second space vector sector, the vector synthesis order of the reference voltage vector is determined to be the second vector synthesis order.

4. The fault-tolerant control method according to claim 1, wherein: The magnitudes of the first fundamental vector and the third fundamental vector are respectively The magnitudes of the second fundamental vector and the fourth fundamental vector are respectively ,in, The bus voltage of the DC bus connected to the inverter; In the αβ axis coordinate system, the spatial vector angle of the first fundamental vector is... The spatial vector angle of the second fundamental vector is The spatial vector angle of the third basic vector is The spatial vector angle of the fourth basic vector is .

5. The fault-tolerant control method according to claim 1, wherein, Based on the reference voltage vector, the plurality of basic vectors, and a predetermined control cycle, the action time of each of the plurality of basic vectors is determined, including: A spatial rectangular coordinate system is constructed using the line containing the first basic vector as the first coordinate axis and the line containing the second basic vector as the second coordinate axis. The reference voltage vector and the plurality of basic vectors are decomposed on the first coordinate axis and the second coordinate axis, respectively, to obtain a plurality of decomposed vectors corresponding to the reference voltage vector and the plurality of basic vectors, respectively; and Based on the multiple decomposed vectors and the control period, and using the volt-second balance equation, the action time of each of the multiple basic vectors is calculated.

6. The fault-tolerant control method according to claim 1, wherein: The vector synthesis order adopts a symmetrical vector order. The basic vector at the center of the vector synthesis sequence takes the required action time, while the basic vectors on either side of the center of the vector synthesis sequence each take half the required action time.

7. The fault-tolerant control method according to any one of claims 1 to 6, wherein, Cutting out the third bridge arm and connecting the output terminal of the third bridge arm to the midpoint of the DC bus includes: All switching devices on the third bridge arm are turned off; and The bidirectional thyristor connected between the output terminal of the third bridge arm and the midpoint of the DC bus is turned on.

8. A fault-tolerant control device for an inverter, wherein, The inverter includes a first bridge arm, a second bridge arm, and a third bridge arm, and the fault-tolerant control device includes: The fault handling unit is used to disconnect the third bridge arm and connect the output terminal of the third bridge arm to the midpoint of the DC bus in the event of a fault in the third bridge arm. The first determining unit is configured to determine the vector synthesis order of the reference voltage vector based on the spatial vector sector where the reference voltage vector is located after the third bridge arm is cut out. The vector synthesis order is the implementation order of multiple basic vectors used to synthesize the reference voltage vector. The basic vectors are spatial vectors determined based on the switching states of the switching devices of the first bridge arm and the switching states of the switching devices of the second bridge arm. The second determining unit is configured to determine the action time of each of the plurality of basic vectors based on the reference voltage vector, the plurality of basic vectors, and a predetermined control period; and The output unit is used to obtain and output control signals for controlling the first bridge arm and the second bridge arm based on the action time of each basic vector and the order of vector synthesis. The first determining unit is further configured to determine the spatial vector sector in which the reference voltage vector is located before determining the vector synthesis order of the reference voltage vector, wherein the spatial vector sector includes a first spatial vector sector and a second spatial vector sector, the first spatial vector sector and the second spatial vector sector are respectively determined by a number of corresponding basic vectors, and the first spatial vector sector is different from the second spatial vector sector. The basic vector determined by the switching states of the switching devices of the first bridge arm and the second bridge arm includes a first basic vector, a second basic vector, a third basic vector, and a fourth basic vector. The first basic vector and the third basic vector are equal in magnitude and opposite in direction, the second basic vector and the fourth basic vector are equal in magnitude and opposite in direction, and the first basic vector is perpendicular to the second basic vector.

9. A fault-tolerant control device for an inverter, comprising: Memory; as well as A processor coupled to the memory, the processor being configured to execute the fault-tolerant control method as described in any one of claims 1 to 7 based on instructions stored in the memory.

10. A fault-tolerant circuit, comprising: The fault-tolerant control device as described in claim 8 or 9.

11. The fault-tolerant circuit according to claim 10, further comprising: An inverter includes a first bridge arm, a second bridge arm, and a third bridge arm, wherein the first bridge arm, the second bridge arm, and the third bridge arm are respectively connected in parallel between the first conductor and the second conductor of the DC bus; The first bridge arm includes a first switching device, a first fuse, a second switching device, and a second fuse connected in series between the first conductor and the second conductor of the DC bus. The second bridge arm includes a third switching device, a third fuse, a fourth switching device, and a fourth fuse connected in series between the first conductor and the second conductor of the DC bus. The third bridge arm includes a fifth switching device, a fifth fuse, a sixth switching device, and a sixth fuse connected in series between the first conductor and the second conductor of the DC bus. The fault-tolerant control device is electrically connected to the control terminals of the first switching device, the second switching device, the third switching device, the fourth switching device, the fifth switching device, and the sixth switching device, respectively.

12. The fault-tolerant circuit according to claim 10, further comprising: A first capacitor and a second capacitor, wherein a first terminal of the first capacitor is electrically connected to a first conductor of the DC bus, a second terminal of the first capacitor is electrically connected to a first terminal of the second capacitor, and a second terminal of the second capacitor is electrically connected to a second conductor of the DC bus. The first bidirectional thyristor is electrically connected between the output terminal of the first bridge arm and the second terminal of the first capacitor; The second bidirectional thyristor is electrically connected between the output terminal of the second bridge arm and the second terminal of the first capacitor; and The third bidirectional thyristor is electrically connected between the output terminal of the third bridge arm and the second terminal of the first capacitor. The fault-tolerant control device is electrically connected to the control terminal of the first bidirectional thyristor, the control terminal of the second bidirectional thyristor, and the control terminal of the third bidirectional thyristor.

13. The fault-tolerant circuit according to claim 12, further comprising: The voltage equalization circuit is electrically connected between the first and second conductors of the DC bus and is used to equalize the voltage at the midpoint of the DC bus.

14. The fault-tolerant circuit according to claim 13, wherein, The voltage equalization circuit includes: A first resistor, wherein a first end of the first resistor is electrically connected to a first end of the first capacitor, and a second end of the first resistor is electrically connected to a second end of the first capacitor; A second resistor, wherein the first end of the second resistor is electrically connected to the first end of the second capacitor, and the second end of the second resistor is electrically connected to the second end of the second capacitor; A seventh switching device, wherein the first terminal of the seventh switching device is electrically connected to the first terminal of the first resistor; A third resistor, the first end of which is electrically connected to the second end of the seventh switching device, and the second end of which is electrically connected to the second end of the first resistor; The eighth switching device, wherein the first terminal of the eighth switching device is electrically connected to the first terminal of the second resistor; A fourth resistor, the first end of which is electrically connected to the second end of the eighth switching device, and the second end of which is electrically connected to the second end of the second resistor.

15. The fault-tolerant circuit according to claim 14, further comprising: A potential equalization control circuit is used to obtain a first voltage of the first capacitor and a second voltage of the second capacitor, and control the switching state of the seventh switching device and the switching state of the eighth switching device based on the first voltage and the second voltage, so as to achieve potential equalization at the midpoint of the DC bus, wherein the potential at the midpoint of the DC bus is the potential of the second terminal of the first capacitor.

16. The fault-tolerant circuit according to claim 15, wherein, The potential equalization control circuit includes: A comparator is used to receive the first voltage and the second voltage, compare the first voltage and the second voltage, and output the comparison result; A trigger is used to receive the comparison result and output a trigger signal when the comparison result exceeds a predetermined range; A driving circuit is configured to receive the trigger signal, and based on the trigger signal, output a first driving signal to the seventh switching device and a second driving signal to the eighth switching device, so as to control the switching state of the seventh switching device and the switching state of the eighth switching device.

17. The fault-tolerant circuit according to claim 16, wherein, The driving circuit includes: NOT gate circuits and driver chips, The output of the flip-flop is directly connected to the first input of the driver chip, and the output of the flip-flop is connected to the second input of the driver chip through the NOT gate circuit. The driver chip is used to output the first driving signal based on the trigger signal received at the first input terminal, and to output the second driving signal based on the inverse signal of the trigger signal received at the second input terminal.

18. The fault-tolerant circuit according to claim 14, wherein, The capacitance of the first capacitor is equal to the capacitance of the second capacitor; The resistance value of the first resistor is equal to the resistance value of the second resistor; The resistance value of the third resistor is equal to the resistance value of the fourth resistor.

19. An electrical device comprising: The fault-tolerant circuit as described in any one of claims 10 to 18.

20. A computer-readable storage medium having stored thereon computer instructions that, when executed by a processor, implement the fault-tolerant control method as described in any one of claims 1 to 7.

21. A computer program product comprising a computer program or instructions that, when executed by a processor, implement the fault-tolerant control method as described in any one of claims 1 to 7.

Images