Error code number calculation method, FPGA test method and error code rate test system

Abstract

The present application belongs to the technical field of electronic system, and particularly relates to a method for calculating error code number, a method for testing FPGA and a test system for error code rate. The method comprises the following steps: selecting a corresponding error code number processing mechanism according to the accuracy of the converter; establishing a connection between the TX link layer and the RX link layer of JESD204B / C and the JESD204 PHY physical layer, and completing the link synchronization between the JESD204B / C TX link layer and the JESD204B / C RX link layer; the TX link layer of JESD204B / C receives the sine wave data required by the converter from the transmission signal end of the upper layer logic of FPGA, and the transmission signal end continuously and cyclically transmits the sine wave data to the TX link layer of JESD204B / C according to the period; the present application can efficiently and real-timely calculate the error code number of the link protocol layer, and is helpful for analyzing whether the link layer works normally.

Description

Technical Field

[0001] This invention belongs to the field of electronic system technology, and specifically relates to a method for calculating bit error rate, an FPGA testing method, and a test system for bit error rate. Background Technology

[0002] In modern electronic systems, the application of high-speed interfaces is receiving increasing attention. The JESD204B / C high-speed serial interface, in particular, focuses on devices such as ADCs, DACs, and FPGAs, and is widely used in fields such as 5G base stations, radar signal processing, medical CT, and satellite communications. Bit error rate (BER) is one of the core metrics for measuring high-speed interfaces. It represents the ratio of erroneous bits transmitted to the total number of transmitted bits, directly reflecting the reliability of data transmission. Due to the high transmission rate and significant signal attenuation and interference, the BER of high-speed interfaces directly affects system stability: a low BER ensures accurate data transmission, avoiding communication interruptions, image distortion, and calculation errors; while an excessive BER can lead to the loss of critical data, and even cause system failures in fields such as aerospace and communication base stations. Therefore, the BER is a key benchmark for evaluating interface performance and ensuring data transmission quality in various application scenarios.

[0003] Existing technologies generally use bit error rate testers to measure bit error rate. In some complex systems, link layer protocol errors, packet loss, etc. may lead to bit error phenomena. However, bit error rate testers can only directly test the physical layer and cannot measure the bit error rate of the link layer. In addition, bit error rate testers are expensive, usually in the millions of yuan range. They are also difficult to operate, which is not conducive to production and testing personnel. Summary of the Invention

[0004] The purpose of this invention is to provide a method for calculating bit error rate, an FPGA testing method, and a bit error rate testing system. This invention can not only efficiently and in real time calculate the bit error rate of the link protocol layer, which helps to analyze whether the link layer is working properly, but also automatically record data and save logs, reducing the burden on operators.

[0005] To address the aforementioned technical problems, this invention provides a method for calculating bit error rate, based on an FPGA hardware platform, comprising:

[0006] Step S1: Select the corresponding bit error rate handling mechanism based on the converter's accuracy;

[0007] Step S2: Establish a connection between the TX and RX link layers of JESD204B / C and the physical layer of JESD204 PHY, and complete link synchronization between the JESD204B / C TX link layer and the JESD204B / C RX link layer.

[0008] Step S3: The TX link layer of JESD204B / C receives the sine wave data required by the converter from the transmitting signal terminal of the upper logic of the FPGA, and the transmitting signal terminal continuously and cyclically sends the sine wave data to the TX link layer of JESD204B / C according to the period.

[0009] Step S4: The RX link layer of JESD204B / C sends the sine wave data of the converter to the receiving signal terminal of the lower logic layer of the FPGA, and the receiving signal terminal continuously receives sine wave data from the RX link layer of JESD204B / C.

[0010] Step S5: After the sine wave data sent to the receiving signal terminal by the converter is valid, wait for a 1μs delay to allow the sine wave data to stabilize, and select the data at this time as the comparison start bit, which is called the starting data of the converter data;

[0011] Step S6: Compare the starting data with each reference data. If the values ​​are the same, record the corresponding reference data identifier and mark it with a marker to form the starting identifier of the reference data. Then proceed to step S7. If no reference data matching the starting data is found, repeat step S5.

[0012] Step S7: For each converter, the converter data and reference data start from the starting data and the starting identifier, respectively. The two are XORed bitwise, and the result is marked as compare_xor[i]. Its bit width is consistent with the converter precision, and i is consistent with the converter number.

[0013] Step S8: For each converter's compare_xor[i], sum all bits in a pipelined manner, and mark the result as cvt_bit_cnt[i].

[0014] Step S9: For all converters, sum all cvt_bit_cnt[i] in a pipelined manner, using the following formula: .

[0015] Preferably, the converter precision includes 12-bit, 16-bit, and 24-bit.

[0016] Preferably, one cycle of the sine wave data has 64 data points, labeled 0 to 63. The bit width of the data is consistent with the converter accuracy, and each data point is different. One cycle of the reference data also has 64 data points, labeled 0 to 63.

[0017] This invention also provides an FPGA testing method for calculating the bit error rate of the JESD204B / C high-speed interface protocol layer, including:

[0018] Step 1: Power on the FPGA hardware platform and begin testing;

[0019] Step 2: Reset and initialize the FPGA hardware platform;

[0020] Step 3: Generate the reference clock, core clock, sampling clock corresponding to the test mode, AXI bus drive clock, and DRP clock required for the JESD204B / C high-speed interface;

[0021] Step 4: Configure parameters according to the test mode, including Ethernet parameters and JESD204B / C parameters;

[0022] Step 5: Calculate the number of bit errors for the JESD204B / C high-speed interface based on the bit error calculation method described above;

[0023] Step 6: Send the bit error rate data to the host computer according to the Ethernet frame format and the configured Ethernet parameters;

[0024] Step 7: Determine if the configuration parameters have been modified. If yes, repeat steps 1 to 6 above; otherwise, end the test.

[0025] Preferably, the Ethernet parameters include the number of Ethernet packets, the size of Ethernet packets, and the interval between Ethernet packets; the JESD204B / C parameters include the encoding type, link mode, scrambling type, subclass type, check type, and SYSREF type.

[0026] The present invention also provides a lower-level machine, which is an FPGA main control board, for executing an FPGA testing method as described above.

[0027] The present invention also provides a bit error rate testing system, comprising a host computer for sending commands and receiving data, and a slave computer as described above; wherein the host computer comprises:

[0028] The system initialization module is used to send initialization start commands to the lower-level machine and the upper-level machine itself, and then receive initialization completion commands.

[0029] The parameter configuration module is used to allocate the relevant parameters of the protocol layer test mode to the host computer and the slave computer, and then receive the parameter configuration completion instruction;

[0030] The bit error rate acquisition module is used to receive the bit error rate sent by the lower-level machine;

[0031] The bit error rate calculation module is used to calculate the bit error rate data from the bit error count data received by the bit error count acquisition module;

[0032] The data storage module saves the calculated bit error rate data to the local path of the host computer;

[0033] The curve plotting module is used to plot the bit error rate data saved by the data storage module as a curve and display it on the host computer interface.

[0034] Preferably, the bit error rate calculation module includes the following calculation process:

[0035] Step 1: If the size of a UDP packet is the threshold bytes thresh_b, proceed to Step 2; if it is less than the threshold bytes thresh_b, discard the UDP packet and wait for the system's receive buffer to be automatically updated, repeating Step 1; if the system does not update the data, end the entire calculation process.

[0036] Step 2: Count the total number of UDP packets and mark it as total_packets_num;

[0037] Step 3: Calculate the sum of bit error counts, that is, accumulate the sum of the data in the UDP packets and mark it as bit_err_cnt;

[0038] Step 4: Determine if the total number of UDP packets is a multiple of the integer N. If yes, proceed to Step 5; otherwise, repeat Steps 1 to 3.

[0039] Step 5: Calculate the total number of bits;

[0040] Step 6: Calculate the bit error rate;

[0041] Step 7: Repeat steps 1 through 6.

[0042] Preferably, the threshold byte thresh_b is 1024; the integer N is 100.

[0043] Preferably, the formula for calculating the total number of bits is: total_bits_num = total_packets_num × thresh_b × cvt_width × cvt_num; where cvt_width is the converter precision in the parameter configuration module, and cvt_num is the number of converters in the parameter configuration module; the formula for calculating the bit error rate is: ber = bit_err_cnt ÷ total_bits_num.

[0044] Compared with the prior art, the present invention has the following beneficial effects:

[0045] This invention is based on an FPGA hardware platform to calculate the bit error rate (BER) of the JESD204B / C high-speed interface protocol layer. Furthermore, it provides an FPGA testing method for calculating the BER of the JESD204B / C high-speed interface protocol layer. This method can efficiently and in real-time calculate the BER of the link protocol layer, which helps in analyzing whether the link layer is functioning correctly. Moreover, this invention provides an automatic testing system for the BER of the JESD204B / C high-speed interface protocol layer. This testing system includes a host computer and a slave computer. The host computer is a computer that sends commands and receives data, including a system initialization module, a parameter configuration module, a BER acquisition module, a BER calculation module, a data storage module, and a curve plotting module. The slave computer is an FPGA main control board. It is low-cost, simple to operate, can automatically save test data, plot curves, and has a user-friendly interface. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the structure of the automatic testing system provided by the present invention.

[0047] Figure 2 The flowchart shows the algorithm for the bit error rate calculation module provided by this invention.

[0048] Figure 3 The flowchart shows the FPGA test bit error rate method provided by this invention.

[0049] Figure 4 A flowchart of the error calculation method provided by the present invention. Detailed Implementation

[0050] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0051] like Figure 1As shown, this embodiment of the invention specifically provides an automatic testing system for the bit error rate (BER) of the JESD204B / C high-speed interface protocol layer. It includes a host computer and a slave computer. The host computer is a computer that sends commands and receives data, including a system initialization module, a parameter configuration module, a BER acquisition module, a BER calculation module, a data storage module, and a curve plotting module; the slave computer is an FPGA main control board. The system initialization module sends an initialization start command to the slave computer and itself, and then receives an initialization completion command; the parameter configuration module allocates relevant parameters of the protocol layer test mode to the host computer and the slave computer, and then receives a parameter configuration completion command; the BER acquisition module receives the BER data sent by the slave computer; the BER calculation module calculates the BER based on the data from the BER acquisition module; the data storage module saves the calculated BER to the host computer's local path; the curve plotting module connects to the data storage module, plots the BER data as a curve, and displays it on the host computer interface.

[0052] The automatic testing system provided in this embodiment of the invention involves a bit error rate calculation module algorithm process as follows: Figure 2 As shown. The bit error rate acquisition module sends data to the bit error rate calculation module, and the bit error rate calculation process begins immediately. The algorithm is as follows:

[0053] Step I: When a UDP packet is 1024 bytes in size, proceed to Step II; if it is less than 1024 bytes, discard the UDP packet and wait for the system's receive buffer to be automatically updated, then repeat Step I; if the system does not update the data, end the entire calculation process.

[0054] Step II: Count the total number of UDP packets, denoted as total_packets_num;

[0055] Step III: Calculate the sum of bit error counts (cumulatively calculate the sum of data in UDP packets), denoted as bit_err_cnt;

[0056] Step IV: Determine if the number of UDP packets is a multiple of 100. If yes, proceed to step V; otherwise, repeat steps I to III.

[0057] Step V: Calculate the total number of bits. The formula is: total_bits_num = total_packets_num × 1024 × cvt_width × cvt_num; cvt_width is the converter precision in the parameter configuration module, and cvt_num is the number of converters in the parameter configuration module.

[0058] Step VI: Calculate the bit error rate using the formula ber = bit_err_cnt ÷ total_bits_num;

[0059] Step VII: Repeat steps I through VI.

[0060] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the invention in any way. For example, the size of a UDP packet can be adjusted, and the number of UDP packets can be optimized.

[0061] This invention provides an FPGA testing method for calculating the bit error rate of the JESD204B / C high-speed interface protocol layer, the process of which is as follows: Figure 3 As shown, it includes the following steps:

[0062] Step 1: Power on the FPGA main control board and start the test;

[0063] Step 2: Reset and initialize the FPGA platform to avoid interference from previous tests;

[0064] Step 3: Generate the reference clock, core clock, sampling clock corresponding to the test mode, AXI bus driver clock, and DRP clock required for the high-speed interface;

[0065] Step 4: Configure parameters according to the test mode, including configuring Ethernet parameters and JESD204B / C parameters; Ethernet parameters include Ethernet packet count, Ethernet packet size, and Ethernet packet interval; JESD204B / C parameters include encoding type, link mode, scrambling type, subclass type, check type, and SYSREF type.

[0066] Step 5: Calculate the number of bit errors for the JESD204B / C high-speed interface based on the "bit error count algorithm";

[0067] Step 6: Send the bit error rate data to the host computer according to the Ethernet frame format and the Ethernet configuration parameters in Step 4;

[0068] Step 7: Determine if the configuration parameters have been changed. If the parameters have been modified, repeat steps 1 to 6; if the parameters have not been modified, end the test.

[0069] The bit error rate (BER) calculation method for FPGA testing provided by this invention involves the following BER algorithm process: Figure 4 As shown, the bit error rate algorithm based on the FPGA hardware platform is as follows:

[0070] Step 1: Select the corresponding error handling mechanism based on the converter precision (12-bit, 16-bit, 24-bit);

[0071] Step II: The JESD204B / C TX link layer, JESD204B / C RX link layer, and JESD204 PHY physical layer establish a connection, and the JESD204B / C TX link layer and JESD204B / C RX link layer complete synchronization.

[0072] Step III: The JESD204B / C TX link layer receives data from the upper-layer logic of the FPGA; this data is the sine wave data generated by the transmitting signal end and required by the converter. There are 64 data points in one cycle (identified by 0~63), the data bit width is consistent with the converter accuracy, and each data point is different; the transmitting signal end continuously and cyclically sends the sine wave data to the JESD204B / C TX link layer in a cycle.

[0073] Step IV: The JESD204B / C RX link layer sends data to the lower-level logic of the FPGA; the receiving signal end continuously receives converter data from the JESD204B / C RX link layer. Ideally, the converter data is a sine wave.

[0074] Step V: After the converter data is valid, wait for a 1μs delay to allow the data to stabilize. Select the data at this time as the comparison start bit, which is called the starting data of the converter.

[0075] Step VI: Compare the starting data with each reference data (64 data points per cycle, labeled 0~63). If the values ​​are the same, record the corresponding reference data label and mark it as a marker, then proceed to step VII. If no reference data matching the starting data is found, repeat step V. The marker is called the starting label of the reference data.

[0076] Step VII: For each converter, the converter data starts from the starting data and the reference data also starts from the starting identifier. The two are XORed bitwise and labeled as compare_xor[i]. The bit width is consistent with the converter precision and i is consistent with the converter number.

[0077] Step VIII: For each converter's compare_xor[i], sum all bits in a pipelined manner, denoted as cvt_bit_cnt[i].

[0078] Step IX: For all converters, sum all cvt_bit_cnt[i] in a pipelined manner, using the following formula: .

[0079] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for calculating bit error rate, based on an FPGA hardware platform, characterized in that, include: Step S1: Select the corresponding error handling mechanism based on the converter precision; the converter precision includes 12-bit, 16-bit, and 24-bit. Step S2: Establish a connection between the TX and RX link layers of JESD204B / C and the physical layer of JESD204 PHY, and complete link synchronization between the JESD204B / C TX link layer and the JESD204B / C RX link layer. Step S3: The TX link layer of JESD204B / C receives the sine wave data required by the converter from the transmitting signal terminal of the upper logic of the FPGA, and the transmitting signal terminal continuously and cyclically sends the sine wave data to the TX link layer of JESD204B / C in a periodic manner; one period of the sine wave data has 64 data points, identified as 0~63, the bit width of the data is consistent with the converter accuracy, and each data point is different; Step S4: The RX link layer of JESD204B / C sends the sine wave data of the converter to the receiving signal terminal of the lower logic layer of the FPGA, and the receiving signal terminal continuously receives sine wave data from the RX link layer of JESD204B / C. Step S5: After the sine wave data sent to the receiving signal terminal by the converter is valid, wait for a 1μs delay to allow the sine wave data to stabilize, and select the data at this time as the comparison start bit, which is called the starting data of the converter data; Step S6: Compare the starting data with each reference data. If the values ​​are the same, record the corresponding reference data identifier and mark it with a marker to form the starting identifier of the reference data, and then proceed to step S7. If no reference data matching the starting data is found, repeat step S5. One cycle of the reference data has 64 data points, labeled 0~63. Step S7: For each converter, the converter data and reference data start from the starting data and the starting identifier, respectively. The two are XORed bitwise, and the result is marked as compare_xor[i]. Its bit width is consistent with the converter precision, and i is consistent with the converter number. Step S8: For each converter's compare_xor[i], sum all bits in a pipelined manner, and mark the result as cvt_bit_cnt[i]. Step S9: For all converters, sum all cvt_bit_cnt[i] in a pipelined manner, using the following formula: .

2. An FPGA testing method for calculating the bit error rate of the JESD204B / C high-speed interface protocol layer, characterized in that, include: Step 1: Power on the FPGA hardware platform and begin testing; Step 2: Reset and initialize the FPGA hardware platform; Step 3: Generate the reference clock, core clock, sampling clock corresponding to the test mode, AXI bus drive clock, and DRP clock required for the JESD204B / C high-speed interface; Step 4: Configure parameters according to the test mode, including Ethernet parameters and JESD204B / C parameters; Step 5: Calculate the number of bit errors of the JESD204B / C high-speed interface based on the bit error calculation method described in claim 1; Step 6: Send the bit error rate data to the host computer according to the Ethernet frame format and the configured Ethernet parameters; Step 7: Determine if the configuration parameters have been modified. If yes, repeat steps 1 to 6 above; otherwise, end the test.

3. The FPGA testing method as described in claim 2, characterized in that, The Ethernet parameters include the number of Ethernet packets, the size of Ethernet packets, and the interval between Ethernet packets; the JESD204B / C parameters include the encoding type, link mode, scrambling type, subclass type, check type, and SYSREF type.

4. A lower-level machine, characterized in that, The lower-level machine is an FPGA main control board, which executes an FPGA testing method as described in claim 2.

5. A bit error rate testing system, characterized in that, It includes a host computer for sending commands and receiving data, and a slave computer as described in claim 4; wherein the host computer includes: The system initialization module is used to send initialization start commands to the lower-level machine and the upper-level machine itself, and then receive initialization completion commands. The parameter configuration module is used to allocate the relevant parameters of the protocol layer test mode to the host computer and the slave computer, and then receive the parameter configuration completion instruction; The bit error rate acquisition module is used to receive the bit error rate sent by the lower-level machine; The bit error rate calculation module is used to calculate the bit error rate data from the bit error count data received by the bit error count acquisition module; The data storage module saves the calculated bit error rate data to the local path of the host computer; The curve plotting module is used to plot the bit error rate data saved by the data storage module as a curve and display it on the host computer interface; The bit error rate calculation module includes the following calculation process: Step 1: If the size of a UDP packet is the threshold bytes thresh_b, proceed to Step 2; if it is less than the threshold bytes thresh_b, discard the UDP packet and wait for the system's receive buffer to be automatically updated, repeating Step 1; if the system does not update the data, end the entire calculation process. Step 2: Count the total number of UDP packets and mark it as total_packets_num; Step 3: Calculate the sum of bit error counts, that is, accumulate the sum of the data in the UDP packets and mark it as bit_err_cnt; Step 4: Determine if the total number of UDP packets is a multiple of the integer N. If yes, proceed to Step 5; otherwise, repeat Steps 1 to 3. Step 5: Calculate the total number of bits; Step 6: Calculate the bit error rate; Step 7: Repeat steps 1 through 6.

6. The bit error rate testing system as described in claim 5, characterized in that, The threshold byte thresh_b is 1024; the integer N is 100.

7. The bit error rate testing system as described in claim 5, characterized in that, The formula for calculating the total number of bits is: total_bits_num = total_packets_num × thresh_b × cvt_width × cvt_num; where cvt_width is the converter precision in the parameter configuration module, and cvt_num is the number of converters in the parameter configuration module; the formula for calculating the bit error rate is: ber = bit_err_cnt ÷ total_bits_num.

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