Memory device and method of manufacturing the same

Abstract

The present disclosure provides a memory device and a method of manufacturing the same, the memory device including: a first semiconductor structure including: a semiconductor pillar; the semiconductor columns extend along a first direction; a gate structure; the gate structures are located between the adjacent semiconductor columns; a bit line; the bit line extends along the second direction and is connected with a first end of two opposite ends of the semiconductor column along the first direction; the first direction is perpendicular to the second direction; a first cavity; the first cavity is located between the bit line and the gate structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, for example, to a memory device and a method for manufacturing the same. Background Art

[0002] With the continuous development of science and technology, semiconductor devices are widely used in various electronic devices and electronic products. For example, dynamic random access memory (DRAM), as a volatile memory, is a commonly used semiconductor memory device in computers. Summary of the Invention

[0003] According to a first aspect of an embodiment of the present disclosure, a memory device is provided, comprising a first semiconductor structure, the first semiconductor structure comprising: a semiconductor pillar; the semiconductor pillar extending along a first direction; a gate structure; the gate structure being located between adjacent semiconductor pillars; a bit line; the bit line extending along a second direction and connected to a first end of two ends of the semiconductor pillar opposite to each other along the first direction; the first direction being perpendicular to the second direction; and a first cavity; the first cavity being located between the bit line and the gate structure.

[0004] In an optional embodiment, a size of the first cavity along the second direction ranges from 10 nm to 60 nm, and / or a size of the first cavity along the first direction ranges from 10 nm to 100 nm.

[0005] In an optional embodiment, the first semiconductor structure includes a plurality of semiconductor pillars, and the plurality of semiconductor pillars constitute a plurality of semiconductor pillar groups, and the semiconductor pillar groups include first semiconductor pillars and second semiconductor pillars, both extending along the first direction and arranged along the second direction; the plurality of semiconductor pillar groups are arranged in an array along the second direction and a third direction; the third direction is perpendicular to the first direction and intersects with the second direction; the gate structure extends along the third direction and is located between the first semiconductor pillar and the second semiconductor pillar of the semiconductor pillar group.

[0006] In an optional embodiment, the first cavity extends along the third direction.

[0007] In an optional embodiment, the first surface of the gate structure is in the shape of an arc surface, and the first surface is a surface close to the bit line among two surfaces of the gate structure that are opposite to each other along the first direction.

[0008] In an optional embodiment, the first semiconductor structure further includes a dielectric layer; the dielectric layer is located between the first semiconductor column and the second semiconductor column of the semiconductor column group and is located on the side surface of the first semiconductor column, the side surface of the second semiconductor column, one of the two opposite surfaces of the gate structure along the first direction close to the bit line, and one of the two opposite surfaces of the bit line along the first direction close to the gate structure.

[0009] In an optional embodiment, the shape of one of the two opposite surfaces of the gate structure along the first direction and close to the bit line is the same as the shape of one of the two opposite surfaces of the gate structure along the first direction and close to the bit line.

[0010] In an optional embodiment, the first semiconductor structure further includes a second cavity; the second cavity is located between two adjacent semiconductor column groups along the second direction.

[0011] In an optional embodiment, a size of the second cavity along the second direction ranges from 10 nm to 60 nm.

[0012] In an optional embodiment, the dielectric layer is also located between the semiconductor column groups adjacent along the second direction and is located on the side of the first semiconductor column, the side of the second semiconductor column, and one of the two opposite surfaces of the bit line along the first direction close to the gate structure.

[0013] In an optional embodiment, the first semiconductor structure further includes a third cavity; the third cavity is located between adjacent bit lines along the third direction.

[0014] In an optional embodiment, the third cavity is connected to both the second cavity and the first cavity.

[0015] In an optional embodiment, a size of the third cavity along the third direction ranges from 5 nm to 50 nm.

[0016] In an optional embodiment, the dielectric layer is also located on a side of the bit line.

[0017] In an optional embodiment, the gate structure includes a first gate layer and a second gate layer arranged in parallel along the second direction, and both the first gate layer and the second gate layer extend along the third direction.

[0018] In an optional embodiment, the memory device further includes a second semiconductor structure; the first semiconductor structure and the second semiconductor structure are stacked along the first direction, and the second semiconductor structure includes a peripheral circuit.

[0019] In an optional embodiment, the first semiconductor structure further includes a plurality of storage structures, and the second end of the semiconductor pillar at two opposite ends along the first direction is connected to the storage structure.

[0020] According to a second aspect of an embodiment of the present disclosure, a method for manufacturing a memory device is provided, the manufacturing method including forming a first semiconductor structure, the forming of the first semiconductor structure including: forming semiconductor pillars; the semiconductor pillars extending along a first direction; forming a gate structure; the gate structure being located between adjacent semiconductor pillars; forming a bit line; the bit line extending along a second direction and being connected to a first end of two ends of the semiconductor pillars opposite to each other along the first direction; the first direction being perpendicular to the second direction; forming a first cavity; the first cavity being located between the bit line and the gate structure.

[0021] In an optional embodiment, forming the semiconductor pillar and forming the bit line includes: forming a plurality of semiconductor pillar groups and a plurality of initial bit lines; the plurality of semiconductor pillar groups are arranged in an array along a second direction and a third direction, the semiconductor pillar group includes a first semiconductor pillar and a second semiconductor pillar arranged along the second direction and both extending along the first direction; the initial bit line extends along the second direction and is located on a first side of the semiconductor pillar group; the second direction intersects with the third direction and is both perpendicular to the first direction; forming the gate structure and forming the first cavity include: forming a first sacrificial structure between the first semiconductor pillar and the second semiconductor pillar in the semiconductor pillar group from the second side; the first sacrificial structure extends along the third direction, and the size of the first sacrificial structure along the first direction is smaller than the size of the semiconductor pillar group along the first direction; the first side and the second side are opposite sides of the plurality of semiconductor pillar groups along the first direction; forming an initial gate structure covering the first sacrificial structure between the first semiconductor pillar and the second semiconductor pillar in the semiconductor pillar group from the second side; removing a portion of the first sacrificial structure and the initial gate structure from the first side to form a gate structure and a first cavity.

[0022] In an optional embodiment, the initial gate structure includes two side portions and a bottom, the side portions extend along the first direction, and the bottom extends along the second direction and connects the two side portions; removing the first sacrificial structure and a portion of the initial gate structure from the first side to form a gate structure and a first cavity includes: removing the first sacrificial structure from the first side to expose the bottom of the initial gate structure, and removing the exposed bottom from the first side to form the first cavity and a first gate layer and a second gate layer respectively formed by the two sides.

[0023] In an optional embodiment, forming the first semiconductor structure also includes: before forming the first sacrificial structure, forming a second sacrificial structure between the semiconductor column groups from the second side; the second sacrificial structure extends along the third direction; and removing the second sacrificial structure from the first side to form a second cavity.

[0024] In an optional embodiment, the first sacrificial structure and the second sacrificial structure are removed simultaneously.

[0025] In an optional embodiment, forming the first semiconductor structure further includes: forming a metal material layer on the initial bit line from the first side; and performing heat treatment on the metal material layer and the initial bit line to form a bit line.

[0026] In an optional embodiment, forming the first semiconductor structure further includes: before forming a metal material layer on the initial bit line from the first side, forming a third sacrificial structure in the first cavity, in the second cavity, and between adjacent initial bit lines; after forming the bit line, removing the third sacrificial structure, thereby forming a third cavity between adjacent bit lines.

[0027] In an optional embodiment, forming the first semiconductor structure also includes: after removing the third sacrificial structure, forming a dielectric layer from the first side on the exposed surface of the first semiconductor column, the exposed surface of the second semiconductor column, the exposed surface of the gate structure, and the exposed surface of the bit line.

[0028] In an optional embodiment, the formation of multiple semiconductor column groups and multiple initial bit lines includes: providing a base structure, and etching the base structure from the second side to form multiple first grooves; the multiple first grooves all extend along the second direction and are arranged along the third direction; etching the base structure from the second side to form multiple second grooves; the multiple second grooves all extend along the third direction and are arranged along the second direction; forming a fourth sacrificial structure in the second groove; etching the base structure from the second side to form multiple third grooves; the multiple third grooves all extend along the third direction and are arranged along the second direction, and the second grooves and the third grooves are arranged alternately along the second direction, and the depth of the first groove is greater than the depth of the second groove and the depth of the third groove; the first groove, the second groove, and the third groove divide the base structure into multiple semiconductor column groups and multiple initial bit lines.

[0029] In an optional embodiment, forming the second sacrificial structure includes: forming the second sacrificial structure in the third groove; and forming the first semiconductor structure further includes: after forming the second sacrificial structure, removing the fourth sacrificial structure from the second side.

[0030] In an optional embodiment, forming the first semiconductor structure further includes forming a plurality of storage structures; the second end of the two opposite ends of the semiconductor column along the first direction is connected to one of the storage structures.

[0031] In an optional embodiment, the manufacturing method further includes: forming a second semiconductor structure, the second semiconductor structure including a peripheral circuit; and bonding the first semiconductor structure and the second semiconductor structure.

[0032] In the embodiments of the present disclosure, firstly, a first cavity is formed between the bit line and the gate structure, thereby reducing interference between transistors on both sides of the first cavity, thereby improving the performance of the memory device. Secondly, in a corresponding formation method, a disconnection process of the initial gate structure is performed from the back side (first side) of the substrate structure to form the first gate layer and the second gate layer, without having to disconnect the initial gate structure from the front side of the substrate structure, thereby reducing the process difficulty. Thirdly, in a corresponding formation method, a first sacrificial structure is first formed from the front side (second side) of the substrate structure below the bottom of the initial gate structure, and after removing the first sacrificial structure from the back side (first side) of the substrate structure, the disconnection process of the initial gate structure is performed. In this way, the height of the two opposite ends of the final gate structure along the first direction, which are close to the bit line, can be controlled by controlling the size of the first sacrificial structure along the first direction, without having to remove a certain height from the side of the initial gate structure from the back side of the substrate structure. As a result, the height of the two opposite ends of the final gate structure along the first direction, which are close to the bit line, can be well controlled, and the height of the two opposite ends of different gate structures along the first direction, which are close to the bit line, is well uniform, thereby improving the performance of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic structural diagram of an electronic device provided in an embodiment of the present disclosure.

[0034] Figure 2 A schematic diagram of the structure of a memory provided in an embodiment of the present disclosure.

[0035] Figure 3 A schematic flow chart of a method for forming a memory device according to an embodiment of the present disclosure is provided.

[0036] Figures 4 to 42 A structural schematic diagram of a formation process of a memory device provided in an embodiment of the present disclosure.

[0037] Figure 43 A schematic diagram of a cross-sectional structure of a memory device provided in an embodiment of the present disclosure Figure 1 .

[0038] Figure 44 A schematic top view of the structure of a memory device provided in an embodiment of the present disclosure is shown.

[0039] Figure 45 A schematic diagram of a cross-sectional structure of a memory device provided in an embodiment of the present disclosure Figure 2 . DETAILED DESCRIPTION

[0040] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0041] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0042] In the drawings, like reference numerals refer to like elements throughout.

[0043] It should be understood that spatial relationship terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" can include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0044] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0045] Figure 1 1 is a schematic diagram of an electronic device 1 according to an embodiment of the present disclosure. The electronic device 1 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device.

[0046] like Figure 1 As shown in FIG, an electronic device 1 may include a host HOST and a memory system 30, the memory system 30 having one or more memories 20 and a controller 10. The host HOST may be a processor of the electronic device (e.g., a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP)). The host HOST may be configured to send data to the memory 20 or receive data from the memory 20. The controller 10 is coupled to the memory 20 and the host HOST and is configured to control the memory 20. The controller 10 may manage data stored in the memory 20 and communicate with the host HOST.

[0047] The controller 10 may be configured to control operations of the memory 20, such as read, erase, write, and refresh operations. In some embodiments, the controller 10 may also be configured to process error correction codes (ECC) on data read from or written to the memory 20. The controller 10 may also perform any other suitable functions, such as formatting the memory 20.

[0048] In some specific embodiments, the controller 10 and one or more memories 20 can be integrated into various types of storage devices. For example, the controller 10 can be integrated into the north bridge of a computer motherboard or directly integrated into the computer CPU, and the multiple memories 20 can be integrated into a memory module. In other words, the memory system 30 can be implemented and packaged into various types of terminal electronic products.

[0049] The controller 10 can send or receive data to or from the host HOST, and can send a command CMD and an address ADDR to the memory 20. The controller 10 may include a command generator 110, an address generator 120, a device interface 130, and a host interface 140. The host interface 140 may receive a command CMD and an address ADDR from the host HOST. The command generator 110 may generate an access command, a refresh command, etc. by decoding the command CMD received from the host HOST, and may provide the access command and the refresh command to the memory 20 through the device interface 130. An access command may be a signal instructing the memory 20 to write or read data by accessing a row of the memory cell array 220 corresponding to the address ADDR. A refresh command may be a signal instructing the memory 20 to read out and rewrite data by accessing a row of the memory cell array 220 corresponding to the refresh address ADDR.

[0050] The address generator 120 in the controller 10 can generate a row address and a column address to be accessed in the memory cell array 220 by decoding the address ADDR received from the host interface 140. In addition, the memory 20 can generate an address of a memory bank to be accessed when the memory cell array 220 includes a plurality of memory banks.

[0051] The controller 10 may control memory operations such as writing and reading by providing various signals to the memory 20 via the device interface 130. For example, the controller 10 may provide a write command to the memory 20. The write command is used to instruct the memory 20 to perform a write operation to store data in the memory 20.

[0052] In some embodiments, the memory 20 includes at least one chip, each chip includes at least one memory bank, each memory bank includes at least one memory block, and each memory block includes a memory cell array 220 and a peripheral circuit 210. The memory cell array includes a plurality of memory cell rows and a plurality of memory cell columns, each memory cell row is coupled to a corresponding word line, and each memory cell column is coupled to a corresponding bit line. The peripheral circuit 210 can write data to or read data from the memory cell array 220 based on a command CMD and an address ADDR received from the controller 10, or can provide a control signal CTRL for refreshing memory cells included in the memory cell array 220 to a row decoder and a column decoder. In other words, the peripheral circuit 210 can perform all operations to process the data in the memory cell array 220. The peripheral circuit 210 may include: a control circuit corresponding to each memory block, such as a sensing amplifier (SA) and a word-line driver (WLD), a control circuit corresponding to each memory bank, such as a row decoder and a column decoder, and a control circuit corresponding to all memory banks, such as a command buffer, a command decoder, an address buffer, a data input / output buffer, a mode register, etc.

[0053] The memory 20 may be a random access memory (RAM), such as a dynamic random access memory (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), double data rate SDRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), etc. The following description only uses DRAM as an example.

[0054] Figure 2 Schematic diagram of a dynamic random access memory according to an embodiment of the present disclosure. Figure 2As shown, the dynamic random access memory includes a memory cell array and peripheral circuits. The memory cell array includes a plurality of memory cells 201 arranged in an array. Each memory cell 201 includes a transistor T (Transistor) and a capacitor C (Capacitor). The word line is coupled to the gate of the transistor T, and the bit line is coupled to the drain of the transistor T. The main working principle of the memory cell is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The memory cells are arranged in an array, and the memory cell array uses rows (Row) and columns (Column) to specify the address. By specifying the intersection of rows and columns (by specifying the row address and column address of the DRAM), the controller can independently access each memory cell in the DRAM chip and read, write or refresh the data stored therein.

[0055] With the development of dynamic random access memory technology, the size of storage cells is getting smaller and smaller, and its array architecture is composed of 8F 2 Go to 6F 2 Then go to 4F 2 , the architecture of transistors in memory cells has also gradually evolved from planar array transistors to vertical gate transistors, thus forming a three-dimensional memory architecture.

[0056] In some embodiments, word lines in a vertical transistor architecture can be formed by forming a U-shaped conductive layer on the front side of the substrate, forming a dielectric layer at the bottom of the U-shaped conductive layer to control the height of the bottom of the U-shaped conductive layer, and then etching the bottom of the U-shaped conductive layer from the front side of the substrate, that is, disconnecting the U-shaped conductive layer to form two separated word lines. In the above embodiment, the process is relatively difficult due to the need to etch the bottom of the U-shaped conductive layer from the front side of the substrate. In other embodiments, word lines in a vertical transistor architecture can be formed by forming a U-shaped conductive layer on the front side of the substrate, removing the bottom of the U-shaped conductive layer from the back side of the substrate, that is, disconnecting the U-shaped conductive layer, and removing a portion of the side of the conductive layer from the back side of the substrate to control the height of the side of the conductive layer. However, in this embodiment, when a portion of the side of the conductive layer is removed from the back side of the substrate, the height of the side of the conductive layer is difficult to control, and the height of the side of the multiple conductive layers is difficult to achieve uniformity, which affects the performance of the memory.

[0057] In view of one or more of the above problems, an embodiment of the present disclosure provides a method for manufacturing a memory device, the method comprising forming a first semiconductor structure, such as Figure 3 As shown, forming the first semiconductor structure includes the following steps.

[0058] Step S100 : forming a semiconductor column; the semiconductor column extends along a first direction.

[0059] Step S200: forming a gate structure; the gate structure is located between adjacent semiconductor pillars.

[0060] Step S300 : forming a bit line; the bit line extends along a second direction and is connected to a first end of two opposite ends of the semiconductor pillar along the first direction; the first direction is perpendicular to the second direction.

[0061] Step S400: forming a first cavity; the first cavity is located between the bit line and the gate structure.

[0062] It should be understood that Figure 3 The steps shown in the operation are not exclusive, and other steps may be performed before, after, or between any steps in the operation shown; Figure 3 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0063] Figures 4 to 42 This is a schematic diagram of a process for forming a memory device according to an embodiment of the present disclosure. Figures 4 to 42 The method for forming the memory device provided in the embodiment of the present disclosure is exemplarily described.

[0064] In some embodiments, forming the semiconductor pillars and forming the bit lines include: forming a plurality of semiconductor pillar groups and a plurality of initial bit lines; the plurality of semiconductor pillar groups are arranged in an array along a second direction and a third direction, and the semiconductor pillar groups include first semiconductor pillars and second semiconductor pillars arranged along the second direction and both extending along the first direction; the initial bit lines extend along the second direction and are located on a first side of the semiconductor pillar groups; the second direction intersects with the third direction and are both perpendicular to the first direction.

[0065] Here, the second direction intersects the third direction. In the embodiments of the present disclosure, the second direction is perpendicular to the third direction as an example for illustrative description. In some specific examples, the first direction may be the Z-axis direction in the drawings of the present disclosure, the second direction may be the X-axis direction in the drawings of the present disclosure, and the third direction may be the Y-axis direction in the drawings of the present disclosure.

[0066] In some embodiments, as Figures 4 to 14As shown, the formation of multiple semiconductor column groups 307 and multiple initial bit lines 306 includes: providing a base structure 321, and etching the base structure 321 from the second side to form a plurality of first grooves 322; the plurality of first grooves 322 all extend along the second direction and are arranged along the third direction; etching the base structure 321 from the second side to form a plurality of second grooves 323; the plurality of second grooves 323 all extend along the third direction and are arranged along the second direction; forming a fourth sacrificial structure 324 in the second grooves 323; The base structure 321 is etched on the second side to form a plurality of third grooves 325; the plurality of third grooves 325 extend along the third direction and are arranged along the second direction, and the second grooves 323 and the third grooves 325 are alternately arranged along the second direction, and the depth of the first groove 322 is greater than the depth of the second groove 323 and the depth of the third groove 325; the first groove 322, the second groove 323, and the third groove 325 divide the base structure 321 into a plurality of semiconductor column groups 307 and a plurality of initial bit lines 306.

[0067] The base structure 321 includes a first side and a second side that are opposite to each other along a first direction. Figure 4 as well as Figure 5 As shown, a first groove 322 is formed by dry etching from the second side of the base structure 321, and the depth of the first groove 322 is H1. Figure 6 As shown, the first dielectric layer 333 may be filled in the first groove 322 by a deposition process. Figure 7 as well as Figure 8 As shown, a patterned mask layer 343 is formed on the substrate structure 321 from the second side of the substrate structure 321, and then a second groove 323 is formed by a dry etching process. The depth of the second groove 323 is H2, H1>H2. Figure 9 As shown, the surface of the base structure 321 exposed in the second groove 323 is oxidized from the second side of the base structure 321 to form a second dielectric layer 334 on the exposed surface of the base structure 321. Figure 10 As shown, a portion of the mask layer 343 is removed from the second side of the base structure 321, and the remaining mask layer 343 covers a portion of the top surface of the base structure 321 between the second grooves 323. Figure 11 As shown, a fourth sacrificial structure 324 is formed in the second groove 323 from the second side of the base structure 321. The fourth sacrificial structure 324 is also formed on the top surface of the base structure 321. The top surface of the fourth sacrificial structure 324 is flush with the top surface of the mask layer 343. Figure 12 As shown, the remaining mask layer 343 is removed from the second side of the base structure 321 to form a fourth groove 329, which extends along the third direction. Figure 13 as well as Figure 14 As shown, the base structure 321 is etched from the second side of the base structure 321 through the fourth groove 329 to form a third groove 325, which extends along the third direction. The depth of the third groove 325 is H3, H1>H3, and H2 and H3 can be equal or unequal.

[0068] The first groove 322, the second groove 323, and the third groove 325 divide the base structure 321 into a plurality of semiconductor pillars 302 and a plurality of initial bit lines 306. The plurality of semiconductor pillars constitute a plurality of semiconductor pillar groups 307. The semiconductor pillar groups 307 include first semiconductor pillars 308 and second semiconductor pillars 309 arranged along the second direction. The initial bit lines 306 extend along the second direction, and the plurality of initial bit lines 306 are arranged along the third direction. In subsequent processes, the base structure 321 can be thinned from the first side thereof to expose the first dielectric layer 333. Here, the first side of the base structure 321 and the first side of the semiconductor pillar group 307 can be understood as the same side, and the second side of the base structure 321 and the second side of the semiconductor pillar group 307 can be understood as the same side.

[0069] Figure 4 for Figure 5 Schematic diagram of the top view of the structure, Figure 7 for Figure 8 Schematic diagram of the top view of the structure, Figure 13 for Figure 14 It should be noted that, Figure 4 、 Figure 7 、 Figure 13 It is a perspective view, in which some structures are omitted.

[0070] In the embodiments of the present disclosure, the deposition process includes but is not limited to chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

[0071] In some specific examples, the material of the first dielectric layer 333 includes, but is not limited to, silicon nitride and silicon oxide; the material of the second dielectric layer 334 includes, but is not limited to, silicon oxide. The material of the fourth sacrificial structure 324 includes, but is not limited to, tungsten. When selecting the material for the fourth sacrificial structure 324, consideration must be given to ensuring that the impact on the fourth sacrificial structure 324 during the subsequent formation of the third and fourth recesses is within an acceptable range. Furthermore, consideration must be given to ensuring that the impact on the fourth dielectric layer 336 during the subsequent removal of the fourth sacrificial structure 324 is within an acceptable range.

[0072] In some embodiments, forming the first semiconductor structure further includes: before forming the first sacrificial structure, forming a second sacrificial structure between the semiconductor pillar groups from the second side; the second sacrificial structure extends along the third direction.

[0073] In some embodiments, forming the second sacrificial structure includes: forming the second sacrificial structure in the third groove; and forming the first semiconductor structure further includes: removing the fourth sacrificial structure from the second side after forming the second sacrificial structure.

[0074] like Figure 15 As shown, a third dielectric layer 335 is formed by a deposition process to cover the sidewalls of the fourth groove 329, the sidewalls of the third groove 325, the bottom wall of the third groove 325, and the top surface of the fourth sacrificial structure 324. Figure 16 As shown, a second sacrificial layer 339 is formed in the third groove 325 and the fourth groove 329, and the second sacrificial layer 339 is also formed on the fourth sacrificial structure 324. Figure 17 As shown, a portion of the second sacrificial layer 339 is removed to form a fifth groove 330, which is located between adjacent fourth sacrificial structures 324. The top surface of the remaining second sacrificial layer 339 is lower than the top surface of the base structure 321, and the remaining second sacrificial layer 339 constitutes the second sacrificial structure 316. Figure 18 As shown, a fourth dielectric layer 336 is formed in the fifth groove 330 and on the fourth sacrificial structure 324. Figure 19 As shown, a portion of the fourth dielectric layer 336 is removed by a planarization process, and the top surface of the remaining fourth dielectric layer 336 is flush with the top surface of the fourth sacrificial structure 324. Figure 20 As shown, the fourth sacrificial structure 324 can be removed by a wet etching process. Figure 21 As shown, the second dielectric layer 334 is removed from the first side.

[0075] In some specific examples, the material of the third dielectric layer 335 includes, but is not limited to, silicon oxide and silicon nitride; the material of the fourth dielectric layer 336 includes, but is not limited to, silicon oxide and silicon nitride. The material of the second sacrificial structure 316 includes, but is not limited to, at least one of titanium nitride, silicon nitride, carbon, tungsten, molybdenum, and aluminum oxide.

[0076] In some specific examples, the base structure 321 may be a substrate, which may include a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (e.g., a silicon-germanium (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.

[0077] In some embodiments, forming the gate structure and forming the first cavity include: forming a first sacrificial structure between the first semiconductor column and the second semiconductor column in the semiconductor column group from the second side; the first sacrificial structure extends along the third direction, and the size of the first sacrificial structure along the first direction is smaller than the size of the semiconductor column group along the first direction; the first side and the second side are two opposite sides of the multiple semiconductor column groups along the first direction.

[0078] In some specific examples, such as Figure 22 As shown, a first sacrificial layer 340 is formed in the second groove 323, and the first sacrificial layer 340 is also formed on the top surface of the base structure 321. Figure 23 As shown, a portion of the first sacrificial layer 340 is removed to form a sixth groove 331, so that the top surface of the remaining first sacrificial layer 340 is lower than the top surface of the base structure 321, and the remaining first sacrificial layer 340 constitutes the first sacrificial structure 310. The sixth groove 331 is located between the first semiconductor pillar 308 and the second semiconductor pillar 309 of the semiconductor pillar group 307, and the sixth groove 331 extends along the third direction.

[0079] In some specific examples, the material of the first sacrificial structure 310 includes, but is not limited to, at least one of titanium nitride, silicon nitride, carbon, tungsten, molybdenum, and aluminum oxide.

[0080] In some specific examples, the material of the first sacrificial structure 310 and the material of the second sacrificial structure 316 may be the same or different. When the material of the first sacrificial structure 310 and the material of the second sacrificial structure 316 are the same, the first sacrificial structure 310 and the second sacrificial structure 316 can be removed simultaneously in a subsequent process. When the material of the first sacrificial structure 310 and the material of the second sacrificial structure 316 are different, the first sacrificial structure 310 and the second sacrificial structure 316 can be removed in separate steps in a subsequent process.

[0081] In some embodiments, an initial gate structure covering the first sacrificial structure is formed between a first semiconductor pillar and a second semiconductor pillar in the group of semiconductor pillars from the second side.

[0082] In some embodiments, the initial gate structure includes two side portions and a bottom portion, the side portions extending along the first direction, and the bottom portion extending along the second direction and connecting the two side portions.

[0083] like Figure 24 As shown, a fifth dielectric layer 337 is formed on the sidewalls of the sixth groove 331, the bottom wall of the sixth groove 331, the top surface of the base structure 321 and the top surface of the fourth dielectric layer 336. Figure 25 As shown, a first conductive layer 341 is formed covering the fifth dielectric layer 337. Figure 26 As described above, a sixth dielectric layer 344 is formed to cover the first conductive layer 341. Figure 27 As shown, a planarization process is performed to disconnect the first conductive layer 341 in the adjacent sixth groove 331. Figure 28 As shown, a portion of the first conductive layer 341 is removed to form a seventh groove 332, so that the top surface of the remaining first conductive layer 341 is lower than the top surface of the base structure 321. Figure 29 As shown, a seventh dielectric layer 338 is formed in the seventh groove 332 and on the base structure 321. Figure 30 As shown, a planarization process is performed to expose the top surface of the base structure 321 . Figure 30 The initial gate structure 311 shown in the figure includes the remaining first conductive layer 341 and the remaining fifth dielectric layer 337. The initial gate structure 311 extends along the third direction and includes two side portions 312 extending along the first direction and two bottom portions 313 extending along the second direction.

[0084] In some specific examples, the material of the fifth dielectric layer 337 includes, but is not limited to, silicon oxide and silicon nitride. The material of the first conductive layer 341 includes, but is not limited to, at least one of titanium nitride and tungsten. The first conductive layer 341 may include a first sub-conductive layer and a second sub-conductive layer. The material of the sixth dielectric layer 344 includes, but is not limited to, silicon oxide and silicon nitride. The material of the seventh dielectric layer 338 includes, but is not limited to, silicon oxide and silicon nitride.

[0085] In some embodiments, the first sacrificial structure and a portion of the initial gate structure are removed from the first side to form a gate structure and a first cavity.

[0086] In some embodiments, removing the first sacrificial structure and a portion of the initial gate structure from the first side to form a gate structure and a first cavity includes: removing the first sacrificial structure from the first side to expose the bottom of the initial gate structure, and removing the exposed bottom from the first side to form the first cavity and a first gate layer and a second gate layer respectively formed by the two sides.

[0087] In some embodiments, forming the first semiconductor structure further includes: removing the second sacrificial structure from the first side to form a second cavity.

[0088] like Figure 31 As shown, the first side of the base structure 321 faces upward and the second side faces downward. In some specific examples, the base structure 321 can be thinned from the first side to expose the first dielectric layer 333 and the initial bit line 306, and a portion of the first dielectric layer 333 is removed to expose the third dielectric layer 335. Figure 32 As shown, a portion of the third dielectric layer 335 is removed from the first side, so that the second sacrificial structure 316 is exposed. Figure 33 As shown, the second sacrificial structure 316 is removed from the first side to form a second cavity 317. In some specific examples, when a portion of the first dielectric layer 333 is removed to expose the third dielectric layer 335, the first sacrificial structure 310 is also exposed. Figure 34 As shown, the first sacrificial structure 310 is removed to form a first cavity 305, and the bottom 313 of the initial gate structure 311 is exposed. Figure 35 As shown, the remaining third dielectric layer 335 is removed. Figure 36 As shown, the bottom 313 exposed by the initial gate structure 311 is removed from the first side, and the first conductive layer 341 in the two side portions 312 of the remaining initial gate structure 311 respectively constitutes a first gate layer 314 and a second gate layer 315, and the fifth dielectric layer 337 in the two side portions 312 of the remaining initial gate structure 311 can constitute two gate insulating layers, where the first gate layer 314 and the second gate layer 315 can be word lines.

[0089] In the embodiment of the present disclosure, on the one hand, the initial gate structure 311 is disconnected from the back side (first side) of the base structure 321 to form the first gate layer 314 and the second gate layer 315. It is not necessary to disconnect the initial gate structure 311 on the front side of the base structure 321, and the process difficulty is small. On the other hand, the first sacrificial structure 310 is first formed at the bottom 313 of the initial gate structure 311. After removing the first sacrificial structure 310 from the back side (first side) of the base structure 321, the disconnection process of the initial gate structure 311 is performed. In this way, the height of the two opposite ends of the finally formed gate structure along the first direction, which is close to the bit line, can be controlled by controlling the size of the first sacrificial structure 310 along the first direction, without the need to disconnect the initial gate structure 311 from the base structure 321. A certain height is removed from the side of the initial gate structure 311 on the back side, so that the height of the gate structure formed in the final stage near the bit line at both ends opposite to each other along the first direction can be better controlled, and the height uniformity of the different gate structures in the stage near the bit line at both ends opposite to each other along the first direction is better, thereby improving the performance of the memory device; thirdly, a first cavity 305 is formed between the bit line and the gate structure, so that the interference between the transistors on both sides of the first cavity 305 is reduced, thereby improving the performance of the memory device; fourthly, a second cavity 317 can be formed from the back side of the substrate structure 321, so as to reduce the interference between the transistors on both sides of the second cavity 317 and the interference of the gate structures on both sides of the second cavity 317.

[0090] In some embodiments, removing the first sacrificial structure 310 and removing the second sacrificial structure 316 are performed simultaneously.

[0091] It is understandable that when the first sacrificial structure 310 and the second sacrificial structure 316 are made of the same material, removing the first sacrificial structure 310 and the second sacrificial structure 316 simultaneously can save process flow and process costs.

[0092] In some embodiments, forming the first semiconductor structure further includes: forming a third sacrificial structure in the first cavity, in the second cavity, and between adjacent initial bit lines before forming a metal material layer on the initial bit lines from the first side.

[0093] In some specific examples, the material of the third sacrificial structure 318 includes but is not limited to carbon. In some specific examples, such as Figure 37 As shown, a third sacrificial layer 342 is formed in the first cavity 305, in the second cavity 317, between adjacent initial bit lines 306, and on the first side of the base structure 321. Figure 38 As shown, a planarization process is performed to remove a portion of the third sacrificial layer 342 , so that the base structure 321 is exposed, and the remaining third sacrificial layer 342 constitutes a third sacrificial structure 318 .

[0094] In some embodiments, as Figures 39 to 41 As shown, forming the first semiconductor structure also includes: forming a metal material layer on the initial bit line 306 from the first side; heat treating the metal material layer and the initial bit line 306 to form a bit line 304; after forming the bit line 304, removing the third sacrificial structure 318, thereby forming a third cavity 319 between adjacent bit lines 304.

[0095] Figure 40 for Figure 41 It should be noted that, Figure 40 In order to show the bit line and the third cavity more clearly, Figure 40 It is a perspective view, in which some structures are omitted.

[0096] In some specific examples, the material of the metal material layer includes but is not limited to metal nickel.

[0097] In some embodiments, as Figure 42 As shown, forming the first semiconductor structure also includes: after removing the third sacrificial structure 318, forming a dielectric layer 320 from the first side on the surface exposed by the first semiconductor pillar 308, the surface exposed by the second semiconductor pillar 309, the surface exposed by the gate structure 303, and the surface exposed by the bit line 304.

[0098] In some specific examples, the material of the dielectric layer 320 includes but is not limited to silicon oxide and silicon nitride.

[0099] In some embodiments, forming the first semiconductor structure further includes forming a plurality of storage structures; the second end of the semiconductor pillar 302 , of the two opposite ends along the first direction, is connected to one of the storage structures.

[0100] The storage structure here includes a storage capacitor. The storage capacitor includes a first plate, a second plate, and a dielectric layer located between the first plate and the second plate. In some specific examples, the first plate can be used as the lower electrode of the storage capacitor, and the second plate can be used as the upper electrode of the storage capacitor. The material of the dielectric layer includes a high dielectric constant (High-K) material. Exemplarily, the material of the dielectric layer may include but is not limited to aluminum oxide (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), etc. The material of the first plate may include a conductive material, and exemplarily, it may be titanium nitride. The material of the second plate may include a conductive material, and exemplarily, it may be titanium nitride or silicon germanium.

[0101] In some embodiments, the manufacturing method further includes: forming a second semiconductor structure, wherein the second semiconductor structure includes a peripheral circuit; and bonding the first semiconductor structure and the second semiconductor structure.

[0102] In some specific examples, the first semiconductor structure and the second semiconductor structure may be bonded using a hybrid bonding process.

[0103] It should be noted that the embodiments of the present disclosure are not limited to the solution of bonding the first semiconductor structure and the second semiconductor structure mentioned in the above embodiments. In the present disclosure, the first semiconductor structure and the second semiconductor structure can also be formed on the same wafer.

[0104] Based on a concept similar to the manufacturing method of the memory device in the above embodiment, the embodiment of the present disclosure further provides a memory device, such as Figures 43 to 45 As shown, the memory device 300 includes a first semiconductor structure 301, and the first semiconductor structure 301 includes: a semiconductor pillar 302; the semiconductor pillar 302 extends along a first direction; a gate structure 303; the gate structure 303 is located between adjacent semiconductor pillars 302; a bit line 304; the bit line 304 extends along a second direction and is connected to the first end of the two ends of the semiconductor pillar 302 opposite to each other along the first direction; the first direction is perpendicular to the second direction; a first cavity 305; the first cavity 305 is located between the bit line 304 and the gate structure 303.

[0105] In the embodiment of the present disclosure, firstly, a first cavity 305 is formed between the bit line 304 and the gate structure 303, so that the interference between the transistors on both sides of the first cavity 305 is reduced, thereby improving the performance of the memory device; secondly, in the corresponding formation method, the initial gate structure 311 is disconnected from the back side (first side) of the substrate structure 321 to form the first gate layer 314 and the second gate layer 315, without the need to disconnect the initial gate structure 311 from the front side of the substrate structure 321, and the process difficulty is small; thirdly, in the corresponding formation method, the first sacrificial structure 310 is first formed under the bottom 313 of the initial gate structure 311 from the front side (second side) of the substrate structure, and the first sacrificial structure 310 is formed from the front side (second side) of the substrate structure. After removing the first sacrificial structure 310 from the back side (first side) of the substrate structure 321, the disconnection process of the initial gate structure 311 is performed, so that the height of the two ends of the gate structure 303 opposite to each other along the first direction close to the bit line 304 can be controlled by controlling the size of the first sacrificial structure 310 along the first direction, without removing a certain height of the side of the initial gate structure 311 from the back side of the substrate structure 321, so that the height of the two ends of the gate structure 303 opposite to each other along the first direction close to the bit line 304 can be better controlled, and the height uniformity of the two ends of different gate structures 303 opposite to each other along the first direction close to the bit line 304 is better, thereby improving the performance of the memory device.

[0106] Figure 44 for Figure 43 It should be noted that, Figure 44 In order to more clearly show the bit line 304, the third cavity 319 and the dielectric layer 320, Figure 40 It is a perspective view, in which some structures are omitted.

[0107] In some specific examples, the material of the bit line 304 may include a conductive material, including a metal material, a metal silicide, the metal material including but not limited to tungsten, titanium, tantalum, aluminum, etc., and the metal silicide including but not limited to tungsten silicide, nickel silicide, cobalt silicide and titanium silicide.

[0108] In some embodiments, a size of the first cavity 305 along the second direction ranges from 10 nm to 60 nm, and / or a size of the first cavity 305 along the first direction ranges from 10 nm to 100 nm.

[0109] In some embodiments, the first semiconductor structure 301 includes a plurality of semiconductor pillars 302, and the plurality of semiconductor pillars 302 constitute a plurality of semiconductor pillar groups 307, and the semiconductor pillar groups 307 include first semiconductor pillars 308 and second semiconductor pillars 309, both extending along the first direction and arranged along the second direction; the plurality of semiconductor pillar groups 307 are arranged in an array along the second direction and a third direction; the third direction is perpendicular to the first direction and intersects with the second direction; the gate structure 303 extends along the third direction and is located between the first semiconductor pillar 308 and the second semiconductor pillar 309 of the semiconductor pillar group 307.

[0110] In some embodiments, the first cavity 305 extends along the third direction.

[0111] In some embodiments, the first surface of the gate structure 303 is an arc surface, and the first surface is a surface close to the bit line 304 among two surfaces of the gate structure 303 that are opposite to each other along the first direction.

[0112] It should be noted that the shape of the first surface of the gate structure 303 in the above embodiment is only an example and is not used to limit the shape of the first surface of the gate structure in the embodiment of the present disclosure. In the embodiment of the present disclosure, the bottom of the initial gate structure is removed from the back side of the base structure to form the gate structure. The shape of the first surface of the gate structure can also be other shapes formed by this method.

[0113] In some embodiments, the first semiconductor structure 301 further includes a dielectric layer 320; the dielectric layer 320 is located between the first semiconductor column 308 and the second semiconductor column 309 of the semiconductor column group 307 and is located on the side of the first semiconductor column 308, the side of the second semiconductor column 309, one of the two opposite surfaces of the gate structure 303 along the first direction close to the bit line 304, and one of the two opposite surfaces of the bit line 304 along the first direction close to the gate structure 303.

[0114] In some specific examples, the material of the dielectric layer 320 includes but is not limited to silicon nitride and silicon oxide.

[0115] In some embodiments, the shape of one of the two opposite surfaces of the gate structure 303 along the first direction and the one of the two opposite surfaces of the gate structure 303 along the first direction and the shape of the one of the two opposite surfaces of the gate structure 303 and the one of the bit line 304 is the same.

[0116] In some embodiments, the first semiconductor structure 301 further includes a second cavity 317 ; the second cavity 317 is located between two adjacent semiconductor column groups 307 along the second direction.

[0117] In the embodiment of the present disclosure, the second cavity 317 is located between two semiconductor column groups 307 adjacent to each other along the second direction, so that interference between transistors on both sides of the second cavity 317 and interference with the gate structures 303 on both sides of the second cavity 317 can be reduced.

[0118] In some embodiments, a size of the second cavity 317 along the second direction ranges from 10 nm to 60 nm.

[0119] In the embodiment of the present disclosure, as the memory device continues to shrink, the size of the formed second cavity along the second direction is relatively large, so that it has a better effect of reducing the interference between the transistors on both sides of the second cavity 317 and reducing the interference of the gate structure 303 on both sides of the second cavity 317.

[0120] In some embodiments, the dielectric layer 320 is also located between the semiconductor column groups 307 adjacent along the second direction and is located on the side of the first semiconductor column 308, the side of the second semiconductor column 309, and one of the two opposite surfaces of the bit line 304 along the first direction close to the gate structure 303.

[0121] In some embodiments, the first semiconductor structure 301 further includes a third cavity 319 ; the third cavity 319 is located between adjacent bit lines 304 along the third direction.

[0122] In the embodiment of the present disclosure, a third cavity 319 is formed between adjacent bit lines 304 , so that interference between adjacent bit lines 304 can be reduced, thereby improving the performance of the memory device.

[0123] In some embodiments, the third cavity 319 is in communication with both the second cavity 317 and the first cavity 305 .

[0124] In some embodiments, a size of the third cavity 319 along the third direction ranges from 5 nm to 50 nm.

[0125] In some embodiments, the dielectric layer 320 is further located on a side of the bit line 304 .

[0126] In some embodiments, the gate structure 303 includes a first gate layer 314 and a second gate layer 315 arranged in parallel along the second direction, and both the first gate layer 314 and the second gate layer 315 extend along the third direction.

[0127] In some embodiments, gate structure 303 includes a gate and a gate insulating layer. The gate includes a first gate layer 314 and a second gate layer 315, which form two word lines. First gate layer 314 and second gate layer 315 are separated by a corresponding dielectric layer 320. The gate material includes a conductive material, such as at least one of tungsten, tantalum, titanium, nickel, platinum, titanium nitride, tungsten nitride, and tantalum nitride. The gate insulating layer material includes, but is not limited to, silicon oxide, silicon nitride, or silicon oxynitride.

[0128] In some embodiments, the memory device 300 further includes a second semiconductor structure 327 ; the first semiconductor structure 301 and the second semiconductor structure 327 are stacked along the first direction, and the second semiconductor structure 327 includes a peripheral circuit 328 .

[0129] In some specific examples, the first semiconductor structure 301 and the second semiconductor structure 327 can be arranged side by side in a direction perpendicular to the first direction, or they can be stacked and arranged along the first direction. Compared with the solution in which the first semiconductor structure 301 and the second semiconductor structure 327 are arranged side by side in a direction perpendicular to the first direction, the stacking arrangement of the first semiconductor structure 301 and the second semiconductor structure 327 along the first direction can save more area of ​​the memory device. The first direction here can be understood as the thickness direction of the memory device, which is also the extension direction of the semiconductor column 302. The first semiconductor structure 301 and the second semiconductor structure 327 can be formed on the same wafer; or the first semiconductor structure 301 and the second semiconductor structure 327 can be formed on different wafers, and then the first semiconductor structure 301 and the second semiconductor structure 327 are bonded so that the first semiconductor structure 301 and the second semiconductor structure 327 are stacked and arranged along the first direction.

[0130] In some embodiments, the first semiconductor structure 301 further includes a plurality of storage structures 326 , and the second ends of the semiconductor pillars 302 , which are opposite to each other along the first direction, are connected to the storage structures 326 .

[0131] The storage structure here includes a storage capacitor. The storage capacitor includes a first plate, a second plate, and a dielectric layer located between the first plate and the second plate. In some specific examples, the first plate can be used as the lower electrode of the storage capacitor, and the second plate can be used as the upper electrode of the storage capacitor. The material of the dielectric layer includes a high dielectric constant (High-K) material. Exemplarily, the material of the dielectric layer may include but is not limited to aluminum oxide (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), etc. The material of the first plate may include a conductive material, and exemplarily, it may be titanium nitride. The material of the second plate may include a conductive material, and exemplarily, it may be titanium nitride or silicon germanium.

[0132] It should be noted that, in the embodiment of the present disclosure, a storage unit including a capacitor and a transistor (1T1C) is used as an example for description, but the present disclosure is not limited to this. The storage unit in the present disclosure may also be a capacitor-free architecture of nT0C, and the present disclosure does not limit this.

[0133] The memory 20 in the embodiment of the present disclosure includes the memory device 300 in the above embodiment.

[0134] Based on a concept similar to the memory in the above embodiments, the embodiment of the present disclosure further provides a memory system 30 , which includes a controller 10 and a memory 20 as described in any of the above embodiments; the controller 10 is configured to control the memory 20 .

[0135] Regarding the memory system 30, the above embodiments have been described. Figure 1 For the sake of brevity, we will not go into details here.

[0136] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0137] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0138] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A memory device, characterized in that: The memory device includes a first semiconductor structure comprising: A semiconductor column; the semiconductor column extends along a first direction; A gate structure; the gate structure is located between adjacent semiconductor pillars; A bit line; the bit line extends along a second direction and is connected to a first end of two ends of the semiconductor pillar opposite to each other along the first direction; the first direction is perpendicular to the second direction; A first cavity is located between the bit line and the gate structure.

2. The memory device according to claim 1, wherein The size of the first cavity along the second direction ranges from 10 nm to 60 nm, and / or the size of the first cavity along the first direction ranges from 10 nm to 100 nm.

3. The memory device according to claim 1, wherein: The first semiconductor structure includes a plurality of semiconductor pillars, the plurality of semiconductor pillars forming a plurality of semiconductor pillar groups, the semiconductor pillar groups including a first semiconductor pillar and a second semiconductor pillar both extending along the first direction and arranged along the second direction; the plurality of semiconductor pillar groups are arranged in an array along the second direction and a third direction; the third direction is perpendicular to the first direction and intersects the second direction; The gate structure extends along the third direction and is located between the first semiconductor pillar and the second semiconductor pillar of the semiconductor pillar group.

4. The memory device according to claim 3, wherein: The first cavity extends along the third direction.

5. The memory device according to claim 3, wherein: The first surface of the gate structure is in the shape of an arc surface, and the first surface is a surface close to the bit line among two surfaces of the gate structure that are opposite to each other along the first direction.

6. The memory device according to claim 3, wherein: The first semiconductor structure also includes a dielectric layer; the dielectric layer is located between the first semiconductor column and the second semiconductor column of the semiconductor column group and is located on the side of the first semiconductor column, the side of the second semiconductor column, one of the two opposite surfaces of the gate structure along the first direction close to the bit line, and one of the two opposite surfaces of the bit line along the first direction close to the gate structure.

7. The memory device according to claim 6, wherein: The shape of one of two opposite surfaces of the portion of the dielectric layer covering the gate structure along the first direction and close to the bit line is the same as the shape of one of two opposite surfaces of the gate structure along the first direction and close to the bit line.

8. The memory device according to claim 6, wherein: The first semiconductor structure further includes a second cavity; the second cavity is located between two adjacent semiconductor column groups along the second direction.

9. The memory device according to claim 8, wherein: A size of the second cavity along the second direction ranges from 10 nm to 60 nm.

10. The memory device according to claim 8, wherein: The dielectric layer is also located between the semiconductor pillar groups adjacent to each other along the second direction and on a side surface of the first semiconductor pillar, a side surface of the second semiconductor pillar, and one of two opposite surfaces of the bit line along the first direction close to the gate structure.

11. The memory device according to claim 8, wherein The first semiconductor structure further includes a third cavity; the third cavity is located between bit lines adjacent to each other along the third direction.

12. The memory device according to claim 11, wherein: The third cavity is communicated with both the second cavity and the first cavity.

13. The memory device according to claim 11, wherein: The size of the third cavity along the third direction ranges from 5 nm to 50 nm.

14. The memory device according to claim 11, wherein: The dielectric layer is also located on a side of the bit line.

15. The memory device according to claim 3, wherein: The gate structure includes a first gate layer and a second gate layer arranged in parallel along the second direction, and both the first gate layer and the second gate layer extend along the third direction.

16. The memory device according to claim 1, wherein: The memory device further includes a second semiconductor structure; the first semiconductor structure and the second semiconductor structure are stacked along the first direction, and the second semiconductor structure includes a peripheral circuit.

17. The memory device according to claim 1, wherein: The first semiconductor structure further includes a plurality of storage structures, and the second end of the semiconductor pillar at two opposite ends along the first direction is connected to the storage structure.

18. A method for manufacturing a memory device, characterized in that: The manufacturing method includes forming a first semiconductor structure, and forming the first semiconductor structure includes: forming a semiconductor column; wherein the semiconductor column extends along a first direction; forming a gate structure; the gate structure is located between adjacent semiconductor pillars; forming a bit line; the bit line extends along a second direction and is connected to a first end of two opposite ends of the semiconductor pillar along the first direction; the first direction is perpendicular to the second direction; A first cavity is formed; the first cavity is located between the bit line and the gate structure.

19. The manufacturing method according to claim 18, characterized in that: Forming the semiconductor pillar and forming the bit line includes: A plurality of semiconductor pillar groups and a plurality of initial bit lines are formed; the plurality of semiconductor pillar groups are arranged in an array along a second direction and a third direction, the semiconductor pillar groups include first semiconductor pillars and second semiconductor pillars arranged along the second direction and both extending along the first direction; the initial bit lines extend along the second direction and are located on a first side of the semiconductor pillar groups; the second direction intersects the third direction and is perpendicular to the first direction; Forming the gate structure and forming the first cavity includes: A first sacrificial structure is formed between a first semiconductor pillar and a second semiconductor pillar in the semiconductor pillar group from the second side; the first sacrificial structure extends along the third direction, and a size of the first sacrificial structure along the first direction is smaller than a size of the semiconductor pillar group along the first direction; the first side and the second side are two opposite sides of the plurality of semiconductor pillar groups along the first direction; forming an initial gate structure covering the first sacrificial structure between the first semiconductor pillar and the second semiconductor pillar in the semiconductor pillar group from the second side; The first sacrificial structure and a portion of the initial gate structure are removed from the first side to form a gate structure and a first cavity.

20. The manufacturing method according to claim 19, characterized in that The initial gate structure includes two side portions and a bottom portion, wherein the side portions extend along the first direction, and the bottom portion extends along the second direction and connects the two side portions; and removing the first sacrificial structure and a portion of the initial gate structure from the first side to form a gate structure and a first cavity, comprising: The first sacrificial structure is removed from the first side to expose the bottom of the initial gate structure, and the exposed bottom is removed from the first side to form the first cavity and the first gate layer and the second gate layer respectively constituted by the two sides.

21. The manufacturing method according to claim 19, characterized in that Forming the first semiconductor structure further includes: Before forming the first sacrificial structure, forming a second sacrificial structure between the semiconductor pillar groups from the second side; the second sacrificial structure extends along the third direction; The second sacrificial structure is removed from the first side to form a second cavity.

22. The manufacturing method according to claim 21, characterized in that Removing the first sacrificial structure and removing the second sacrificial structure are performed simultaneously.

23. The manufacturing method according to claim 21, characterized in that Forming the first semiconductor structure further includes: forming a metal material layer on the initial bit line from the first side; The metal material layer and the initial bit line are thermally treated to form a bit line.

24. The manufacturing method according to claim 23, characterized in that Forming the first semiconductor structure further includes: Before forming a metal material layer on the initial bit line from the first side, forming a third sacrificial structure in the first cavity, in the second cavity, and between adjacent initial bit lines; After forming the bit lines, the third sacrificial structure is removed, thereby forming a third cavity between adjacent bit lines.

25. The manufacturing method according to claim 24, characterized in that Forming the first semiconductor structure further includes: After removing the third sacrificial structure, a dielectric layer is formed from the first side on the exposed surface of the first semiconductor pillar, the exposed surface of the second semiconductor pillar, the exposed surface of the gate structure, and the exposed surface of the bit line.

26. The manufacturing method according to claim 21, characterized in that The forming of a plurality of semiconductor pillar groups and a plurality of initial bit lines comprises: Providing a base structure, and etching the base structure from the second side to form a plurality of first grooves; the plurality of first grooves all extend along the second direction and are arranged along the third direction; Etching the base structure from the second side to form a plurality of second grooves; the plurality of second grooves all extend along the third direction and are arranged along the second direction; forming a fourth sacrificial structure in the second groove; The base structure is etched from the second side to form a plurality of third grooves; the plurality of third grooves all extend along the third direction and are arranged along the second direction, and the second grooves and the third grooves are alternately arranged along the second direction, and the depth of the first groove is greater than the depth of the second groove and the depth of the third groove; the first groove, the second groove, and the third groove divide the base structure into a plurality of semiconductor column groups and a plurality of initial bit lines.

27. The manufacturing method according to claim 26, characterized in that Forming the second sacrificial structure includes: forming the second sacrificial structure in the third groove; Forming the first semiconductor structure further includes: After forming the second sacrificial structure, the fourth sacrificial structure is removed from the second side.

28. The manufacturing method according to claim 18, characterized in that Forming the first semiconductor structure further includes forming a plurality of storage structures; the second end of the semiconductor pillar at two opposite ends along the first direction is connected to one of the storage structures.

29. The manufacturing method according to claim 18, characterized in that The manufacturing method further comprises: forming a second semiconductor structure, the second semiconductor structure including a peripheral circuit; The first semiconductor structure and the second semiconductor structure are bonded together.

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