Dynamic random access memory
By adopting a two-transistor memory cell design and stacking structure, the problem of high aspect ratio limitation of capacitors in three-dimensional dynamic random access memory is solved, and a three-dimensional dynamic random access memory with high integration and no floating body effect is realized.
Patent Information
- Application Number
- CN202411235059.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-04-15
- Filing Date
- 2024-09-04
- Publication Date
- 2025-10-21
AI Technical Summary
Existing three-dimensional dynamic random access memory is limited by the high aspect ratio of capacitors, and traditional memory cell designs are difficult to shrink. In particular, dynamic random access memory with a 1T1C structure encounters difficulties in increasing its integration density.
A memory cell design includes two transistors, one of which acts as a capacitor. The floating body effect is eliminated through a stacked structure and wire connection. No selection transistor is required to select the memory cell, and operation is performed using a combination of bit lines, word lines, source lines, and drain lines.
A three-dimensional dynamic random access memory is realized without the need for high-dielectric-constant capacitors, which improves the integration level, eliminates the floating body effect, and simplifies the operation process.
Smart Images
Figure CN120825934A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a memory, and more particularly to a three-dimensional (3D) dynamic random access memory (DRAM). Background Art
[0002] With the rapid advancement of technology, dynamic random access memory (DRAM) designs are shrinking in size and moving towards higher integration to meet consumer demand for miniaturized electronic devices. However, for DRAM consisting of one transistor and one capacitor (1T1C), shrinking in size is even more challenging. Therefore, three-dimensional DRAM has been proposed to overcome this problem. However, conventional 3D DRAM is still limited by the high aspect ratio of the capacitors. Summary of the Invention
[0003] The present invention is directed to a dynamic random access memory, wherein a memory cell includes two transistors, and one of the transistors is used as a capacitor.
[0004] The dynamic random access memory of the present invention includes a first channel, a second channel, a storage node, a bit line, a word line, a first conductive line, a first dielectric layer, a second dielectric layer, a second conductive line, a source line, and a drain line. The first channel and the second channel are arranged on a substrate and are separated from each other in a first direction. The storage node is arranged on the substrate between the first channel and the second channel and is electrically connected to the first channel. The bit line is arranged on the substrate on a side of the first channel away from the storage node and is electrically connected to the first channel. The word line and the first conductive line are respectively arranged on the substrate on opposite sides of the first channel in a second direction intersecting with the first direction, wherein the first conductive line is electrically connected to the first channel. The first dielectric layer is arranged between the word line and the first channel. The second dielectric layer is arranged between the storage node and the second channel. The second conductive line is arranged on the substrate on a side of the second channel away from the storage node and is electrically connected to the second channel. The source line and the drain line are respectively arranged on the substrate on opposite sides of the second channel in a second direction, wherein the source line and the drain line are respectively electrically connected to the second channel.
[0005] The dynamic random access memory of the present invention includes a first stack structure, a second stack structure, a plurality of storage nodes, bit lines, conductive lines, a plurality of word lines, a first dielectric layer, a second dielectric layer, a second conductive line, a source line, and a drain line. The first stack structure is disposed on a substrate and includes a plurality of first channels and a plurality of first insulating layers stacked alternately. The second stack structure is disposed on the substrate on one side of the first stack structure in a first direction and includes a plurality of second channels and a plurality of second insulating layers stacked alternately, wherein the first insulating layers and the second insulating layers at the same level are connected together. The plurality of storage nodes are respectively disposed between the first channels and the second channels at the same level and are electrically connected to the corresponding first channels. The bit lines are disposed on the substrate on the side of the first stack structure away from the storage nodes and are electrically connected to each of the first channels. The conductive lines and the plurality of word lines are disposed on the substrate on opposite sides of the first stack structure in a second direction intersecting the first direction, wherein the conductive lines are electrically connected to each of the first channels, and each word line and the corresponding first channel are located at the same level. The first dielectric layer is disposed between each word line and the corresponding first channel. A second dielectric layer is disposed between each storage node and the corresponding second channel. A second conductive line is disposed on the substrate on a side of the second stacked structure away from the plurality of storage nodes and is electrically connected to each second channel. A source line and a drain line are disposed on the substrate on opposite sides of the second stacked structure in a second direction, wherein the source line and the drain line are electrically connected to each second channel.
[0006] In summary, the memory cell of the dynamic random access memory of the present invention includes two transistors, one of which serves as a capacitor. Therefore, the memory cell does not need to include a high-k capacitor. In addition, during operation, the dynamic random access memory composed of stacked memory cells does not require a select transistor to select the memory cell to be operated. In addition, the two transistors are each electrically connected to a conductive line, thereby effectively eliminating the floating body effect. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 、 Figure 2A and Figure 4A Schematic top views of dynamic random access memories according to different embodiments of the present invention;
[0008] Figure 2B 、 Figure 2C and Figure 2D Along Figure 2A Schematic cross-sectional views of section line II, section line II-II and section line III-III;
[0009] Figure 3A schematic circuit diagram of a three-dimensional dynamic random access memory according to the present invention;
[0010] Figure 4B 、 Figure 4C and Figure 4D Along Figure 4A Schematic cross-sectional view of line II, line II-II and line III-III. DETAILED DESCRIPTION
[0011] Figure 1 This is a top-down schematic diagram of a dynamic random access memory according to a first embodiment of the present invention. The dynamic random access memory of this embodiment includes two transistors, one of which functions as a capacitor. The gate of the transistor serving as the capacitor is coupled to the source of the other transistor. The storage node can simultaneously serve as the source of one transistor and the gate of the other transistor. Furthermore, each of the two transistors is electrically connected to a conductive wire to eliminate the floating body effect. The dynamic random access memory of this embodiment is described in detail below.
[0012] Please refer to Figure 1 The dynamic random access memory 10 of this embodiment includes a first channel 102, a second channel 104, a storage node 106, a bit line 108, a word line 110, a first conductive line 112, a first dielectric layer 114, a second dielectric layer 116, a second conductive line 118, a source line 120, and a drain line 122 disposed on a substrate 100.
[0013] The substrate 100 is a dielectric substrate, which may be a dielectric layer formed on a silicon substrate, but the present invention is not limited thereto. A first channel 102 and a second channel 104 are disposed on the substrate 100 and are separated from each other in a first direction D1 parallel to the surface of the substrate 100. The first direction D1 may be an X-direction parallel to the surface of the substrate 100. The material of the first channel 102 and the second channel 104 may be doped polysilicon and have a first conductivity type. The first conductivity type is one of p-type and n-type, and the second conductivity type is the other of p-type and n-type.
[0014] Furthermore, the insulator 124 may be disposed in the first trench 102, and the insulator 126 may be disposed in the second trench 104. The first trench 102 surrounds the insulator 124, and the second trench 104 surrounds the insulator 126, but the present invention is not limited thereto. The insulator 124 and the insulator 126 may be omitted depending on practical circumstances.
[0015] Storage node 106 is disposed on substrate 100 between first channel 102 and second channel 104 and is electrically connected to first channel 102. Storage node 106 may be made of doped polysilicon of a first conductivity type. Contact 128 is disposed between first channel 102 and storage node 106. Contact 128 may be of a second conductivity type. Contact 128 may be a doped polysilicon layer disposed on the sidewalls of first channel 102, and storage node 106 is connected to the doped polysilicon layer. Furthermore, second dielectric layer 116 is disposed between storage node 106 and second channel 104. Second dielectric layer 116 may be an oxide layer.
[0016] Bitline 108 is disposed on substrate 100 on a side of first channel 102 away from storage node 106 and is electrically connected to first channel 102. That is, storage node 106 and bitline 108 are located on opposite sides of first channel 102 in first direction D1. Bitline 108 may be made of a metal, such as tungsten. Contact 130 is disposed between first channel 102 and bitline 108. Like contact 128, contact 130 may be of the second conductivity type. Contact 130 may be a doped polysilicon layer disposed on the sidewalls of first channel 102, and bitline 108 is connected to the doped polysilicon layer.
[0017] Word line 110 and first conductive line 112 are respectively disposed on substrate 100 on opposite sides of first trench 102 in a second direction D2 that intersects first direction D1. Second direction D2 may be a Y-direction parallel to the surface of substrate 100. Word line 110 may be made of doped polysilicon and have a first conductivity type. A first dielectric layer 114 is disposed between word line 110 and first trench 102. First dielectric layer 114 may be an oxide layer. First conductive line 112 is electrically connected to first trench 102. First conductive line 112 may be made of a metal, such as tungsten. Contact 132 is disposed between first trench 102 and first conductive line 112. Like contact 128, contact 132 may be a film layer having a second conductivity type. Contact 132 may be a doped polysilicon layer disposed on the sidewalls of first trench 102, and first conductive line 112 is connected to the doped polysilicon layer.
[0018] A second conductive line 118 is disposed on the substrate 100 on a side of the second channel 104 away from the storage node 106 and is electrically connected to the second channel 104. The storage node 106 and the second conductive line 118 are located on opposite sides of the second channel 104 in the first direction D1. The material of the second conductive line 118 can be a metal, such as tungsten. A contact 134 is disposed between the second channel 104 and the second conductive line 118. Like the contact 128, the contact 134 can be of the second conductivity type. The contact 134 can be a doped polysilicon layer disposed on the sidewall of the second channel 104, and the second conductive line 118 is connected to the doped polysilicon layer.
[0019] Source line 120 and drain line 122 are disposed on substrate 100 on opposite sides of second channel 104 in the second direction D2, and are electrically connected to second channel 104. Source line 120 and drain line 122 may be made of a metal, such as tungsten. Furthermore, contact 136 is disposed between second channel 104 and source line 120, and contact 138 is disposed between second channel 104 and drain line 122. Like contact 128, contact 136 and contact 138 may be of the second conductivity type. Contact 136 and contact 138 may be doped polysilicon layers disposed on the sidewalls of second channel 104, and source line 120 and drain line 122 are connected to the doped polysilicon layers.
[0020] In the dynamic random access memory 10 of this embodiment, the first channel 102, storage node 106, bit line 108, word line 110, and first dielectric layer 114 may constitute a transistor T1, wherein word line 110 may serve as a gate, first dielectric layer 114 may serve as a gate dielectric layer, and storage node 106 may serve as a drain. Furthermore, the second channel 104, storage node 106, second dielectric layer 116, source line 120, and drain line 122 may constitute a transistor T2, wherein storage node 106 may serve as a gate, and second dielectric layer 116 may serve as a gate dielectric layer. Storage node 106 may serve as both the drain of transistor T1 and the gate of transistor T2, and transistor T2 may serve as a capacitor of the dynamic random access memory.
[0021] Furthermore, the first conductive line 112 is electrically connected to the first channel 102 of the transistor T1 and may be grounded or connected to a reference voltage, thereby eliminating a floating body effect of the transistor T1 during operation. Similarly, the second conductive line 118 is electrically connected to the second channel 104 of the transistor T2 and may be grounded or connected to a reference voltage, thereby eliminating a floating body effect of the transistor T2 during operation.
[0022] Multiple DRAMs 10 can be stacked on a substrate to form a 3D DRAM. In other words, the DRAM 10 can serve as a DRAM cell in a 3D DRAM. This will be described in detail below.
[0023] Figure 2A FIG. 1 is a top view schematically showing a dynamic random access memory according to a second embodiment of the present invention. Figure 2B For the Figure 2A Schematic cross-sectional view of line II in FIG. Figure 2C For the Figure 2A Schematic cross-sectional view of the II-II section line. Figure 2D For the Figure 2ASchematic cross-sectional view of line III-III in FIG. The same components as those in the first embodiment are denoted by the same reference symbols and will not be described again. In addition, in order to make the drawings clear and convenient for description, Figure 2A The top insulation layer is omitted.
[0024] Please also refer to Figure 2A 、 Figure 2B 、 Figure 2C and Figure 2D The DRAM 20 is disposed on a substrate 200. The substrate 200 is a dielectric substrate, which may be a dielectric layer formed on a silicon substrate, but the present invention is not limited thereto. The DRAM 20 is formed by stacking a plurality of DRAMs 10, each serving as a DRAM cell, with two adjacent DRAMs 10 separated by an insulating layer.
[0025] In the dynamic random access memory 20, a plurality of stacked transistors T1 are separated by a plurality of first insulating layers 202a, and the first channel 102 in each transistor T1 and these first insulating layers 202a form a first stacked structure S1. Furthermore, a plurality of stacked transistors T2 are separated by a plurality of second insulating layers 202b, and the second channel 104 in each transistor T2 and these second insulating layers 202b form a second stacked structure S2. Furthermore, each first insulating layer 202a in the first stacked structure S1 is connected to a second insulating layer 202b located at the same level in the second stacked structure S2, such that each first channel 102 in the first stacked structure S1 is located at the same level as the corresponding second channel 104 in the second stacked structure S2. The first insulating layers 202a and second insulating layers 202b located at the same level can be connected to form a single insulating layer 202.
[0026] Furthermore, in the dynamic random access memory 20, the bit lines 108 in each layer are connected vertically, and the first conductive line 112, the second conductive line 118, the source line 120, and the drain line 122 all conduct current vertically. The insulators 124 in each layer are connected vertically to form an insulating pillar that penetrates the first stacked structure S1, and the insulators 126 in each layer are connected vertically to form an insulating pillar that penetrates the second stacked structure S2.
[0027] Taking the 3D dynamic random access memory 20 as an example, the circuit diagram of the 3D dynamic random access memory of the present invention is shown as follows: Figure 3 As shown. Figure 3, the drains of transistors T1 located in different layers are connected together through a bit line 108, the sources of transistors T2 located in different layers are connected together through a source line 120, and the drains of transistors T2 located in different layers are connected together through a drain line 122. In this way, during operation, the target memory cell can be operated by applying the required voltages to the bit line 108, the word line 110, the source line 120, and the drain line 122 respectively, without the need to select the memory cell to be operated through a selection transistor. In other words, there is no need to additionally set up a selection transistor in the dynamic random access memory of the present invention. In addition, in the dynamic random access memory of the present invention, a transistor in a memory cell can be used as a capacitor, so there is no need to additionally set up a capacitor.
[0028] Figure 4A FIG. 1 is a top view schematically showing a dynamic random access memory according to a third embodiment of the present invention. Figure 4B For the Figure 4A Schematic cross-sectional view of line II in FIG. Figure 4C For the Figure 4A Schematic cross-sectional view of the II-II section line. Figure 4D For the Figure 4A Schematic cross-sectional view of the III-III section line in FIG. The same components as those in the second embodiment will be represented by the same reference symbols and will not be described again. In addition, in order to make the drawings clear and convenient for description, Figure 4A The topmost first insulating layer and the second insulating layer are omitted.
[0029] Please also refer to Figure 4A 、 Figure 4B 、 Figure 4C and Figure 4D The difference between the dynamic random access memory 30 of this embodiment and the dynamic random access memory 20 is that the dynamic random access memory 30 further includes a through-layer channel 300 and a through-layer channel 302 .
[0030] Specifically, the through-layer trench 300 is disposed between the insulating pillars formed by connecting the insulators 124 in each layer and the first trench 102, and between the insulating pillars and the first insulating layer 202a. That is, the through-layer trench 300 surrounds the insulating pillars and connects the first trenches 102 in each layer. The through-layer trench 300 is made of the same material as the first trench 102, allowing the through-layer trench 300 to connect to the first trench 102 in each layer.
[0031] Furthermore, through-layer trenches 302 are disposed between the insulating pillars formed by connecting the insulators 126 in each layer and the second trenches 104, and between the insulating pillars and the second insulating layer 202b. That is, the through-layer trenches 302 surround the insulating pillars and connect the second trenches 104 in each layer. The through-layer trenches 302 are made of the same material as the second trenches 104, allowing the through-layer trenches 302 to connect to the second trenches 104 in each layer.
[0032] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A dynamic random access memory, characterized in that: include: The first channel and the second channel are disposed on the substrate and are separated from each other in a first direction; a storage node, disposed on the substrate between the first channel and the second channel and electrically connected to the first channel; a bit line, disposed on the substrate at a side of the first channel away from the storage node and electrically connected to the first channel; word lines and first conductive lines, respectively disposed on the substrate on opposite sides of the first channel in a second direction intersecting the first direction, wherein the first conductive line is electrically connected to the first channel; a first dielectric layer disposed between the word line and the first channel; a second dielectric layer disposed between the storage node and the second channel; a second conductive line, disposed on the substrate at a side of the second channel away from the storage node and electrically connected to the second channel; and A source line and a drain line are respectively arranged on the substrate at two opposite sides of the second channel in the second direction, wherein the source line and the drain line are respectively electrically connected to the second channel.
2. The dynamic random access memory according to claim 1, wherein: A contact is also included, which is disposed between the first channel and the bit line, between the first channel and the storage node, or between the first channel and the first conductive line.
3. The dynamic random access memory according to claim 1, wherein: A contact is also included, which is arranged between the second channel and the source line, between the second channel and the drain line, or between the second channel and the second conductive line.
4. A dynamic random access memory comprising: A first stacked structure is disposed on the substrate and includes a plurality of first channels and a plurality of first insulating layers stacked alternately; a second stacked structure, disposed on the substrate on one side of the first stacked structure in the first direction, and comprising a plurality of second channels and a plurality of second insulating layers stacked alternately, wherein the first insulating layers and the second insulating layers at the same level are connected together; a plurality of storage nodes, each disposed between the first channel and the second channel at the same level, and each electrically connected to the corresponding first channel; a bit line disposed on the substrate on a side of the first stack structure away from the storage node and electrically connected to each of the first channels; A first conductive line and a plurality of word lines are respectively arranged on the substrate at opposite sides of the first stacked structure in a second direction intersecting the first direction, wherein the first conductive line is electrically connected to each of the first channels, and each of the word lines and the corresponding first channel are located at the same level; a first dielectric layer disposed between each of the word lines and the corresponding first channel; a second dielectric layer disposed between each of the storage nodes and the corresponding second channel; a second conductive line disposed on the substrate at a side of the second stack structure away from the plurality of storage nodes and electrically connected to each of the second channels; as well as A source line and a drain line are respectively disposed on the substrate at two opposite sides of the second stack structure in the second direction, wherein the source line and the drain line are respectively electrically connected to each of the second channels.
5. The dynamic random access memory according to claim 4, wherein: A contact is also included, which is arranged between each of the first channels and the bit line, between each of the first channels and the corresponding storage node, or between each of the first channels and the first conductive line.
6. The dynamic random access memory according to claim 4, wherein: A contact is further included, which is arranged between each of the second channels and the source line, between each of the second channels and the drain line, or between each of the second channels and the second conductive line.
7. The dynamic random access memory according to claim 4, wherein: The device further includes an insulating column penetrating the first stack structure and located in the plurality of first trenches.
8. The dynamic random access memory according to claim 7, wherein: The invention also includes a through-layer channel, which is arranged between the insulating column and the plurality of first channels and between the insulating column and the plurality of first insulating layers.
9. The dynamic random access memory according to claim 4, wherein: The device further includes an insulating column penetrating the second stack structure and located in the plurality of second trenches. 10 . The dynamic random access memory according to claim 9 , further comprising a through-layer trench disposed between the insulating pillar and the plurality of second trenches and between the insulating pillar and the plurality of second insulating layers.