Semiconductor structure and manufacturing method thereof
By depositing an oxide barrier layer on a semiconductor material layer, the leakage problem caused by the reduction in component spacing is solved, thereby improving the process yield and component reliability of the semiconductor structure.
Patent Information
- Application Number
- CN202411239389.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-04-09
- Filing Date
- 2024-09-05
- Publication Date
- 2025-10-21
AI Technical Summary
With the high integration of semiconductor structures, the reduction in component spacing has led to increased leakage, affecting process yield.
First and second barrier layers are deposited on the rough surface of the semiconductor material layer. The STI region surface is modified and protected by oxides to reduce the corrosive effect of chlorides and form a flat insulating region to improve the contact between components.
By depositing an oxide barrier layer at high temperatures, leakage current is reduced, thereby improving the process yield of semiconductor structures and the reliability of components.
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Figure CN120825935A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor structure and a method for manufacturing the same. More particularly, the present disclosure relates to a semiconductor structure including a barrier layer between a semiconductor material layer and an insulating layer and a method for manufacturing the same. Background Art
[0002] As electronic devices become thinner and lighter, semiconductor devices such as dynamic random access memory (DRAM) are becoming more highly integrated. Furthermore, DRAM performance is improved by shortening the pitch between semiconductor structures. However, the shrinking size of semiconductor structures not only increases manufacturing complexity but also makes components within the semiconductor structure more susceptible to leakage due to close spacing.
[0003] Therefore, in the semiconductor manufacturing process, how to reduce leakage to improve the process yield of the semiconductor structure becomes an important issue. Summary of the Invention
[0004] Some embodiments of the present disclosure provide a method for fabricating a semiconductor structure, comprising the following steps: forming a plurality of trenches in a substrate; forming a semiconductor material layer on inner surfaces of the trenches and on a top surface of the substrate, wherein the semiconductor material layer has a roughened inner surface contacting the substrate and a roughened outer surface exposed by the trenches; depositing a first barrier layer on the roughened outer surface of the semiconductor material layer, wherein the outer surface of the first barrier layer is flat; and depositing a second barrier layer on the first barrier layer.
[0005] In some embodiments, the first barrier layer includes an oxide, and the second barrier layer includes an oxide.
[0006] In some embodiments, the content of the oxide of the second barrier layer is different from the content of the oxide of the first barrier layer.
[0007] In some embodiments, the temperature at which the first barrier layer is formed is higher than the temperature at which the second barrier layer is formed.
[0008] In some embodiments, chlorides are generated during the process of forming the semiconductor material layer, and the rough inner surface and the rough outer surface of the semiconductor material layer are roughened by the chlorides.
[0009] In some embodiments, an inner surface of the first barrier layer contacting the rough outer surface of the layer of semiconductor material is conformal to the rough outer surface of the layer of semiconductor material.
[0010] In some embodiments, the thickness of the semiconductor material layer is greater than the thickness of the first barrier layer.
[0011] In some embodiments, the method further comprises the following steps: depositing an insulating layer on the second barrier layer to form a plurality of insulating regions; and planarizing the insulating layer until the topmost surface of the semiconductor material layer is exposed to form a plurality of active regions adjacent to the insulating regions.
[0012] In some embodiments, a topmost surface of the semiconductor material layer, a top surface of the first barrier layer, a top surface of the second barrier layer, and a top surface of the insulating layer are coplanar.
[0013] In some embodiments, the method further comprises the following steps: After depositing the insulating layer, forming a plurality of word line structures in the active region.
[0014] Some embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes multiple active regions and multiple insulating regions. The active regions are disposed in a substrate and surrounded by a semiconductor material layer, wherein a surface of the semiconductor material layer contacting the active regions is a rough surface. The insulating regions are disposed in the substrate and surround the active regions, wherein the insulating regions include the semiconductor material layer, a first barrier layer disposed on the semiconductor material layer, and an insulating layer disposed above the first barrier layer, and wherein the top surface and the bottom surface of the semiconductor material layer are roughened.
[0015] In some embodiments, a top surface of the semiconductor material layer is higher than a top surface of the substrate.
[0016] In some embodiments, a top surface of the semiconductor material layer is flat, and the top surface of the semiconductor material layer is coplanar with a top surface of the insulating layer.
[0017] In some embodiments, the insulating region further includes a second barrier layer disposed between the first barrier layer and the insulating layer.
[0018] In some embodiments, a surface of the first barrier layer contacting a surface of the second barrier layer is planar, and another surface of the first barrier layer contacting another surface of the semiconductor material layer on the sidewall of the active region is conformal.
[0019] In some embodiments, the semiconductor material layer has a thickness of 55 angstroms to 80 angstroms.
[0020] In some embodiments, the first barrier layer has a thickness of 15 angstroms to 20 angstroms.
[0021] In some embodiments, the semiconductor structure further includes a plurality of word line structures extending through the insulating region and the active region, and a plurality of source / drain regions disposed in each active region and on opposite sides of the word line structures. The word line structures include a conductive layer, a capping layer disposed on the conductive layer, and a dielectric liner layer surrounding the conductive layer and the capping layer.
[0022] In some embodiments, the semiconductor material layer surrounds sidewalls of an upper portion of the word line structure.
[0023] In some embodiments, a top surface of the conductive layer is higher than a bottom surface of the source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The following examples are presented in conjunction with the accompanying drawings for a clearer understanding of the present disclosure. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of discussion.
[0025] Figure 1 is a top view of a semiconductor structure including multiple active regions according to some embodiments of the present disclosure;
[0026] Figure 2 and Figure 3 According to some embodiments of the present disclosure, a method for manufacturing a semiconductor structure is provided wherein a semiconductor material layer is formed along Figure 1 A cross-sectional view taken along section line NN';
[0027] Figure 4 and Figure 5 According to some embodiments of the present invention, a method for manufacturing a semiconductor structure is provided wherein the insulating layer is formed along the Figure 1 A cross-sectional view taken along section line NN';
[0028] Figure 6 is a top view of a semiconductor structure including a plurality of word line structures according to some embodiments of the present disclosure; and
[0029] Figure 7 and Figure 8 The method for manufacturing a semiconductor structure according to some embodiments of the present disclosure is to form a plurality of word line structures along Figure 6 A cross-sectional view taken along section line NN'. DETAILED DESCRIPTION
[0030] Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.
[0031] Furthermore, for ease of description, spatially relative terms such as "on," "above," "below," and "between" may be used throughout this disclosure to describe the relationship or function of one element or feature to another element as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used throughout this disclosure should be interpreted accordingly.
[0032] The terms "including", "having", "comprising" and the like used in this disclosure are open-ended terms, meaning including but not limited to.
[0033] It should be noted that when the following drawings (such as Figures 1 to 8 ) are described and illustrated as a series of operations or steps, the order in which these operations or steps are described should not be construed as limiting. For example, some operations or steps may be performed in a different order than in the present disclosure, or some operations or steps may occur simultaneously, or some operations may not be performed, and / or some operations or steps may be repeated. In addition, the actual operations or steps of the process stages may occur in different orders than those in the present disclosure, or some operations or steps may occur simultaneously, or some operations may not be performed, and / or some operations or steps may be repeated. Figure 8 Additional operations or steps are performed before, during, or after the semiconductor structure 100 in the embodiment to form the semiconductor structure 100. Therefore, the present disclosure may briefly describe some of these additional operations or steps. In addition, unless otherwise specified, for the following figures (e.g. Figures 1 to 8 )The same explanations discussed above can be directly applied to the other figures.
[0034] As the components of semiconductor structures become increasingly dense, for example, when manufacturing the active area of the semiconductor structure, the shallow trench isolation (STI) area is designed to be increasingly dense, so a layer of silicon (Si) (such as polysilicon) is first grown in the STI area to protect the substrate of the STI area and increase the landing area of the word line. However, chloride is a by-product in the growth process of the silicon layer. The chloride has a corrosive effect at high temperatures, causing the surface of the STI area to become rough, and the rough surface of the STI area causes the STI area to be less straight. This in turn affects the landing area of the word line. In order to solve the above problems, an embodiment of the present invention provides a solution for adding a layer of oxide (such as SiO2) to the surface of the Si layer in a short time and at high temperature. This solution allows the surface of each STI area to be modified and defined by an oxide layer. Moreover, the protection of the STI area is also enhanced by the additional layer of oxide, thereby avoiding Si oxidation and consumption.
[0035] See also Figures 1 to 3 . Figure 1 is a top view of a semiconductor structure including multiple active regions according to some embodiments of the present disclosure, and Figure 2 and Figure 3 According to some embodiments of the present disclosure, a method for manufacturing a semiconductor structure is provided wherein a semiconductor material layer is formed along Figure 1 The cross-sectional view is taken along the section line NN'. Figure 2 In the embodiment of the present invention, a substrate 110 is provided, and the substrate 110 is configured to form a plurality of trenches TR in the substrate 110. The substrate 110 is a semiconductor material and may include silicon, such as crystalline silicon, polycrystalline silicon, or amorphous silicon. In some embodiments, the substrate 110 may include an elemental semiconductor, such as germanium (Ge). In some embodiments, the substrate 110 may include an alloy semiconductor, such as silicon germanium (SiGe), silicon carbide phosphide (SiPC), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium phosphide (GaInAsP), or other suitable materials. In some embodiments, the substrate 110 may include a compound semiconductor, such as silicon carbide (SiC), silicon phosphide (SiP), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), zinc oxide (ZnO), zinc selenide (ZnSe), zinc sulfide (ZnS), zinc telluride (ZnTe), cadmium selenide (CdSe), cadmium sulfide (CdS), cadmium telluride (CdTe), or other suitable materials.
[0036] Next, a semiconductor material layer 120 is formed on the inner surface of each trench TR and the top surface of the substrate 110. The inner surface IRS of the semiconductor material layer 120 directly contacts the inner surface of each trench TR in the substrate 110, and the outer surface ORS of the semiconductor material layer 120 is exposed by each trench TR. During the formation of the semiconductor material layer 120, byproducts including chloride 122 are generated. Furthermore, the inner surface IRS and the outer surface ORS of the semiconductor material layer 120 are roughened by the chloride 122. In some embodiments, the thickness of the semiconductor material layer 120 is to
[0037] exist Figure 3 In the embodiment, the first barrier layer 130 is conformally deposited on the semiconductor material layer 120. The inner surface of the first barrier layer 130 directly contacts the inner surface of the semiconductor material layer 120. In addition, the outer surface of the first barrier layer 130 is substantially flat. In some embodiments, the first barrier layer 130 comprises an oxide, such as SiO2. In some embodiments, the thickness of the semiconductor material layer 120 is greater than the thickness of the first barrier layer 130. In some embodiments, the thickness of the first barrier layer 130 is to In some embodiments, the first barrier layer 130 is deposited by atomic layer deposition (ALD). In some embodiments, the first barrier layer 130 is deposited at a high temperature (e.g., 800° C.). By providing the first barrier layer 130, the continuous generation of chloride 122 can be reduced, and the insulating region (e.g., Figure 1 The surface of each insulating region 114) can be formed to be flat.
[0038] Further, see Figure 4 and Figure 5 . Figure 4 and Figure 5 According to some embodiments of the present invention, a method for manufacturing a semiconductor structure is provided wherein the insulating layer is formed along the Figure 1 The cross-sectional view is taken along the section line NN'. Figure 4 In the embodiment, the second barrier layer 140 is conformally deposited on the first barrier layer 130. Furthermore, the thickness of the second barrier layer 140 is greater than that of the first barrier layer 130. In some embodiments, the thickness of the second barrier layer 140 is to In some embodiments, the second barrier layer 140 includes an oxide, such as SiO2. In some embodiments, the oxide content of the second barrier layer 140 is different from the oxide content of the first barrier layer 130. In some embodiments, the second barrier layer 140 is deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), ALD, or any suitable deposition process. In some embodiments, the deposition process configured to form the second barrier layer 140 is different from the deposition process configured to form the first barrier layer 130. In some embodiments, the temperature at which the second barrier layer 140 is deposited is lower than the temperature at which the first barrier layer 130 is deposited. For example, the second barrier layer 140 is deposited at a temperature of 600°C.
[0039] In addition, Figure 4 In the embodiment, insulating layer 150 is deposited on second barrier layer 140, and the top surface of insulating layer 150 is higher than the topmost surface of second barrier layer 140. The insulating layer 150 includes an oxide, such as SiO2. In some embodiments, insulating layer 150 is deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), ALD, or any suitable deposition process. In some embodiments, the deposition process configured to form insulating layer 150 is the same as the deposition process configured to form second barrier layer 140. In some embodiments, the oxide content of insulating layer 150 is the same as the oxide content of second barrier layer 140.
[0040] exist Figure 5 In the embodiment, after the insulating layer 150 is deposited, a planarization process is performed on the insulating layer 150 until the top surface of the semiconductor material layer 120 is exposed, so as to form a plurality of insulating regions 114 in the substrate 110. Figure 1 As shown in the top view of FIG, a plurality of active regions 112 are formed, and the active regions 112 are surrounded by insulating regions 114. Furthermore, the boundary between each active region 112 and each insulating region 114 is substantially based on the outer surface ORS of the semiconductor material layer 120. In other words, each active region 112 is defined from one outer surface ORS to the nearest outer surface ORS, without crossing the first barrier layer 130, the second barrier layer 140, and the insulating layer 150; and each insulating region 114 is defined from one outer surface ORS to the nearest outer surface ORS, crossing the first barrier layer 130. Furthermore, after the planarization process, the top surface of the semiconductor material layer 120, the top surface of the first barrier layer 130, the top surface of the second barrier layer 140, and the top surface of the insulating layer 150 are coplanar. The topmost surface of the semiconductor material layer 120 becomes flat after the planarization process.
[0041] Next, see Figures 6 to 8 . Figure 6 is a top view of a semiconductor structure including a plurality of word line structures according to some embodiments of the present disclosure. Figure 7 and Figure 8 The method for manufacturing a semiconductor structure according to some embodiments of the present disclosure is to form a plurality of word line structures along Figure 6 The cross-sectional view is taken along the section line NN'. Figure 7 In the embodiment of the present invention, a plurality of source / drain regions S / D are formed in the active region 112 of the substrate 110. Ion implantation can be performed on the upper portion of the substrate 110 and the upper portion of the semiconductor material layer 120 to introduce N-type or P-type dopants into the active region 112 of the substrate 110, thereby forming doped regions 110D and doped semiconductor material layer 120D, respectively. Furthermore, the doped regions 110D and the doped semiconductor material layer 120D are collectively referred to as source / drain regions S / D. In some embodiments, the N-type dopant may include phosphorus or arsenic, and the P-type dopant may include boron or boron fluoride.
[0042] Further, please also refer to Figure 6 Top view and Figure 7 , forming a plurality of openings OP corresponding to the plurality of word line structures WL, and the openings OP extend through the insulating region 114 and the active region 112. Figure 7 As shown, based on the section line NN′, openings OP are formed in the active region 112 , and a bottom surface of each opening OP is lower than the bottom surface of the semiconductor.
[0043] exist Figure 8In the embodiment, a dielectric liner layer 162 is formed in each opening OP (eg Figure 7 ) on the inner surface of the substrate. In some embodiments, the dielectric liner layer 162 may include silicon oxide or a high-k dielectric material. In some embodiments, the high-k dielectric material may be hafnium oxide (HfO2), zirconium oxide (ZrO2), tantalum pentoxide (Ta2O5), or a combination thereof. The dielectric liner layer 162 is formed by a CVD process, an ALD process, an oxygen plasma oxidation process, a thermal oxidation process, other suitable techniques, or a combination thereof.
[0044] Then, at each opening OP (such as Figure 7 A conductive layer 164 is formed in the dielectric liner layer 162 and on the dielectric liner layer 162 (as shown). The conductive layers 164 and 164 at least partially overlap with each source / drain region S / D. That is, each source / drain region S / D is disposed on opposite sides of the conductive layer 164. In some embodiments, the conductive layer 164 is formed of a conductive material, such as a semiconductor, a metal, a metal nitride, a metal silicide, other suitable conductive materials, or a combination thereof. For example, the conductive layer 164 may include doped polysilicon, titanium (Ti), tungsten (W), tantalum (Ta), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), other suitable conductive materials, or a combination thereof.
[0045] In addition, a capping layer 166 is formed at each opening OP (eg Figure 7 As shown in FIG, the cover layer 166 is stacked on the conductive layer 164, and the bottom surface of the cover layer 166 directly contacts the top surface of the conductive layer 164. The dielectric liner layer 162 surrounds the sidewalls and bottom surface of the conductive layer 164 and the sidewalls of the cover layer 166. Then, as shown in FIG. Figure 6 As shown in the top view of , each word line structure WL is linear and extends across the insulating region 114 and the active region 112 .
[0046] In addition, some embodiments of the present disclosure also provide a semiconductor structure 100 including a semiconductor material layer 120. Figure 8As shown, the semiconductor structure 100 includes a plurality of active regions 112 and a plurality of insulating regions 114 surrounding each active region 112. Each active region 112 is disposed in a substrate 110 and surrounded by a semiconductor material layer 120. Furthermore, an inner surface IRS of the semiconductor material layer 120 contacting each active region 112 is roughened. Furthermore, the semiconductor material layer 120 is disposed on each active region 112, and a top surface (topmost surface) of the semiconductor material layer 120 of each active region 112 is higher than the top surface of the substrate 110 of each active region 112. The top surface of the semiconductor material layer 120 on each active region 112 is flat, while the bottom surface of the semiconductor material layer 120 contacting each active region 112 is roughened.
[0047] Each insulating region 114 is disposed in the substrate 110 and surrounds each active region 112. Each insulating region 114 includes a semiconductor material layer 120, a first barrier layer 130 disposed on the semiconductor material layer 120, a second barrier layer 140 disposed on the first barrier layer 130, and an insulating layer 150 disposed on the second barrier layer 140. In some embodiments, the top surface of the semiconductor material layer 120 in each active region 112 is coplanar with the top surface of the insulating layer 150.
[0048] Furthermore, the surface of the first barrier layer 130 in contact with the second barrier layer 140 is flat, and the surface of the first barrier layer 130 in contact with the semiconductor material layer 120 is conformal to the surface of the semiconductor material layer 120 disposed on the sidewalls of each active region 112. In other words, the surface of the first barrier layer 130 in contact with the semiconductor material layer 120 is rough. Because the surface of the first barrier layer 130 in contact with the second barrier layer 140 is flat, both surfaces of the second barrier layer 140 are flat. Furthermore, the surface of the insulating layer 150 in contact with the second barrier layer 140 is flat. It is worth noting that some features of the semiconductor material layer 120, the first barrier layer 130, and the second barrier layer 140 have been described above and are not further elaborated here.
[0049] Furthermore, the semiconductor structure 100 further includes a plurality of wordline structures WL and a plurality of source / drain regions S / D in the active region 112. Each wordline structure WL extends through the insulating region 114 and the active region 112. Each wordline structure WL includes a conductive layer 164, a capping layer 166 disposed on the conductive layer 164, and a dielectric liner layer 162 surrounding the conductive layer 164 and the capping layer 166. Specifically, the top surface of the conductive layer 164 directly contacts the bottom surface of the capping layer 166, and the dielectric liner layer 162 surrounds the sidewalls and bottom surface of the conductive layer 164 and the sidewalls of the capping layer 166. In some embodiments, the semiconductor material layer 120 surrounds the sidewalls of the upper portion of each wordline structure WL. Furthermore, each source / drain region S / D is defined on opposite sides of each wordline structure WL. In some embodiments, the top surface of the conductive layer 164 is higher than the bottom surface of each source / drain region S / D.
[0050] As described above, embodiments of the present invention modify the surface of the insulating region (e.g., the STI region) into a flat structure by providing a first barrier layer between the insulating layer and the semiconductor material layer. This solves the problem of word line landing zones. Furthermore, the first barrier layer protects the surface of the insulating region from oxidation, thereby enhancing protection of the insulating region.
[0051] Although some embodiments of the present disclosure have been described in considerable detail, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described herein.
[0052] The above briefly describes the features of various embodiments of the present disclosure, making it easier for those skilled in the art to understand the present disclosure. Anyone skilled in the art will understand that this disclosure can easily serve as a basis for modifying or designing other structures or processes to achieve the same objectives and / or obtain the same advantages as the embodiments of the present disclosure. Anyone skilled in the art will also understand that structures equivalent to the above do not depart from the spirit and scope of the present disclosure, and that changes, substitutions, and modifications may be made without departing from the spirit and scope of the present disclosure.
[0053]
Explanation of symbols
[0054] 100:Semiconductor structure
[0055] 110:Substrate
[0056] 110D: doped region
[0057] 112: Active Zone
[0058] 114: Insulation area
[0059] 120: semiconductor material layer
[0060] 120D: doped semiconductor material layer
[0061] 130: first barrier layer
[0062] 140: Second barrier layer
[0063] 150: Insulation layer
[0064] 162: Dielectric liner layer
[0065] 164: conductive layer
[0066] 166: Covering
[0067] NN': hatch line
[0068] IRS: Inner Surface
[0069] ORS: Outer Surface
[0070] OP: Opening
[0071] S / D: Source / Drain region
[0072] TR: Groove
[0073] WL: character line structure.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: include: forming a plurality of trenches in a substrate; forming a semiconductor material layer on the inner surface of each of the trenches and on the top surface of the substrate, wherein the semiconductor material layer has a rough inner surface contacting the substrate and a rough outer surface exposed by each of the trenches; depositing a first barrier layer on the rough outer surface of the semiconductor material layer, wherein the outer surface of the first barrier layer is flat; as well as A second barrier layer is deposited on the first barrier layer.
2. The method according to claim 1, characterized in that The first barrier layer includes an oxide, and the second barrier layer includes the oxide.
3. The method according to claim 2, characterized in that A content of the oxide of the second barrier layer is different from a content of the oxide of the first barrier layer.
4. The method according to claim 1, wherein The temperature for forming the first barrier layer is higher than the temperature for forming the second barrier layer.
5. The method according to claim 1, wherein Chloride is generated during the formation of the semiconductor material layer, and The rough inner surface and the rough outer surface of the semiconductor material layer are roughened by the chloride.
6. The method according to claim 1, characterized in that An inner surface of the first barrier layer that contacts the rough outer surface of the semiconductor material layer is conformal to the rough outer surface of the semiconductor material layer.
7. The method according to claim 1, characterized in that The thickness of the semiconductor material layer is greater than that of the first barrier layer.
8. The method according to claim 1, characterized in that Further including: depositing an insulating layer on the second barrier layer to form a plurality of insulating regions; as well as The insulating layer is planarized until the topmost surface of the semiconductor material layer is exposed to form a plurality of active regions adjacent to each of the insulating regions.
9. The method according to claim 8, characterized in that The topmost surface of the semiconductor material layer, the top surface of the first barrier layer, the top surface of the second barrier layer, and the top surface of the insulating layer are coplanar.
10. The method according to claim 8, characterized in that Further including: After depositing the insulating layer, a plurality of word line structures are formed in the plurality of active regions.
11. A semiconductor structure, characterized in that include: A plurality of active regions are disposed in the substrate and surrounded by a semiconductor material layer, wherein a surface of the semiconductor material layer contacting each of the active regions is a rough surface; as well as A plurality of insulating regions are arranged in the substrate and surround each of the active regions, wherein each of the insulating regions includes the semiconductor material layer, a first barrier layer located on the semiconductor material layer, and an insulating layer located above the first barrier layer, and wherein the top surface of the semiconductor material layer and the bottom surface of the semiconductor material layer are rough.
12. The semiconductor structure according to claim 11, wherein: The top surface of the semiconductor material layer is higher than a top surface of the substrate.
13. The semiconductor structure according to claim 11, wherein: The top surface of the semiconductor material layer is flat, and the top surface of the semiconductor material layer is coplanar with the top surface of the insulating layer.
14. The semiconductor structure according to claim 11, wherein: Each of the insulating regions further comprises: The second barrier layer is disposed between the first barrier layer and the insulating layer.
15. The semiconductor structure according to claim 14, wherein: One surface of the first barrier layer in contact with one surface of the second barrier layer is flat, and another surface of the first barrier layer in contact with another surface of the semiconductor material layer on the sidewalls of each active region is conformal.
16. The semiconductor structure according to claim 11, wherein: The thickness of the semiconductor material layer is 55 angstroms to 80 angstroms.
17. The semiconductor structure according to claim 11, wherein: The thickness of the first barrier layer is 15 angstroms to 20 angstroms.
18. The semiconductor structure according to claim 11, wherein: Further including: A plurality of word line structures extending through the plurality of insulating regions and the plurality of active regions, wherein each of the word line structures comprises: conductive layer; a covering layer disposed on the conductive layer; and a dielectric liner layer surrounding the conductive layer and the cover layer; and A plurality of source / drain regions are disposed in the plurality of active regions and located on opposite sides of each of the word line structures.
19. The semiconductor structure according to claim 18, wherein: The semiconductor material layer surrounds the sidewalls of the upper portion of each word line structure.
20. The semiconductor structure according to claim 18, wherein A top surface of the conductive layer is higher than a bottom surface of each of the source / drain regions.