Three-dimensional NAND memory and manufacturing method thereof
By optimizing the via structure and material combination of the 3D NAND memory, the RC delay problem was solved, and the memory performance was improved.
Patent Information
- Application Number
- CN202410450940.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-15
- Publication Date
- 2025-10-21
AI Technical Summary
The RC latency problem in existing 3D NAND flash memory has not been effectively solved, affecting memory performance.
By adjusting the via structure and material combination, including forming a contact structure of polysilicon plug layer, titanium layer, titanium nitride layer and tungsten layer in the stacked structure, and reducing the thickness of polysilicon plug layer and increasing via diameter by wet etching, the insulating layer material is optimized to reduce bit line capacitance.
It effectively reduces the RC latency of 3D NAND memory, improves the read/write window and data write time, and enhances memory performance.
Smart Images
Figure CN120825944A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a three-dimensional (3D) NAND memory and a method for manufacturing the same. Background Art
[0002] Memory is commonly used in integrated circuits to store data. Memory typically includes volatile memory and non-volatile memory. An example of non-volatile memory is flash memory, such as floating-gate 3D NAND memory.
[0003] For 3D NAND memory technology, it is common to use OPOP (i.e., a structure in which polysilicon (poly) and oxide (oxide) are stacked in sequence, for example, a silicon oxide / polysilicon / silicon oxide / polysilicon structure), and the number of stacked layers will increase. Summary of the Invention
[0004] An object of the present invention is to provide a three-dimensional NAND memory with reduced RC delay and a method for manufacturing the same.
[0005] A three-dimensional NAND memory device according to one aspect includes: a stacked structure comprising alternating memory cell layers and a first insulating layer, the stacked structure further comprising a drain select gate layer composed of polysilicon disposed above the uppermost memory cell layer; a first through-hole formed in the stacked structure and passing through the stacked structure in a stacking direction; a first through-hole layer composed of an insulating material formed in the first through-hole; a second insulating layer disposed above the stacked structure, the second through-hole formed in the second insulating layer, the second through-hole located directly above the first through-hole; a polysilicon plug layer, a titanium layer, a titanium nitride layer, and a tungsten layer stacked sequentially from the bottom in the second through-hole; and a third insulating layer disposed above the second insulating layer, the third through-hole formed in the third insulating layer, the third through-hole having a diameter smaller than the second through-hole, the third through-hole located directly above the second through-hole, and the third through-hole filled with tungsten.
[0006] In one aspect of the three-dimensional NAND memory, the second through hole includes a small diameter portion and a large diameter portion, the polysilicon plug layer is located in the small diameter portion, and the contact structure composed of the titanium layer, titanium nitride layer, and tungsten layer is located in the large diameter portion.
[0007] In one aspect of the three-dimensional NAND memory, the first insulating layer is an oxide layer, the insulating material constituting the first via layer is an oxide or a nitride, the second insulating layer is a nitride layer, and the third insulating layer is an oxide layer.
[0008] In one aspect of the three-dimensional NAND memory, the oxide constituting the first insulating layer is silicon oxide, the insulator constituting the first via layer is silicon oxide or silicon nitride, the nitride constituting the second insulating layer is silicon nitride, and the oxide constituting the third insulating layer is silicon oxide.
[0009] A method for manufacturing a three-dimensional NAND memory in one aspect includes: a stacked structure forming step of forming a stacked structure, the stacked structure including a stacked structure including memory cell layers and a first insulating layer alternately stacked, the stacked structure further including a drain select gate layer composed of polysilicon disposed on an uppermost memory cell layer, a first through hole formed in the stacked structure passing through the stacked structure in a stacking direction, a first through hole layer composed of an insulating material formed in the first through hole, and the stacked structure further including: A second insulating layer is located above the stacked structure, a second through hole is formed in the second insulating layer, the second through hole is located directly above the first through hole, and a polysilicon plug layer is provided in the second through hole; a contact structure forming process of sequentially forming a titanium layer, a titanium nitride layer and a tungsten layer above the polysilicon plug layer in the second through hole of the second insulating layer; a process of forming a third insulating layer on the second insulating layer; a process of forming a third through hole having a diameter smaller than that of the second through hole at a position in the third insulating layer corresponding to the second through hole; and a process of filling tungsten in the third through hole.
[0010] In one aspect, the method for manufacturing a three-dimensional NAND memory further includes, between the stacked structure forming step and the contact structure forming step, a polysilicon plug layer thickness reducing step of removing a portion of polysilicon in the second through hole by wet etching to reduce the thickness of the polysilicon plug layer.
[0011] In one aspect, the method for manufacturing a three-dimensional NAND memory further includes, between the step of reducing the thickness of the polysilicon plug layer and the step of forming the contact structure, a step of wet-etching the sidewall of the second through hole to increase the diameter of the second through hole.
[0012] In one aspect of the method for manufacturing a three-dimensional NAND memory, the first insulating layer is an oxide layer, the insulating material constituting the first via layer is an oxide or a nitride, the second insulating layer is a nitride layer, and the third insulating layer is an oxide layer.
[0013] In one aspect of the method for manufacturing a three-dimensional NAND memory, the oxide constituting the first insulating layer is silicon oxide, the insulator constituting the first through-hole layer is silicon oxide or silicon nitride, the nitride constituting the second insulating layer is silicon nitride, and the oxide constituting the third insulating layer is silicon oxide.
[0014] According to the three-dimensional NAND memory and the manufacturing method thereof of the present invention, the RC delay of the three-dimensional NAND memory can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 This is a schematic cross-sectional view of a stacked structure used to manufacture 3D NAND memory.
[0016] Figures 2A to 2F It is a schematic cross-sectional view showing the process of manufacturing the 3D NAND memory according to the first embodiment.
[0017] Figures 3A to 3F It is a schematic cross-sectional view showing a process of manufacturing the 3D NAND memory according to the second embodiment.
[0018] Figure 4 It is a schematic cross-sectional view of a 3D NAND memory according to the third embodiment. DETAILED DESCRIPTION
[0019] Hereinafter, preferred modes for carrying out the present invention will be described. However, the following embodiments are merely illustrative, and the present invention is not limited to the following embodiments.
[0020] In addition, in the drawings of this specification, for the sake of illustration and easy understanding, the vertical and horizontal dimensions, the dimensional ratios, etc. are appropriately changed compared to the actual objects.
[0021] One or more aspects of one embodiment may be combined with one or more aspects of another embodiment within a range that does not cause inconsistency.
[0022] When a plurality of steps are described in a method such as a manufacturing method, other steps not described may be performed between the described steps. In addition, the order of the steps is not limited to the extent that no contradiction occurs.
[0023] (First embodiment)
[0024] Next, use Figure 1 and Figures 2A to 2F The 3D NAND memory according to the first embodiment and a process of manufacturing the 3D NAND memory 100A will be described.
[0025] First, if Figure 1 As shown, a stacked structure 110 is prepared. The stacked structure 110 includes a stacked structure 120 including insulating layers 101a, 101b, and 101c and memory cell layers 102a, 102b, and 102c stacked alternately. In this embodiment, the insulating layers 101a, 101b, and 101c are oxide (silicon oxide) layers. Figure 1In FIG. 4 , the width of the memory cell layers 102 a , 102 b , and 102 c and the insulating layers 101 a , 101 b , and 101 c is approximately 60 nm.
[0026] Although Figure 1 Although not explicitly shown in the figure, as understood by those skilled in the art, a plurality of memory cells and associated circuit elements, such as silicon-based word line segments, floating gates, control gates, non-silicon metal word line segments, etc., may be formed in the memory cell layers 102a, 102b, and 102c. However, it should be understood that although Figure 1 3 insulating layers and 3 memory cell layers are shown in FIG, but this is only for illustration. In an actual memory, there may be more or fewer insulating layers and memory cell layers, and the thickness of each layer may be the same or different from each other. Figure 1 2 through holes 105 are shown in FIG. , but the present invention is not limited thereto, and the number of through holes 105 may be 1 or 3 or more. The through holes 105 include a through hole 105a located at the bottom and a through hole 105b located at the top.
[0027] The stacked structure 120 further includes a SGD (Selected Gate Drain) layer 103 made of polysilicon and disposed on the memory cell layer 102 c . The SGD layer 103 serves to switch each memory cell.
[0028] The through hole 105a is along the stacking direction ( Figure 1 The through hole layer 106 is formed in the through hole 105a. In this embodiment, the insulating material constituting the through hole layer 106 is an oxide (silicon oxide) or a nitride (silicon nitride). For the sake of convenience, in this specification, Figure 1 Only the through-hole layer 106 is formed in the through-hole 105a. However, in the actual structure, in addition to the through-hole layer 106, other structures such as a channel layer are also formed in the through-hole 105a (specifically, other structures such as the channel layer (not shown) are actually formed between the insulating layers 101a, 101b, 101c and the memory cell layers 102a, 102b, 102c and the through-hole layer 106). Detailed description is omitted here.
[0029] The stacked structure 110 further includes an insulating layer 104 positioned above the stacked structure 120. A through hole 105b is formed in the insulating layer 104, and a polysilicon plug layer 107 is disposed within the through hole 105b. The thickness of the insulating layer 104 and the polysilicon plug layer 107 is approximately 100 nm. The diameters of the through holes 105a and 105b are approximately 100 nm. The insulating material constituting the insulating layer 104 is nitride (silicon nitride).
[0030] In such Figure 1 After forming the stacked structure 110 as shown, Figure 2A As shown, an insulating layer 108 is formed on the surface of the stacked structure 110 by chemical vapor deposition. In this embodiment, the insulating material constituting the insulating layer 108 is an oxide (silicon oxide) with a thickness of approximately 170 nm. Furthermore, the method for forming the insulating layer (silicon oxide layer) 108 is not limited to chemical vapor deposition; other methods may also be used.
[0031] Then as Figure 2B As shown, a through hole 109 is formed in the insulating layer 108 by photolithography or dry etching until the surface of the polysilicon plug layer 107 is exposed. In this embodiment, a portion of the polysilicon plug layer 107 is also etched, so that the thickness of the polysilicon plug layer 107 is reduced.
[0032] Then as Figure 2C As shown, in via 109, a Ti (titanium) layer 121, a TiN (titanium nitride) layer 122, and a W (tungsten) layer 123 are sequentially deposited on the polysilicon plug layer 107, forming a contact structure consisting of Ti layer 121, TiN layer 122, and W layer 123. The thickness of Ti layer 121 is approximately 15 nm, the thickness of TiN layer 122 is approximately 5 nm, and the thickness of W layer 123 is approximately 160 nm. The function of W layer 123 is to connect the polysilicon plug layer 107 to the bit line contact described later. The function of Ti layer 121 and TiN layer 122 is to prevent high contact resistance generated when W layer 123 is directly connected to the polysilicon plug layer 107.
[0033] After forming the contact structure composed of the Ti layer 121, the TiN layer 122 and the W layer 123 in the through hole 109, a chemical mechanical polishing (CMP) process may be performed to smooth the upper surfaces of the insulating layer 108 and the W layer 123 to remove unnecessary portions.
[0034] Then, if Figure 2D As shown, an insulating layer 124 is formed by chemical vapor deposition on the surface of the stacked structure 110. In this embodiment, the insulating material constituting the insulating layer 124 is oxide (silicon oxide) and has a thickness of approximately 60 nm.
[0035] Then, if Figure 2E As shown, a through hole 125 is formed in the insulating layer 124 by photolithography or dry etching until the surface of the W layer 123 is exposed. In this embodiment, the diameter of the through hole 125 is smaller than that of the through hole 109, which is about 20 nm.
[0036] Finally, if Figure 2FAs shown, a W (tungsten) layer 126 is deposited in the via 125. This W layer 126 constitutes a bit line and contacts the W layer 123 in the via 109. Here, in order to smooth the upper surfaces of the insulating layer 124 and the W layer 126, a CMP process may be performed to remove unnecessary portions.
[0037] Through the above-described process, the 3D NAND memory 100A of this embodiment is manufactured.
[0038] Two metrics are commonly used to evaluate the performance of 3D NAND memory. One is the Read Window Budget (RWB), where a larger RWB indicates a lower probability of error. The other is T-prog, which represents the time required to write data to the 3D NAND memory. The bit line capacitance (BL CAP) of 3D NAND memory is a parameter that influences both of these metrics.
[0039] Through simulations, the inventors have determined that in 3D NAND memory 100A, the bitline capacitance based on the W layer 123 accounts for approximately 30% of the total bitline capacitance. Reducing the bitline capacitance based on the W layer 123 can improve the 3D NAND memory's RWB and T-prog, and reduce RC delay. RC delay refers to the signal delay caused by the charge and discharge processes of the resistor (R) and control capacitor (C) in an integrated circuit. The embodiments described below provide 3D NAND memories capable of reducing RC delay.
[0040] (Second embodiment)
[0041] Next, use Figure 1 and Figures 3A to 3F A 3D NAND memory according to the second embodiment and a process for manufacturing the 3D NAND memory will be described.
[0042] Compared with the first embodiment, this embodiment Figure 1 The structures shown are the same, so the details about Figure 1 The difference between this embodiment and the first embodiment is that Figures 3A to 3F The following method is shown Figures 3A to 3F The method shown is explained.
[0043] First, if Figure 3A As shown, the wet etching removes Figure 1In the stacked structure 110, the thickness of the polysilicon plug layer 107 is reduced to form a recess 130. The thickness of the recess 130 is about 60 nm, and the thickness of the polysilicon plug layer 107 after the removal of the portion is about 40 nm.
[0044] Then, if Figure 3B As shown, a portion of the sidewall of recess 130 (via 105b) is removed by wet etching, thereby increasing the diameter of recess 130. The portion of via 105b with the increased diameter (larger diameter portion) is designated 130a, and the portion of via 105b that remains unetched (smaller diameter portion) is designated 130b. The remaining polysilicon plug layer 107 is located within small diameter portion 130b. The purpose of increasing the diameter of recess 130 by wet etching is to ensure that via 135, which will be formed later, is located above recess 130, thereby ensuring contact between W layer 133 and W layer 136.
[0045] Then as Figure 3C As shown, in the recess 130 (large diameter portion 130a), a Ti layer 131, a TiN layer 132, and a W layer 133 are sequentially deposited to form a contact structure consisting of the Ti layer 131, the TiN layer 132, and the W layer 133. The thickness of the Ti layer 131 is approximately 15 nm, the thickness of the TiN layer 132 is approximately 5 nm, and the thickness of the W layer 133 is approximately 40 nm.
[0046] After forming the contact structure composed of the Ti layer 131 , the TiN layer 132 and the W layer 133 in the recess 130 , a CMP process may be performed to smooth the upper surfaces of the insulating layer 104 and the W layer 133 and remove unnecessary portions.
[0047] Then, if Figure 3D As shown, an insulating layer 134 is formed by chemical vapor deposition on the surfaces of the insulating layer 104 and the W layer 133. In this embodiment, the insulating material constituting the insulating layer 134 is oxide (silicon oxide) and has a thickness of about 60 nm.
[0048] Then, if Figure 3E As shown, a through hole 135 is formed in the insulating layer 134 by photolithography or dry etching until the surface of the W layer 133 is exposed. In this embodiment, the diameter of the through hole 135 is smaller than the diameter of the through hole 105b (recess 130) and is approximately 20 nm.
[0049] Finally, if Figure 3FAs shown, a W (tungsten) layer 136 is deposited in the through hole 135. This W layer 136 constitutes a bit line and contacts the W layer 133 in the recess 130. Here, in order to smooth the upper surfaces of the insulating layer 134 and the W layer 136, a CMP process may be performed to remove unnecessary portions.
[0050] Through the above-described process, the 3D NAND memory 100B of this embodiment is manufactured.
[0051] According to the 3D NAND memory 100B of this embodiment, compared with the 3D NAND memory 100A of the first embodiment, the insulating layer 108 and the W layer 123 formed in the insulating layer 108 are omitted, which can improve the RWB and T-prog of the 3D NAND memory and reduce the RC delay.
[0052] (Third embodiment)
[0053] Next, use Figure 4 A 3D NAND memory according to a third embodiment and a process for manufacturing the 3D NAND memory will be described.
[0054] Compared with the second embodiment, this embodiment omits Figure 3B The steps shown and other steps are the same as those in the second embodiment.
[0055] like Figure 4 As shown, in the 3D NAND memory 100C, the sidewalls of the through hole 105b are not etched, and the large-diameter portion and the small-diameter portion are not formed as in the second embodiment. A contact structure composed of a Ti layer 131a, a TiN layer 132a, and a W layer 133a is formed in the through hole 105b.
[0056] According to the 3D NAND memory 100C of this embodiment, compared with the 3D NAND memory 100A of the first embodiment, the insulating layer 108 and the W layer 123 formed in the insulating layer 108 are omitted, which can improve the RWB and T-prog of the 3D NAND memory and reduce the RC delay; and compared with the 3D NAND memory 100B of the second embodiment, because the insulating layer 108 and the W layer 123 formed in the insulating layer 108 are omitted, the RWB and T-prog of the 3D NAND memory can be improved. Figure 3B The step of increasing the diameter of the recess 130 (through hole 105b) is omitted, so cost can be saved.
[0057] While the preferred modes for carrying out the present invention have been described above, it should be understood that the above embodiments are merely illustrative and the present invention is not limited thereto.
[0058] For example, in each of the above embodiments, specific values are described for the thickness of each layer. However, these values are merely examples, and those skilled in the art can obviously modify these values appropriately. Such modified embodiments also fall within the scope of the present invention.
[0059] In addition, in each of the above embodiments, specific film-forming methods are described for each film layer. However, these film-forming methods are merely illustrative, and those skilled in the art will appreciate that other film-forming methods may be employed. Embodiments in which the film-forming methods are modified also fall within the scope of the present invention.
[0060] In addition, in this specification, terms such as "first" and "second" are used for illustrative purposes only and should not be construed as indicating or implying the relative importance or order of technical features. A feature specified as "first" or "second" explicitly or implicitly includes one or more of the features.
Claims
1. A three-dimensional NAND memory, characterized in that: include: A stack structure comprising memory cell layers and a first insulating layer alternately stacked, the stack structure further comprising a drain select gate layer composed of polysilicon disposed on an uppermost memory cell layer, a first through hole passing through the stack structure in a stacking direction formed in the stack structure, and a first through hole layer composed of an insulating material formed in the first through hole; a second insulating layer located above the stacked structure, wherein a second through hole is formed in the second insulating layer, the second through hole being located directly above the first through hole, and wherein a polysilicon plug layer, a titanium layer, a titanium nitride layer, and a tungsten layer are sequentially stacked in the second through hole from the bottom; and A third insulating layer is formed on the second insulating layer. A third through hole having a diameter smaller than that of the second through hole is formed in the third insulating layer. The third through hole is located directly above the second through hole and is filled with tungsten.
2. The three-dimensional NAND memory according to claim 1, wherein: The second through hole includes a small diameter portion and a large diameter portion. The polysilicon plug layer is located in the small diameter portion, and the contact structure composed of a titanium layer, a titanium nitride layer, and a tungsten layer is located in the large diameter portion.
3. The three-dimensional NAND memory according to claim 1 or 2, wherein: The first insulating layer is an oxide layer, The insulating material constituting the first through-hole layer is oxide or nitride, The second insulating layer is a nitride layer, The third insulating layer is an oxide layer.
4. The three-dimensional NAND memory according to claim 3, wherein: The oxide constituting the first insulating layer is silicon oxide. The insulating material constituting the first through-hole layer is silicon oxide or silicon nitride. The nitride constituting the second insulating layer is silicon nitride. The oxide constituting the third insulating layer is silicon oxide.
5. A method for manufacturing a three-dimensional NAND memory, characterized in that: include: a stacked structure forming step of forming a stacked structure, the stacked structure comprising a stacked structure including memory cell layers and a first insulating layer alternately stacked, the stacked structure further comprising a drain select gate layer composed of polysilicon disposed on an uppermost memory cell layer, a first through-hole formed in the stacked structure passing through the stacked structure in a stacking direction, a first through-hole layer composed of an insulating material formed in the first through-hole, the stacked structure further comprising a second insulating layer located above the stacked structure, a second through-hole formed in the second insulating layer, the second through-hole being located directly above the first through-hole, and a polysilicon plug layer disposed in the second through-hole; a contact structure forming step of sequentially forming a titanium layer, a titanium nitride layer, and a tungsten layer above the polysilicon plug layer in the second through hole of the second insulating layer; forming a third insulating layer on the second insulating layer; forming a third through hole having a smaller diameter than the second through hole at a position corresponding to the second through hole in the third insulating layer; and A step of filling the third through hole with tungsten.
6. The method for manufacturing a three-dimensional NAND memory according to claim 5, wherein: Between the stacked structure forming step and the contact structure forming step, the method further includes a polysilicon plug layer thickness reducing step of removing a portion of polysilicon in the second through hole by wet etching to reduce the thickness of the polysilicon plug layer.
7. The method for manufacturing a three-dimensional NAND memory according to claim 6, wherein: Between the step of reducing the thickness of the polysilicon plug layer and the step of forming the contact structure, the method further includes a step of wet-etching the sidewall of the second through hole to enlarge the diameter of the second through hole.
8. The method for manufacturing a three-dimensional NAND memory according to any one of claims 5 to 6, wherein: The first insulating layer is an oxide layer, The insulating material constituting the first through-hole layer is oxide or nitride, The second insulating layer is a nitride layer, The third insulating layer is an oxide layer.
9. The method for manufacturing a three-dimensional NAND memory according to claim 8, wherein: The oxide constituting the first insulating layer is silicon oxide. The insulating material constituting the first through-hole layer is silicon oxide or silicon nitride. The nitride constituting the second insulating layer is silicon nitride. The oxide constituting the third insulating layer is silicon oxide.