Formation method of semiconductor structure, semiconductor structure and integrated chip

Abstract

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure forming method, a semiconductor structure and an integrated chip. The method comprises the following steps: providing a semiconductor substrate; performing doping treatment on a preset region of the semiconductor substrate; forming a first target layer on the semiconductor substrate, or forming a second target layer on the semiconductor substrate by using a preset low-temperature deposition process; the first target layer comprises an amorphous silicon layer; the preset low-temperature deposition process comprises a furnace tube process, so that gap silicon can be prevented from being formed on the semiconductor substrate, and diffusion of doped elements is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure, a semiconductor structure and an integrated chip. Background Art

[0002] In semiconductor manufacturing, element doping processes are usually involved. For example, in the manufacturing process of Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET), the substrate is doped to form an N-well or P-well, a source region, etc. The purpose of the doping process is many, and doping of different positions and elements will play different roles, such as adjusting Vt (threshold voltage), leakage (anti-breakdown), reducing resistance, etc.

[0003] As the complexity of semiconductor devices increases, their corresponding preparation processes are also becoming more and more complicated. The processes at the front end may be affected by the back end processes. For example, after the above-mentioned doping process is completed, the deposition process may be involved in the subsequent process. In order to ensure uniform and efficient deposition methods in the existing technology, plasma enhanced chemical vapor deposition (PECVD) is usually adopted, which makes the doped elements in the substrate easy to diffuse, thereby affecting the electrical performance of the finally prepared semiconductor device. Summary of the Invention

[0004] To solve the above-mentioned technical problem of easy diffusion of elements doped in a substrate during semiconductor manufacturing, the present application discloses, in one aspect, a method for forming a semiconductor structure, comprising:

[0005] providing a semiconductor substrate;

[0006] performing a doping process on a predetermined area of ​​the semiconductor substrate;

[0007] A first target layer is formed on the semiconductor substrate, or a second target layer is formed on the semiconductor substrate using a preset low-temperature deposition process; the first target layer includes an amorphous silicon layer; and the preset low-temperature deposition process includes a furnace tube process.

[0008] In a feasible embodiment, the second target layer includes a dielectric layer;

[0009] The dielectric layer includes a silicon oxide layer or a silicon nitride layer.

[0010] In a feasible embodiment, forming a first target layer on the semiconductor substrate includes:

[0011] The amorphous silicon layer is formed on the semiconductor substrate by using a furnace process.

[0012] In a feasible embodiment, the preset low-temperature deposition process further includes a low-energy plasma deposition process;

[0013] The energy of the low energy plasma deposition process is less than 300 watts;

[0014] The deposition temperature for forming the first target layer is lower than 400 degrees Celsius;

[0015] The deposition temperature corresponding to the furnace tube process for forming the second target layer is lower than 800 degrees Celsius.

[0016] In a feasible embodiment, forming the second target layer on the semiconductor substrate by using a predetermined low-temperature deposition process includes:

[0017] The dielectric layer is formed on the semiconductor substrate by utilizing the furnace tube process.

[0018] In a feasible embodiment, forming the second target layer on the semiconductor substrate by using a predetermined low-temperature deposition process includes:

[0019] The second target layer is formed on the semiconductor substrate by using the low energy plasma deposition process.

[0020] In a feasible embodiment, the ions used in the doping treatment include N-type ions and P-type ions;

[0021] The N-type ions include phosphorus ions, arsenic ions or antimony ions;

[0022] The P-type ions include boron ions, boron fluoride ions or indium ions.

[0023] In a feasible embodiment, providing a semiconductor substrate includes:

[0024] providing a substrate;

[0025] forming a mask material layer on the substrate;

[0026] patterning the mask material layer to form a mask on the substrate;

[0027] The substrate is etched to a preset depth, and then the mask is removed to form the semiconductor substrate. The semiconductor substrate includes a supporting substrate and a plurality of fin structures provided on the supporting substrate with preset intervals.

[0028] In a feasible embodiment, performing doping on a predetermined area of ​​the semiconductor substrate includes:

[0029] N-type or P-type ion implantation is performed into a first region of the semiconductor substrate to form an N-well or P-well in the first region of the semiconductor substrate; the first region includes a region of the supporting substrate close to the fin structure and a region of the fin structure close to the supporting substrate.

[0030] In a feasible embodiment, the thickness of the first target layer is 1 to 6 nanometers.

[0031] On the other hand, the present application discloses a semiconductor structure, which is prepared based on the above method.

[0032] In another aspect, the present application discloses a semiconductor device, which includes the above-mentioned semiconductor structure.

[0033] On the other hand, the present application discloses an integrated chip, which includes the above-mentioned semiconductor device.

[0034] By adopting the above technical solution, the method for forming a semiconductor structure provided by the present application has the following beneficial effects:

[0035] The embodiment of the present application provides a semiconductor substrate; performs doping treatment on a preset area of ​​the semiconductor substrate; forms a first target layer on the semiconductor substrate, or forms a second target layer on the semiconductor substrate using a preset low-temperature deposition process; the first target layer includes an amorphous silicon layer; the preset low-temperature deposition process includes a furnace tube process, thereby avoiding the formation of interstitial silicon in the semiconductor substrate and reducing the diffusion of doping elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0037] Figure 1 is a schematic structural diagram of a semiconductor substrate provided in an embodiment of the present application;

[0038] Figure 2 This is a schematic diagram of atomic distribution of a semiconductor substrate provided in an embodiment of the present application;

[0039] Figure 3 This is a schematic diagram of a method for generating gap silicon provided by an embodiment of the present application;

[0040] Figure 4 This is another schematic diagram of generating gap silicon provided by an embodiment of the present application;

[0041] Figure 5This is a simplified structural diagram of a plasma enhanced chemical vapor deposition device provided in an embodiment of the present application;

[0042] Figure 6 This is a boron diffusion condition of boron doped in different depth regions of a semiconductor structure provided by an embodiment of the present application;

[0043] Figures 7-11 This is a schematic diagram of a process for forming a semiconductor structure provided in an embodiment of the present application.

[0044] The following is a supplementary description of the accompanying drawings:

[0045] 1-semiconductor substrate; 101-support substrate; 102-fin structure; 2-first target layer; 3-second target layer; 4-isolation layer; 5-deposition chamber; 6-controller; 7-heating device; 8-carrying platform; 9-inlet channel; 10-exhaust channel. DETAILED DESCRIPTION

[0046] The following, in conjunction with the accompanying drawings, provides a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments represent only a portion of the embodiments of the present application, and not all of the embodiments. The terms "one embodiment" or "embodiment" herein refer to specific features, structures, or characteristics that may be included in at least one implementation of the present application. Throughout the description of the present application, it should be understood that the terms "upper," "lower," "top," and "bottom," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely for ease of description and simplification. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting the present application. Furthermore, the terms "first" and "second" are used solely for descriptive purposes and should not be construed to indicate or imply relative importance or to implicitly specify the number of the technical features indicated. Therefore, features designated "first" or "second" may explicitly or implicitly include one or more of such features. Furthermore, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential sequence. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein.

[0047] When a numerical range is disclosed herein, the above range is considered to be continuous and includes the minimum and maximum values ​​of the range, as well as every value between such minimum and maximum values. Further, when a range refers to an integer, every integer between the minimum and maximum values ​​of the range is included. In addition, when multiple ranges are provided to describe a feature or characteristic, the ranges can be merged. In other words, unless otherwise indicated, all ranges disclosed herein should be understood to include any and all subranges included therein. For example, a specified range from "1 to 10" should be considered to include any and all subranges between the minimum value of 1 and the maximum value of 10. Exemplary subranges of the range 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc. It should be understood that one of ordinary skill in the art will be able to think of various equivalents that, although not explicitly described herein, embody the principles of the present invention.

[0048] Example 1

[0049] Metal-oxide semiconductor field-effect transistors (MOS transistors) are a common type of transistor used in integrated circuits. Their operating principle is to control the switching of a semiconductor conductive channel by applying a voltage between a metal gate and a source across an oxide layer, generating an electric field. Based on the channel type, MOS transistors can be divided into P-channel MOS field-effect transistors (PMOS) and N-channel MOS field-effect transistors (NMOS). PMOS refers to a MOS transistor with an N-type substrate and a P-type channel, which uses the flow of holes to carry current. NMOS refers to a MOS transistor with a P-type substrate and an N-type channel, which uses the flow of holes to carry current. With the continuous improvement of chip integration and performance requirements, MOS transistors have gradually evolved from a planar structure to a 3D structure, developing a multi-gate MOSFET structure. Because of its fin-like shape, this transistor is called a FinFET (Fin Field-Effect Transistor). Its gate-wrapped structure enhances gate control capabilities, providing better electrical control of the channel, thereby reducing leakage current and suppressing short-channel effects. Similarly, FinFET devices can be classified into P-type FinFET devices and N-type FinFET devices based on their channel type. Specifically, FinFET devices can be dual-gate devices, tri-gate devices, and / or other structures. FinFET devices can be included in integrated circuits such as microprocessors, memory devices, and / or other ICs.

[0050] Generally, a FinFET device includes a semiconductor substrate 1, a plurality of isolation structures and a gate structure. Figure 1The semiconductor substrate 1 may include a supporting substrate 101 and a plurality of fin structures 102, with a gate structure disposed on the fin structures 102. Each fin structure 102 includes a source region and a drain region. An isolation structure, also referred to as shallow trench isolation (STI), is disposed between adjacent fin structures 102. The isolation structure may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials. The isolation structure may be formed by etching a substrate to form a trench and then filling the trench with an isolation material. The fin structure 102 is used to form the source region of the device, and the channel region of the transistor device is formed in the fin structure 102. The material of the fin structure 102 may include silicon or other elemental semiconductors such as germanium. For example, compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide may be used. Optionally, the fin structure 102 can be formed by continuously etching the substrate using plasma etching technology. Specifically, a mask can be formed on the substrate by photolithography, and then the substrate (such as a silicon layer) is etched to a certain depth based on the mask to form the fin structure 102. Figure 1 The semiconductor substrate 1 shown includes a fin structure 102. Of course, the fin structure 102 can also be formed using self-aligned double patterning (SADP) technology as needed. Specifically, an auxiliary layer (such as silicon nitride) can be first formed on the substrate, followed by etching to form a gate-like structure, etching to form a gate sidewall structure, removing the auxiliary layer to form a hard mask, and then continuing etching to form the fin structure 102.

[0051] The manufacturing process of FinFET devices is relatively complex and involves multiple doping, etching and deposition processes. For example, Figure 1After the semiconductor substrate 1 is formed, it is necessary to dope the semiconductor substrate 1, i.e., perform ion implantation, to dope the portion of the supporting substrate 101 and the portion of the fin structure 102 of the semiconductor substrate 1 to form a P-well or N-well. Subsequently, deposition, photolithography, and other processes are required to prepare an isolation structure. Ion implantation is then performed in the channel region of the fin structure 102 to form an N-type channel or a P-type channel. Multiple deposition and photolithography processes are then performed to prepare a gate structure. In a FinFET device, doping the semiconductor substrate 1 is primarily to form the well region and the channel, which are used to adjust the threshold voltage (Vt), leakage current (breakdown resistance), and reduce resistance. Ideally, it is hoped that the doped elements will not diffuse at all, and the initial doping location and dosage will be the same as the doping location and dosage after all processes are completed. However, in actual processes, elements can diffuse due to temperature or other factors, which can prevent the desired effect from being achieved. Research has found that this is mainly because the deposition or other processes involved after doping are prone to element diffusion. Compared to planar structures, three-dimensional FinFET devices have smaller feature sizes and more complex three-dimensional spatial structures. There are higher requirements for the position and concentration of doping elements (such as boron and phosphorus). When the elements diffuse, the effect of element doping will be greatly weakened, such as Vt shift, leakage and other problems.

[0052] There are two main mechanisms for boron and phosphorus diffusion: vacancy-substitutional diffusion and interstitial diffusion. In the absence of interstitial silicon, the temperature-induced diffusion mechanism is vacancy-substitutional diffusion. When interstitial silicon is present, temperature-induced diffusion occurs not only through vacancy-substitutional diffusion but also through interstitial diffusion. The diffusion coefficients under these two mechanisms are greater than those under simple vacancy-substitutional diffusion.

[0053] The following are Figure 2-4 Explanation of the various atomic diagrams shown in:

[0054] Represents silicon atom

[0055] Represents interstitial silicon atoms

[0056] Represents oxygen atoms

[0057] Represents the oxygen atom occupying the silicon atom position

[0058] ●Atoms representing inert gases (such as argon)

[0059] Previous solutions to reduce boron and phosphorus diffusion mainly focused on reducing the temperature after doping. However, even if the temperature is reduced to the process limit, there are still other processes that cause significant diffusion. Figure 2, which shows a schematic diagram of the arrangement of silicon atoms in a semiconductor substrate. When the thermal oxidation process is carried out, the presence of interstitial silicon will increase the thermal diffusion coefficient, such as Figure 3 As shown in the figure, oxygen atoms in the thermal oxidation process will occupy the position of the top silicon atoms, causing the occupied silicon atoms to diffuse into the substrate to form interstitial silicon. It can also occur in plasma deposition processes, such as PECVD deposition, see Figure 4 The plasma generated will bombard the substrate silicon, not only causing oxygen atoms to occupy the positions of the top silicon atoms, causing the occupied silicon atoms to diffuse into the substrate to form interstitial silicon, but also due to the bombardment of argon atoms, directly causing the top silicon atoms to diffuse into the substrate to form interstitial silicon, thereby accelerating the diffusion of boron and phosphorus. To this end, the present application proposes a solution to reduce interstitial silicon in the silicon substrate. Specifically, a layer of amorphous silicon (a-Si) can be first grown on the surface of the semiconductor substrate 1, or a contact layer of the substrate silicon can be formed using a non-plasma deposition process or a low-energy plasma deposition process. This can improve the problem of enhanced boron and phosphorus diffusion due to interstitial silicon in the semiconductor manufacturing process, and achieve precise control of the position and concentration of doping, effectively adjusting Vt, controlling leakage, and reducing resistance.

[0060] The following is a brief description of the process equipment involved in the embodiments of the present application (such as PECVD deposition and furnace tube process).

[0061] See also Figure 5 , which shows a simplified structural diagram of a plasma enhanced chemical vapor deposition device provided in an embodiment of the present application. The plasma enhanced chemical vapor deposition device includes a deposition chamber 5, a carrier platform 8, a controller 6, a heating device 7, a gas supply device and an exhaust device, etc. A semiconductor substrate 1 is placed on the carrier platform 8, and the carrier platform 8 is electrically connected to the heating device 7, so that the carrier platform 8 can be heated by controlling the heating device 7 as needed, thereby achieving heating of the semiconductor substrate 1. Optionally, the heating device 7 can also be electrically connected to the controller 6, and the heating device 7 can be controlled based on the controller 6. An air inlet channel 9 and a plasma generating area are provided at the top of the deposition chamber 5. The air inlet channel 9 is connected to the gas supply device, and the gas supply device is used to provide gas to the plasma generating area through the air inlet channel 9. The plasma generating area is electrically connected to the controller 6, so that the power pulse of plasma generation can be controlled based on the controller 6. Optionally, the exhaust device is connected to the exhaust channel 10 of the deposition chamber 5 for discharging excess gas in the deposition chamber 5. The characteristic of PECVD deposition is that it uses microwaves or radio frequencies to form plasma with gases containing atoms that make up the film. The chemical activity of plasma is very strong and it is easy to react, thereby depositing the desired film on the substrate.

[0062] The furnace tube process is a process for depositing a semiconductor substrate 1 using a furnace tube apparatus. The furnace tube apparatus includes a furnace tube chamber, a heating device, and a processor. Specifically, the semiconductor substrate 1 is placed in the furnace tube chamber, and then reacting gases are delivered into the furnace tube chamber through a multi-channel air inlet. By controlling parameters such as the pressure and temperature within the furnace tube chamber, these gases react to form the desired thin film. A controller is electrically connected to the gas supply device, heating device, etc., and is used to control the operating parameters of each device or component (such as the heating device) in the furnace tube apparatus to achieve deposition and formation of the desired thin film on the semiconductor substrate 1.

[0063] It should be noted that although the embodiments of the present application mainly describe the doping and deposition process steps involved in FinFET devices, in fact, as long as the processing of semiconductor devices involves high temperature or plasma deposition steps after doping, the above-mentioned element diffusion problem will exist, which will in turn affect electrical properties such as threshold voltage and leakage.

[0064] See also Figure 6 , which shows the boron diffusion situation of boron doped in different depth areas of a semiconductor structure provided by an embodiment of the present application. Among them, curve a represents the boron diffusion situation obtained after boron is doped only in the substrate doping region of the substrate of the semiconductor structure and heated in an inert gas atmosphere. Curve b represents the boron diffusion situation obtained after boron is doped in the substrate doping region of the substrate of the semiconductor structure and heated in an oxidizing gas atmosphere (this process will cause thermal oxidation on the surface to produce interstitial silicon). Curve c represents the boron diffusion situation obtained after boron is doped in the substrate doping region of the substrate of the semiconductor structure, and then a layer of silicon dioxide is deposited by PECVD, and finally heated in an inert gas atmosphere. Comparing the above curves a, b, and c, it can be seen that after boron is doped in the substrate doping region of the substrate, subsequent heating (whether in an inert atmosphere or an oxidizing atmosphere) or PECVD deposition of a film on the substrate doping region will cause the boron in the substrate doping region to diffuse into the substrate non-doped region. Moreover, it is obvious that the use of plasma bombardment will accelerate the diffusion of boron compared to the heating method. This is because a large amount of interstitial silicon will be formed during the formation of the thin film on the semiconductor substrate 1. Surface oxidation accounts for only a small portion of the interstitial silicon formation process. The primary source is RF-generated plasma bombardment (plasma bombardment originates from a variety of processes, such as PEALD, PEOX, and PES IN). This involves ion bombardment of numerous silicon atoms from the surface of doped single-crystal silicon into the substrate, forming a significant amount of interstitial silicon. Subsequently, under increased temperature, boron and phosphorus diffuse significantly. Thin film deposition on the substrate silicon surface is essential, and the PECVD thin-film deposition process involves plasma bombardment, which can lead to boron and phosphorus diffusion.

[0065] In view of this, an embodiment of the present application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate 1; performing a doping treatment on a predetermined region of the semiconductor substrate 1; and forming a first target layer 2 on the semiconductor substrate 1, wherein the first target layer 2 comprises an amorphous silicon layer. Optionally, the deposition temperature for forming the first target layer is less than 400 degrees Celsius.

[0066] In this embodiment, the semiconductor substrate is Figure 1 As an example, the structure shown is a substrate containing a fin structure 102 in a FinFET device. The semiconductor substrate 1 structure includes a supporting substrate 101 and a plurality of fin structures 102 located on the supporting substrate 101. Optionally, the method for forming the semiconductor substrate may include: providing a substrate (specifically, a silicon wafer), coating a photoresist on the substrate, patterning the photoresist using a photolithography process, etching the substrate using an etching process, and then removing the residual photoresist to obtain the structure shown in FIG. Figure 1 The semiconductor structure shown. Optionally, the above etching process can be a wet etching process or a dry etching process, which is not limited here. A reasonable choice is made based on the type of photoresist and the required etching accuracy. Of course, in addition to the above photoresist, the etching mask can also be a hard mask, such as silicon nitride. The method for forming the above semiconductor substrate 1 may include: providing a substrate (specifically, it can be a silicon wafer), forming a mask material layer on the substrate using a deposition process, and then patterning the mask material layer to form a mask, and subsequently etching the substrate to a preset depth using a dry etching process based on the mask to form a film such as Figure 1 The semiconductor structure shown. Optionally, the specific method of patterning the mask material layer can be to form a patterned hard mask using a self-aligned double imaging technique, such as forming an auxiliary layer on the surface of the patterned mask material layer, and then forming a gate-like structure, the width of the gate-like structure is equal to the width between the lines of the hard mask after subsequent patterning, and depositing a layer of silicon dioxide on the surface of the gate-like structure as a mask. By controlling the thickness of the silicon dioxide layer, the width of the hard mask can be controlled, and then a dry etching process is used to form a gate sidewall structure, and then the auxiliary layer is removed, and the hard mask material layer is etched. The silicon dioxide layer is removed to obtain a patterned hard mask. Other dry etching methods can also be used, which are not limited here. Specifically, a layer of photoresist can be coated on the hard mask material layer, and then the exposure-development-wet etching process steps are performed to obtain a patterned hard mask.

[0067] In this embodiment, in order to further improve the vertical accuracy of the fin structure 102, multiple photolithography processes can be used in the process of patterning the mask material layer. Specifically, a first photoresist can be coated on the mask material layer, the first photoresist is patterned to form a first photoresist mask, the mask material layer is etched based on the first photoresist mask, and then the remaining first photoresist is removed. Then, a second photoresist is coated on the mask material layer, the second photoresist is patterned to form a second photoresist mask, the mask material layer is etched based on the second photoresist mask, and the remaining second photoresist is removed. The above steps of coating photoresist, patterning photoresist, etching the mask material layer based on the photoresist mask, and removing the remaining photoresist are repeated until the patterning of the mask material layer is completed, and the position of the etching window of the patterned photoresist is different each time. Optionally, in order to further improve the efficiency of patterning the mask material layer, the following scheme can also be used: a first photoresist can be first spin-coated on the mask material layer, the first photoresist can be patterned using an exposure and development process, and then the first photoresist can be chemically frozen. A second photoresist can be spin-coated on the first photoresist, and the second photoresist can be patterned using an exposure and development process. The second photoresist can be chemically frozen, and another photoresist can be repeatedly spin-coated on the photoresist, and the photoresist can be patterned using an exposure and development process. Finally, multiple patterned photoresists are formed on the mask material layer, and the mask material layer is patterned using a dry etching process or a wet etching process. The photoresist is removed to obtain a patterned hard mask.

[0068] In this embodiment, the semiconductor substrate 1 may be a silicon substrate, and a layer of amorphous silicon may be grown on the surface of the semiconductor substrate 1 using a furnace tube process. Optionally, the temperature for growing the amorphous silicon is lower than 400 degrees Celsius, thereby avoiding not only the effect of plasma bombardment on the diffusion of dopant elements in the semiconductor substrate 1 but also the effect of temperature on the diffusion of dopant elements in the semiconductor substrate 1. After the amorphous silicon layer is formed on the semiconductor substrate 1, the following can be obtained: Figure 7 The structure shown in Figure 1 can be represented by the atomic distribution as follows: Figure 8 As shown in the structural diagram, it can be seen that the silicon in the amorphous silicon layer is in an amorphous state. Subsequently, when the second target layer 3 (such as a silicon oxide layer) is formed on the first target layer 2, the following is obtained: Figure 9 When the structure is shown, please refer to Figure 10Even if the process for forming the second target layer 3 is a plasma deposition process, the amorphous arrangement of silicon atoms and the resulting collisions at various angles and directions make it difficult to bombard silicon atoms into the substrate silicon containing dopant atoms, preventing the formation of interstitial silicon and thus eliminating the strong diffusion caused by interstitial silicon. Optionally, the second target layer 3 can be formed using a plasma deposition process or a furnace tube process. Specifically, the furnace tube process can be used to thermally oxidize the semiconductor substrate 1 to form the silicon oxide layer on the semiconductor substrate 1. Optionally, the second target layer 3 can also be a silicon nitride layer.

[0069] In one feasible embodiment, the thickness of the first target layer is 1 to 6 nanometers, thereby preventing subsequent film layers from forming gap silicon in the substrate silicon. For example, the thickness of the first target layer can be 1 nanometer, 2 nanometers, 3 nanometers, 4 nanometers, 5 nanometers, or 6 nanometers.

[0070] In this embodiment, the doping position and the type of elements are different depending on the doping function. For example, when the FinFET device to be formed in the embodiment of the present application is a P-type FinFET device, and the well region to be formed, then the above-mentioned doping treatment of the preset area of ​​the semiconductor substrate 1 may specifically include: performing N-type ion implantation into the first area of ​​the semiconductor substrate 1 to form an N-well in the first area of ​​the semiconductor substrate 1. The first area includes an area in the supporting substrate 101 close to the fin structure 102 and an area in the fin structure 102 close to the supporting substrate 101. Optionally, the N-type ions may be elements corresponding to Group V, such as phosphorus, arsenic or antimony. After forming the second target layer 3, the method further includes: forming a third target layer on the second target layer 3, and the third target layer may be an isolation layer 4, to obtain the following. Figure 11 The structure shown is subsequently subjected to chemical mechanical polishing and photolithography on the isolation layer 4 to form an isolation structure. Typically, an isolation structure is provided between adjacent fin structures 102. If a channel region is to be formed, the above-mentioned doping treatment of the preset region of the semiconductor substrate 1 may specifically include: performing P-type ion implantation into the second region of the semiconductor substrate 1 to form a P channel in the second region of the semiconductor substrate 1; the second region may be a region near the top of the fin structure 102. P-type ions may include boron ions, boron fluoride ions or indium ions. After forming the second target layer 3, the method further includes: forming a third target layer on the second target layer 3; the third target layer may be a polysilicon layer for the subsequent preparation of a gate structure.

[0071] When the FinFET device to be formed in the embodiment of the present application is an N-type FinFET device and a well region is to be formed, then the above-mentioned doping treatment of the preset region of the semiconductor substrate 1 may specifically include: performing P-type ion implantation into the first region of the semiconductor substrate 1 to form a P-well in the first region of the semiconductor substrate 1. If a channel region is to be formed, then the above-mentioned doping treatment of the preset region of the semiconductor substrate 1 may specifically include: performing N-type ion implantation into the second region of the semiconductor substrate 1 to form an N-channel in the second region of the semiconductor substrate 1; the second region may be the region near the top of the fin structure 102. After forming the second target layer 3, the method further includes: forming a third target layer on the second target layer 3. The third target layer may be a polysilicon layer for subsequent preparation of a gate structure.

[0072] It should be noted that the above-mentioned isolation layer 4 can be formed by different processes depending on the required filling thickness, including sub-pressure chemical vapor deposition (SACVD), high-density plasma chemical vapor deposition (HDP-CVD), flame chemical vapor deposition (FCVD), etc. Among them, the HDP-CVD process is a special form of PECVD, in which thin film deposition and sputtering occur simultaneously, and it can achieve bottom-up filling of grooves and pores. The films deposited by HDP-CVD have higher density and lower impurity content, and are generally used to deposit films of 45 to 130 nanometers. The SACVD process operates at sub-normal pressure. This high-pressure environment reduces the molecular free path of gas-phase chemical reaction materials. Oxygen inclusion generates highly reactive oxygen radicals at high temperatures, increasing intermolecular collisions and achieving superior pore-filling capabilities. It is typically used to deposit films with thicknesses between 14 and 45 nanometers. The FCVD process is used for seamless filling of fine trenches. FCVD is a remote plasma deposition technology that introduces reaction precursors into the reaction chamber in a targeted manner, achieving top-down trench filling. This process can meet the pore-filling requirements of films below 14 nanometers.

[0073] Example 2

[0074] This embodiment of the present application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate 1; performing a doping treatment on a predetermined region of the semiconductor substrate 1; and forming a second target layer 3 on the semiconductor substrate 1 using a predetermined low-temperature deposition process, wherein the predetermined low-temperature deposition process is a furnace tube process. Optionally, the furnace tube process for forming the second target layer has a deposition temperature below 800 degrees Celsius.

[0075] In this embodiment, the semiconductor substrate is Figure 1 As an example, the structure shown is a substrate containing a fin structure 102 in a FinFET device. The semiconductor substrate 1 structure includes a supporting substrate 101 and a plurality of fin structures 102 located on the supporting substrate 101. Optionally, the method for forming the semiconductor substrate may include: providing a substrate (specifically, a silicon wafer), coating a photoresist on the substrate, patterning the photoresist using a photolithography process, etching the substrate using an etching process, and then removing the residual photoresist to obtain the structure shown in FIG. Figure 1 The semiconductor structure shown. Optionally, the above etching process can be a wet etching process or a dry etching process, which is not limited here. A reasonable choice is made based on the type of photoresist and the required etching accuracy. Of course, in addition to the above photoresist, the etching mask can also be a hard mask, such as silicon nitride. The method for forming the above semiconductor substrate may include: providing a substrate (specifically, a silicon wafer), forming a mask material layer on the substrate using a deposition process, and then patterning the mask material layer to form a mask, and subsequently etching the substrate to a preset depth using a dry etching process based on the mask to form a film such as Figure 1 The semiconductor structure shown. Optionally, the specific method of patterning the mask material layer can be to form a patterned hard mask using a self-aligned double imaging technique, such as forming an auxiliary layer on the surface of the patterned mask material layer, and then forming a gate-like structure, the width of the gate-like structure is equal to the width between the lines of the hard mask after subsequent patterning, and depositing a layer of silicon dioxide on the surface of the gate-like structure as a mask. By controlling the thickness of the silicon dioxide layer, the width of the hard mask can be controlled, and then a dry etching process is used to form a gate sidewall structure, and then the auxiliary layer is removed, and the hard mask material layer is etched. The silicon dioxide layer is removed to obtain a patterned hard mask. Other dry etching methods can also be used, which are not limited here. Specifically, a layer of photoresist can be coated on the hard mask material layer, and then the exposure-development-wet etching process steps are performed to obtain a patterned hard mask.

[0076] In this embodiment, in order to further improve the vertical accuracy of the fin structure 102, multiple photolithography processes can be used in the process of patterning the mask material layer. Specifically, a first photoresist can be coated on the mask material layer, the first photoresist is patterned to form a first photoresist mask, the mask material layer is etched based on the first photoresist mask, and then the remaining first photoresist is removed. Then, a second photoresist is coated on the mask material layer, the second photoresist is patterned to form a second photoresist mask, the mask material layer is etched based on the second photoresist mask, and the remaining second photoresist is removed. The above steps of coating photoresist, patterning photoresist, etching the mask material layer based on the photoresist mask, and removing the remaining photoresist are repeated until the patterning of the mask material layer is completed, and the position of the etching window of the patterned photoresist is different each time. Optionally, in order to further improve the efficiency of patterning the mask material layer, the following scheme can also be used: a first photoresist can be first spin-coated on the mask material layer, the first photoresist can be patterned using an exposure and development process, and then the first photoresist can be chemically frozen. A second photoresist can be spin-coated on the first photoresist, and the second photoresist can be patterned using an exposure and development process. The second photoresist can be chemically frozen, and another photoresist can be repeatedly spin-coated on the photoresist, and the photoresist can be patterned using an exposure and development process. Finally, multiple patterned photoresists are formed on the mask material layer, and the mask material layer is patterned using a dry etching process or a wet etching process. The photoresist is removed to obtain a patterned hard mask.

[0077] In this embodiment, the doping position and the type of elements are different depending on the doping function. For example, when the FinFET device to be formed in the embodiment of the present application is a P-type FinFET device, and the well region to be formed, then the above-mentioned doping treatment of the preset area of ​​the semiconductor substrate 1 may specifically include: performing N-type ion implantation into the first area of ​​the semiconductor substrate 1 to form an N-well in the first area of ​​the semiconductor substrate 1. The first area includes an area in the supporting substrate 101 close to the fin structure 102 and an area in the fin structure 102 close to the supporting substrate 101. Optionally, the N-type ions may be elements corresponding to Group V, such as phosphorus, arsenic or antimony. After forming the second target layer 3, the method further includes: forming a third target layer on the second target layer 3, and the third target layer may be an isolation layer 4, to obtain the following. Figure 11The structure shown is subsequently subjected to chemical mechanical polishing and photolithography on the isolation layer 4 to form an isolation structure. Typically, an isolation structure is provided between adjacent fin structures 102. If a channel region is to be formed, the above-mentioned doping treatment of the preset region of the semiconductor substrate 1 may specifically include: implanting P-type ions into the second region of the semiconductor substrate 1 to form a P channel in the second region of the semiconductor substrate 1; the second region may be a region near the top of the fin structure 102. P-type ions may include boron ions, boron fluoride ions or indium ions. After forming the second target layer 3, the method further includes: forming a third target layer on the second target layer 3; the third target layer may be a polysilicon layer for the subsequent preparation of a gate structure.

[0078] When the FinFET device to be formed in the embodiment of the present application is an N-type FinFET device, and the well region to be formed, then the above-mentioned doping treatment of the preset region of the semiconductor substrate 1 may specifically include: performing P-type ion implantation into the first region of the semiconductor substrate 1 to form a P-well in the first region of the semiconductor substrate 1. If a channel region is to be formed, then the above-mentioned doping treatment of the preset region of the semiconductor substrate 1 may specifically include: performing N-type ion implantation into the second region of the semiconductor substrate 1 to form an N-channel in the second region of the semiconductor substrate 1; the second region may be the region near the top of the fin structure 102. After forming the second target layer 3, the method further includes: forming a third target layer on the second target layer 3. The third target layer may be a polysilicon layer for subsequent preparation of a gate structure.

[0079] In this embodiment, the semiconductor substrate 1 can be a silicon substrate, and the second target layer 3 can be a silicon oxide layer. The second target layer 3 can be formed by thermal oxidation on the semiconductor substrate 1 using a furnace process (i.e., a non-plasma deposition process). Since the interstitial silicon formed by pure thermal oxidation is much weaker than plasma bombardment, the presence of interstitial silicon can be effectively suppressed by controlling the thermal growth temperature, thereby reducing the diffusion of dopant elements. Optionally, the second target layer 3 can be silicon nitride in addition to silicon oxide.

[0080] Example 3

[0081] The present embodiment provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate 1; performing a doping treatment on a predetermined region of the semiconductor substrate 1; and forming a second target layer 3 on the semiconductor substrate 1 using a predetermined low-temperature deposition process; the predetermined low-temperature deposition process is a low-energy plasma deposition process. Optionally, the energy of the low-energy plasma deposition process is less than 300 watts.

[0082] In this embodiment, the semiconductor substrate is Figure 1As an example, the structure shown is a substrate containing a fin structure 102 in a FinFET device. The semiconductor substrate 1 structure includes a supporting substrate 101 and a plurality of fin structures 102 located on the supporting substrate 101. Optionally, the method for forming the semiconductor substrate may include: providing a substrate (specifically, a silicon wafer), coating a photoresist on the substrate, patterning the photoresist using a photolithography process, etching the substrate using an etching process, and then removing the residual photoresist to obtain the structure shown in FIG. Figure 1 The semiconductor structure shown. Optionally, the above etching process can be a wet etching process or a dry etching process, which is not limited here. A reasonable choice is made based on the type of photoresist and the required etching accuracy. Of course, in addition to the above photoresist, the etching mask can also be a hard mask, such as silicon nitride. The method for forming the above semiconductor substrate may include: providing a substrate (specifically, a silicon wafer), forming a mask material layer on the substrate using a deposition process, and then patterning the mask material layer to form a mask, and subsequently etching the substrate to a preset depth using a dry etching process based on the mask to form a film such as Figure 1 The semiconductor structure shown. Optionally, the specific method of patterning the mask material layer can be to form a patterned hard mask using a self-aligned double imaging technique, such as forming an auxiliary layer on the surface of the patterned mask material layer, and then forming a gate-like structure, the width of the gate-like structure is equal to the width between the lines of the hard mask after subsequent patterning, and depositing a layer of silicon dioxide on the surface of the gate-like structure as a mask. By controlling the thickness of the silicon dioxide layer, the width of the hard mask can be controlled, and then a dry etching process is used to form a gate sidewall structure, and then the auxiliary layer is removed, and the hard mask material layer is etched. The silicon dioxide layer is removed to obtain a patterned hard mask. Other dry etching methods can also be used, which are not limited here. Specifically, a layer of photoresist can be coated on the hard mask material layer, and then the exposure-development-wet etching process steps are performed to obtain a patterned hard mask.

[0083] In this embodiment, in order to further improve the vertical accuracy of the fin structure 102, multiple photolithography processes can be used in the process of patterning the mask material layer. Specifically, a first photoresist can be coated on the mask material layer, the first photoresist is patterned to form a first photoresist mask, the mask material layer is etched based on the first photoresist mask, and then the remaining first photoresist is removed. Then, a second photoresist is coated on the mask material layer, the second photoresist is patterned to form a second photoresist mask, the mask material layer is etched based on the second photoresist mask, and the remaining second photoresist is removed. The above steps of coating photoresist, patterning photoresist, etching the mask material layer based on the photoresist mask, and removing the remaining photoresist are repeated until the patterning of the mask material layer is completed, and the position of the etching window of the patterned photoresist is different each time. Optionally, in order to further improve the efficiency of patterning the mask material layer, the following scheme can also be used: a first photoresist can be first spin-coated on the mask material layer, the first photoresist can be patterned using an exposure and development process, and then the first photoresist can be chemically frozen. A second photoresist can be spin-coated on the first photoresist, and the second photoresist can be patterned using an exposure and development process. The second photoresist can be chemically frozen, and another photoresist can be repeatedly spin-coated on the photoresist, and the photoresist can be patterned using an exposure and development process. Finally, multiple patterned photoresists are formed on the mask material layer, and the mask material layer is patterned using a dry etching process or a wet etching process. The photoresist is removed to obtain a patterned hard mask.

[0084] In this embodiment, the doping position and the type of elements are different depending on the doping function. For example, when the FinFET device to be formed in the embodiment of the present application is a P-type FinFET device, and the well region to be formed, then the above-mentioned doping treatment of the preset area of ​​the semiconductor substrate 1 may specifically include: performing N-type ion implantation into the first area of ​​the semiconductor substrate 1 to form an N-well in the first area of ​​the semiconductor substrate 1. The first area includes an area in the supporting substrate 101 close to the fin structure 102 and an area in the fin structure 102 close to the supporting substrate 101. Optionally, the N-type ions may be elements corresponding to Group V, such as phosphorus, arsenic or antimony. After forming the second target layer 3, the method further includes: forming a third target layer on the second target layer 3, and the third target layer may be an isolation layer 4, to obtain the following. Figure 11The structure shown is subsequently subjected to chemical mechanical polishing and photolithography on the isolation layer 4 to form an isolation structure. Typically, an isolation structure is provided between adjacent fin structures 102. If a channel region is to be formed, the above-mentioned doping treatment of the preset region of the semiconductor substrate 1 may specifically include: implanting P-type ions into the second region of the semiconductor substrate 1 to form a P channel in the second region of the semiconductor substrate 1; the second region may be a region near the top of the fin structure 102. P-type ions may include boron ions, boron fluoride ions or indium ions. After forming the second target layer 3, the method further includes: forming a third target layer on the second target layer 3; the third target layer may be a polysilicon layer for the subsequent preparation of a gate structure.

[0085] When the FinFET device to be formed in the embodiment of the present application is an N-type FinFET device, and the well region to be formed, then the above-mentioned doping treatment of the preset region of the semiconductor substrate 1 may specifically include: performing P-type ion implantation into the first region of the semiconductor substrate 1 to form a P-well in the first region of the semiconductor substrate 1. If a channel region is to be formed, then the above-mentioned doping treatment of the preset region of the semiconductor substrate 1 may specifically include: performing N-type ion implantation into the second region of the semiconductor substrate 1 to form an N-channel in the second region of the semiconductor substrate 1; the second region may be the region near the top of the fin structure 102. After forming the second target layer 3, the method further includes: forming a third target layer on the second target layer 3. The third target layer may be a polysilicon layer for subsequent preparation of a gate structure.

[0086] In this embodiment, the semiconductor substrate 1 may be a silicon substrate, and the second target layer 3 may be formed on the semiconductor substrate 1 using a low-energy plasma deposition process. This effectively reduces the presence of interstitial silicon and, in turn, reduces the diffusion of dopant elements. Alternatively, the second target layer 3 may be silicon oxide, silicon nitride, or the like, without limitation.

[0087] Example 4

[0088] The present application discloses a semiconductor structure fabricated using the aforementioned method. Specifically, during the formation of the semiconductor structure, a layer of amorphous silicon is grown on the surface of an elementally doped semiconductor substrate 1, or a contact layer of substrate silicon is formed using a non-plasma deposition process or a low-energy plasma deposition process, followed by other processing steps. This improves the problem of enhanced boron and phosphorus diffusion caused by interstitial silicon in the semiconductor manufacturing process, allowing for precise control of the doping location and concentration, effectively adjusting Vt, controlling leakage, and reducing resistance.

[0089] Example 5

[0090] The present application discloses a semiconductor device comprising the aforementioned semiconductor structure. Specifically, the semiconductor device may be any transistor, such as a FinFET device (an N-type FinFET device or a P-type FinFET device). The structure during the formation of the semiconductor device may be defined as a semiconductor structure. During the formation of the semiconductor structure, a layer of amorphous silicon is grown on the surface of an element-doped semiconductor substrate 1 (such as a semiconductor substrate 1 having an n-well or p-well formed therein), or a contact layer of substrate silicon is formed using a non-plasma deposition process or a low-energy plasma deposition process, followed by other processing steps. This improves the problem of enhanced boron and phosphorus diffusion due to interstitial silicon in the semiconductor manufacturing process, allows precise control of the doping position and concentration, and effectively adjusts Vt, controls leakage, and reduces resistance.

[0091] Example 6

[0092] The present application discloses an integrated chip including the aforementioned semiconductor device. Specifically, the integrated chip includes one or more semiconductor devices, such as an N-type FinFET device and a P-type FinFET device. The structure during the formation of the semiconductor device can be defined as a semiconductor structure. In the formation of the semiconductor structure, a layer of amorphous silicon is grown on the surface of an element-doped semiconductor substrate 1 (such as a semiconductor substrate 1 having an n-well or p-well formed therein), or a contact layer of substrate silicon is formed using a non-plasma deposition process or a low-energy plasma deposition process, and then other processes are performed. This can improve the problem of enhanced boron and phosphorus diffusion caused by interstitial silicon in the semiconductor manufacturing process, achieve precise control of the position and concentration of doping, and achieve the effects of effectively adjusting Vt, controlling leakage, and reducing resistance.

[0093] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a semiconductor substrate; performing a doping process on a predetermined area of ​​the semiconductor substrate; forming a first target layer on the semiconductor substrate, or forming a second target layer on the semiconductor substrate using a preset low-temperature deposition process; The first target layer includes an amorphous silicon layer; and the preset low-temperature deposition process includes a furnace tube process.

2. The forming method according to claim 1, wherein: The second target layer includes a dielectric layer; The dielectric layer includes a silicon oxide layer or a silicon nitride layer.

3. The forming method according to claim 2, wherein: The forming of a first target layer on the semiconductor substrate comprises: The amorphous silicon layer is formed on the semiconductor substrate by using a furnace process.

4. The forming method according to claim 3, wherein: The preset low temperature deposition process also includes a low energy plasma deposition process; The energy of the low energy plasma deposition process is less than 300 watts; The deposition temperature for forming the first target layer is lower than 400 degrees Celsius; The deposition temperature corresponding to the furnace tube process for forming the second target layer is lower than 800 degrees Celsius.

5. The forming method according to claim 4, wherein: The forming of the second target layer on the semiconductor substrate by using a preset low-temperature deposition process comprises: The dielectric layer is formed on the semiconductor substrate by utilizing the furnace tube process.

6. The forming method according to claim 4, wherein: The forming of the second target layer on the semiconductor substrate by using a preset low-temperature deposition process comprises: The second target layer is formed on the semiconductor substrate by using the low energy plasma deposition process.

7. The forming method according to claim 4, wherein: The ions doped include N-type ions and P-type ions; The N-type ions include phosphorus ions, arsenic ions or antimony ions; The P-type ions include boron ions, boron fluoride ions or indium ions.

8. The forming method according to claim 7, wherein: The method provides a semiconductor substrate, comprising: providing a substrate; forming a mask material layer on the substrate; patterning the mask material layer to form a mask on the substrate; The substrate is etched to a preset depth, and then the mask is removed to form the semiconductor substrate. The semiconductor substrate includes a supporting substrate and a plurality of fin structures provided on the supporting substrate with preset intervals.

9. The forming method according to claim 8, wherein: The step of performing doping on a predetermined area of ​​the semiconductor substrate includes: N-type or P-type ion implantation is performed into a first region of the semiconductor substrate to form an N-well or P-well in the first region of the semiconductor substrate; the first region includes a region of the supporting substrate close to the fin structure and a region of the fin structure close to the supporting substrate.

10. The forming method according to claim 1, wherein: The thickness of the first target layer is 1 to 6 nanometers.

11. A semiconductor structure, characterized in that It is prepared based on the method according to any one of claims 1 to 10.

12. A semiconductor device, characterized in that: Comprising the semiconductor structure according to claim 11.

13. An integrated chip, characterized in that: Comprising the semiconductor device according to claim 12.

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