Preparation method of semiconductor graphical epitaxial thin film, embedded electrode structure and application

Abstract

The invention relates to the technical field of semiconductor wafers, in particular to a preparation method of a semiconductor graphical epitaxial thin film, an embedded electrode structure and application, and the method comprises the following steps: S1, carrying out the pretreatment of a substrate layer, and carrying out the low-temperature deposition of a high-temperature-resistant hard mask layer on the surface of the pretreated substrate layer; s2, performing segmented etching treatment on the deposited high-temperature-resistant hard mask layer and part of the substrate layer according to a photoetching pattern, and removing the photoresist after etching treatment to obtain a first substrate; s3, the first substrate is placed in a PLD cavity, a bottom electrode thin film layer is epitaxially deposited on the etching face of the first substrate, the thickness of the bottom electrode thin film layer is the same as the etched depth of the substrate layer, and a second substrate is obtained; and S4, performing wet etching on the second substrate until the high-temperature-resistant hard mask layer is completely removed, and performing post-processing to obtain the embedded electrode structure. According to the technical scheme, the problems of high-temperature failure, cavity carbon pollution, pattern collapse, surface roughness and the like of traditional optical cement are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor wafers, and in particular to a preparation method of a semiconductor patterned epitaxial film, an embedded electrode structure and application. BACKGROUND

[0002] In the post-Moore era, new information devices such as integrated storage and calculation and sensing storage fusion have put forward three requirements of "patterned, ultra-thin and CMOS back-end compatible" for the local epitaxial growth of ferroelectric, resistive or phase change storage films. As a mainstream method for preparing high-quality epitaxial oxide films such as HfZrO2, SrFeOx and BiFeO3, pulse laser deposition (PLD) has a typical substrate temperature of >400℃ and an oxygen partial pressure of usually higher than 100 mTorr. Traditional ultraviolet photoresists (such as AZ 5214 and S1813) will decompose and carbon will volatilize within a few minutes in this environment, resulting in mask morphology collapse and loss of pattern transfer precision, decomposition products (C, H, O) polluting the PLD chamber, reducing the crystalline quality of the film and shortening the service life of the target material, carbon remaining at the epitaxial interface forming a leakage channel, and the ferroelectric O phase or resistive active layer being disabled, and the integration of "under-buried electrode + local epitaxy" cannot be achieved.

[0003] The prior art CN202411819211.8 discloses a preparation method of an ultra-thin single-crystal ferroelectric PZT film, which uses a pulse laser deposition (PLD) method to bombard a PZT target with a pulse laser to grow a single-crystal ferroelectric PZT film on a single-crystal substrate. The deposition process includes two stages: a single-crystal layer growth stage and a rapid cooling stage. The method is simple and easy to operate, and the growth of an ultra-thin ferroelectric single-crystal film is realized by controlling the laser energy, substrate deposition growth temperature and oxygen pressure during PLD growth. However, this technology is only suitable for full-area uniform film growth and cannot solve the key technical problems of local patterned epitaxial growth on oxide substrates such as SrTiO3 substrate layers. In particular, when preparing an embedded electrode structure, it is necessary to first form a local patterned region on the substrate and deposit a bottom electrode material, and then perform selective epitaxy of a functional film, which requires precise mask protection in a PLD high-temperature environment of 600-800℃. Since traditional photoresists cannot withstand such harsh process conditions, the prior art cannot achieve the preparation of a patterned embedded electrode structure, which seriously limits the application of such oxide substrates in high-integration storage devices. SUMMARY

[0004] Therefore, the present application provides a preparation method of a semiconductor patterned epitaxial film to solve the technical problem that the prior art cannot achieve the integration of "under-buried electrode + local epitaxy".

[0005] The technical scheme of the present application is implemented as follows: The present application provides a preparation method of a semiconductor patterned epitaxial film, comprising the following steps: S1, pretreating a substrate layer, and depositing a high-temperature-resistant hard mask layer on the surface of the pretreated substrate layer at low temperature; S2, performing segmented etching treatment on the deposited high-temperature-resistant hard mask layer and part of the substrate layer according to a photolithography pattern, removing photoresist after the etching treatment, and obtaining a first substrate; S3, placing the first substrate into a PLD cavity, epitaxially depositing a bottom electrode film layer on the etched surface of the first substrate, the thickness of the bottom electrode film layer being the same as the etched depth of the substrate layer, and obtaining a second substrate; S4, performing wet etching on the second substrate until the high-temperature-resistant hard mask layer is completely removed, and obtaining an embedded electrode structure after post-processing, wherein the embedded electrode is in a strip shape.

[0006] Specifically, the present application proposes an integrated preparation method of "high-temperature-resistant hard mask + segmented etching + epitaxial deposition + selective removal" in view of the technical challenges faced by the preparation of an embedded electrode structure on an oxide substrate such as STO. First, in view of the core problem that the traditional photoresist decomposes and carbon volatilizes at a high temperature (600-800℃) in the PLD environment, resulting in mask failure, the present application uses a high-temperature-resistant hard mask material such as a SiN layer to replace the traditional photoresist, forms a stable mask protection layer on the surface of the oxide substrate through a low-temperature deposition process, and ensures the integrity of the mask structure and the accuracy of the pattern transfer in the subsequent high-temperature PLD process. Secondly, in view of the technical difficulty of realizing the accurate preparation of the embedded electrode structure on the special oxide substrate, the present application designs a segmented etching strategy, selectively etches the hard mask layer to form a pattern, accurately etches the substrate layer to form an embedded groove, fills the conductive oxide in the groove through the PLD epitaxial deposition technology to form a bottom electrode, and finally uses phosphoric acid wet etching to selectively remove the hard mask layer, thereby realizing the embedded electrode structure with a smooth surface. This technical route effectively avoids the limitations of silicon-based materials in traditional CMOS processes, specially adapts to the special physical and chemical properties of oxide substrates, and provides a key structural basis for new memory devices.

[0007] On the basis of the above technical scheme, preferably, in step S1, the substrate layer comprises any one of SrTiO3 substrate layer, LaAlO3 substrate layer, La 0.3 Sr 0.7 Al 0.65 Ta 0.35 O3 substrate layer and DyScO3 substrate layer, and the thickness of the substrate layer is 450-550μm.

[0008] On the basis of the above technical scheme, preferably, in step S1, the high-temperature-resistant hard mask layer is any one of SiN layer, Al2O3 layer, DLC layer and TiN / TaN layer, and the thickness of the high-temperature-resistant hard mask layer is 50-100 nm.

[0009] Different hard mask materials have different adaptability to the high-temperature PLD environment of the oxide substrate. The SiN layer has excellent thermal expansion coefficient matching and interface bonding force with the oxide substrate, and maintains structural integrity at 800℃ high temperature; the Al2O3 layer has strong chemical inertness but is prone to stress cracking; the DLC layer has high hardness but high cost; the TiN / TaN layer may interfere with subsequent testing due to its electrical conductivity. As a more preferred solution, the SiN layer not only has excellent high-temperature resistance, but also forms an ideal etching selectivity ratio with phosphoric acid, ensuring complete removal without damaging the bottom electrode.

[0010] On the basis of the above technical scheme, preferably, in step S1, the high-temperature-resistant hard mask layer is deposited by ICP-CVD low-temperature deposition, the deposition temperature is 150-250℃, and the deposition rate is 20-60 nm / min.

[0011] On the basis of the above technical scheme, preferably, in step S2, the etching depth is 100-150 nm, wherein the etching depth includes the depth of etching through the high-temperature-resistant hard mask layer and partially etching the substrate layer.

[0012] On the basis of the above technical scheme, preferably, in step S2, the segmented etching process specifically includes: S21, first etching the high-temperature-resistant hard mask layer, the etching gas being any one of CF4, CHF3, Ar and O2, the pressure being 5-30 mTorr, the power being 100-1000 W, and the etching rate being 80-200 nm / min; S22, then etching the substrate layer, the etching gas being Cl2 / BCl3 / Ar or CHCl3 / Ar, the pressure being 3-10 mTorr, the ICP power being 800-1200 W, and the etching rate being 40-80 nm / min.

[0013] Specifically, the segmented etching strategy realizes precise layer-by-layer pattern transfer based on the difference between the hard mask layer and the oxide substrate material characteristics. In step S21, a fluorine-based chemical etching system is used for the hard mask layer such as SiN, and relatively high pressure and medium power parameters are set to ensure sufficient chemical reaction while avoiding excessive ion bombardment damage, achieving a fast etching rate of 80-200 nm / min to improve process efficiency. In step S22, the oxide substrate is processed by switching to a chlorine-based chemical system, which uses lower pressure to enhance ion directionality, while significantly increasing ICP power to provide sufficient ion energy to overcome the chemical inertness of the oxide, but controls a lower etching rate to ensure accurate depth control and surface quality. The segmented parameter design fully considers the etching threshold and reaction mechanism differences of different materials, avoids the technical contradiction that a single process condition cannot simultaneously meet the optimal etching requirements of two materials, and ensures accurate transfer of the hard mask pattern and high-quality morphology of the substrate trench.

[0014] On the basis of the above technical scheme, preferably, in step S3, the parameters for epitaxial deposition of the bottom electrode thin film layer are: deposition temperature 600-800℃, laser frequency 1~10Hz, laser energy 200~500mJ, and the bottom electrode thin film layer is 50~100nm.

[0015] On the basis of the above technical scheme, preferably, in step S4, the wet etching of the second substrate specifically includes: soaking the second substrate in 65~75 wt% phosphoric acid for wet etching, the temperature of the wet etching is 25-30℃, and the rate is 2~4nm / min.

[0016] The application also provides an embedded electrode structure, wherein the semiconductor patterned epitaxial thin film is prepared by the preparation method according to any one of claims 1-8.

[0017] The application also provides the use of the embedded electrode structure as described above, wherein the embedded electrode structure is used for preparing a semiconductor wafer.

[0018] The preparation method of the semiconductor patterned epitaxial thin film, the embedded electrode structure and the use of the application have the following beneficial effects compared with the prior art: In this invention, low-temperature SiN (≤350 °C) is first deposited on a substrate, and micro / nano patterns are defined in the SiN using conventional photolithography-dry etching. Subsequently, resist is removed and high-temperature PLD epitaxy is performed. The SiN remains chemically and morphologically stable under an oxidizing atmosphere, serving as a physical barrier for localized growth. After epitaxy, a high-selectivity wet process (thermal phosphoric acid) is used to remove the SiN, exposing buried electrodes or conductive channels, achieving an integrated structure of "embedded electrode-localized epitaxial film". This process completely avoids the limitations of high-temperature resists, and the PLD cavity is free of carbon contamination. Therefore, this invention solves the problems of high-temperature resist failure, cavity carbon contamination, pattern collapse, and surface roughness in traditional photoresist methods. It is suitable for wafer-level fabrication of ferroelectric FeFETs, RRAMs, and neuromorphic in-memory computing devices, offering advantages of high flatness and high pattern accuracy. It provides a highly reliable, flat, and CMOS-compatible process route for patterned epitaxy of novel memories and ferroelectric / resistive switching arrays. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart of the method for preparing a semiconductor patterned epitaxial thin film according to the present invention; Figure 2 This is an electron microscope image of STO etching in an embodiment of the present invention; Figure 3 This is a resistivity retention data diagram of the STO substrate prepared in Example 1 of the present invention; Figure 4 This is a resistivity retention data diagram of the STO substrate prepared in Comparative Example 1 of the present invention. Detailed Implementation

[0021] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0022] Example 1 like Figure 1 As shown, this embodiment provides a method for fabricating a semiconductor patterned epitaxial thin film and an embedded electrode structure, including the following steps: (1) 500 μm SrTiO3 (STO) was cleaned in acetone, ethanol and deionized water respectively using ultrasonic wave, and each solution was cleaned for 15 min; (2) 50 nm SiN hard mask layer was deposited at a low temperature using ICP-CVD, and the deposition temperature was 200 °C and the deposition rate was 40 nm / min; (3) The finished thin film was subjected to photolithography treatment, and the deposited SiN hard mask layer and part of the STO substrate were etched according to the photolithography pattern, wherein in the etching process of SiN, the etching depth was 130 nm, the etching gas was CF4, the pressure was 20 mTorr, the ICP power was 600 W, and the etching rate was 140 nm / min. In the etching process of STO, the etching gas was Cl2 / BCl3 / Ar, the pressure was 6 mTorr, the ICP power was 1000 W, and the etching rate was 60 nm / min; as shown in Figure 2 , an electron microscope image after STO etching is shown, and the etched region arranged at intervals can be seen in the figure. Figure 2

[0023] (4) The photoresist of the above structure was removed in an acetone solution, and the etched substrate was cleaned using ethanol and deionized water to obtain a first substrate; (5) The first substrate was placed in a PLD cavity, and an 80 nm SRO bottom electrode was prepared at a temperature of 700 °C, a laser frequency of 5 Hz and a laser energy of 350 mJ to obtain a second substrate; (6) The second substrate was soaked in 70 wt% phosphoric acid at room temperature, and the wet etching rate was about 3 nm / min. The soaking time was selected according to the thickness of the hard mask layer, until the hard mask layer was completely removed, and then the substrate was cleaned with acetone, ethanol and deionized water to obtain a STO substrate with a smooth surface and a strip-shaped SRO electrode embedded structure. As shown in Figure 3 , the resistance retention data of the STO substrate is 60 Ω. Figure 3

[0024] Example 2 The present embodiment provides a preparation method of a semiconductor patterned epitaxial thin film and an embedded electrode structure, comprising the following steps: (1) 500 μm LaAlO3 (LAO) was cleaned in acetone, ethanol and deionized water respectively using ultrasonic wave, and each solution was cleaned for 15 min; (2) 50 nm Al2O3 hard mask layer was prepared using magnetron sputtering, and the deposition temperature was 200 °C and the deposition rate was 4 nm / min; ​​(3) The completed film is subjected to photolithography treatment, and the deposited Al2O3 hard mask layer and part of the LAO substrate are subjected to etching treatment according to the photolithography pattern. In the etching process of Al2O3, the etching depth is 130 nm, the etching gas can be Cl2, the pressure is 15 mTorr, the ICP power is 600 W, and the etching rate is 60 nm / min. In the etching process of LAO, the etching gas is Cl2 / BCl3 / Ar, the pressure is 6 mTorr, the ICP power is 1000 W, and the etching rate is 60 nm / min; (5) The photoresist of the above structure is removed in an acetone solution, and the etched substrate is cleaned with ethanol and deionized water to obtain a first substrate; (6) The first substrate is placed in a PLD cavity, and an 80 nm LSMO bottom electrode (i.e. La 0.7 Sr 0.3 MnO3) is prepared at a temperature of 700°C, a laser frequency of 5 Hz, and a laser energy of 350 mJ to obtain a second substrate; (7) The second substrate is soaked in 70 wt% phosphoric acid at room temperature, and the wet etching rate is about 3 nm / min. The soaking time is selected according to the thickness of the hard mask layer until the hard mask layer is completely removed, and then acetone, ethanol and deionized water are cleaned to obtain a LAO substrate with a smooth surface and a strip-shaped LSMO electrode embedded structure.

[0025] Example 3 The embodiment provides a preparation method of a semiconductor patterned epitaxial film and an embedded electrode structure, including the following steps: (1) The 450 μm SrTiO3 (STO) is cleaned in acetone, ethanol and deionized water respectively using ultrasonic cleaning, and the cleaning time of each solution is 15 min; (2) A 100 nm SiN hard mask layer is deposited at a low temperature by ICP-CVD, the deposition temperature is 150°C, and the deposition rate is 20 nm / min; (3) The completed film is subjected to photolithography treatment, and the deposited SiN hard mask layer and part of the STO substrate are subjected to etching treatment according to the photolithography pattern. In the etching process of SiN, the etching depth is 150 nm, the etching gas is CF4, the pressure is 5 mTorr, the ICP power is 100 W, and the etching rate is 80 nm / min. In the etching process of STO, the etching gas is Cl2 / BCl3 / Ar, the pressure is 3 mTorr, the ICP power is 800 W, and the etching rate is 40 nm / min; (4) The photoresist of the above structure is removed in an acetone solution, and the etched substrate is cleaned with ethanol and deionized water to obtain a first substrate; (5) Put the first substrate into the PLD cavity, and prepare a 50-nm SRO bottom electrode at a temperature of 600°C, a laser frequency of 1 Hz, and a laser energy of 200 mJ to obtain a second substrate; (6) Soak the second substrate in 65 wt% phosphoric acid at room temperature, and the wet etching rate is about 2 nm / min. The soaking time is selected according to the thickness of the hard mask layer, until the hard mask layer is completely removed, and then the substrate is cleaned with acetone, ethanol, and deionized water, to obtain a STO substrate with a smooth surface and a strip-shaped SRO electrode embedded structure.

[0026] Example 4 The embodiment provides a preparation method of a semiconductor patterned epitaxial film and an embedded electrode structure, and includes the following steps. (1) Clean a 550-μm SrTiO3 (STO) substrate in acetone, ethanol, and deionized water respectively, and the cleaning time of each solution is 15 min; (2) Deposit a 50-nm SiN hard mask layer at a low temperature by ICP-CVD, and the deposition temperature is 250°C and the deposition rate is 60 nm / min; (3) Perform photolithography on the completed film, and etch the deposited SiN hard mask layer and part of the STO substrate according to the photolithography pattern. In the etching process of SiN, the etching depth is 150 nm, the etching gas is CHF3, the pressure is 30 mTorr, the ICP power is 1000 W, and the etching rate is 200 nm / min. In the etching process of STO, the etching gas is CHCl3 / Ar, the pressure is 10 mTorr, the ICP power is 1200 W, and the etching rate is 80 nm / min; (4) Remove the photoresist of the above structure in an acetone solution, and clean the etched substrate with ethanol and deionized water to obtain a first substrate; (5) Put the first substrate into the PLD cavity, and prepare a 100-nm SRO bottom electrode at a temperature of 800°C, a laser frequency of 10 Hz, and a laser energy of 500 mJ to obtain a second substrate; (6) Soak the second substrate in 75 wt% phosphoric acid at room temperature, and the wet etching rate is about 4 nm / min. The soaking time is selected according to the thickness of the hard mask layer, until the hard mask layer is completely removed, and then the substrate is cleaned with acetone, ethanol, and deionized water, to obtain a STO substrate with a smooth surface and a strip-shaped SRO electrode embedded structure.

[0027] Comparative Example 1 The comparative example provides a preparation method of a semiconductor patterned epitaxial film and an electrode structure, and includes the following steps. (1) 500 μm SrTiO3 (STO) is cleaned in acetone, ethanol and deionized water respectively by using ultrasonic wave, and each solution cleaning time is 15 minutes; (2) Part of the STO substrate is etched according to the photoetching pattern, wherein the etching depth of the STO is 125 nm, the etching gas is Cl2 / BCl3 / Ar, the pressure is 6 mTorr, the ICP power is 1000 W, and the etching rate is 60 nm / min; (3) The etched substrate is placed in a PLD cavity, and an 80 nm SRO bottom electrode is prepared at a laser frequency of 5 Hz and a laser energy of 200 mJ at a temperature of 200 °C (because there is photoresist on the substrate, the substrate temperature and the laser energy are limited), wherein the SRO cannot be completely crystallized at this time, and the resistance is large; (4) The substrate obtained in the above step (4) is cleaned in acetone, ethanol and deionized water, and the STO substrate with a rough surface and an SRO electrode (amorphous structure) structure is obtained. Figure 4 As shown in FIG. 3, Figure 4 The resistance retention data of the STO substrate is shown in FIG. 3, and the resistance is 1500 Ω, which is too large and is not conducive to the preparation of the electrode.

[0028] The above only describes the preferred embodiments of the present application and is not used to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a patterned semiconductor epitaxial thin film, characterized in that, Includes the following steps: S1. Pre-treat the substrate layer, and deposit a high-temperature resistant hard mask layer at low temperature on the surface of the pre-treated substrate layer. S2. The deposited high-temperature resistant hard mask layer and part of the substrate layer are etched in sections according to the photolithography pattern. After etching, the photoresist is removed to obtain the first substrate. S3. Place the first substrate into the PLD cavity, and epitaxially deposit a bottom electrode thin film layer on the etched surface of the first substrate. The thickness of the bottom electrode thin film layer is the same as the etched depth of the substrate layer to obtain the second substrate. S4. Perform wet etching on the second substrate until the high-temperature hard mask layer is completely removed. After post-processing, the embedded electrode structure is obtained.

2. The method for preparing a semiconductor patterned epitaxial thin film as described in claim 1, characterized in that: In step S1, the substrate layer includes an SrTiO3 substrate layer, a LaAlO3 substrate layer, and a La... 0.3 Sr 0.7 Al 0.65 Ta 0.35 Either an O3 substrate or a DyScO3 substrate, with a substrate thickness of 450-550 μm.

3. The method for preparing a semiconductor patterned epitaxial thin film as described in claim 1, characterized in that: In step S1, the high-temperature resistant hard mask layer is any one of SiN layer, Al2O3 layer, DLC layer and TiN / TaN layer, and the thickness of the high-temperature resistant hard mask layer is 50~100nm.

4. The method for preparing a semiconductor patterned epitaxial thin film as described in claim 1, characterized in that: In step S1, a high-temperature resistant hard mask layer is deposited using ICP-CVD at a low temperature of 150~250℃ and a deposition rate of 3~60 nm / min.

5. The method for preparing a semiconductor patterned epitaxial thin film as described in claim 1, characterized in that: In step S2, the etching depth is 100~150nm.

6. The method for preparing a semiconductor patterned epitaxial thin film as described in claim 1, characterized in that: In step S2, the segmented etching process specifically includes: S21. First, the high-temperature resistant hard mask layer is etched. The etching gas is any one of CF4, CHF3, Ar and O2. The pressure is 5~30 mTorr, the power is 100~1000 W, and the etching rate is 80~200 nm / min. S22. Then, the substrate is etched using Cl2 / BCl3 / Ar or CHCl3 / Ar as the etching gas, at a pressure of 3~10 mTorr, an ICP power of 800~1200 W, and an etching rate of 40~80 nm / min.

7. The method for preparing a semiconductor patterned epitaxial thin film as described in claim 1, characterized in that: In step S3, the parameters for epitaxial deposition of the bottom electrode thin film layer are: deposition temperature 600-800℃, laser frequency 1~10Hz, laser energy 200~500mJ, and bottom electrode thin film layer thickness 50~100nm.

8. The method for preparing a semiconductor patterned epitaxial thin film as described in claim 1, characterized in that: In step S4, the wet etching of the second substrate specifically includes: immersing the second substrate in 65-75 wt% phosphoric acid for wet etching, with the etching temperature being 25-30℃ and the etching rate being 2-4 nm / min.

9. An embedded electrode structure, characterized in that: The embedded electrode structure is prepared by the preparation method described in any one of claims 1-8.

10. The application of the embedded electrode structure as described in claim 9, characterized in that: The embedded electrode structure is used to fabricate semiconductor wafers.

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