Hybrid detector featuring low-temperature surface passivation

Abstract

The systems, apparatus, and methods include a detector including a plurality of detection elements comprising a portion of a silicon substrate, the portion of the silicon substrate including: a front side of the portion of the silicon substrate including a PIN or NIP diode including a p-type region and an n-type region; and a back side of the portion of the silicon substrate opposite the front side, the back side including a low-temperature deposited passivation layer that configures the PIN or NIP diode to detect electrons entering the back side of the portion of the silicon substrate when a bias is applied.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to European Application No. 22216866.8, filed December 28, 2022, which is incorporated herein by reference in its entirety. [Background technology]

[0002] TECHNICAL FIELD

[0002] The description herein relates to the field of inspection systems, and more particularly to systems for detecting particles using a detector during inspection.

[0003]

[0003] During the integrated circuit (IC) manufacturing process, unfinished and completed circuit components are inspected to ensure they are manufactured as designed and are free of defects. Inspection systems that use optical microscopes typically have a resolution of up to a few hundred nanometers, which is limited by the wavelength of light. As the physical size of IC components continues to shrink to less than 100 nanometers or even less than 10 nanometers, inspection systems capable of higher resolution than those that use optical microscopes are needed.

[0004]

[0004] Charged particle (e.g., electron) beam microscopes capable of sub-nanometer resolution, such as scanning electron microscopes (SEMs) or transmission electron microscopes (TEMs), serve as viable tools for inspecting IC components with feature sizes of less than 100 nanometers. Using an SEM, electrons from a single primary electron beam, or from multiple primary electron beams, can be focused onto a target location on a wafer under inspection. The primary electrons interact with the wafer and may be backscattered or may cause the wafer to emit secondary electrons. The intensity of the electron beam, including the backscattered and secondary electrons, can vary based on the characteristics of the wafer's internal and external structure, thereby indicating whether the wafer has defects. Summary of the Invention

[0005]

[0005] Embodiments of the present disclosure provide apparatus, systems, and methods for forming a passivation layer on an electron detector, the apparatus, systems, and methods including depositing or synthesizing a passivation material on a surface of a wafer as part of forming an electron detector on the wafer, wherein the wafer is heated to less than 400°C during deposition of the passivation material and during all remaining fabrication steps of the electron detector. In some embodiments, the systems and methods include a silicon substrate thinned to a thickness of 50 nm to 1 mm, a front side of the silicon substrate including a lateral or vertical PIN diode formed by a p-type region and an n-type region, a region between the p-type region and the n-type region configured to form an intrinsic region when a reverse bias is applied between the p-type region and the n-type region, a back side of the silicon substrate opposite the front side, the back side including a surface that is substantially transparent to electrons, and a passivation layer on either the diode surface or the back side opposite the front side of the silicon substrate, wherein the lateral or vertical PIN diode is configured to detect electrons incident on the back side of the silicon substrate and passing through the silicon substrate to a depletion region.

[0006]

[0006] In some embodiments, the detector may include a plurality of detection elements, each of the plurality of detection elements comprising a portion of a silicon substrate, the portion of the silicon substrate including a front side of the portion of the silicon substrate including a PIN or NIP diode including a p-type region and an n-type region, a back side of the portion of the silicon substrate opposite the front side, the back side including a substantially transparent surface, and a passivation layer on the back side of the portion of the silicon substrate, the region between the p-type region and the n-type region being configured to form a depleted region or an intrinsic region when a reverse bias is applied between the p-type region and the n-type region, and the PIN diode being configured to detect electrons incident on the back side of the portion of the silicon substrate and passing through the portion of the silicon substrate to the depleted region or the intrinsic region.

[0007]

[0007] In some embodiments, the detector may include a plurality of detection elements, each of the plurality of detection elements comprising a portion of a silicon substrate, the portion of the silicon substrate including a front side of the portion of the substrate including a PIN diode including a p-type region and an n-type region, a back side of the portion of the substrate opposite the front side, the back side including a substantially transparent surface, and a layer on the back side of the portion of the substrate, wherein the front side interconnect patterning is deposited at a low temperature.

[0008]

[0008] In some embodiments, the detector may include a plurality of detection elements, each of the plurality of detection elements including a portion of a substrate, the portion of the substrate including a front side of the portion of the substrate including a p-type region and an n-type region forming a PIN diode, and a back side of the portion of the substrate opposite the front side, the back side including a substantially transparent surface, and the back side passivation is deposited at low temperature after the front side interconnect patterning process.

[0009]

[0009] In some embodiments, a method of forming a detection element of a detector may include forming a PIN diode on a front side of a silicon substrate by inserting p-type dopants into the silicon substrate to form a p-type region and inserting n-type dopants to form an n-type region, wherein the region between the p-type region and the n-type region is configured to form a depleted region or an intrinsic region when a reverse bias is applied between the p-type region and the n-type region; and thinning a back side of the silicon substrate opposite the front side, wherein the back side comprises a substantially transparent surface that acts as a defect-neutralizing passivation layer using ultra-thin aluminum-doped silicon formed by metal-induced crystallization or layer exchange (from Al(Si X%), where X can vary from 0), or new materials such as chemical vapor deposition (CVD) (e.g., low-pressure CVD and plasma-enhanced CVD, etc.) boron. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic diagram illustrating an exemplary electron beam inspection (EBI) system consistent with an embodiment of the present disclosure. [Figure 2A]

[0011] 2 is a schematic diagram illustrating an example multi-beam system that is part of the example charged particle beam inspection system of FIG. 1, consistent with an embodiment of the present disclosure. [Figure 2B]

[0012] 2 is a schematic diagram illustrating an example single beam system that is part of the example charged particle beam inspection system of FIG. 1, consistent with an embodiment of the present disclosure. [Figure 3A]

[0013] 1 is a schematic diagram of an exemplary structure of a detector, consistent with embodiments of the present disclosure. [Figure 3B]

[0014] 1 is a schematic diagram of a cross-sectional structure of a substrate of a detector, consistent with an embodiment of the present disclosure. [Figure 3C]

[0015] 1 is a schematic diagram of a cross-sectional structure of a substrate of a detector, consistent with an embodiment of the present disclosure. [Figure 3D]

[0016] 1 is a schematic diagram of an individual sensing element consistent with an embodiment of the present disclosure. [Figures 4A-4C]

[0017] Schematic of the process for developing a conventional electron detector. [Figure 5A-5B]

[0018] 1 is a schematic diagram of an exemplary process for developing an electron sensing element using low temperature passivation, consistent with embodiments of the present disclosure. [Figures 6A-6C]

[0019] 1 is a schematic diagram of another exemplary process for developing an electron sensing element using low temperature passivation, consistent with embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011]

[0020] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, in which like numbers represent the same or similar elements in the various figures, unless otherwise indicated. The implementations described in the following description of exemplary embodiments do not represent all implementations consistent with the present disclosure. Instead, they are merely examples of apparatus and methods consistent with aspects related to the subject matter recited in the appended claims. For example, while some embodiments are described in the context of utilizing electron beams, the disclosure is not so limited. Other types of charged particle beams may be applied as well. Furthermore, other imaging systems that produce corresponding types of images may be used, such as optical imaging, photon detection, x-ray detection, extreme ultraviolet inspection, deep ultraviolet inspection, etc.

[0012]

[0021] Electronic devices are built from circuits formed on a piece of silicon called a substrate. Many circuits can be formed together on the same piece of silicon, and they are called integrated circuits, or ICs. The size of these circuits is shrinking dramatically, resulting in more circuits being able to fit on a substrate. For example, the IC chip in a smartphone can be as small as a thumbnail, yet contain over 2 billion transistors, each less than 1 / 1000 the size of a human hair.

[0013]

[0022] Manufacturing these tiny ICs is a complex, time-consuming, and expensive process, often involving hundreds of individual steps. An error in even one step can result in a defect that renders the finished IC unusable. Therefore, one of the goals of the manufacturing process is to prevent such defects and maximize the number of functional ICs produced during the process—in other words, to increase the overall process yield.

[0014]

[0023] One factor in improving yield is monitoring the chip manufacturing process to ensure that a sufficient number of functional integrated circuits are being produced. One way to monitor the process is to inspect the chip circuit structures at various stages of their formation. Inspection can be performed using a scanning electron microscope (SEM). The SEM can be used to image these extremely small structures, essentially taking a "picture" of the structures on the wafer. The images can be used to determine whether the structures were formed properly and in the right location. If the structures are defective, the process can be adjusted to make the defect less likely to recur. Defects can occur during various stages of semiconductor processing. For the reasons stated above, it is important to find defects as early, accurately, and efficiently as possible.

[0015]

[0024] The operating principle of an SEM is similar to that of a camera. A camera takes a picture by receiving and recording the brightness and color of light reflected or emitted from a person or object. An SEM takes a "picture" by receiving and recording the energy or quantity of electrons reflected or emitted from a structure. Before taking such a "picture," an electron beam can be directed onto the structure. As electrons reflect or emit ("emit") from the structure, the SEM's detector can receive and record the energy or quantity of those electrons to generate an image. Some SEMs use a single electron beam to take such a "picture" (called a "single-beam SEM"), while other SEMs use multiple electron beams to take multiple "photographs" of the wafer (called a "multi-beam SEM"). By using multiple electron beams, the SEM can direct more electron beams onto the structure to obtain these multiple "photographs," resulting in more electrons being emitted from the structure. Thus, the detector can simultaneously receive more emitted electrons, allowing for more efficient and faster generation of images of the wafer's structures.

[0016]

[0025] During process development of these conventional detectors, passivation layers are incorporated to reduce leakage current caused by surface defects and to reduce signal charge captured by surface traps. Current processes for depositing passivation materials (e.g., boron) involve heating the wafer to temperatures in excess of 700°C.

[0017]

[0026] However, the use of high temperatures makes the development process more complicated. For example, materials with low melting points, such as CMOS IC metal interconnects or MOSFET gates, must be formed after the high-temperature step to avoid being damaged by temperatures above their melting points. Due to this requirement, some hybrid detectors (e.g., detectors containing multiple elements) or detectors requiring backside processing undergo at least three steps of processing: 1) high-temperature front-side processing, including ion implantation and implant activation; 2) high-temperature backside passivation; and 3) front-side low-temperature processing, including metal deposition and gate formation.

[0018]

[0027] Some of the disclosed embodiments provide systems and methods that address some or all of these shortcomings by providing new, high-quality passivation layers that can be applied (e.g., deposited or synthesized) at lower temperatures so that the passivation layers can be safely incorporated without damaging IC metal interconnects or MOSFET gates already formed on the wafer. The ability to apply passivation layers at lower temperatures can simplify the development process, improve yields, and reduce costs.

[0019]

[0028] The low-temperature passivation layer is distinguished from standard CMOS surface passivation in that it functions as a defect-neutralizing passivation. The defect-neutralizing passivation reduces defects formed on the surface by providing a reduced density of surface states available for defect agglomeration. This defect-neutralizing passivation also functions as a diffusion barrier to prevent re-oxidation of the surface, which can lead to additional surface defects. The passivation material is configured to be substantially transparent to the electrons of the electron beam, where substantially transparent can be greater than 90%, greater than 95%, or greater than 99%. SiN, AlO x and SiON are some of the commonly used materials for CMOS surface passivation. The commonly used materials mentioned above are often deposited at temperatures greater than 200° C., often lack defect neutralization, and require complex doping and deposition strategies to truly mitigate defectivity. At least some embodiments of the present disclosure use ultra-thin aluminum-doped silicon (e.g., 10 nm or less in some embodiments, 50 nm or less in other embodiments) or high-purity boron material, for example, formed by metal-induced crystallization or layer exchange (from Al(Si X%), where X can vary from 0), as a passivation layer for defect reduction because these types of materials not only allow for low-temperature deposition but also have superior defect reduction compared to the standard materials mentioned above.

[0020]

[0029] The relative dimensions of components in the figures may be exaggerated for clarity. In the following description of the drawings, the same or similar reference numbers refer to the same or similar components or entities, and only the differences relative to the individual embodiments are described.

[0021]

[0030] As used herein, unless otherwise indicated, the term "or" includes all possible combinations unless impracticable. For example, if a component is described as possibly including A or B, the component may include A or B, or may include A and B, unless otherwise indicated or impracticable. As a second example, if a component is described as possibly including A, B, or C, the component may include A or B or C, or A and B, or A and C, or B and C, or A, B, and C, unless otherwise indicated or impracticable.

[0022]

[0031] Some embodiments may be described in the context of providing detectors and methods of detection in systems utilizing electron beams without limiting the scope of the disclosure. However, the disclosure is not so limited. Other types of charged particle beams may be similarly applicable. Furthermore, the systems and methods for detection may be used in other imaging systems, such as optical imaging, photon detection, x-ray detection, ion detection, etc.

[0023]

[0032] FIG. 1 illustrates an exemplary electron beam inspection (EBI) system 100 consistent with embodiments of the present disclosure. The EBI system 100 can be used for imaging. As shown in FIG. 1 , the EBI system 100 includes a main chamber 101, a load lock chamber 102, an electron beam tool 104, and an equipment front-end module (EFEM) 106. The electron beam tool 104 is positioned within the main chamber 101. The EFEM 106 includes a first loading port 106a and a second loading port 106b. The EFEM 106 may include additional loading ports. The first loading port 106a and the second loading port 106b receive wafer front-opening integrated pods (FOUPs) containing wafers (e.g., semiconductor wafers or wafers made of other materials) or samples (wafers and samples may be used interchangeably) to be inspected. A "lot" is a plurality of wafers that can be loaded for processing as a batch.

[0024]

[0033] One or more robot arms (not shown) in the EFEM 106 can transfer wafers to the load lock chamber 102. The load lock chamber 102 is connected to a load lock vacuum pumping system (not shown), which removes gas molecules from the load lock chamber 102 to reach a first pressure below atmospheric pressure. After the first pressure is reached, one or more robot arms (not shown) can transfer the wafers from the load lock chamber 102 to the main chamber 101. The main chamber 101 is connected to a main chamber vacuum pumping system (not shown), which removes gas molecules from the main chamber 101 to reach a second pressure below the first pressure. After the second pressure is reached, the wafers are inspected by the electron beam tool 104. The electron beam tool 104 can be a single beam system or a multi-beam system.

[0025]

[0034] The controller 109 is electronically connected to the electron beam tool 104. The controller 109 may be a computer configured to perform various controls of the EBI system 100. Although the controller 109 is shown in FIG. 1 as being external to the structure including the main chamber 101, the load lock chamber 102, and the EFEM 106, it will be understood that the controller 109 may be part of that structure.

[0026]

[0035] In some embodiments, the controller 109 may include one or more processors (not shown). A processor may be a general-purpose or specialized electronic device capable of manipulating or processing information. For example, a processor may include any combination of any number of central processing units (or "CPUs"), graphics processing units (or "GPUs"), optical processors, programmable logic controllers, microcontrollers, microprocessors, digital signal processors, intellectual property (IP) cores, programmable logic arrays (PLAs), programmable array logic (PALs), generic array logic (GALs), complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), systems-on-chips (SoCs), application-specific integrated circuits (ASICs), and any type of circuitry capable of processing data. A processor may also be a virtual processor, including one or more processors distributed across multiple machines or devices coupled via a network.

[0027]

[0036] In some embodiments, the controller 109 may further include one or more memories (not shown). Memory may be a general-purpose or specialized electronic device capable of storing code and data accessible to a processor (e.g., via a bus). For example, memory may include any combination of any number of random access memories (RAMs), read-only memories (ROMs), optical disks, magnetic disks, hard drives, solid-state drives, flash drives, security digital (SD) cards, memory sticks, compact flash (CF) cards, or any type of storage device. Code may include an operating system (OS) and one or more application programs (i.e., "apps") for specific tasks. Memory may also be virtual memory, including one or more memories distributed across multiple machines or devices coupled via a network.

[0028]

[0037] Embodiments of the present disclosure may provide a single charged particle beam imaging system ("single beam system"). In comparison to a single beam system, a multiple charged particle beam imaging system ("multi-beam system") can be designed to optimize throughput for different scanning modes. Embodiments of the present disclosure provide a multi-beam system that can optimize throughput for different scanning modes by using beam arrays with different geometries and accommodate different throughput and resolution requirements.

[0029]

[0038] 2A, which is a schematic diagram illustrating an exemplary electron beam tool 104, including a multi-beam inspection tool that is part of the EBI system 100 of FIG. 1, consistent with embodiments of the present disclosure. In some embodiments, the electron beam tool 104 can be operated as a single-beam inspection tool that is part of the EBI system 100 of FIG. 1. The multi-beam electron beam tool 104 (also referred to herein as apparatus 104) includes an electron source 201, a Coulomb aperture plate (or "gun aperture plate") 271, a condenser lens 210, a source transformation unit 220, a primary projection system 230, a motorized stage 209, and a sample holder 207 supported by the motorized stage 209 for holding a sample 208 (e.g., a wafer or photomask) to be inspected. The multi-beam electron beam tool 104 may further include a secondary projection system 250 and an electron detection device 240. The primary projection system 230 may include an objective lens 231. The electronic detection device 240 may include a number of detection elements 241, 242 and 243. The beam separator 233 and the deflection scanning unit 232 may be arranged inside the primary projection system 230.

[0030]

[0039] The electron source 201, gun aperture plate 271, condenser lens 210, source conversion unit 220, beam separator 233, deflection scanning unit 232, and primary projection system 230 may be aligned with a primary optical axis 204 of the apparatus 104. The secondary projection system 250 and electron detection device 240 may be aligned with a secondary optical axis 251 of the apparatus 104.

[0031]

[0040] The electron source 201 may include a cathode (not shown) and an extractor or anode (not shown), and in operation the electron source 201 is configured to emit primary electrons from the cathode, which are extracted or accelerated by the extractor and / or anode to form a primary electron beam 202, which forms a (virtual or real) primary beam crossover 203. The primary electron beam 202 can be visualized as being emitted from the primary beam crossover 203.

[0032]

[0041] The source conversion unit 220 may include an image-forming element array (not shown), an aberration compensator array (not shown), a beam-limiting aperture array (not shown), and a pre-bending micro-deflector array (not shown). In some embodiments, the pre-bending micro-deflector array deflects multiple primary beamlets 211, 212, 213 of the primary electron beam 202 to be perpendicularly incident on the beam-limiting aperture array, the image-forming element array, and the aberration compensator array. In some embodiments, the apparatus 104 can be operated as a single-beam system so that a single primary beamlet is generated. In some embodiments, the condenser lens 210 is designed to focus the primary electron beam 202 into a parallel beam that is perpendicularly incident on the source conversion unit 220. The imaging element array may include multiple micro-deflectors or micro-lenses to influence the multiple primary beamlets 211, 212, 213 of the primary electron beam 202 and form multiple (virtual or real) parallel images of the primary beam crossover 203, one for each of the primary beamlets 211, 212, and 213. In some embodiments, the aberration compensator array may include a field curvature compensator array (not shown) and an astigmatism compensator array (not shown). The field curvature compensator array may include multiple micro-lenses to compensate for field curvature aberration of the primary beamlets 211, 212, and 213. The astigmatism compensator array may include multiple micro-astigmatists to compensate for astigmatism of the primary beamlets 211, 212, and 213. The beam-limiting aperture array may be configured to limit the diameter of each of the primary beamlets 211, 212, and 213. 2A shows, by way of example, three primary beamlets 211, 212, and 213, it being understood that the source conversion unit 220 can be configured to form any number of primary beamlets. The controller 109 can be connected to various parts of the EBI system 100 of FIG. 1, such as the source conversion unit 220, the electronic detection device 240, the primary projection system 230, or the motorized stage 209. In some embodiments, the controller 109 can perform various image and signal processing functions, as described in more detail below.The controller 109 may also generate various control signals to control the operation of the charged particle beam inspection system.

[0033]

[0042] The condenser lens 210 is configured to focus the primary electron beam 202. The condenser lens 210 may be further configured to adjust the current of the primary beamlets 211, 212, and 213 downstream of the source conversion unit 220 by changing the focusing power of the condenser lens 210. Alternatively, the current can be changed by changing the radial size of the beam-limiting aperture in the beam-limiting aperture array corresponding to each primary beamlet. The current can be changed by changing both the radial size of the beam-limiting aperture and the focusing power of the condenser lens 210. The condenser lens 210 may be an adjustable condenser lens that may be configured such that the position of its first principal plane is movable. The adjustable condenser lens may be configured to be magnetic, such that the off-axis beamlets 212 and 213 may irradiate the source conversion unit 220 with a rotation angle. The rotation angle varies with the focusing power or the position of the first principal plane of the adjustable condenser lens. The collecting lens 210 may be an anti-rotation collecting lens that may be configured to keep the rotation angle constant while changing the focusing power of the collecting lens 210. In some embodiments, the collecting lens 210 may be an adjustable anti-rotation collecting lens, in which the rotation angle does not change when the focusing power and the position of the first principal plane change.

[0034]

[0043] The objective lens 231 may be configured to focus the beamlets 211, 212, and 213 onto the sample 208 for inspection, and in the current embodiment, to form three probe spots 221, 222, and 223 on the surface of the sample 208. The Coulomb aperture plate 271 is configured to block peripheral electrons of the primary electron beam 202 during operation to reduce the Coulomb effect, which may increase the size of each of the probe spots 221, 222, and 223 of the primary beamlets 211, 212, 213 and therefore reduce the inspection resolution.

[0035]

[0044] The beam separator 233 may be, for example, a Wien filter including electrostatic deflectors that generate electrostatic and magnetic dipole fields (not shown in FIG. 2A ). During operation, the beam separator 233 may be configured to exert an electrostatic force on individual electrons of the primary beamlets 211, 212, and 213 by the electrostatic dipole field. The electrostatic force is equal in magnitude but opposite in direction to the magnetic force exerted on individual electrons by the magnetic dipole field of the beam separator 233. Thus, the primary beamlets 211, 212, and 213 may pass at least substantially straight through the beam separator 233 with at least substantially zero deflection angle.

[0036]

[0045] During operation, the deflection scanning unit 232 is configured to deflect the primary beamlets 211, 212, and 213 to scan the probe spots 221, 222, and 223 across respective scan areas within a section of the surface of the sample 208. In response to the incidence of the primary beamlets 211, 212, and 213, or the probe spots 221, 222, and 223, on the sample 208, electrons emerge from the sample 208 and generate three secondary electron beams 261, 262, and 263. Each of the secondary electron beams 261, 262, and 263 typically includes secondary electrons (having an electron energy of 50 eV or less) and backscattered electrons (having an electron energy between 50 eV and the landing energy of the primary beamlets 211, 212, and 213). The beam separator 233 is configured to deflect the secondary electron beams 261, 262, and 263 towards the secondary projection system 250. Secondary projection system 250 then focuses secondary electron beams 261, 262, and 263 onto detector elements 241, 242, and 243 of electron detection device 240. Detector elements 241, 242, and 243 are arranged to detect corresponding secondary electron beams 261, 262, and 263 and generate corresponding signals that are sent to controller 109 or a signal processing system (not shown), for example, to construct an image of a corresponding scanned area of ​​sample 208.

[0037]

[0046] In some embodiments, detector elements 241, 242, and 243 detect corresponding secondary electron beams 261, 262, and 263, respectively, and generate corresponding intensity signal outputs (not shown) to an image processing system (e.g., controller 109). In some embodiments, each detector element 241, 242, and 243 may include one or more pixels. The intensity signal output of a detector element may be the sum of signals generated by all of the pixels in the detector element.

[0038]

[0047] In some embodiments, the controller 109 may include an image processing system including an image acquirer (not shown) and storage (not shown). The image acquirer may include one or more processors. For example, the image acquirer may include a computer, a server, a mainframe host, a terminal, a personal computer, any type of mobile computing device, etc., or a combination thereof. The image acquirer may be communicatively coupled to the electronic detection device 240 of the apparatus 104 via a medium such as electrical conductors, a fiber optic cable, a portable storage medium, IR, Bluetooth, the Internet, a wireless network, wireless radio, or a combination thereof, among others. In some embodiments, the image acquirer may receive signals from the electronic detection device 240 and construct an image. In this manner, the image acquirer may acquire an image of the sample 208. The image acquirer may also perform various post-processing functions, such as generating contours and superimposing indicators on the acquired image. The image acquirer may be configured to perform adjustments, such as brightness and contrast, on the acquired image. In some embodiments, the storage may be a storage medium, such as a hard disk, a flash drive, cloud storage, random access memory (RAM), or other types of computer-readable memory. The storage may be coupled to the image acquirer and can be used to store raw scanned image data as original images and to store post-processed images.

[0039]

[0048] In some embodiments, the image acquirer can acquire one or more images of the sample based on an imaging signal received from the electronic detection device 240. The imaging signal can correspond to a scanning operation to perform charged particle imaging. The acquired image can be a single image including multiple imaging areas. The single image can be stored in storage. The single image can be an original image that can be divided into multiple regions. Each region can include one imaging area that includes a feature of the sample 208. The acquired image can include multiple images of a single imaging area of ​​the sample 208 sampled multiple times over a time series. The multiple images can be stored in storage. In some embodiments, the controller 109 can be configured to perform image processing steps using multiple images of the same location of the sample 208.

[0040]

[0049] In some embodiments, the controller 109 may include measurement circuitry (e.g., an analog-to-digital converter) to obtain a distribution of detected secondary electrons. The electron distribution data collected during the detection time window may be used in combination with corresponding scan path data for each of the primary beamlets 211, 212, and 213 incident on the wafer surface to reconstruct an image of the wafer structure under inspection. The reconstructed image may be used to reveal various features of the internal or external structure of the sample 208, thereby revealing defects that may be present in the wafer.

[0041]

[0050] In some embodiments, the controller 109 may control the motorized stage 209 to move the sample 208 during inspection of the sample 208. In some embodiments, the controller 109 may enable the motorized stage 209 to move the sample 208 continuously in one direction at a constant speed. In other embodiments, the controller 109 may enable the motorized stage 209 to vary the speed of movement of the sample 208 over time depending on the step in the scanning process.

[0042]

[0051] 2A shows that apparatus 104 uses three primary electron beams, it will be understood that apparatus 104 may use one, two, or more primary electron beams. This disclosure does not limit the number of primary electron beams used in apparatus 104. In some embodiments, apparatus 104 may be an SEM used for lithography. In some embodiments, electron beam tool 104 may be a single beam system or a multi-beam system.

[0043]

[0052] For example, as shown in FIG. 2B , electron beam tool 100B (also referred to herein as apparatus 100B) may be a single-beam inspection tool for use in EBI system 10 consistent with embodiments of the present disclosure. Apparatus 100B includes a wafer holder 136 supported by a motorized stage 134 for holding a wafer 150 to be inspected. Electron beam tool 100B includes an electron emitter, which may include a cathode 103, an anode 121, and a gun aperture 122. Electron beam tool 100B further includes a beam-limiting aperture 125, a condenser lens 126, a column aperture 135, an objective lens assembly 132, and a detector 144. In some embodiments, objective lens assembly 132 may be a modified SORIL lens, including a pole piece 132a, a control electrode 132b, a deflector 132c, and an excitation coil 132d. In the imaging process, an electron beam 161 emerging from the tip of the cathode 103 may be accelerated by the anode 121 voltage, pass through the gun aperture 122, the beam limiting aperture 125, the condenser lens 126, and be focused into a probe spot 170 by a modified SORIL lens, where it may impinge on the surface of the wafer 150. The probe spot 170 may be scanned across the surface of the wafer 150 by a deflector, such as deflector 132c or another deflector in the SORIL lens. Secondary particles or scattered primary particles, such as secondary electrons or scattered primary electrons, emerging from the wafer surface may be collected by the detector 144 so that the intensity of the beam may be determined and an image of the area of ​​interest on the wafer 150 may be reconstructed.

[0044]

[0053] An image processing system 199 may also be provided, including the image acquirer 120, the storage 130, and the controller 109. The image acquirer 120 may include one or more processors. For example, the image acquirer 120 may include a computer, a server, a mainframe host, a terminal, a personal computer, any type of mobile computing device, etc., or a combination thereof. The image acquirer 120 may be connected to the detector 144 of the electron beam tool 100B via a medium such as electrical conductors, a fiber optic cable, a portable storage medium, IR, Bluetooth, the Internet, a wireless network, wireless radio, or a combination thereof. The image acquirer 120 may receive signals from the detector 144 and construct an image. In this manner, the image acquirer 120 may acquire an image of the wafer 150. The image acquirer 120 may also perform various post-processing functions, such as generating contours and superimposing indicators on the acquired image. The image acquirer 120 may be configured to perform adjustments, such as brightness and contrast, on the acquired image. The storage 130 may be a storage medium such as a hard disk, random access memory (RAM), cloud storage, or other type of computer-readable memory. The storage 130 may be coupled to the image acquirer 120 and may be used to store raw scanned image data as original images and to store post-processed images. The image acquirer 120 and the storage 130 may be connected to the controller 109. In some embodiments, the image acquirer 120, the storage 130, and the controller 109 may be integrated together as a single electronic control unit.

[0045]

[0054] In some embodiments, the image acquirer 120 can acquire one or more images of the sample based on an imaging signal received from the detector 144. The imaging signal can correspond to a scanning motion for performing charged particle imaging. The acquired image can be a single image that includes multiple imaging areas that can include various features of the wafer 150. The single image can be stored in the storage 130. The imaging can be performed based on imaging frames.

[0046]

[0055] The condenser and illumination optics of the electron beam tool may include or be supplemented by electromagnetic quadrupole electron lenses. For example, as shown in FIG. 2B , electron beam tool 100B may include a first quadrupole lens 148 and a second quadrupole lens 158. In some embodiments, the quadrupole lenses are used to control the electron beam. For example, first quadrupole lens 148 may be controlled to adjust the beam current, and second quadrupole lens 158 may be controlled to adjust the beam spot size and beam shape.

[0047]

[0056] 2B illustrates a charged particle beam device in which the inspection system may use a single primary beam that may be configured to generate secondary electrons by interacting with the wafer 150. As in the embodiment shown in FIG. 2B, the detector 144 may be positioned along the optical axis 105. The primary electron beam may be configured to travel along the optical axis 105. Thus, the detector 144 may include a hole in its center to allow the primary electron beam to pass through and reach the wafer 150.

[0048]

[0057] Referring now to Figure 3A, Figure 3A shows a schematic diagram of an exemplary structure of a detector 300, consistent with embodiments of the present disclosure. Detector 300 may be provided as detector 144 or electron detection device 240, with reference to Figures 2A and 2B. While one array is shown in Figure 3A, it will be understood that detector 300 may include multiple arrays, such as one array for each secondary electron beam.

[0049]

[0058] Detector 300 may include an array of detector elements, including detector elements 311, 312, and 313. The detector elements may be arranged in a planar two-dimensional array, with the plane of the array substantially perpendicular to the direction of incidence of the incoming charged particles. In some embodiments, detector 300 may be arranged at an angle to the direction of incidence.

[0050]

[0059] The detector 300 may include a substrate 310. The substrate 310 may be a semiconductor substrate that may include a detector element. The detector element may be a diode. The detector element may be a diode-like element that can convert incident energy into a measurable signal. The detector element may include, for example, a PIN diode, an avalanche diode, an electron multiplier tube (EMT), or the like, or a combination thereof. Furthermore, the term "detector element" may encompass or cover "sensing element," "sensor element," "detector cell," "detector segment," or the like. In some embodiments, a pixel on a detector may be a detector element.

[0051]

[0060] Area 325 may be provided between adjacent detector elements. Area 325 may be an isolation area for isolating sides or corners of adjacent detector elements from one another. Area 325 may include an insulating material that is a different material from the material of other areas of the detector 300's detection surface. Area 325 may be provided as a cross-shaped area as seen in the plan view of FIG. 3A . Area 325 may be provided as a square. In some embodiments, area 325 may not be provided between adjacent sides of detector elements. For example, in some embodiments, no isolation area may be provided on the detector's detection surface.

[0052]

[0061] The detector element can generate an electrical signal in response to charged particles received by the active area of ​​the detector element. For example, the detector element can generate a current signal in response to the energy of the received electrons. A pre-processing circuit can convert the generated current signal into a voltage that can represent the intensity of the electron beam spot or a portion thereof. The pre-processing circuit can include, for example, a pre-amplifier circuit. The pre-amplifier circuit can include, for example, a charge transfer amplifier (CTA), a transimpedance amplifier (TIA), or an impedance conversion circuit coupled to the CTA or TIA. In some embodiments, a signal processing circuit can be provided that provides an output signal in any unit in time series. One or more substrates, such as dies, can be provided that can form circuit layers for processing the output of the detector element. The dies can be stacked together across the thickness of the detector. Other circuits can be provided for other functions. For example, a switch actuation circuit can be provided that can control switch elements for connecting the detector elements to each other.

[0053]

[0062] Referring now to FIG. 3B, FIG. 3B shows a schematic diagram of a cross-sectional structure of a substrate 310, which may be an example of a structure included in a PIN detector consistent with embodiments of the present disclosure. The substrate 310 may include one or more layers. For example, the substrate 310 may be configured to have multiple layers stacked in a thickness direction, with the thickness direction being substantially parallel to the incident direction of the electron beam. In some embodiments, the substrate 310 may have multiple layers stacked in a direction perpendicular to the incident direction of the electron beam. The substrate 310 may be provided with a sensor surface 301 for receiving incident charged particles. Detecting elements (e.g., detecting elements 311, 312, and 313) may be provided in a sensing layer of the substrate 310. Areas 325 may be provided between adjacent detecting elements. For example, the substrate 310 may include trenches or other structures made of or filled with insulating material. In some embodiments, the areas 325 may extend entirely or partially through the substrate 310.

[0054]

[0063] As shown in FIG. 3C , in some embodiments, an area 325 may not be provided between sensing elements consistent with embodiments of the present disclosure. For example, no insulating material may be provided between sides of adjacent sensing elements in a cross-sectional view. Multiple sensing elements may be contiguous in a cross-sectional view. Isolation between adjacent sensing elements may also be achieved by other means, such as controlling an electric field. For example, an electric field may be controlled between each sensing element.

[0055]

[0064] Although the figures may show the detector elements 311, 312, and 313 as discrete units, such division may not actually exist. For example, the detector elements may be formed by semiconductor devices that constitute a PIN diode device. The PIN diode device may be fabricated as a substrate having multiple layers, including a p-type region, an intrinsic region, and an n-type region. One or more of such layers may be continuous in cross-section. However, in some embodiments, physical separation may be provided between the detector elements. In addition to the sensor layer, further layers may be provided, such as a circuit layer and a readout layer.

[0056]

[0065] As an example of additional layers, the detector 300 may include one or more circuit layers adjacent to the sensor layer. The one or more circuit layers may include lines, interconnects, and various electronic circuit components. The one or more circuit layers may include a processing system. The one or more circuit layers may include signal processing circuitry. The one or more circuit layers may be configured to receive detected output current from the sensing elements of the sensor layer. The one or more circuit layers and the sensor layer may be provided on the same or separate dies, for example.

[0057]

[0066] FIG. 3D shows a schematic diagram of an individual detector element, which may be an example of one of detector elements 311, 312, and 313, consistent with embodiments of the present disclosure. For example, FIG. 3D shows detector element 311A. Detector element 311A ​​may include a semiconductor structure of p-type layer 321, intrinsic layer 322, and n-type layer 323. Detector element 311A ​​may include two terminals, such as an anode and a cathode. A reverse bias may be applied to detector element 311A, forming a depleted region 330 that may span a portion of the length of p-type layer 321, substantially the entire length of intrinsic layer 322, and a portion of the length of n-type layer 323. In depleted region 330, charge carriers may disappear, and new charge carriers generated in depleted region 330 may be swept away according to their charge. For example, when an incoming charged particle reaches the sensor surface 301, an electron-hole pair may be generated, with the hole 351 being attracted towards the p-type layer 321 while the electron 352 is attracted towards the n-type layer 323. In some embodiments, a passivation layer may be provided on the sensor surface 301.

[0058]

[0067] During operation, the depletion region of the sensing element can function as a trapping region. Incoming charged particles can interact with the semiconductor material in the depletion region, generating new charges. For example, the sensing element can be configured such that charged particles having energy above a certain amount dislodge electrons from the lattice of the semiconductor material, creating electron-hole pairs. The resulting electrons and holes can travel in opposite directions due to, for example, an electric field within the depletion region. The generation of carriers traveling toward the terminals of the sensing element can correspond to a current flow in the sensing element.

[0059]

[0068] In a comparative example, a photodiode may be configured to generate an electric charge in response to receiving a photon. The photon may have an energy corresponding to its wavelength or frequency. Typically, photons in the visible light spectrum may have an energy on the order of about 1 eV. However, a semiconductor photodiode may typically require about 3.6 eV to generate one electron-hole pair. Therefore, photodiodes may face the following problems when detecting current generation:

[0060]

[0069] Generally, the energy level of a photon may be similar to that required to generate an electron-hole pair in a semiconductor photodiode. Therefore, to generate a stable and reliable current, high-energy photons may be required to be incident on the semiconductor photodiode. If the photon frequency is above a certain level, the photon may have enough energy to generate one electron-hole pair.

[0061]

[0070] Furthermore, the current generated by the electron-hole pair in response to a photon arrival event may be relatively small. The current generated in response to a photon arrival event may not be sufficient to overcome background noise. Some diodes, such as photodiodes biased in avalanche or Geiger counting mode, may utilize amplification to generate larger levels of current so that a useful detection signal can be generated. In some embodiments, the photodiode can be biased in an avalanche mode of operation. In some embodiments, amplification can be provided by a gain block attached to the photodiode. The avalanche effect can arise from a strong internal electric field created by a bias voltage. The avalanche effect can be used to achieve amplification by impact ionization.

[0062]

[0071] 4A-4C show schematic diagrams of a process for developing an electron detector of conventional design developed at high temperatures. For example, FIG. 4A shows detector element 400 including substrate 403 (conventionally constructed of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), etc.) with a vertical PIN diode, the PIN diode including p-type regions 404 and 405 and n-type region 406 that may be prepared for processing. The PIN diode may be formed on front side 401 of detector element 400. While the figure and corresponding description refer to a vertical PIN diode, it will be understood that a lateral PIN diode may also be used, in which region 404 is an n-type region, region 405 is a p-type region, and region 406 is an intrinsic region. Furthermore, although the figure and corresponding description refer to a PIN diode, it will be understood that a NIP diode may also be used.

[0063]

[0072] 4B, the process continues by turning sensing element 400 over and depositing a passivation layer 407 on the backside 402 of sensing element 400. In conventional systems, passivation layer 407 is composed of boron and is formed on the backside 402 of sensing element 400 at a high temperature of 700° C.

[0064]

[0073] As shown in Figure 4C, the process continues by turning sensing element 400 over again and performing processing on front side 401. As shown in Figure 4C, metal interconnects 408-410 may be applied to sensing element 400. In conventional systems, interconnects 408-410 are applied to sensing element 400 after passivation layer 407 is applied because temperatures as high as 700°C would damage metal interconnects 408-410. Furthermore, conventional processing techniques limit the library of interconnect types that can withstand high temperature processing at 700°C.

[0065]

[0074] As discussed above, the disclosed embodiments provide systems and methods that address some or all of these shortcomings of conventional systems by providing a new passivation layer that can be applied (e.g., deposited or synthesized) at lower temperatures. This passivation layer is configured to reduce leakage caused by surface defects and reduce electron capture caused by surface traps. The ability to apply the passivation layer at lower temperatures can simplify the development process and reduce costs, and the passivation layer acts as a defect-neutralizing passivation. Figures 5A and 5B illustrate a simplified process for developing a detector element (e.g., detector elements 311, 312, 313) consistent with embodiments of the present invention. In Figure 5A, a first step is shown: detector element 500 can include a substrate 503 (e.g., a silicon substrate) with a vertical PIN diode, where the PIN diode includes pp-type regions 504 and 505 and n-type region 506. The PIN diode can be formed on a front side 501 of detector element 500. After forming the PIN diodes, metal interconnects 507, 508, and 509 may be deposited at a temperature of 400° C. or less over the PIN diodes formed on front side 501 of detector element 500. For example, the metal interconnects may be made of aluminum, which may be tempered at a temperature of 700° C. Although the figures and corresponding description refer to vertical PIN diodes, it will be understood that lateral PIN diodes may also be used, in which region 504 is an n-type region, region 505 is a p-type region, and region 506 is an intrinsic region.

[0066]

[0075] After the interconnects are applied, the process may continue to deposit a passivation layer 510 on the backside 502 of the substrate 503, as shown in Figure 5B. In some embodiments, the passivation layer 510 may comprise ultra-thin Al-doped Si formed by metal-induced crystallization or layer exchange (Al(Si X%), where X can vary from 0), CVD (e.g., low-pressure CVD, plasma-enhanced CVD, etc.) boron, indium, tin, or new compositions of materials including, but not limited to, other metals, semiconductors, or alloys.

[0067]

[0076] Additionally, the passivation layer 510 can be applied (e.g., deposited or synthesized) to the backside 502 at temperatures below 400°C. In some embodiments, the passivation layer 510 can be deposited on the same side as the diode. Low-temperature passivation processes produce defect-neutralizing passivation that offers advantages in integration simplicity and help target the surface defect limitations of conventional systems by allowing passivation with the interconnect material already present. They can also help expand the library of materials used to pattern the frontside 501 for gain enhancement. By applying (e.g., depositing, synthesizing, etc.) the passivation layer at low temperatures, the interconnect materials can be expanded to include Al, Mo, Co, Cu, Ru, Ni, and their alloys.

[0068]

[0077] Furthermore, when compared to conventional systems that require partial front-side processing (as shown in Figures 4A-4C), followed by flipping and high-temperature back-side processing, and then flipping again to apply interconnects to the front side at low temperature, the process is simpler because the complete front-side processing can be performed before processing the back-side with a low-temperature passivation layer.

[0069]

[0078] The thickness of the passivation layer 510 can be in the range of 1 nm to 1000 nm. A thickness close to 1 nm can adequately passivate surface and interface traps while maintaining a low dead zone (increasing the thickness shortens the lifetime of generated charges). On the other hand, a thickness close to 1000 nm can reduce the sheet resistance and provide a better resistance-capacitance (RC) time constant. The appropriate thickness can be evaluated by considering both aspects. Furthermore, the specific profile of the passivation can be engineered (Gaussian or ERFC profile) to generate a good in-built electric field that helps guide the generated signal charges toward the collecting electrode.

[0070]

[0079] 6A-6C, which illustrate another exemplary process for forming a sensing element 600 (eg, sensing elements 311, 312, 313, 500, etc.) consistent with embodiments of the present disclosure.

[0071]

[0080] For example, as shown in FIG. 6A, a first step may be performed on detector element 600, which may include substrate 603 (e.g., substrate 503 of FIG. 5B) (e.g., bulk silicon, epitaxial silicon, silicon-on-insulator (SOI), or other soft metal substrate prepared for processing). In some embodiments, substrate 603 may be a thick substrate (e.g., ranging from 50 nm to 1 mm, and in selected embodiments, 500 to 600 μm) that may serve as intrinsic region 603 of a PIN diode (e.g., substrate and intrinsic region 503 of FIG. 5B). The PIN diode may include p-type regions 604-605 (e.g., p-type regions 504-505 of FIG. 5B) and n-type region 606 (e.g., n-type region 506 of FIG. 5B). The PIN diode may be formed on front side 601 of detector element 600 (e.g., front side 501 of FIG. 5B).

[0072]

[0081] After forming the PIN diodes on the substrate 603, the interconnects 607, 608, and 609 (e.g., interconnects 507, 508, and 509 in FIG. 5B ) can be printed on the front side 601 of the sensing element 600 (e.g., front side 501 in FIG. 5B ), as shown in FIG. 6B . As mentioned above, the metal interconnects 607-609 can be deposited at temperatures of 400° C. or less on top of the PIN diodes formed on the front side 601 of the sensing element 600. For example, the metal interconnects can be made of aluminum, which can be damaged at temperatures of 700° C. Due to the application of a low-temperature passivation layer, the metal interconnects 607-609 can be applied at these low temperatures.

[0073]

[0082] After the interconnects are applied, the process can continue by depositing a defect-neutralizing passivation layer 610 on the exposed backside 602 of the substrate 603, as shown in Figure 6C. In some embodiments, the passivation layer 610 can be deposited on the same side as the diode. In some embodiments, such as the example shown in Figure 6C, the substrate 603 can be trimmed by a mechanical or chemical trimming process (e.g., chemical-mechanical planarization, wet stripping, dry etching) to a thickness of 100 μm (although the trim can be thinner or thicker than 100 μm if desired).

[0074]

[0083] A passivation layer 610 (e.g., passivation layer 510 in FIG. 5B) can be formed on the exposed backside 602 of the detector element or on the same side as the diode. Passivation layer 610 can include ultra-thin Al-doped Si formed by metal-induced crystallization or layer exchange (Al(Si X%), where X can vary from 0), CVD (e.g., low-pressure CVD, plasma-enhanced CVD, etc.) boron, indium, tin, or new compositions of materials including, but not limited to, other metals, semiconductors, or alloys.

[0075]

[0084] Additionally, the passivation layer 610 can be deposited on the exposed backside 602 at temperatures below 400°C. The passivation layer is configured to reduce leakage caused by surface defects and reduce electron capture caused by surface traps. The low-temperature defect-neutralizing passivation process offers the advantage of integration simplicity by enabling passivation with the interconnect material already present. It can also help expand the library of materials used to pattern the frontside 601 for gain enhancement. By applying the passivation layer at low temperatures, the interconnect materials can be expanded to include Al, Mo, Co, Cu, Ru, Ni, and their alloys.

[0076]

[0085] Furthermore, when compared to conventional systems that require partial front-side processing (as shown in Figures 4A-4C), followed by flipping and high-temperature back-side processing, and then flipping again to apply interconnects to the front side at low temperature, the process is simpler because the complete front-side processing can be performed before processing the back-side with a low-temperature passivation layer.

[0077]

[0086] The embodiments can be further described using the following clauses. 1. A method for forming a passivation layer on an electron detector, comprising: applying a passivation material onto a surface of the wafer as part of forming the electron detector on the wafer; A method in which the wafer is heated to less than 400° C. during application of the passivation material and during all remaining fabrication steps of the electron detector. 2. The method of clause 1, wherein heating of the wafer is performed to less than 30° C. during application of the passivation material. 3. The method of clauses 1 and 2, wherein the passivation material comprises Al-doped Si or CVD boron. 4. Passivation materials include SiN and AlO x 4. The method of any one of clauses 1 to 3, wherein the method is not composed of either SiO 2 or SiON. 5. The method of any one of clauses 1-3, wherein the passivation material is configured to be substantially transparent to electrons of the electron beam. 6. The method of any one of clauses 1 to 5, wherein the applied passivation material has a thickness of 1 nm to 1000 nm. 7. The method of any one of clauses 1-6, wherein front side patterning of the wafer is completed prior to application of passivation material to the back side of the wafer. 8. The method of clause 7, wherein the front side patterning includes forming a MOSFET gate. 9. The method of clause 7, wherein the front side patterning includes forming metal interconnects. 10. The method of any one of clauses 1-7, further comprising forming a PIN or NIP diode on the front side of the wafer before depositing passivation material on the back side of the wafer. 11. The method of clause 10, wherein the PIN or NIP diode is a vertical diode. 12. The method of clause 10, wherein the PIN or NIP diode is a lateral diode. 13. The method of any one of clauses 1-12, further comprising forming interconnects on the front side of the wafer before applying the passivation material to the back side of the wafer. 14. The method of clause 13, wherein the interconnect is comprised of at least one of Al, Mo, Co, Ru, Cu, Ni, or alloys thereof. 15. A substrate comprising a silicon wafer; a diode formed on the first side of the wafer, the diode configured to facilitate detection of charged particles emitted from the sample imaged by the charged particle microscope; an interconnect formed on a first side of the wafer; a passivation material formed on a second side of the wafer, the passivation material being formed after the interconnect lines are formed; A detection element comprising: 16. The sensing element of clause 15, wherein the passivation material is comprised of Al-doped Si or CVD boron. 17. Passivation materials include SiN and AlO x or a sensing element according to clause 15, not constructed from SiON. 18. A sensing element as described in clause 15, wherein the passivation material is configured to be substantially transparent to electrons of the electron beam. 19. A sensing element according to any one of clauses 15 to 18, wherein the passivation material has a thickness of 1 nm to 1000 nm. 20. The sensing element of any one of clauses 15 to 19, wherein the interconnect is composed of at least one of Al, Mo, Co, Ru, Cu, Ni, or alloys thereof. 21. A sensing element according to any one of clauses 15 to 20, wherein the passivation material is formed on the second side of the wafer by heating the wafer to less than 400°C during application of the passivation material. 22. A sensing element according to any one of clauses 15 to 21, wherein the passivation material is formed on the second side of the wafer by heating the wafer to less than 30°C during application of the passivation material. 23. A detection element according to any one of clauses 15 to 22, wherein the diode is a PIN diode or a NIP diode. 24. A sensing element according to clause 23, wherein the PIN or NIP diode is a vertical diode. 25. A sensing element according to clause 23, wherein the PIN or NIP diode is a lateral diode. 26. A detector comprising: a plurality of detection elements, each of the plurality of detection elements comprising: a substrate comprising a silicon wafer; a diode formed on the first side of the wafer, the diode configured to facilitate detection of charged particles emitted from the sample imaged by the charged particle microscope; an interconnect formed on a first side of the wafer; a passivation material formed on the first side or the second side of the wafer, the passivation material being formed after the interconnect lines are formed. 27. A detector as described in clause 26, wherein the passivation material is composed of Al-doped Si or CVD boron. 28. Passivation materials include SiN and AlO x 28. A detector according to any one of clauses 26 and 27, wherein the detector is not constructed from SiON. 29. A detector according to any one of clauses 26 to 28, wherein the passivation material is configured to be substantially transparent to electrons of the electron beam. 30. A detector according to any one of clauses 26 to 29, wherein the passivation material has a thickness of between 1 nm and 1000 nm. 31. A detector according to any one of clauses 26 to 30, wherein the interconnect is made of at least one of Al, Mo, Co, Ru, Cu, Ni or alloys thereof. 32. A detector according to any one of clauses 26 to 31, wherein the passivation material is formed on the second side of the wafer by heating the wafer to less than 400°C during application of the passivation material. 33. A detector according to any one of clauses 26 to 32, wherein the passivation material is formed on the second side of the wafer by heating the wafer to less than 30°C during application of the passivation material. 34. A detector according to any one of clauses 26 to 33, wherein the diode is a PIN diode or a NIP diode. 35. A detector according to clause 34, wherein the PIN or NIP diode is a vertical diode. 36. A detector according to clause 34, wherein the PIN or NIP diode is a lateral diode. 37. A charged particle beam microscope comprising: a detector, the detector comprising: a plurality of detection elements, each of the plurality of detection elements comprising: a substrate comprising a silicon wafer; a diode formed on the front side of the wafer, the diode configured to facilitate detection of charged particles emitted from the sample imaged by the charged particle microscope; an interconnect formed on a first side of the wafer; a passivation material formed on a second side of the wafer, the passivation material being formed after the interconnect lines are formed. 38. A charged particle microscope as described in clause 37, wherein the passivation material comprises Al-doped Si or CVD boron. 39. Passivation materials include SiN and AlO x 39. The charged particle microscope of any one of clauses 37 and 38, wherein the charged particle microscope is not constructed from SiON. 40. A charged particle microscope according to any one of clauses 37 to 39, wherein the passivation material is configured to be substantially transparent to electrons of the electron beam. 41. A charged particle microscope according to any one of clauses 37 to 40, wherein the passivation material has a thickness of 1 nm to 1000 nm. 42. A charged particle microscope according to any one of clauses 37 to 41, wherein the interconnect is made of at least one of Al, Mo, Co, Ru, Cu, Ni or alloys thereof. 43. A charged particle microscope as described in any one of clauses 37 to 42, wherein the passivation material is formed on the second side of the wafer by heating the wafer to less than 400°C during application of the passivation material. 44. A charged particle microscope as described in any one of clauses 37 to 43, wherein the passivation material is formed on the second side of the wafer by heating the wafer to less than 30°C during application of the passivation material. 45. A charged particle microscope according to any one of clauses 37 to 44, wherein the diode is a PIN diode or a NIP diode. 46. ​​A charged particle microscope according to clause 45, wherein the PIN or NIP diode is a vertical diode. 47. A charged particle microscope according to clause 45, wherein the PIN or NIP diode is a lateral diode. 48. The method of clause 1, wherein the passivation material is configured to provide defect-neutralizing passivation. 49. The sensing element of clause 15, wherein the passivation material is configured to provide defect-neutralizing passivation. 50. The detector of clause 26, wherein the passivation material is configured to provide defect-neutralizing passivation. 51. The charged particle microscope of clause 37, wherein the passivation material is configured to provide defect-neutralizing passivation.

[0078]

[0087] It will be understood that the embodiments of the present disclosure are not limited to the precise configurations described above and illustrated in the accompanying drawings, and that various modifications and changes can be made without departing from the scope thereof.

Claims

1. 1. A method for forming a passivation layer on an electron detector, comprising: applying a passivation material onto a surface of the wafer as part of forming the electron detector on the wafer; The method wherein the wafer is heated to less than 400° C. during application of the passivation material and during all remaining fabrication steps of the electron detector.

2. 10. The method of claim 1, wherein the wafer is heated to less than 30[deg.] C. during application of the passivation material.

3. The method of claim 1 , wherein the passivation material consists of Al-doped Si or CVD boron.

4. The passivation material is SiN, AlO ｘ The method of claim 1 , wherein the insulating layer is not composed of either silicon dioxide or silicon monoxide.

5. The method of claim 1 , wherein the passivation material is configured to be substantially transparent to electrons of an electron beam.

6. The method of claim 1 , wherein the applied passivation material has a thickness of between 1 nm and 1000 nm.

7. 10. The method of claim 1, wherein front side patterning of the wafer is completed prior to application of the passivation material to the back side of the wafer.

8. The method of claim 7 , wherein the front side patterning comprises forming a MOSFET gate.

9. The method of claim 7 , wherein the front side patterning comprises forming metal interconnects.

10. 10. The method of claim 1, further comprising forming a PIN or NIP diode on the front side of the wafer prior to applying the passivation material to the back side of the wafer.

11. The method of claim 10, wherein the PIN or NIP diode is a vertical diode.

12. The method of claim 10, wherein the PIN or NIP diode is a lateral diode.

13. The method of claim 1 , further comprising forming interconnects on the front side of the wafer before applying the passivation material to the back side of the wafer.

14. 14. The method of claim 13, wherein the interconnect is comprised of at least one of Al, Mo, Co, Ru, Cu, Ni, or alloys thereof.

15. a substrate comprising a silicon wafer; a diode formed on a first side of the wafer, the diode configured to facilitate detection of charged particles emitted from a sample imaged by a charged particle microscope; an interconnect formed on the first side of the wafer; a passivation material formed on a second side of the wafer, the passivation material being formed after the interconnects are formed; and A detection element comprising:

Images