A p-type field effect transistor based on tunneling effect and a preparation method thereof

Abstract

The present application relates to the technical field of transistor, and relates to a P-type field effect transistor based on tunneling effect, which comprises a substrate, a buffer layer, a channel layer, a barrier layer and a first P-type material layer arranged in sequence; a second P-type material layer, a dielectric layer and a third P-type material layer are arranged above the first P-type material layer; a source electrode is arranged above the second P-type material layer; a drain electrode is arranged above the third P-type material layer; the dielectric layer covers the source electrode, the second P-type material layer, the third P-type material layer and the drain electrode; a gate electrode is arranged on the dielectric layer; the drain electrode and the third P-type material layer form an ohmic contact, and the source electrode and the second P-type material layer form a Schottky contact. The present application further provides a preparation method, which comprises the following steps: S1, providing an epitaxial structure; S2, depositing a drain electrode; S3, depositing a source electrode; S4, selectively etching a P-type material layer; S5, depositing a dielectric layer; S6, selectively removing the dielectric layer; and S7, depositing a gate electrode. The present application can guarantee the always-off characteristic and reduce the on-resistance.

Description

Technical Field

[0001] This invention relates to the technical field of transistors, and more specifically, to a P-type field-effect transistor based on the tunneling effect and its fabrication method. Background Technology

[0002] Gallium nitride (GaN), with its excellent physical properties—including a wide bandgap, high breakdown electric field, high electron saturation velocity, and high electron mobility—has become a core material for next-generation power electronic devices. Currently, normally-off devices based on improved gallium nitride high electron mobility transistors (HEMTs), such as P-gate HEMTs and trench-gate HEMTs, have achieved large-scale applications in key areas such as commercial energy management and information communication due to their superior electrical performance and reliability. However, in the process of driving the development of all-gallium nitride integrated circuits towards higher integration densities, developing gallium nitride P-type field-effect transistors that logically complement N-type HEMT devices has become a core technological challenge that urgently needs to be overcome.

[0003] In existing technologies, gallium nitride (GaN) P-type field-effect transistors (FETs) often employ trench gate structures to achieve normally-off characteristics: by etching and thinning the P-type GaN layer, the gate can completely deplete the channel carriers when in the off state. However, this makes it difficult to balance the device's on-resistance and threshold voltage. Specifically, thinning the channel to obtain a more negative threshold voltage to ensure normally-off operation leads to a thinner conductive channel, which in turn causes an increase in on-resistance. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of existing P-type field-effect transistor structures in balancing on-resistance and threshold voltage. It proposes a P-type field-effect transistor based on the tunneling effect, avoiding deep etching of the P-type GaN layer. This technology can hinder hole transport through the wider barrier width of the Schottky junction interface, ensuring normally-off characteristics. Simultaneously, it can reduce the on-resistance when the device is turned on by decreasing the access region distance between the source and gate.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] A P-type field-effect transistor based on the tunneling effect is provided, comprising:

[0007] The substrate, buffer layer, channel layer, barrier layer, first P-type material layer, and dielectric layer are arranged sequentially from bottom to top.

[0008] A second P-type material layer and a third P-type material layer are protruding above the first P-type material layer. The top of the first P-type material layer, the sidewall of the second P-type material layer, and the sidewall of the third P-type material layer together form a first groove structure.

[0009] The second P-type material layer is covered with a source electrode; the third P-type material layer is covered with a drain electrode.

[0010] The dielectric layer continuously covers the top and sidewalls of the source electrode, the first groove structure, and the top and sidewalls of the drain electrode, thereby forming a second groove structure on the upper surface of the dielectric layer; a gate electrode is disposed in the second groove structure and on the side closer to the source electrode.

[0011] In this configuration, an ohmic contact is formed between the drain and the third P-type material layer, and a Schottky contact is formed between the source and the second P-type material layer, forming a Schottky junction. The gate controls the hole tunneling behavior by adjusting the barrier width of the Schottky junction through the dielectric layer.

[0012] The P-type channel transistor based on the tunneling effect of the present invention comprises a substrate, a buffer layer, a channel layer, a barrier layer, and a first P-type material layer stacked from bottom to top to form the basic structure of the device. Above the first P-type material layer, the sidewalls of the second P-type material layer and the sidewalls of the third P-type material layer together form a first groove structure, and a dielectric layer is disposed on the first groove structure. The dielectric layer simultaneously covers the top and sidewalls of the source, the first groove structure, and the top and sidewalls of the drain. The source covered above the second P-type material layer forms a Schottky contact with it, constituting a Schottky junction. The gate disposed above the dielectric layer applies a vertical electric field through the dielectric layer to dynamically control the barrier width of the Schottky junction. A first P-type material layer, a second P-type material layer, a third P-type material layer, a source, a gate, and a drain, all disposed on the barrier layer, together constitute a P-type channel field-effect transistor. The equivalent Schottky junction formed by the second P-type material layer and the source has a triangular barrier at its interface that can be modulated by the electric field between the gate and the dielectric layer. This allows the formation and depletion of the conductive channel to be controlled by the tunneling effect through adjusting the barrier width, thus avoiding the process steps of deep etching of the P-GaN layer. The relatively wide barrier width at the Schottky junction interface hinders hole transport, which can improve the threshold voltage, ensure excellent normally-off characteristics, and reduce the on-resistance when the device is turned on.

[0013] Furthermore, when the gate is in a zero-bias state, the Schottky junction maintains its original barrier width, thereby blocking hole transport. When a negative bias voltage is applied to the gate, the dielectric layer acts on the Schottky junction, thereby reducing the barrier width and increasing the hole tunneling probability. When the gate is in a zero-bias state, the triangular barrier formed by the Schottky junction maintains its original width, effectively blocking hole transport, suppressing carrier tunneling, and ensuring reliable device turn-off. However, when a negative bias voltage is applied to the gate, the gate electric field acts on the Schottky junction interface through the dielectric layer, causing the band structure of the P-type material layer to shift upward, resulting in a narrowing of the triangular barrier width and a significant increase in the hole tunneling probability, thereby inducing the formation of a hole conductive channel.

[0014] Furthermore, the first P-type material layer, the second P-type material layer, and the third P-type material layer are made of the same material. Maintaining the same material for the first, second, and third P-type material layers eliminates band breaks at the heterogeneous interface, ensuring unimpeded hole transport between layers, while also simplifying the epitaxial growth process and improving interface quality. In actual processing, the first, second, and third P-type material layers can be integrally formed by etching grooves in the P-type material layer of the epitaxial wafer.

[0015] Furthermore, the thickness of the first P-type material layer is greater than 30 nm, and the thicknesses of the second and third P-type material layers are the same and both greater than 10 nm. The thickness of the second and third P-type material layers, and their depths, are both greater than 10 nm, meaning the depth of the first groove structure is greater than 10 nm, thus providing sufficient sidewall space to ensure gate control capability. The thickness of the first P-type material layer being greater than 30 nm helps prevent the depletion of the two-dimensional hole gas beneath the first groove structure.

[0016] Furthermore, the doping concentration of the first P-type material layer, the second P-type material layer, and the third P-type material layer is 2 × 10⁻⁶. 19 cm -3 ~4×10 19 cm -3 This is because the transistor in this invention needs to be compatible with existing commercial platforms, and there are certain requirements for the doping concentration range of the P-type material. The selection within this range is to balance the gate control capability and the on-resistance. When the doping concentration is too high, it will cause leakage current in the off state; when the doping concentration is too low, it will increase the on-resistance of the first P-type material layer, the second P-type material layer and the third P-type material layer.

[0017] Furthermore, the source, gate, and drain materials are all one or more combinations of titanium, aluminum, gold, nickel, tungsten, and titanium nitride. Since a Schottky barrier needs to be formed between the source and the second P-type material layer, in 10... 19 To ensure a good on / off ratio for the p-type material layer with orders of magnitude doping, the barrier height between the metal and p-GaN should be no less than 0.8 eV. Therefore, the source metal material is selected from one or more combinations of titanium, gold, tungsten, and titanium nitride.

[0018] Furthermore, the dielectric layer thickness is 10nm~30nm. The dielectric layer thickness is designed to balance the required gate control capability and threshold voltage of the device. Increasing the dielectric layer thickness will increase the subthreshold swing and raise the threshold voltage, and vice versa.

[0019] Furthermore, the gate is disposed on the second recessed structure and partially covers the region of the dielectric layer directly above the source and drain. The gate allows for simultaneous modulation of the electric field at the first, second, and third P-type material layers, reducing the resistance in this region and thus lowering the overall on-resistance of the device. In actual fabrication, a self-aligned process is used during gate deposition. If the gate completely covers the dielectric layer instead of only partially covering it, making the gate shape identical to the dielectric layer shape without exposing the top edge region, then, if there is a process alignment deviation, the gate material may directly extend onto the source or drain metal, causing a short circuit.

[0020] This invention also provides a method for fabricating a P-type field-effect transistor based on the tunneling effect, comprising the following steps:

[0021] S1. Provide an epitaxial structure, wherein the epitaxial structure comprises, from bottom to top, a substrate, a buffer layer, a channel layer, a barrier layer, and a P-type material layer;

[0022] S2. Deposit a drain electrode in the preset drain electrode region of the P-type material layer, and form an ohmic contact by high-temperature annealing;

[0023] S3. Deposit a source electrode in the preset source electrode region of the P-type material layer to form a Schottky contact;

[0024] S4. Using the source and drain as hard masks, selectively etch the P-type material layer between the source and drain to form a separated second P-type material layer and a third P-type material layer, as well as a first groove structure.

[0025] S5. Deposit a dielectric layer covering the top and sidewalls of the source electrode, the sidewalls of the second P-type material layer, the top of the first P-type material layer, the sidewalls of the third P-type material layer, and the top and sidewalls of the drain electrode to form a second groove structure.

[0026] S6. Selectively remove the dielectric layer covering the top surfaces of the source and the drain.

[0027] S7. Deposit a gate on the surface of the dielectric layer near the source electrode.

[0028] The method for fabricating a P-channel transistor based on the tunneling effect of the present invention firstly forms an ohmic contact in the drain region and a Schottky contact simultaneously in the source region on a complete epitaxial structure using a differentiated contact process; then, using the source and drain as hard masks, the P-type material layer between them is etched to form a separated second P-type material layer and a third P-type material layer, forming a first groove structure; next, a dielectric layer is deposited to fully cover the top surface, forming a second groove structure, and the top surfaces of the source and drain are exposed by selective windowing; finally, the gate is precisely deposited on the dielectric layer near the source sidewall, constructing a tunneling control architecture that controls the width of the Schottky barrier by the gate voltage.

[0029] Furthermore, in step S4, when selectively etching the P-type material layer between the source and the drain, a continuous first P-type material layer is retained at the bottom of the P-type material layer by controlling the etching depth. A raised second and third P-type material layer are formed below the source and drain, respectively. A two-dimensional hole gas is formed at the interface between the first P-type material layer and the barrier layer. By selectively etching to retain a continuous hole transport channel at the bottom, a foundation is laid for precise gate control of the tunneling barrier of the source-end Schottky junction.

[0030] Compared with the prior art, the beneficial effects of the present invention are:

[0031] 1. By adjusting the barrier width of the Schottky junction interface through the gate, the tunneling probability of holes is changed, thereby realizing the turn-on and turn-off of the device. This avoids the need for deep etching of the P-type GaN layer to achieve normal off operation, without the need to balance the on-resistance and threshold voltage.

[0032] 2. The overall on-resistance of the device consists only of the channel resistance at the Schottky junction and the access region resistance between the gate and drain, eliminating the resistance between the gate and source in the traditional channel gate structure, and eliminating the need to thin the conductive channel, thereby reducing the overall on-resistance of the device. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of a P-type field-effect transistor based on the tunneling effect.

[0034] Figure 2 Left view of a P-type field-effect transistor based on the tunneling effect;

[0035] Figure 3 This is a top view of a P-type field-effect transistor based on the tunneling effect.

[0036] Figure 4 This is a schematic diagram of the structure of the P-type field-effect transistor based on the tunneling effect in Example 2;

[0037] Figure 5This is a schematic diagram of the fabrication process of a P-type field-effect transistor based on the tunneling effect.

[0038] In the attached figures: 1. Substrate; 2. Buffer layer; 3. Channel layer; 4. Barrier layer; 5. First P-type material layer; 6. Second P-type material layer; 7. Source; 8. Gate; 9. Drain; 10. Dielectric layer; 11. Third P-type material layer. Detailed Implementation

[0039] The present invention will be further described below with reference to specific embodiments. The accompanying drawings are for illustrative purposes only, representing schematic diagrams rather than actual physical objects, and should not be construed as limiting the scope of this patent. To better illustrate the embodiments of the present invention, some components in the drawings may be omitted, enlarged, or reduced, and do not represent the actual dimensions of the product. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0040] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present patent. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0041] Example 1

[0042] This embodiment is the first embodiment of a P-type field-effect transistor based on the tunneling effect, such as... Figure 1 , Figure 2 , Figure 3 As shown, from bottom to top, the substrate 1, buffer layer 2, channel layer 3, barrier layer 4, first P-type material layer 5, and dielectric layer 10 are arranged sequentially.

[0043] A second P-type material layer 6 and a third P-type material layer 11 are provided above the first P-type material layer 5. The top of the first P-type material layer 5, the side wall of the second P-type material layer 6, and the side wall of the third P-type material layer 11 together form the first groove structure.

[0044] The second P-type material layer 6 is covered with an active electrode 7; the third P-type material layer 11 is covered with a drain electrode 9.

[0045] The dielectric layer 10 continuously covers the top and sidewalls of the source electrode 7, the first groove structure, and the top and sidewalls of the drain electrode 9, thereby forming a second groove structure on the upper surface of the dielectric layer 10; a gate electrode 8 is disposed in the second groove structure and on the side closer to the source electrode 7.

[0046] In this configuration, an ohmic contact is formed between the drain 9 and the third P-type material layer 11, and a Schottky contact is formed between the source 7 and the second P-type material layer 6, thus forming a Schottky junction. The gate 8 controls the hole tunneling behavior by adjusting the barrier width of the Schottky junction through the dielectric layer 10.

[0047] In this embodiment, the P-type channel transistor based on the tunneling effect consists of a substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4, and a first P-type material layer 5 stacked from bottom to top, forming the basic structure of the device. The first P-type material layer 5, the second P-type material layer 6, and the third P-type material layer 11 together form a first groove structure. The dielectric layer 10 simultaneously covers the top and sidewalls of the source 7, the first groove structure, and the top and sidewalls of the drain 9, forming a second groove structure. The source 7 covered above the second P-type material layer 6 forms a Schottky contact with it, constituting a Schottky junction. The gate 8 disposed above the dielectric layer 10 applies a vertical electric field through the dielectric layer 10, dynamically controlling the barrier width of the Schottky junction. The first P-type material layer 5, the second P-type material layer 6, the third P-type material layer 11, the source 7, the gate 8, and the drain 9 disposed on the barrier layer 4 together constitute a P-type channel field-effect transistor. The equivalent Schottky junction formed by the second P-type material layer 6 and the source 7 has a triangular barrier at its interface that can be electrically modulated by the gate 8 and the dielectric layer 10. This allows the formation and depletion of the conductive channel to be controlled by the tunneling effect through barrier modulation, avoiding the process steps of deep etching of the P-GaN layer. The relatively wide barrier width of the Schottky junction interface hinders hole transport, which can improve the threshold voltage, ensure excellent normally-off characteristics, and reduce the on-resistance when the device is turned on.

[0048] In this device structure, since the gate 8 is located near the source 7, the resistance between the gate 8 and the source 7 is negligible. The overall on-resistance of the device consists only of the channel resistance at the Schottky junction and the access region resistance between the gate 8 and the drain 9. This eliminates the resistance between the gate 8 and the source 7 in the traditional channel gate structure, thereby reducing the overall on-resistance of the device.

[0049] When gate 8 is in a zero-bias state, the Schottky junction maintains its original barrier width, thus blocking hole transport. When a negative bias is applied to gate 8, the dielectric layer 10 acts on the Schottky junction, thereby reducing the barrier width and increasing the hole tunneling probability. When gate 8 is in a zero-bias state, the triangular barrier formed by the Schottky junction maintains its original width, effectively blocking hole transport, suppressing carrier tunneling, and ensuring reliable device turn-off. However, when a negative bias is applied to gate 8, the electric field of gate 8 acts on the Schottky junction interface through the dielectric layer 10, causing the band structure of the P-type material layer to shift upward, resulting in a narrowing of the triangular barrier width and a significant increase in the hole tunneling probability, thereby inducing the formation of a hole conductive channel.

[0050] The first P-type material layer 5, the second P-type material layer 6, and the third P-type material layer 11 are made of the same material. Maintaining the same material for these three layers eliminates band breaks at the heterogeneous interface, ensuring unimpeded hole transport between layers, while also simplifying the epitaxial growth process and improving interface quality. In actual processing, the first P-type material layer 5, the second P-type material layer 6, and the third P-type material layer 11 can be integrally formed by etching grooves in the P-type material layer of the epitaxial wafer.

[0051] The thickness of the first P-type material layer 5 is greater than 30 nm, and the thicknesses of the second P-type material layer 6 and the third P-type material layer 11 are the same and both greater than 10 nm. The thickness of the second P-type material layer 6 and the depth of the third P-type material layer 11 are both greater than 10 nm, meaning the depth of the first groove structure is greater than 10 nm, thus providing sufficient sidewall space to ensure the control capability of the gate 8. The thickness of the first P-type material layer 5 being greater than 30 nm helps to prevent the two-dimensional hole gas below the first groove structure from being depleted.

[0052] The doping concentration of the first P-type material layer 5, the second P-type material layer 6, and the third P-type material layer 11 is 2 × 10⁻⁶. 19 cm -3 ~4×10 19 cm -3 This is because the transistor in this invention needs to be compatible with existing commercial platforms, and there are certain requirements for the doping concentration range of the P-type material. The selection within this range is to balance the gate control capability and the on-resistance. When the doping concentration is too high, it will lead to an increase in off-state leakage current and a reduction in the switching ratio of the device. When the doping concentration is too low, it will increase the on-resistance of the first P-type material layer 5, the second P-type material layer 6, and the third P-type material layer 11.

[0053] The source 7, gate 8, and drain 9 are all made of one or more of titanium, aluminum, gold, nickel, tungsten, and titanium nitride. Since the source 7 and the second P-type material layer 6 need to form a Schottky barrier, in an e19-level doped P-type material layer, to ensure a good on / off ratio, the barrier height between the metal and p-GaN should be no less than 0.8 eV. Therefore, the source 7 metal material is chosen to be one or more of titanium, gold, tungsten, and titanium nitride.

[0054] The thickness of dielectric layer 10 is 10nm~30nm. The thickness of dielectric layer 10 is designed to balance the gate control capability and threshold voltage required by the device. Increasing the thickness of dielectric layer 10 will increase the subthreshold swing and increase the threshold voltage, and vice versa.

[0055] The materials of the first P-type material layer 5, the second P-type material layer 6, and the third P-type material layer 11 are one or more combinations of gallium nitride, aluminum nitride, aluminum gallium nitride, and indium gallium nitride. By limiting the first P-type material layer 5, the second P-type material layer 6, and the third P-type material layer 11 to gallium nitride, aluminum nitride, aluminum gallium nitride, or indium gallium nitride, on the one hand, their wide bandgap characteristics and high hole injection efficiency can be utilized to provide a stable structural basis for the tunneling effect in the Schottky junction; on the other hand, these materials are all common channel materials for constructing P-type gallium nitride devices.

[0056] The dielectric layer 10 is made of at least one of the following materials: aluminum oxide, silicon oxide, silicon nitride, aluminum nitride, gallium oxynitride, aluminum oxynitride, silicon oxynitride, hafnium oxide, and yttrium oxide. The oxide, nitride, and oxynitride materials used in the dielectric layer 10 all have the insulating effect of hindering diffusion and preventing current flow, so that no leakage current will occur when the gate 8 controls the electric field.

[0057] In this embodiment, the barrier layer 4 is made of at least one of gallium nitride, aluminum nitride, and aluminum gallium nitride. The selection of gallium nitride, aluminum nitride, or aluminum gallium nitride as the barrier layer 4, through its interface with the first P-type material layer 5, forms a high concentration of two-dimensional hole gas, which helps reduce the resistance of the gate-drain access region.

[0058] In this embodiment, substrate 1 is one of a silicon substrate, a silicon carbide substrate, or a sapphire substrate. Choosing a silicon, silicon carbide, or sapphire substrate takes into account lattice matching, cost advantages, and process compatibility, making it suitable for growing gallium nitride epitaxy.

[0059] Example 2

[0060] This embodiment is a second embodiment of a P-type field-effect transistor based on the tunneling effect. This embodiment is similar to the first embodiment, except that, as shown in the example... Figure 4As shown, the gate 8 is disposed on the second recessed structure and partially covers the region of the dielectric layer 10 directly above the source 7 and drain 9. The gate 8 allows for simultaneous modulation of the electric field at the first P-type material layer 5, the second P-type material layer 6, and the third P-type material layer 11, reducing the resistance in this region and thus lowering the overall on-resistance of the device. In actual fabrication, a self-aligned process is used when depositing the gate 8. If the gate 8 completely covers the dielectric layer 10 instead of only covering a portion of it, and if the shape of the gate 8 is identical to the shape of the dielectric layer 10 without exposing the top edge region, then, if there is a process alignment deviation, the gate 8 material may directly extend onto the metal of the source 7 or drain 9, causing a short circuit.

[0061] Example 3

[0062] This embodiment is the first embodiment of a method for fabricating a P-type field-effect transistor based on the tunneling effect, including the following steps:

[0063] S1. Provide an epitaxial structure, which from bottom to top includes a substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4, and a P-type material layer;

[0064] S2. Deposit drain electrode 9 in the pre-defined drain electrode 9 region of the P-type material layer, and form ohmic contact after high-temperature annealing;

[0065] S3. Deposit source electrode 7 in the preset source electrode 7 region of the P-type material layer to form a Schottky contact;

[0066] S4. Using the source electrode 7 and the drain electrode 9 as hard masks, selectively etch the P-type material layer between the source electrode 7 and the drain electrode 9 to form a separated second P-type material layer 6, a third P-type material layer 11 and a first groove structure.

[0067] S5. A dielectric layer 10 is deposited covering the top and sidewalls of the source electrode 7, the sidewalls of the second P-type material layer 6, the top of the first P-type material layer 5, the sidewalls of the third P-type material layer 11, and the top and sidewalls of the drain electrode 9, forming a second groove structure.

[0068] S6. Selectively remove the dielectric layer 10 covering the top surfaces of the source electrode 7 and the drain electrode 9;

[0069] S7. Deposit gate 8 on the surface of dielectric layer 10 near source 7.

[0070] like Figure 5As shown in the figure, (1), (2), (3), (4), (5), (6), and (7) represent the various steps in the preparation method. First, on the complete epitaxial structure, an ohmic contact is formed in the drain 9 region through a differentiated contact process, and a Schottky contact is simultaneously formed in the source 7 region. Then, using the source 7 and drain 9 as hard masks, the P-type material layer between them is etched to form a separated second P-type material layer 6 and a third P-type material layer 11, forming the first groove structure. Next, the top surface of the deposited dielectric layer 10 is fully covered to form the second groove structure, and the top surfaces of the source 7 and drain 9 are selectively exposed by opening windows. Finally, the gate 8 is precisely deposited on the side of the dielectric layer 10 near the sidewall of the source 7, thus constructing a tunneling control architecture that controls the width of the Schottky barrier by the gate voltage.

[0071] In step S4, when selectively etching the P-type material layer between the source electrode 7 and the drain electrode 9, the etching depth is controlled to retain a continuous first P-type material layer 5 at the bottom of the P-type material layer, and a raised second P-type material layer 6 and a third P-type material layer 11 are formed below the source electrode 7 and the drain electrode 9, respectively. A two-dimensional hole gas is formed at the interface between the first P-type material layer 5 and the barrier layer 4.

[0072] In the specific implementation of the above embodiments, the technical features can be combined in any non-contradictory way. For the sake of brevity, not all possible combinations of the above technical features are described. However, as long as the combination of these technical features is not contradictory, it should be considered to be within the scope of this specification.

[0073] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A P-type field-effect transistor based on the tunneling effect, characterized in that, include: The following layers are arranged sequentially from bottom to top: substrate (1), buffer layer (2), channel layer (3), barrier layer (4), first P-type material layer (5), and dielectric layer (10); A second P-type material layer (6) and a third P-type material layer (11) are provided above the first P-type material layer (5). The top of the first P-type material layer (5), the side wall of the second P-type material layer (6), and the side wall of the third P-type material layer (11) together form the first groove structure. The second P-type material layer (6) is covered with an active electrode (7); the third P-type material layer (11) is covered with a drain electrode (9); The dielectric layer (10) continuously covers the top and sidewall of the source electrode (7), the first groove structure, and the top and sidewall of the drain electrode (9), thereby forming a second groove structure on the upper surface of the dielectric layer (10); a gate electrode (8) is disposed in the second groove structure and on the side closer to the source electrode (7); Wherein, an ohmic contact is formed between the drain (9) and the third P-type material layer (11), and a Schottky contact is formed between the source (7) and the second P-type material layer (6) to form a Schottky junction. The gate (8) controls the barrier width of the Schottky junction through the dielectric layer (10) to control the hole tunneling behavior. When the gate (8) is in a zero bias state, the Schottky junction maintains its original barrier width, thereby blocking hole transport; when the gate (8) is subjected to a negative bias voltage, the dielectric layer (10) acts on the Schottky junction, thereby reducing the barrier width of the Schottky junction and increasing the hole tunneling probability. The gate (8) is disposed on the second groove structure and partially covers the area of ​​the dielectric layer (10) located directly above the source (7) and the drain (9).

2. The P-type field-effect transistor based on tunneling effect according to claim 1, characterized in that, The first P-type material layer (5), the second P-type material layer (6), and the third P-type material layer (11) are made of the same material.

3. The P-type field-effect transistor based on tunneling effect according to claim 2, characterized in that, The thickness of the first P-type material layer (5) is greater than 30 nm, and the thickness of the second P-type material layer (6) is the same as that of the third P-type material layer (11), and both are greater than 10 nm.

4. The P-type field-effect transistor based on tunneling effect according to claim 2, characterized in that, The doping concentration of the first P-type material layer (5), the second P-type material layer (6), and the third P-type material layer (11) is 2 × 10⁻⁶. 19 cm -3 ~4×10 19 cm -3 .

5. The P-type field-effect transistor based on tunneling effect according to claim 1, characterized in that, The source (7), gate (8), and drain (9) are all made of one or more of the following materials: titanium, aluminum, gold, nickel, tungsten, and titanium nitride.

6. The P-type field-effect transistor based on tunneling effect according to claim 1, characterized in that, The thickness of the dielectric layer (10) is 10nm~30nm.

7. A method for fabricating a P-type field-effect transistor based on the tunneling effect, used to fabricate the P-type field-effect transistor based on the tunneling effect as described in any one of claims 1 to 6, characterized in that, Includes the following steps: S1. Provide an epitaxial structure, which includes, from bottom to top, a substrate (1), a buffer layer (2), a channel layer (3), a barrier layer (4), and a P-type material layer; S2. Deposit a drain electrode (9) in the preset drain electrode region of the P-type material layer, and form an ohmic contact by high-temperature annealing; S3. Deposit a source electrode (7) in the preset source electrode region of the P-type material layer to form a Schottky contact; S4. Using the source electrode (7) and the drain electrode (9) as hard masks, selectively etch the P-type material layer between the source electrode (7) and the drain electrode (9) to form a separated second P-type material layer (6), a third P-type material layer (11) and a first groove structure. S5. Deposit a dielectric layer (10) covering the top and sidewalls of the source electrode (7), the sidewalls of the second P-type material layer (6), the top of the first P-type material layer (5), the sidewalls of the third P-type material layer (11), and the top and sidewalls of the drain electrode (9) to form a second groove structure. S6. Selectively remove the dielectric layer (10) covering the top surface of the source (7) and the drain (9); S7. Deposit a gate (8) on the surface of the dielectric layer (10) on the side near the source (7).

8. The method for fabricating a P-type field-effect transistor based on the tunneling effect according to claim 7, characterized in that, In step S4, when selectively etching the P-type material layer between the source (7) and the drain (9), by controlling the etching depth, a continuous first P-type material layer (5) is retained at the bottom of the P-type material layer, and a raised second P-type material layer (6) and a third P-type material layer (11) are formed below the source (7) and the drain (9), respectively. A two-dimensional hole gas is formed at the interface between the first P-type material layer (5) and the barrier layer (4).

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