A primary and secondary fusion pole-mounted circuit breaker low-delay control method and system

Abstract

The present application relates to the field of circuit breaker, specifically to a kind of primary and secondary fusion pole-mounted circuit breaker low-delay control method and system, method includes FPGA synchronous sampling voltage, current analog signal and analog-digital conversion, internal hardware logic kernel parallel computing at least including current effective value, rate of change and voltage effective value Multi-dimensional electrical characteristic quantity;MCU receives the characteristic quantity by high-speed interface;MCU executes first level extremely fast response, compares current rate of change with preset threshold value, and when overrun, first trip signal is directly generated by hardware circuit;While executing second level prediction protection, running adaptive prediction algorithm, based on historical and real-time data, the trend of line electrical parameters is predicted, and second trip signal is generated when fault condition is met;Two signals are sent to high-speed drive module, and circuit breaker is driven to open. The present application shortens the delay from fault detection to tripping, solves the problem of high delay of traditional MCU serial processing, and adaptive prediction algorithm reduces the protection misoperation rate.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of circuit breakers, in particular to a primary and secondary fusion pole-mounted circuit breaker low-delay control method and system. BACKGROUND

[0002] In the power system distribution network, the pole-mounted circuit breaker as a key dividing switch device undertakes the important functions of line fault detection, isolation and power supply recovery, and the response speed of its protection control is directly related to the safety and reliability of the power grid operation. With the large-scale access of distributed power sources and the improvement of user requirements for power supply quality, the traditional pole-mounted circuit breaker protection system gradually exposes obvious technical bottlenecks. In the prior art, most pole-mounted circuit breakers use a micro control unit (MCU) to undertake all tasks such as data sampling, characteristic quantity calculation and protection decision, which is limited by the serial processing mechanism of the MCU, and has problems such as poor sampling synchronization and long time-consuming for characteristic quantity calculation, resulting in a total response time from fault occurrence to circuit breaker tripping usually exceeding 50 ms, which is difficult to meet the requirements of modern distribution network for short-circuit fault fast removal. At the same time, the traditional protection algorithm relies on a single current threshold for judgment, lacks the ability to predict the development trend of the fault, and is easily disturbed by power grid fluctuations, leading to misoperation or refusal to operate, which may cause over-level tripping and expand the power outage range.

[0003] The comparative document CN218826917U discloses a trip unit with a communication interface, which uses an MCU circuit to realize sampling calculation and control signal output of the power grid voltage. The core of this scheme is to realize the connection of the trip unit through the communication interface, and the protection decision still relies on the serial processing flow of a single MCU, which cannot solve the problem of high protection delay in the traditional architecture. In actual application, this design is difficult to meet the fast response requirement of the distribution network short-circuit fault, and cannot effectively avoid the dynamic and thermal stability impact of short-circuit current on transformers, distribution lines and other equipment, so there is an urgent need for a control method that can realize low delay of the whole link of sampling, calculation and decision. SUMMARY

[0004] The present application relates to the field of circuit breakers, in particular to a primary and secondary fusion pole-mounted circuit breaker low-delay control method and system.

[0005] To achieve the above-mentioned purpose, the following technical solutions are adopted.

[0006] A primary and secondary fusion pole-mounted circuit breaker low-delay control method, comprising the following steps:

[0007] The analog signals accessed by the voltage sensor and the current sensor are synchronously sampled and analog-digital converted by a field programmable gate array, and a plurality of multi-dimensional electrical characteristic quantities including at least the current effective value, the current change rate and the voltage effective value are calculated in real time by a hardware logic kernel running in parallel inside the field programmable gate array;

[0008] The micro control unit receives the multi-dimensional electrical characteristic quantities from the field programmable gate array through a high-speed serial peripheral interface SPI or a high-speed parallel bus;

[0009] The micro control unit performs a first level fast response operation, which includes comparing the current change rate di / dt with a preset first current change rate threshold value, and directly generating a first trip control signal through a hardware comparator circuit or a programmable logic array of the micro control unit when the current change rate exceeds the first current change rate threshold value;

[0010] Meanwhile, the micro control unit performs a second level prediction protection operation, which includes running an adaptive prediction algorithm to predict the trend of the electrical parameter change of the line at a future time based on the historical data sequence and real-time data of the multi-dimensional electrical characteristic quantities, and generating a second trip control signal when the prediction result meets a preset fault condition;

[0011] The first trip control signal or the second trip control signal is sent to a high-speed drive module for driving the operating mechanism of a primary and secondary fusion pole-mounted circuit breaker to perform the opening action.

[0012] Optionally, the adaptive prediction algorithm in the second level prediction protection operation performed by the micro control unit specifically includes the following steps:

[0013] The predicted value of the current effective value at at least one future sampling point is calculated by linear extrapolation or least squares fitting algorithm using the real-time data and the historical data sequence of the current effective value within a predetermined time window in the past; meanwhile, the real-time data and the direction of the current change rate are analyzed; if the predicted value of the current effective value exceeds a preset current instantaneous protection setting value, and at the same time the real-time value of the current change rate is positive and exceeds a preset second current change rate threshold value, it is determined that the fault condition is met and the second trip control signal is generated.

[0014] Optionally, the second level prediction protection operation performed by the micro control unit further includes:

[0015] The second harmonic content of the current is calculated in real time by the hardware logic kernel of the field programmable gate array;

[0016] The adaptive prediction algorithm further takes the second harmonic content as part of the comprehensive criterion, if the predicted value of the current effective value exceeds the preset current instantaneous trip protection setting value, the real-time value of the current rate of change is positive and exceeds the second current rate of change threshold value, and the second harmonic content is lower than the preset harmonic blocking threshold value, it is determined that the fault condition is met and the second trip control signal is generated.

[0017] Optionally, it further comprises a third level protection operation executed by the micro control unit, which is a backup protection, including the following steps:

[0018] Based on the current effective value and the voltage effective value sent by the field programmable gate array, the classic protection algorithm including timing limit overcurrent protection, inverse time limit overcurrent protection and overvoltage protection is executed, and the third trip control signal is generated when the algorithm condition is met; the third trip control signal is also sent to the high-speed drive module.

[0019] Optionally, it further comprises a system external communication optimization operation: when the micro control unit needs to communicate with the remote master station or adjacent intelligent terminal, a set of simplified communication frames are constructed and sent, the frame format of the simplified communication frame only contains the state flag bit, the maximum value in the multi-dimensional electrical characteristic quantity, the prediction result obtained by the adaptive prediction algorithm and the cyclic redundancy check code, and is transmitted through the high-speed industrial Ethernet physical interface.

[0020] Optionally, it further comprises a preprocessing operation executed by the field programmable gate array: the hardware logic core running in parallel inside the field programmable gate array also calculates the active power, reactive power and power factor in real time; the micro control unit receives the complete characteristic data packet containing the current effective value, the current rate of change, the voltage effective value, the active power, the reactive power and the power factor through the high-speed serial peripheral interface SPI or high-speed parallel bus.

[0021] A primary and secondary fusion pole-mounted circuit breaker low-delay control system, comprising,

[0022] The sensing and sampling module comprises a voltage sensor for collecting line voltage signals, a current sensor for collecting line current signals, and a high-precision analog-to-digital converter (ADC) chip connected to the output terminals of the voltage sensor and the current sensor.

[0023] The field programmable gate array preprocessing module has a data input port connected to the digital output port of the high-precision analog-to-digital converter (ADC) chip, and a plurality of independent hardware logic cores are arranged inside the field programmable gate array preprocessing module for parallel processing of ADC sampling data and real-time output of the multi-dimensional electrical characteristic quantity.

[0024] A micro control unit intelligent decision module is interconnected with the data output port of the FPGA preprocessing module through a high-speed serial peripheral interface (SPI) or a high-speed parallel bus. The micro control unit intelligent decision module internally integrates a hardware comparator circuit or a programmable logic array unit for implementing the first level of extremely fast response operation. Meanwhile, the micro control unit intelligent decision module internally stores a program code and runs the adaptive prediction algorithm for implementing the second level of prediction protection operation.

[0025] A high-speed drive module has a control signal input port connected with a trip signal output port of the micro control unit intelligent decision module. The high-speed drive module is used for receiving the first trip control signal or the second trip control signal and performing power amplification on the first trip control signal or the second trip control signal, and outputting a tripping current for driving a tripping mechanism of a primary and secondary fusion pole-mounted circuit breaker.

[0026] An optimized communication module is connected with a communication interface of the micro control unit intelligent decision module. The optimized communication module includes a high-speed industrial Ethernet phy chip and a transformer, and is used for implementing transmission of a simplified communication frame.

[0027] Optionally, the FPGA preprocessing module and the micro control unit intelligent decision module are integrated on a same printed circuit board (PCB). The wiring length of the high-speed serial peripheral interface (SPI) or the high-speed parallel bus is limited within 10 cm. The communication clock frequency of the high-speed serial peripheral interface (SPI) is configured to be greater than 20 MHz, so as to ensure low-delay transmission of the multi-dimensional electrical characteristic quantity.

[0028] Optionally, the high-speed drive module includes a high-speed optocoupler isolation unit, a gate drive chip and a high-power metal-oxide semiconductor field effect transistor (MOSFET). An input end of the high-speed optocoupler isolation unit is connected with a trip signal output port of the micro control unit intelligent decision module. An output end of the high-speed optocoupler isolation unit is connected with an input end of the gate drive chip. An output end of the gate drive chip drives a gate of the high-power metal-oxide semiconductor field effect transistor (MOSFET). A source and a drain of the high-power metal-oxide semiconductor field effect transistor (MOSFET) are connected in series on a loop of a tripping coil of the primary and secondary fusion pole-mounted circuit breaker, and are used for controlling power-on and power-off of the tripping coil.

[0029] A primary and secondary fusion pole-mounted circuit breaker includes a circuit breaker body, a tripping mechanism and the low-delay control system of the primary and secondary fusion pole-mounted circuit breaker. An output end of the high-speed drive module is electrically connected with a tripping coil of the tripping mechanism. A primary side of a voltage sensor and a current sensor of the sensing and sampling module is respectively connected with a corresponding primary terminal of the circuit breaker body.

[0030] Compared with the prior art, the application has the following beneficial effects:

[0031] The application synchronously samples voltage and current signals and calculates parallel characteristic quantities through a field programmable gate array (FPGA), receives data through a high-speed interface of a micro control unit (MCU) and performs a first level fast response operation, significantly shortening the delay time from fault detection to generation of a trip signal. The FPGA can generate key characteristic quantities such as current effective value and current rate of change in real time, the MCU directly judges the threshold of the current rate of change through a hardware comparator and generates a trip signal, effectively solving the problem of excessively high protection delay caused by serial processing of a traditional MCU, ensuring that a short circuit fault can be cut off in a shorter time and reducing the impact of the fault on power grid equipment. On this basis, a second level adaptive prediction algorithm realizes accurate prediction of the development trend of the fault through fusion analysis of historical data and real-time data, further reduces the protection misoperation rate in combination with a comprehensive criterion of the second harmonic content, and a third level classical protection algorithm as a backup mechanism improves the reliability of system operation. An optimized simplified communication frame structure and a high-speed industrial Ethernet transmission mode reduce data interaction delay, the integrated PCB design of the FPGA and the MCU and the use of a high-speed drive module guarantee the realization of low delay characteristics from the hardware level, and parallel calculation of multi-dimensional characteristic quantities also provides comprehensive data support for power grid state evaluation, thereby improving the protection performance of the pole-mounted circuit breaker and the stability of power grid operation as a whole. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 is a step flowchart of an embodiment of the low delay control method of the primary and secondary fusion pole-mounted circuit breaker.

[0033] Figure 2 is a module structure diagram of an embodiment of the low delay control system of the primary and secondary fusion pole-mounted circuit breaker.

[0034] Figure 3 is a high-speed drive module structure diagram of an embodiment of the low delay control system of the primary and secondary fusion pole-mounted circuit breaker.

[0035] Figure 4 is an external structure diagram of an embodiment of the primary and secondary fusion pole-mounted circuit breaker.

[0036] Figure 5 is an internal structure diagram of an embodiment of the primary and secondary fusion pole-mounted circuit breaker.

[0037] 1, circuit breaker body; 2, operating mechanism; 3, opening coil; 4, voltage sensor; 5, current sensor; 6, high-speed drive module. DETAILED DESCRIPTION

[0038] The present invention will now be described in detail with reference to the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0039] The following detailed description is exemplary and intended to provide further detailed explanation of the invention. Unless otherwise specified, all technical terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used in this invention is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention.

[0040] Example 1

[0041] like Figure 1 As shown, a low-latency control method for a primary and secondary integrated pole-mounted circuit breaker is used to achieve low-latency control of the primary and secondary integrated pole-mounted circuit breaker. Its core is to complete the entire process of low-latency processing from signal acquisition, feature calculation to protection decision through the collaborative work of field programmable gate array (FPGA) and microcontroller unit (MCU). The following details each step of the method and its extended implementation.

[0042] In the signal sampling and multi-dimensional electrical characteristic calculation stage, the selection and connection design of voltage sensor 4 and current sensor 5 must first be completed. Voltage sensor 4 can be a voltage divider type, whose input side can be connected in parallel with the primary terminal of the pole-mounted circuit breaker body 1 to collect the three-phase voltage analog signal of the line. This type of sensor has the characteristics of good linearity and fast response speed, ensuring the accuracy of voltage signal acquisition. Current sensor 5 can be a Rogowski coil current sensor, which can be connected in series with the primary circuit of the circuit breaker through a through-hole installation to collect the three-phase current analog signal of the line. This avoids the magnetic saturation problem of traditional current transformers and is suitable for collecting large current signals during short-circuit faults. The output terminals of both types of sensors can be connected to the analog input port of a high-precision analog-to-digital converter (ADC) chip. The ADC chip can be a model with 16-bit resolution and a single-channel sampling rate of not less than 200kSPS, and can support multi-channel synchronous sampling function, which can simultaneously perform analog-to-digital conversion on voltage and current analog signals, ensuring the time consistency of sampling data from different channels, laying the foundation for the accuracy of subsequent characteristic calculations.

[0043] The digital output port of the ADC chip can be directly connected to the data line of the FPGA. Multiple independent hardware logic cores can be pre-configured inside the FPGA. Each logic core can correspond to a multi-dimensional electrical characteristic calculation task to achieve parallel processing. The hardware logic core used to calculate the effective value of the current can employ the root mean square (RMS) algorithm. This involves calculating the sum of squares, the mean, and the square root of N consecutive sampling points from the digital current sampling sequence output by the ADC to obtain the real-time effective current value. The value of N can be determined based on the line frequency; for example, in a 50Hz power frequency line, N can be set to 20 to ensure coverage of a complete power frequency cycle. The hardware logic core used to calculate the rate of change of current (di / dt) can employ a differential algorithm. This involves calculating the difference between the current values ​​of two adjacent sampling points and dividing by the sampling interval to obtain the real-time di / dt value. The sampling interval can be determined by the ADC's sampling rate; if the sampling rate is 200 kSPS, the sampling interval can be set to 5 μs to ensure the real-time performance of the di / dt calculation. The hardware logic core used to calculate the effective value of the voltage can maintain the same algorithm structure as the logic core for calculating the effective value of the current, only the input data is replaced with a digital voltage sampling sequence. Furthermore, to further enrich the dimensions of characteristic quantities, the FPGA can also be configured with hardware logic cores for calculating active power, reactive power, and power factor: the active power calculation logic core can be obtained by multiplying the voltage and current sample values ​​at the same moment and averaging the product over a power frequency cycle; the reactive power calculation logic core can be calculated based on the relationship between active power and the effective values ​​of voltage and current through formula derivation; the power factor can be obtained from the ratio of active power to apparent power, where apparent power is the product of the effective values ​​of voltage and current. The parallel operation of all hardware logic cores can control the calculation time of multi-dimensional electrical characteristic quantities to the microsecond level, significantly reducing the latency of characteristic quantity acquisition.

[0044] Data transmission between the MCU and FPGA can be achieved using either a high-speed serial peripheral interface (SPI) or a high-speed parallel bus, depending on the specific application scenario. When the system has low requirements for data transmission bandwidth and limited wiring space, the SPI interface can be selected. In this case, the SPI communication clock frequency can be configured to be above 20MHz, such as 25MHz, to ensure that the transmission time of each data frame (containing all multi-dimensional electrical characteristics) does not exceed 1μs. When the system needs to transmit a large amount of data, and the FPGA and MCU are integrated on the same printed circuit board (PCB), a high-speed parallel bus can be selected. The bus width can be set to 16 bits or 32 bits, while strictly controlling the wiring length to within 10 cm. Equal-length wiring design can be used to reduce signal transmission delay differences, avoid signal distortion during data transmission, and ensure that multi-dimensional electrical characteristics can be transmitted to the MCU completely and quickly.

[0045] When the MCU performs the first-level ultra-fast response operation, it can utilize its internally integrated hardware comparator circuit or programmable logic array (PLA). The input of the hardware comparator circuit can be connected to the real-time di / dt value transmitted by the FPGA and a preset first current change rate threshold value. The threshold value can be set by combining the rated current of the line, the calculated short-circuit current value, and the equipment's withstand capability. For example, for a line with a rated current of 100A, the first current change rate threshold value can be set to 50A / ms. When the hardware comparator detects that the real-time di / dt value exceeds this threshold value, it can directly generate the first trip control signal through the hardware circuit without going through the MCU's software calculation. The response time of this process can be controlled within 10ns, achieving an ultra-fast response to severe short-circuit faults and preventing the short-circuit current from acting on the line and equipment for a long time.

[0046] When the MCU performs the second-level predictive protection operation, the adaptive prediction algorithm can be implemented based on historical data sequences and real-time data of multi-dimensional electrical characteristics. First, a data buffer can be created within the MCU to store historical data of the effective current value within a predetermined time window. The length of the predetermined time window can be determined based on the characteristics of line fault development; for example, it can be set to 10 sampling periods (corresponding to 200μs, based on a 200kSPS sampling rate). During algorithm execution, the historical data sequence and the current real-time effective current value are read from the buffer. A linear extrapolation method is used to calculate the predicted effective current value for at least one future sampling point: a linear fit is performed on the historical data sequence with time as the x-axis and the effective current value as the y-axis to obtain a linear equation showing the change of the effective current value over time. Substituting this equation with the time parameters of the future sampling point yields the predicted value. If the line current variation is complex, a least squares fitting algorithm can be used to improve the accuracy of the predicted value by minimizing the sum of squared errors between the historical data and the fitted curve. Simultaneously, the algorithm can analyze the magnitude and direction of di / dt in real time. When the real-time value of di / dt is positive, it indicates that the current is in an upward phase, potentially indicating a fault development trend. When the predicted value of the effective current exceeds the preset instantaneous overcurrent protection setting (this setting can be determined based on the maximum allowable short-circuit current of the line, for example, it can be set to 10 times the rated current), and the real-time value of di / dt is positive and exceeds the preset second current change rate threshold (this threshold can be less than the first current change rate threshold, for example, it can be set to 30A / ms to predict faults in advance), the fault condition is determined to be met, and a second trip control signal can be generated. If it is necessary to further improve the accuracy of protection decision, the second harmonic content of the current can also be introduced as a comprehensive criterion: the FPGA needs to be additionally configured with a hardware logic core for calculating the second harmonic content. This logic core can perform harmonic decomposition on the current sampling sequence through the Fourier transform algorithm, extract the amplitude of the second harmonic component, and calculate its percentage of the fundamental component (i.e., the second harmonic content). This data can also be transmitted to the MCU. At this time, the adaptive prediction algorithm can simultaneously determine: the predicted value of the effective current value, the overspeed determination value, the real-time value of di / dt is positive and exceeds the second threshold, and the second harmonic content is lower than the preset harmonic blocking threshold value (this threshold value can be determined according to the second harmonic content under non-fault conditions such as no-load closing, for example, it can be set to 5%). Only when all three conditions are met will the second trip control signal be generated, effectively avoiding protection maloperation caused by no-load closing, motor starting and other conditions.

[0047] When the first and second level protection operations fail to respond in a timely manner, the third level protection operation executed by the MCU can serve as backup protection. This level can run classic protection algorithms such as definite-time overcurrent protection, inverse-time overcurrent protection, and overvoltage protection based on the RMS current and voltage values ​​transmitted by the FPGA. The operating current setting of definite-time overcurrent protection can be set to 1.2-1.5 times the rated line current, and the operating time can be determined according to the coordination between upper and lower level protections, for example, it can be set to 0.5s to ensure reliable operation after the fault lasts for a certain period of time. Inverse-time overcurrent protection can adopt the IEC standard inverse-time characteristic curve, and the operating time can decrease as the fault current increases. For example, when the fault current is 5 times the rated current, the operating time can be set to 0.2s to achieve the protection effect of faster operation as the fault becomes more severe. The operating voltage setting of overvoltage protection can be set to 1.1-1.2 times the rated voltage. When the line voltage exceeds this setting, a protection signal can be generated quickly. When the above algorithms meet the operating conditions, a third trip control signal can be generated to ensure that the fault can be reliably cleared.

[0048] In addition, the MCU can also perform external communication optimization. When communication with a remote master station or adjacent intelligent terminal is required, the MCU can construct a simplified communication frame: the beginning of the frame structure can be set to an 8-bit status flag to identify the current operating status of the circuit breaker (such as normal, fault, open, closed); then it can be set to a 16-bit multi-dimensional electrical characteristic maximum value field to store the maximum values ​​of characteristic quantities such as current RMS and voltage RMS over a period of time (such as 1 second), so that the master station can grasp the line's operating limit state; next, it can be set to a 32-bit prediction result field to store the predicted value of the future current RMS obtained by the adaptive prediction algorithm; finally, it can be set to a 16-bit cyclic redundancy check code (using the CCITT standard CRC algorithm) to verify the integrity of the frame data and avoid transmission errors. This simplified communication frame can be transmitted through the MCU's high-speed industrial Ethernet physical interface. The Ethernet physical interface can be selected to support a chip with a rate of 100Mbps to ensure that the data transmission rate meets the real-time monitoring requirements, while reducing the amount of communication data and reducing network bandwidth usage.

[0049] Example 2

[0050] like Figure 2 and Figure 3 As shown, the low-delay control system for the primary and secondary integrated pole-mounted circuit breaker is used to implement the control method in Embodiment 1 above, as detailed below:

[0051] In the sensing and sampling module, voltage sensor 4 can be a voltage divider sensor conforming to GB / T13850 standard, with a rated input voltage that matches the line's rated voltage (e.g., 10kV) and an output voltage that can be set to a 0-5V analog signal. Current sensor 5 can be a Rogowski coil sensor conforming to GB / T20840 standard, with a rated input current that matches the line's rated current (e.g., 200A), and its output current signal can be converted to a 0-5V analog signal by a signal conditioning circuit before being connected to the ADC chip. The ADC chip can be a multi-channel synchronous sampling model, with a filter capacitor configured at its power supply terminal to reduce the impact of power supply noise on sampling accuracy. The digital output terminal can be connected to the FPGA's GPIO pins via a ribbon cable.

[0052] The field-programmable gate array (FPGA) preprocessing module can use Xilinx Artix series FPGA chips. These chips offer abundant logic resources and high-speed data processing capabilities. The internal hardware logic cores can be implemented using Verilog HDL, and the clock signals for each logic core can be provided by the FPGA's internal phase-locked loop (PLL), ensuring clock frequency stability. The FPGA's configuration chip can use an SPI interface to store the configuration program for the hardware logic cores. Upon power-up, the configuration is automatically loaded, ensuring the FPGA quickly enters a working state.

[0053] The intelligent decision-making module of the microcontroller unit can be selected from the STM32H7 series MCU. This model integrates a high-speed hardware comparator and PLA unit, and supports SPI and high-speed parallel bus interfaces. The SPI interface or parallel bus between the MCU and the FPGA can be designed with impedance matching on the PCB, and terminating resistors can be connected in parallel at both ends of the bus to reduce signal reflection. The MCU's program memory can store the code for adaptive prediction algorithms, classic protection algorithms, and communication protocol stacks, while the data memory can be used to cache historical data of multi-dimensional electrical characteristics.

[0054] In the high-speed drive module 6, the high-speed optocoupler isolation unit can be a 6N137 model optocoupler to isolate the trip control signal output by the MCU from the subsequent high-voltage circuit and avoid interference; the gate driver chip can be an IR2110 model, whose output terminal can provide sufficient drive current to ensure reliable MOSFET conduction and turn-off; the high-power MOSFET can be an N-channel enhancement type model, with a rated voltage of not less than 60V and a rated current of not less than 50A. Its source and drain can be connected in series in the circuit of the trip coil 3. The drain can be connected to one end of the trip coil 3 through a wire, and the source can be grounded. The other end of the trip coil 3 can be connected to a DC power supply (such as 24V).

[0055] The optimized communication module can include a high-speed industrial Ethernet PHY chip and an Ethernet transformer. The PHY chip can be the DP83848 model, which supports 10 / 100Mbps adaptive rate and connects to the MCU through the MII interface. The Ethernet transformer can be the HR601680 model, whose input can be connected to the differential signal pin of the PHY chip, and whose output can be connected to an external communication line through an RJ45 interface to realize the physical layer transmission of simplified communication frames.

[0056] Example 3

[0057] like Figure 4 and Figure 5 As shown, the primary and secondary integrated pole-mounted circuit breaker of this embodiment consists of a circuit breaker body 1, an operating mechanism 2, and the low-latency control system in the above embodiment 2.

[0058] The circuit breaker body 1 can be an outdoor vacuum circuit breaker, with its arc-extinguishing chamber using a ceramic shell, providing excellent weather resistance and insulation performance. Its rated voltage can match the line voltage level (e.g., 10kV), rated current can match the line rated current (e.g., 200A), and short-circuit breaking current can be no less than 12.5kA, ensuring reliable interruption of short-circuit fault current. The operating mechanism 2 can be a spring-operated mechanism 2. This type of mechanism has a fast operating speed, with a tripping time controllable within 20ms, matching the fast response characteristics of the low-delay control system. The parameters of the tripping coil 3 of the operating mechanism 2 can be matched with the output of the high-speed drive module 6; the rated voltage can be set to 24V, and the rated current to 10A, ensuring the drive module can provide sufficient tripping current.

[0059] In the sensing and sampling module of the low-latency control system, the primary side of the voltage sensor 4 can be fixedly connected to the primary terminal of the circuit breaker body 1 by bolts, and connected to the line in parallel to ensure that the collected voltage signal is consistent with the line voltage; the primary side of the current sensor 5 can be installed in a through-hole manner, and the conductive rod of the primary terminal of the circuit breaker body 1 can pass through the center hole of the current sensor 5 to achieve series connection with the line, ensuring that the collected current signal is consistent with the line current.

[0060] The output of the high-speed drive module 6 can be connected to the terminal block of the trip coil 3 of the operating mechanism 2 via a high-temperature resistant wire. The cross-sectional area of ​​the wire can be determined according to the rated current of the trip coil 3 (e.g., 2.5 mm²), and the outer layer of the wire can be wrapped with an insulating sleeve to prevent insulation aging in outdoor environments. When the low-delay control system generates a trip control signal, the high-speed drive module 6 can amplify the signal and output a trip current. The trip current flowing through the trip coil 3 can generate electromagnetic force, driving the mechanical parts of the operating mechanism 2 to move, thereby causing the moving and stationary contacts of the circuit breaker body 1 to separate, achieving isolation of line faults.

[0061] The housing of the entire primary and secondary integrated pole-mounted circuit breaker can be made of stainless steel. The PCB board of the low-latency control system can be installed in a waterproof cavity inside the housing. Heat sinks can be installed in the cavity to ensure that chips such as FPGA and MCU can work stably in outdoor high-temperature environments, while avoiding the influence of rain and dust on electronic components, thus ensuring the overall reliability and stability of the circuit breaker.

[0062] As is known from common technical knowledge, this invention can be implemented through other embodiments that do not depart from its spirit or essential characteristics. Therefore, the disclosed embodiments described above are merely illustrative in all respects and are not the only ones. All modifications within the scope of this invention or its equivalents are included in this invention.

Claims

1. A low-delay control method for a primary and secondary integrated pole-mounted circuit breaker, characterized in that, Includes the following steps: The analog signals connected to the voltage sensor (4) and the current sensor (5) are synchronously sampled and converted from analog to digital by a field-programmable gate array (FPGA). Multi-dimensional electrical characteristics are calculated and generated by parallel hardware logic within the FPGA. The multi-dimensional electrical characteristics include at least the effective value of current, the rate of change of current, and the effective value of voltage. The microcontroller receives the multi-dimensional electrical characteristics from the field-programmable gate array via a high-speed serial peripheral interface (SPI) or a high-speed parallel bus. The microcontroller unit performs a first-level ultra-fast response operation, which includes comparing the current change rate with a preset first current change rate threshold value, and when the current change rate exceeds the first current change rate threshold value, directly generating a first trip control signal through the hardware comparator circuit or programmable logic array of the microcontroller unit. Simultaneously, the microcontroller unit performs a second-level predictive protection operation, which includes running an adaptive prediction algorithm. This algorithm predicts the future trends of electrical parameters of the line based on historical data sequences and real-time data of the multi-dimensional electrical characteristics, and generates a second trip control signal when the prediction result meets preset fault conditions. Specifically, the adaptive prediction algorithm in the second-level predictive protection operation performed by the microcontroller unit includes the following steps: Using the real-time data of the effective current value and its historical data sequence within a predetermined time window, the predicted value of the effective current value at at least one sampling point in the future is calculated by linear extrapolation or least squares fitting algorithm; at the same time, the real-time data and direction of the current change rate are analyzed; if the predicted value of the effective current value exceeds the preset instantaneous overcurrent protection setting, and the real-time value of the current change rate is positive and exceeds the preset second current change rate threshold, then the fault condition is determined to be met and the second trip control signal is generated; The first trip control signal or the second trip control signal is sent to the high-speed drive module (6) to drive the operating mechanism (2) of the primary and secondary fusion pole-mounted circuit breaker to perform the tripping action; It also includes a third-level protection operation performed by the microcontroller unit as backup protection, which includes the following steps: Based on the effective current value and effective voltage value sent by the field programmable gate array, the classic protection algorithm including definite time overcurrent protection, inverse time overcurrent protection and overvoltage protection is executed, and a third trip control signal is generated when the algorithm conditions are met; the third trip control signal is also sent to the high-speed drive module (6).

2. The low-delay control method for a primary and secondary integrated pole-mounted circuit breaker according to claim 1, characterized in that, The microcontroller unit also performs the second-level predictive protection operation in the following ways: The second harmonic content of the current is calculated by verifying the hardware logic of the field-programmable gate array. The adaptive prediction algorithm further incorporates the second harmonic content as part of the comprehensive criterion. If the predicted value of the effective current exceeds the preset instantaneous overcurrent protection setting, the real-time value of the current change rate is positive and exceeds the second current change rate threshold, and the second harmonic content is lower than the preset harmonic blocking threshold, then the fault condition is determined to be met and the second trip control signal is generated.

3. The low-delay control method for a primary and secondary integrated pole-mounted circuit breaker according to claim 1, characterized in that, It also includes external communication optimization operations: when the microcontroller needs to communicate with a remote master station or adjacent intelligent terminal, it constructs and sends a set of simplified communication frames. The frame format of the simplified communication frames only includes status flag bits, the maximum value of the multi-dimensional electrical characteristic quantities, the prediction result obtained by the adaptive prediction algorithm, and the cyclic redundancy check code, and is transmitted through a high-speed industrial Ethernet physical interface.

4. The low-delay control method for a primary and secondary integrated pole-mounted circuit breaker according to claim 1, characterized in that, It also includes preprocessing operations performed by the field-programmable gate array: the hardware logic cores running in parallel inside the field-programmable gate array also calculate and generate active power, reactive power and power factor in real time; the microcontroller receives a complete feature data packet containing the effective value of the current, the rate of change of the current, the effective value of the voltage, the active power, the reactive power and the power factor through the high-speed serial peripheral interface SPI or the high-speed parallel bus.

5. A low-delay control system for a primary and secondary integrated pole-mounted circuit breaker, based on the low-delay control method for a primary and secondary integrated pole-mounted circuit breaker according to any one of claims 1 to 4, characterized in that, include, The sensing and sampling module includes a voltage sensor (4) for acquiring line voltage signals, a current sensor (5) for acquiring line current signals, and a high-precision analog-to-digital converter (ADC) chip connected to the output terminals of the voltage sensor (4) and the current sensor (5). The field-programmable gate array (FPGA) preprocessing module has its data input port connected to the digital output port of the high-precision analog-to-digital converter (ADC) chip. The FPGA preprocessing module has multiple independent hardware logic cores inside, which are used to process the ADC sampled data in parallel and output the multi-dimensional electrical characteristic quantities in real time. The microcontroller intelligent decision module is interconnected with the data output port of the field-programmable gate array preprocessing module via a high-speed serial peripheral interface SPI or a high-speed parallel bus. The microcontroller intelligent decision module integrates a hardware comparator circuit or a programmable logic array unit to implement the first-level ultra-fast response operation. At the same time, the microcontroller intelligent decision module also stores program code and runs the adaptive prediction algorithm to implement the second-level predictive protection operation. The high-speed drive module (6) has its control signal input port connected to the trip signal output port of the intelligent decision module of the microcontroller unit. It is used to receive the first trip control signal or the second trip control signal and amplify it to output the tripping current of the primary and secondary fusion pole-mounted circuit breaker operating mechanism (2). An optimized communication module is connected to the communication interface of the intelligent decision-making module of the microcontroller unit. The optimized communication module includes a high-speed industrial Ethernet PHY chip and a transformer, which is used to realize the transmission of simplified communication frames.

6. The low-delay control system for a primary and secondary integrated pole-mounted circuit breaker according to claim 5, characterized in that, The field-programmable gate array preprocessing module and the microcontroller intelligent decision-making module are integrated on the same printed circuit board (PCB). The wiring length of the high-speed serial peripheral interface (SPI) or high-speed parallel bus is less than 10 cm, and the communication clock frequency of the high-speed serial peripheral interface (SPI) is greater than 20 MHz.

7. The low-delay control system for a primary and secondary integrated pole-mounted circuit breaker according to claim 5, characterized in that, The high-speed drive module (6) includes a high-speed optocoupler isolation unit, a gate driver chip, and a high-power metal-oxide-semiconductor field-effect transistor (MOSFET). The input terminal of the high-speed optocoupler isolation unit is connected to the trip signal output port of the intelligent decision module of the microcontroller unit. The output terminal of the high-speed optocoupler isolation unit is connected to the input terminal of the gate driver chip. The output terminal of the gate driver chip drives the gate of the high-power metal-oxide-semiconductor field-effect transistor (MOSFET). The source and drain of the high-power metal-oxide-semiconductor field-effect transistor (MOSFET) are connected in series in the circuit of the trip coil (3) of the primary and secondary fusion on-pillar circuit breaker to control the energization and de-energization of the trip coil (3).

8. A primary and secondary integrated pole-mounted circuit breaker, characterized in that, The system includes a circuit breaker body (1), an operating mechanism (2), and a low-delay control system for a primary and secondary integrated pole-mounted circuit breaker as described in any one of claims 5 to 7. The output terminal of the high-speed drive module (6) is electrically connected to the trip coil (3) of the operating mechanism (2), and the primary side of the voltage sensor (4) and the current sensor (5) of the sensing and sampling module are respectively connected to the corresponding primary terminals of the circuit breaker body (1).

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